JP2006031133A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor device for detecting the abnormality of two input clock signals. <P>SOLUTION: The semiconductor device is provided with a counting part 11 for inputting clock signals fc and fs which are asynchronous and different, and for counting the number of clocks of the clock signal fc in a predetermined period based on the clock signal fs, and for outputting a count value sc and a judging part 12 for outputting an error signal err showing the abnormality of the clock signal fc or fs when the count value sc from the counting part 11 is not present in a predetermined range. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device to which two clock signals having different periods are input, and more particularly, to a semiconductor device having a clock signal abnormality detection function.

  In a system in which the entire operation is controlled by the CPU, a watchdog timer that monitors a system clock is employed to detect a deadlock due to a runaway of the CPU. (For example, refer to Patent Document 1.) For this reason, the conventional semiconductor device is designed to be reset by a reset signal generated by a watchdog timer when an abnormality occurs in the system.

  However, since the watchdog timer is controlled by the software of the CPU, it often did not function well when a temporary abnormality occurred in the system clock due to poor contact of the mounted crystal oscillator. .

  Therefore, the conventional semiconductor device has a problem that it is difficult to prevent malfunction and runaway due to an abnormal system clock.

  On the other hand, in recent years, a semiconductor device using two system clocks having different periods has been developed in response to a demand for power saving in a portable device such as a cellular phone. That is, when the power saving operation is performed, the second clock signal having a cycle 500 to 1000 times the normal time is used as the system clock.

By the way, in this case, that is, when operating with a clock signal having a long cycle, in the conventional system clock monitoring by the watchdog timer, in addition to the above-described problems, the time until an abnormality is detected becomes very long. There was also a problem of end up.
Japanese Patent Laid-Open No. 9-297698

  The present invention provides a semiconductor device capable of detecting an abnormality of an input clock signal.

  According to one aspect of the present invention, first and second clock signals having different periods that are not synchronized are input, and the number of clocks of the first clock signal is set for a predetermined period based on the second clock signal. Counting means for counting and outputting the count value, and determination for outputting an error signal indicating an abnormality in the first or second clock signal when the count value from the counting means is not within a predetermined range There is provided a semiconductor device comprising means.

  According to the present invention, it is possible to detect abnormality of two input clock signals.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a semiconductor device according to an embodiment of the present invention. Here, the part mainly related to the abnormality detection of the input clock signal is shown.

  The semiconductor device according to the embodiment of the present invention includes a counting unit 11 that counts a clock signal and outputs a count value (hereinafter referred to as “sc”), and an abnormality of the clock signal when sc is out of a predetermined range. The determination unit 12 outputs an error signal (hereinafter referred to as “err”).

  A 16 MHz clock signal (hereinafter referred to as “fc”) is input to the first input of the counting unit 11, and a 32 kHz clock signal (hereinafter referred to as “fs”) is input to the second input of the counting unit 11. , And the output of the counting unit 11 is supplied to the first input of the determination unit 12 as sc.

  The second input of the determination unit 12 is fs, and the output of the determination unit 12 is supplied to a circuit block (not shown) such as a CPU as err.

  The counting unit 11 counts the number of clocks of fc for each cycle of fs, and outputs the value to the determination unit 12 as 10-bit sc.

  The determination unit 12 compares sc from the counting unit 11 with a predetermined range, and if sc is within the predetermined range, “OK” is output as err, and if it does not, “NG” is output as “err”. "Is output.

  As shown in FIG. 1, the counting unit 11 includes a control circuit 13 that generates a control signal, a counter 14 and a counter 15 that counts up fc, and an output of the counter 14 (hereinafter referred to as “cnt1”) or a counter 15. Is selected (hereinafter referred to as “cnt2”) and is output as sc.

  Fs is input to the input of the control circuit 13, the first output of the control circuit 13 is supplied to the control input of the selector 16 as sel, and the second output of the control circuit 13 is supplied to the control input of the counter 14 as rst1. The third output of the control circuit 13 is supplied to the control input of the counter 15 as rst2.

  Fc is input to the input of the counter 14, and its output is connected to the first input of the selector 16 with a 10-bit width.

  Fc is input to the input of the counter 15, and its output is connected to the second input of the selector 16 with a 10-bit width.

  The output of the selector 16 is connected to the first input of the determination unit 12 with a 10-bit width as sc that is the output of the counting unit 11.

  The control circuit 13 generates signals rst1, rst2, and sel that control the counter 14, the counter 15, and the selector 16, and supplies them to the respective control inputs.

  FIG. 2 is a circuit diagram showing the control circuit 13 in the semiconductor device according to the embodiment of the present invention. Here, as an example, a circuit in the case where the duty ratio of fs is 1: 1 is shown.

  The control circuit 13 in the semiconductor device according to the embodiment of the present invention includes two data latches 21 and 22 (hereinafter referred to as “DL21 and DL22”) and an inverter 23 (hereinafter referred to as “INV23”). Yes.

  Fs is input to the clock input of DL21, and the output Q of DL21 is connected to the control input of the counter 15 as the input of INV23, the input D of DL22, and rst2.

  The output of INV23 is connected to the input D of DL21, fs is input to the clock input of DL22, and the output Q of DL22 is connected to the control input of the counter 14 as rst1.

  At the same time, the output Q of the DL 22 is connected to the control input of the selector 16 as sel.

  With such a configuration, the control circuit 13 generates a control signal rst2 obtained by dividing fs by 2, and control signals rst1 and sel obtained by inverting rst2. (Refer to FIGS. 4 to 6 to be described later for specific waveform examples.)

  The counter 14 is a binary counter circuit having a 10-bit configuration, and counts up the number of clocks of fc while rst1 is “L”.

  Therefore, the counter 14 sequentially outputs the counted 10-bit binary number as cnt1 every clock cycle of fc.

  The configuration and function of the counter 15 are the same as those of the counter 14. The difference from the counter 14 is that rst2 is input to the control input and its output cnt2 is connected to the second input of the selector 16.

  The selector 16 is composed of ten 2-input 1-output selection circuits. Each selection circuit selects and outputs the first input when the control input is “L”, and the control input is “H”. Sometimes the second input is selected and output.

  Sel is input to the control input of each selection circuit, each bit of cnt1 is connected to each first input, and each bit of cnt2 is connected to each second input.

  Further, the output of each selection circuit is connected to the first input of the determination unit 12 as each bit of sc.

  With such a configuration, the selector 16 selects cnt1 during the period when sel is “L” and outputs it to the determination unit 12, and selects cnt2 during the period when sel is “H” and outputs it to the determination unit 12. To do.

  As illustrated in FIG. 1, the determination unit 12 holds an upper limit register 17 that holds an upper limit value that indicates the upper limit of the normal range of sc, and a lower limit value that indicates the lower limit of the normal range of sc. The lower limit register 18, sc is provided with a comparator 19 that compares the upper limit value and the lower limit value, and a sampling circuit 20 that holds an output from the comparator 19 (hereinafter referred to as "cmp").

  The output of the upper limit register 17 is connected to the first input of the comparator 19, and the output of the lower limit register 18 is connected to the second input of the comparator 19. Further, sc from the counting unit 11 is input to the third input of the comparator 19, and the output (“cmp”) of the comparator 19 is connected to the data input of the sampling circuit 20.

  Fs is input to the clock input of the sampling circuit 20, and the output of the sampling circuit 20 is supplied to a circuit block (not shown) such as a CPU as err which is the output of the determination unit 12.

  The upper limit register 17 is composed of ten data latches, and their outputs are supplied to the first input of the comparator 19 as binary numbers having a 10-bit width. Although not shown in FIG. 1, the upper limit value is set in the upper limit value register 17 by the CPU. For example, “501” is set.

  The configuration and function of the lower limit register 18 are the same as those of the upper limit register 17. The difference from the upper limit register 17 is that the output is connected to the second input of the comparator 19 and the lower limit set by the CPU is, for example, “499”.

  The comparator 19 compares sc with the upper limit value and the lower limit value, and if sc is a value between the upper limit value and the lower limit value (more than the lower limit value and less than the upper limit value), it outputs “L” as cmp. Otherwise, “H” is output as cmp.

  The comparison is performed as a 10-bit binary number.

  As described above, sc, which is the output of the counting unit 11, is incremented every clock cycle of fc, so cmp also changes sequentially. (Refer to FIGS. 4 to 6 to be described later for specific waveform examples of sc and cmp.)

  The sampling circuit 20 latches cmp and holds it for one period of fs, and outputs err indicating whether or not sc is in a normal range. That is, if sc is between the upper limit value and the lower limit value at the rise of fs (more than the lower limit value and less than the upper limit value), err becomes “L” indicating “OK”, otherwise, err is “NG”. "H" indicating "".

  “NG” in err means that an abnormality such as a momentary interruption has occurred in fc or fs.

  FIG. 3 is a circuit diagram showing the sampling circuit 20 in the semiconductor device according to the embodiment of the present invention. Here, as an example, a configuration example using the data latch 24 (hereinafter referred to as “DL24”) is shown.

  The cmp is connected to the input D of the DL 24, fs is connected to the clock input of the DL 24, and err is connected to the output Q of the DL 24.

  With such a configuration, the sampling circuit 20 can latch cmp at the rising edge of fs, hold it for one period of fs, and continue to output it as err. (See FIGS. 4 to 6 to be described later for specific waveform examples of fs, cmp, and err.)

  Next, the operation of the semiconductor device having the above-described configuration will be described. Here, the operations related to the counting unit 11 and the determination unit 12 described above will be mainly described.

  First, a normal operation when there is no abnormality in the clock signals fc and fs will be described. FIG. 4 is a waveform diagram showing a normal operation of the semiconductor device according to the embodiment of the present invention.

  FIG. 4 shows three clocks of fs (time t0 to t3).

  Since fc, cnt1, cnt2, and sc have a minimum clock period of 1/500 of that of fs, such portions are indicated by vertical stripes.

  In addition, the notation “[0-9]” in cnt1, cnt2, and sc indicates that these are 10 bits wide.

  Further, numerical values with arrows on the top of cnt1 and cnt2 indicate the respective output values in decimal numbers.

  Furthermore, the time scale (horizontal direction in the drawing) of FIG. 4 is drawn by being appropriately expanded and contracted depending on the position in the horizontal direction for the sake of explanation. That is, for example, the ratio between the pulse width of fs and the pulse width of cmp in the figure does not reflect the actual ratio.

  However, the time (vertical direction in the drawing) is drawn with all the waveforms aligned.

  First, when fs rises at time t0, the control circuit 13 sets rst1 to “L” and sets rst2 and sel (not shown in FIG. 4) to “H”.

  Upon receiving this rst1, the counter 14 starts counting up fc. In response to rst2, the output cnt2 of the counter 15 is reset to “0”, and the value is held until time t1.

  The selector 16 receives the sel and selects its first input, that is, cnt1, until time t1, and outputs it as sc.

  The comparator 19 compares the input sc with the upper limit value (“501”) held in the upper limit value register 17 and the lower limit value (“499”) held in the lower limit value register 18, and compares the comparison result. Output as cmp.

  Since sc is smaller than the lower limit value for a while after the counter 14 starts counting up, cmp remains “H”.

  When the counter 14 counts up by fc and cnt1 reaches “499”, sc enters the normal range (more than the lower limit value and less than the upper limit value), so cmp transitions to “L”.

  When fs rises at time t1, first, the sampling circuit 20 latches and outputs “L” of cmp as err.

  At the same time, the control circuit 13 sets rst1 to “H”, and sets rst2 and sel (not shown in FIG. 4) to “L”.

  Upon receiving this rst1, the output cnt1 of the counter 14 is reset to “0”, and the value is held until time t2. In response to rst2, the counter 15 starts counting up fc.

  The selector 16 receives the sel and selects its second input, that is, cnt2 until time t2, and outputs it as sc.

  Therefore, sc is reset to “0” at this time, and cmp transitions to “H”. Here, since err is latched by the sampling circuit 20, it remains “L” regardless of the state of cmp.

  Since sc is smaller than the lower limit value for a while after the counter 15 starts counting up, cmp remains “H”.

  When the counter 15 counts up by fc and cnt2 reaches “499”, sc enters the normal range, so cmp transitions to “L”.

  When fs rises at time t2, the sampling circuit 20 latches and outputs “L” of cmp as err.

  At the same time, the control circuit 13 sets rst1 to “L”, sets rst2 and sel (not shown in FIG. 4) to “H”, and the counting unit 11 and the determination unit 12 are in the same state as the time t0. Return.

  In this way, if the ratio of the period of fc and fs is between 1: 499 and 1: 501, that is, the count value sc of fc by the counter 14 or the counter 15 is between 499 and 501 at the rise of fs. If it is, the counting unit 11 and the determination unit 12 repeat the above-described operation, and err continues to output “L” indicating “OK”.

  Next, the abnormality detection operation of the counting unit 11 and the determination unit 12 when an instantaneous interruption occurs in the clock signal fc will be described.

  FIG. 5 is a waveform diagram showing an operation for detecting an abnormality in fc in the semiconductor device according to the embodiment of the present invention. Here, as an example, a case will be described in which fc is momentarily interrupted between times t1 and t2.

  In addition, since the notation method etc. in a figure are the same as that of FIG. 4, description is abbreviate | omitted. Also, the operation at times t0 to t1 is the same as the normal operation of FIG.

  When fs rises at time t1, the counter 15 starts counting up as in FIG. Then, the same operation as in FIG. 4 proceeds until time t2.

  However, as shown in FIG. 5, since there is an instantaneous interruption in fc between times t1 and t2, when the time t2 is reached, the counter 15 counts up to “300” only. It is.

  Therefore, at this time, the output cmp of the comparator 19 is still “H”.

  In FIG. 5, in the waveforms of cnt2 [0-9] and sc [0-9], white portions at times t1 to t2 indicate that the count-up by fc is stopped.

  Next, at the rise of fs at time t2, the sampling circuit 20 latches and outputs “H” of cmp. That is, err becomes “H” indicating “NG” at the next rising edge of fs after a momentary break in fc, and the CPU or the like that receives err can detect an abnormality.

  At time t2, the control circuit 13 sets rst1 to “L”, sets rst2 and sel (not shown in FIG. 5) to “H”, excludes err, and determines the counting unit 11 and the determination. The unit 12 returns to the same state as the time t0, and the counter 14 starts counting up.

  The operation from time t2 to t3 is the same as the operation from time t0 to t1 except for err. When cnt1 that is the output of the counter 14 reaches “499”, cmp transitions to “L”.

  During this time, err is held at “H” by the sampling circuit 20.

  When fs rises at time t3, as in the operation at time t1, the sampling circuit 20 latches “L” of cmp, resets err, and err returns to “L” indicating “OK”. .

  In this way, the counting unit 11 and the determination unit 12 return to the same state as at the time t1.

  Next, an abnormality detection operation of the counting unit 11 and the determination unit 12 when an instantaneous interruption occurs in the clock signal fs will be described.

  FIG. 6 is a waveform diagram showing an operation for detecting an abnormality in fs in the semiconductor device according to the embodiment of the present invention. Here, as an example, a case where fs is momentarily interrupted between times t1 and t2 will be described.

  Note that the notation and the like in the figure are the same as those in FIG. Also, the operation at times t0 to t1 is the same as the normal operation of FIG.

  In FIG. 6, since fs is interrupted, fs does not rise even at time t1. Therefore, the states of rst1, rst2, and sel (not shown in FIG. 6) do not change, the counter 14 continues to count up, and the selector 16 also continues to select cnt1.

  When cnt1 which is the output of the counter 14 reaches “501”, sc reaches the upper limit value, so cmp transitions to “H”.

  Then, at the rise of fs at time t2, the sampling circuit 20 latches and outputs “H” of cmp. That is, err becomes “H” indicating “NG” at the next rise of fs in which an instantaneous interruption occurs, and the CPU or the like that receives err can detect an abnormality.

  At the same time, at time t2, the control circuit 13 sets rst1 to “H”, sets rst2 and sel (not shown in FIG. 6) to “L”, and except for err, the counting unit 11 and the determination The unit 12 returns to the same state as the time t1 in FIG. 4, and the count up of the counter 15 is started.

  The operation from time t2 to t3 is the same as the operation from time t1 to t2 in FIG. 4 except for err. When cnt2 that is the output of the counter 15 reaches “499”, cmp changes to “L”. .

  During this time, err is held at “H” by the sampling circuit 20.

  When fs rises at time t3, as in the operation at time t2 in FIG. 4, the sampling circuit 20 latches “L” of cmp, resets err, and err is “L” indicating “OK”. Return to.

  In this way, the counting unit 11 and the determination unit 12 return to the same state as at time t2 in FIG.

  According to the above embodiment, since the ratio of the periods is monitored using the two input clock signals fc and fs having different periods, the abnormality of fc or fs can be detected without using the control of the CPU software. A semiconductor device to be detected can be realized.

  Further, since the abnormality is detected at the rise of fs immediately after an abnormality such as a momentary interruption occurs in fc or fs, the time required for detecting the abnormality of the clock signal can be greatly reduced.

  Furthermore, according to the above-described embodiment, the normal range of the cycle ratio of fc and fs is defined by the upper limit value and the lower limit value set in advance in the upper limit value register 17 and the lower limit value register 18, so that the cycle of fc and fs The abnormality can be detected both when the ratio is smaller than the normal range and when the period ratio of fc and fs is larger than the normal range.

  That is, the abnormality can be detected not only when the cycle of fc or fs becomes longer due to a momentary interruption or the like, but also when the cycle of fc or fs becomes shorter due to unexpected multiple transmission or the like.

  In the above-described embodiment, fc is 16 MHz and fs is 32 KHz. However, the present invention is not limited to this. In principle, any frequency can be used as long as the periods of fc and fs are different. Is possible.

  Also, even if fc and fs have the same frequency, if they are asynchronous clock signals, for example, the present invention can be applied by dividing fs by a predetermined number of times.

  Further, in the above-described embodiment, the counter 14 and the counter 15 are 10-bit binary counter circuits, and the upper limit register 17 and the lower limit register 18 are configured by 10 data latches. It is not limited to.

  Further, although cnt1, cnt2, sc, the upper limit value, and the lower limit value are 10-bit binary numbers, the present invention is not limited to this.

  Furthermore, in the above-described embodiment, the normal range of the count value sc is “more than the lower limit value and less than the upper limit value”, but the present invention is not limited to this. The following may be used.

  Further, in the above-described embodiment, the duty ratio of fs is 1: 1, but the present invention is not limited to this. For example, a signal with a duty ratio of 1: 1 is obtained by dividing fs. It may be generated and used.

  Further, in the above-described embodiment, the control circuit 13 and the sampling circuit 20 are mainly configured by the data latch. However, the present invention is not limited to this, and is implemented using another circuit configuration having an equivalent function. You may do it.

  Furthermore, in the above-described embodiments, for the sake of explanation, the control signal and the like are positive logic, that is, active at “H” and inactive at “L”, but the present invention is not limited to this. For example, the circuit can be configured with negative logic.

1 is a circuit block diagram showing a semiconductor device according to an embodiment of the present invention. The circuit diagram which shows the control circuit in the semiconductor device concerning the Example of this invention. The circuit diagram which shows the sampling circuit in the semiconductor device concerning the Example of this invention. The wave form diagram which shows the normal operation | movement of the semiconductor device concerning the Example of this invention. The wave form diagram which shows the operation | movement which detects abnormality of fc in the semiconductor device concerning the Example of this invention. The wave form diagram which shows the operation | movement which detects abnormality of fs in the semiconductor device concerning the Example of this invention.

Explanation of symbols

11 Counting unit 12 Determination unit 13 Control circuit 14, 15 Counter 16 Selector 17 Upper limit register 18 Lower limit register 19 Comparator 20 Sampling circuit

Claims (3)

First and second clock signals having different periods that are not synchronized are input, the number of clocks of the first clock signal is counted for a predetermined period based on the second clock signal, and the count value is output. Counting means;
A semiconductor device comprising: determination means for outputting an error signal indicating an abnormality of the first or second clock signal when the count value from the counting means is not within a predetermined range. The determination means includes
First storage means for holding an upper limit value indicating the upper limit of the predetermined range;
Second storage means holding a lower limit value indicating the lower limit of the predetermined range;
The values held in the first and second storage means are compared with the count value output from the counting means, and when the count value is between the upper limit value and the lower limit value, “OK” Comparing means for outputting "NG" otherwise, indicating "NG",
2. The semiconductor device according to claim 1, further comprising third storage means for holding the output of the comparison means at a predetermined timing for one period based on the second clock signal. The counting means includes
A first control signal that periodically and alternately repeats the first and second states based on the second clock signal; and second and third control signals that are inverted signals of the first control signal; Control means for generating and outputting
A first counter that counts up and outputs the first clock signal when the first control signal is in the first state;
A second counter for counting up and outputting the first clock signal when the second control signal is in the first state;
When the third control signal is in the first state, the output from the second counter is selected, and when the third control signal is in the second state, from the first counter The semiconductor device according to claim 1, further comprising a selector that selects the output of the output and outputs the output as a counter value.

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