JP2006024718A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with STI that is structured not to cause transistor characteristics to deteriorate, and to provide a manufacturing method therefor. <P>SOLUTION: The semiconductor device comprises an Si substrate 1 having a trench isolation structure which is formed on an isolation region where a main surface is divided into a plurality of element regions A1 to A3, wherein an epitaxial layer is selectively grown on the element regions A2, A3. The semiconductor device comprises a first n-type MOS transistor having a channel region formed on the element region A1; and a second n channel MOS transistor, and a p channel MOS transistor having a channel region formed on the epitaxial layer. The channel length direction size of the epitaxial layer, where the channel region of the second n channel type MOS transistor is formed, is smaller than the channel lengthwise direction size of the element region A1, where the first n channel MOS transistor channel region is formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having an element isolation structure and a method for manufacturing the same.

  In a conventional semiconductor integrated circuit device, a LOCOS (Local Oxidation of Silicon) structure is formed on the substrate surface in order to electrically isolate transistor elements from each other. However, from the generation of LSI with a design rule of 0.25 to 0.18 μm, in order to achieve a higher degree of integration, a shallow groove of about 0.3 μm is formed on the substrate surface, and the inside of the groove is an insulator. Trench isolation (STI) technology has been used.

Patent Document 1 discloses a semiconductor device in which element isolation is performed by STI. Non-Patent Document 1 reports the electrical characteristics of a MOS transistor having a channel region in an element region separated by STI.
JP 2000-82808 A European Solid-State Device Research, 2003.ESSDERC '03 .33rd Conference on, 16-18 Sept. 2003, Pages: 359-362

  As the degree of integration of transistors in a semiconductor device is improved and the size of each element region is reduced, stress (compressive stress) due to STI has become a problem.

FIG. 8 schematically shows stress generated in the element region of the Si substrate 100 on which the STI 102 is formed. The reason why such stress occurs is that the inside of the trench formed on the surface of the Si substrate 100 is buried with an insulator such as SiO ₂ , and there is a difference in thermal expansion coefficient between this insulator and Si. This is because it exists.

  Non-Patent Document 1 describes the influence of stress due to STI on the characteristics of MOS transistors. FIG. 9 is a graph disclosed in Non-Patent Document 1, and shows how the drain current Id changes depending on the parameter a that defines the channel length direction of the element region. Here, the “parameter a” shown on the horizontal axis of the graph is the size shown in FIG. 10, and the unit is [μm (micrometer: micron)]. 9 indicates the ratio of the drain current Id to the drain current Id (a = 10 μm) when the parameter a shown in FIG. 10 is 10 μm. Note that the “channel length direction” in this specification means a direction that defines the distance between the source region S and the drain region D, as shown in FIG. It shall mean the size in that direction. The size of the element region shown in FIG. 10 in the channel length direction is equal to “channel length + 2 · a”. The “channel length” is equal to the size (gate length) of the gate G in the channel length direction.

  As is clear from FIG. 9, in the region where the size of the parameter a is 5 μm or less, the characteristics of the N-channel MOS transistor (nMOS) are greatly deteriorated as the parameter a is reduced. This is presumably because the field effect mobility of electrons decreases due to stress (compressive stress) caused by STI.

  As described above, in the case of the conventional semiconductor device using the STI structure for element isolation, the characteristics of the N-channel type MOS transistor are greatly deteriorated as the integration degree of the MOS transistor element is further improved and the size of the element region is reduced. It has become a problem to do.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a structure that does not cause deterioration of transistor characteristics even when the STI technique is used for element isolation, and a method for manufacturing the same. There is to do.

  The semiconductor device of the present invention includes a substrate having a semiconductor layer having a main surface, and having a trench isolation structure formed in an isolation region that divides the main surface into a plurality of element regions, and the plurality of the main surfaces of the semiconductor layer. And an epitaxial layer selectively grown on at least one of the element regions, wherein a channel region formed in any of the plurality of element regions on the main surface of the semiconductor layer is provided. A first N-channel MOS transistor having a second N-channel MOS transistor having a channel region formed in the epitaxial layer, one of the plurality of element regions in a main surface of the semiconductor layer, or the A P-channel MOS transistor having a channel region formed in the epitaxial layer, and the second N-channel type Channel length direction size of the epitaxial layer in which a channel region of the OS transistor is formed is smaller than the channel length direction size of the first N-channel device region where a channel region is formed of MOS transistors.

  In a preferred embodiment, the channel length direction size of the epitaxial layer in which the channel region of the second N-channel MOS transistor is formed is 10 μm or less.

  In a preferred embodiment, a channel length direction size of an element region in which a channel region of the first N-channel MOS transistor is formed exceeds 10 μm.

  In a preferred embodiment, a P-channel MOS transistor having a channel region in an element region having a size in the channel length direction of 10 μm or less among the plurality of element regions in the main surface of the semiconductor layer is provided.

  In a preferred embodiment, the trench isolation structure applies a compressive stress in a lateral direction to the element region in the semiconductor layer.

  In a preferred embodiment, the semiconductor layer is made of single crystal silicon.

  In a preferred embodiment, the epitaxial layer includes a layer containing silicon and germanium.

  In a preferred embodiment, the epitaxial layer has a thickness of 1 nm to 100 nm.

  The method for manufacturing a semiconductor device according to the present invention includes a step (A) of preparing a substrate having a semiconductor layer having a main surface, and a separation groove for dividing the main surface of the semiconductor layer into a plurality of element regions. A step (B) of forming on the main surface, a step (C) of forming an STI by filling the isolation groove of the semiconductor layer with an insulator, and some elements included in a plurality of element regions of the semiconductor layer A step (D) of growing an epitaxial layer on the region, and a step (E) of forming a MOS transistor having a channel region in one of the plurality of element regions on the main surface of the semiconductor layer or the epitaxial layer. The step (E) includes a step (e1) of forming a first N-channel MOS transistor having a channel region in any of the plurality of element regions in the main surface of the semiconductor layer. A step (e2) of forming a second N-channel MOS transistor having a channel region in the epitaxial layer, and a channel region in any one of the plurality of element regions in the main surface of the semiconductor layer, or in the epitaxial layer A step (e3) of forming a P-channel MOS transistor having a channel length direction size of an epitaxial layer in which a channel region of the second N-channel MOS transistor is formed is the first N-channel type It is smaller than the channel length direction size of the element region in which the channel region of the MOS transistor is formed.

  Although the present invention is an element isolation technique suitable for improving the degree of integration, it is possible to effectively reduce the characteristics of an N-channel MOS transistor by using a technique that relieves stress while employing STI that generates stress. A semiconductor device that avoids the problem is provided.

  The inventors of the present invention selectively epitaxially grow a semiconductor layer including a SiGe layer in a specific region of a Si substrate, thereby performing a normal Si MOS transistor (Si element) and a SiGe MOS transistor (SiGe) on one Si substrate. The development of a semiconductor device in which an element is mixedly mounted has been studied. When the epitaxial layer including the SiGe layer is selectively grown on the element region of the Si substrate, the characteristics of the MOS transistor in which the channel region is formed in the epitaxial layer are reduced even if the epitaxial layer has a smaller channel length direction size. The inventors have found that it is difficult to deteriorate and have come up with the present invention. This is considered to be because even when stress due to STI is applied to the element region of the Si substrate, the stress is released in the epitaxial layer grown thereon.

FIG. 1 is a cross-sectional view schematically showing a state in which stress is released in an epitaxial layer 103 formed by selective growth. Since the STI 102 in which an insulator made of SiO ₂ or the like is embedded is formed inside the trench formed on the surface of the Si substrate 100, compressive stress is generated in the element region of the Si substrate 100. The stress of the epitaxial layer 103 selectively grown on the element region of the substrate 100 is relaxed. Such stress relaxation occurs regardless of the type and composition of the semiconductor constituting the epitaxial layer 103. The degree of stress relaxation is considered to vary depending on the structure (composition and thickness) of the epitaxial layer 103 to be grown.

  In the present invention, not all of the N-channel MOS transistors whose characteristics are likely to deteriorate due to the stress are formed in the epitaxial layer 103, but are formed by appropriately distributing the element region and the epitaxial layer 103 in the Si substrate 100. Yes. This is because in the element region having a relatively large size, attention has been paid to the fact that the characteristics of the N-channel MOS transistor are hardly deteriorated even when there is stress.

  Note that by forming an N-channel MOS transistor on the surface of the Si substrate 100 instead of the epitaxial layer 103, variations in element characteristics due to variations in the thickness of the epitaxial layer 103 are less likely to occur. When the influence of the stress due to the STI 102 becomes larger than the influence due to the variation in the thickness of the epitaxial layer 103, it is more preferable to form the N-channel MOS transistor on the epitaxial layer 103 than on the surface of the Si substrate 100. preferable. The present invention can optimize the formation region of the N-channel MOS transistor in consideration of the influence of stress due to the STI 102.

  Hereinafter, preferred embodiments of the present invention will be described.

[Embodiment 1]
A first embodiment of the present invention will be described with reference to the drawings.

  First, refer to FIGS. 2 (a) and 2 (b). FIG. 2A shows a partial cross section of the semiconductor device according to this embodiment, and FIG. 2B shows the top surface thereof.

  The semiconductor device of this embodiment includes a Si substrate 200 having a plurality of element regions formed on the main surface, and an epitaxial layer 203 is formed on a part of the Si substrate 200. In the example shown in FIG. 2A, the epitaxial 203 has a three-layer structure. In the Si substrate 200, STI 202 is formed in a region (isolation region) other than the element region.

  FIG. 2 shows three element regions A1 to A3. The element region A1 includes an N-channel MOS transistor (first N-channel MOS transistor) 206 having a channel region in the element region of the Si substrate 200. Is formed.

  On the other hand, an epitaxial layer 203 having a thickness of, for example, 1 nm to 100 nm is selectively grown on the element regions A2 and A3. A P-channel MOS transistor 208 is formed in the epitaxial layer 203 grown on the element region A2, and an N-channel MOS transistor (second N-channel MOS transistor) 210 is formed in the epitaxial layer 203 grown on the element region A3. Is formed.

  The size in the channel length direction of the epitaxial layer 203 in which the channel region of the second N-channel MOS transistor 210 is formed is the channel length of the element region A1 in which the channel region of the first N-channel MOS transistor 206 is formed. Smaller than the direction size. Specifically, the channel length direction size of the element region A1 exceeds 10 μm, but the channel length direction size of the epitaxial layer in which the channel region of the second N-channel MOS transistor 210 is formed is 10 μm or less (for example, 1.5 μm).

  As described above, in this embodiment, the plurality of N-channel MOS transistors 206 and 210 are distributed and formed into the element region A1 and the epitaxial layer 203 of the Si substrate 200 according to the size.

  Note that if the size of the element region in the channel length direction is 2 μm or more, the stress due to the STI 202 is somewhat reduced, so an N-channel MOS transistor may be formed in the element region of the Si substrate 200 in some cases. However, it is preferable to form the N-channel MOS transistor in the element region of the Si substrate 200 when the size of the element region in the channel length direction is 10 μm or more.

  On the other hand, when the size of the element region in the channel length direction is less than 10 μm, it is preferable to form an N-channel MOS transistor in the epitaxial layer 203. In particular, when the size of the element region in the channel length direction is less than 2 μm, the effect obtained by forming the N-channel MOS transistor in the epitaxial layer 203 becomes remarkable.

  The P-channel MOS transistor can be formed in any one of the element region of the Si substrate 200 or the epitaxial layer 203 regardless of the size of the element region in the channel length direction. Although not shown in FIG. 2, a P-channel MOS transistor may be formed in the element region of the Si substrate 200. Since the characteristics of the P-channel MOS transistor may be improved by applying stress, the P-channel type transistor is directly formed in the element region without growing the epitaxial layer 203 in the element region whose size in the channel length direction is less than 10 μm. A MOS transistor may be formed. In the case of forming a P-channel MOS transistor, the size of the element region in the channel length direction is preferably as small as possible, for example, less than 2 μm.

  An epitaxial layer may be grown on a relatively large element region having a channel length direction size of 10 μm or more.

  Hereinafter, with reference to FIGS. 3 to 6, a preferred embodiment of the method of manufacturing the semiconductor device of the present embodiment will be described.

First, as shown in FIG. 3A, the surface of the Si substrate 1 is thermally oxidized at about 1000 to 1100 ° C. to form a protective oxide layer (SiO ₂ layer) 2 having a thickness of about 20 to 30 nm. The Si substrate 1 is typically a single crystal Si wafer, but may be an SOI substrate. Next, a polysilicon layer 3 having a thickness of about 50 nm is deposited on the protective oxide layer 2 by the CVD method, and then a SiN layer 4 having a thickness of about 150 nm is deposited on the polysilicon layer 3 by the CVD method. The deposition temperature of the SiN layer 4 is about 700 to 800 ° C. Thereafter, a resist mask that defines the pattern of the element regions A1, A2, and A3 is formed on the SiN layer 4 by lithography.

The SiN layer 4, the polysilicon layer 3, and the protective oxide layer 2 are patterned by etching a portion of the laminated structure that is not covered with the resist mask. This etching is preferably performed by a highly anisotropic dry etching method. As a dry etching gas, CF ₄ and CHF ₃ can be used for etching the SiN layer 4 and the protective oxide layer 2. Further, a gas such as Cl ₂ or HBr can be used for etching the polysilicon layer 3. By this dry etching, the main surface of the Si substrate 1 is partially exposed. Thereafter, the exposed portion of the Si substrate 1 is etched to form element isolation grooves (trench) 5 shown in FIG. 3B on the surface of the Si substrate 1. Etching of Si can be performed by dry etching using a gas such as Cl ₂ or HBr. The depth of the element isolation trench 5 is set within a range of 250 to 350 nm, for example.

  FIG. 4A is a drawing showing the upper surface of the Si substrate 1 at this stage. FIG. 4B is a cross-sectional view taken along the line B-B ′, and corresponds to FIG.

  Next, the Si surface exposed inside the element isolation trench 5 is thermally oxidized at about 1000 to 1100 ° C. to form a protective oxide layer 6 having a thickness of about 20 to 30 nm as shown in FIG. Thereafter, the inside of the element isolation trench 5 is filled with the Si oxide film 7 as shown in FIG. 3D by a high density plasma (HDP) method. The thickness of the deposited Si oxide film 7 is set to a value sufficiently larger than the depth of the element isolation trench 5, for example, a value in the range of 500 to 800 nm.

  Next, surface polishing by CMP is performed. This polishing is performed until the SiN layer 4 is exposed as shown in FIG. At the stage where this polishing is completed, the upper surface of the insulator formed on the Si substrate 1 is flattened, and the flat upper surface is formed from the polished surface of the Si oxide film 7 and the SiN layer 4. It is divided into areas formed from A region formed from the polished surface of the Si oxide film 7 is located on the element isolation trench 5, and a region formed from the SiN layer 4 is located on the element regions A1, A2, and A3.

  Next, after removing the SiN layer 4 using hot concentrated phosphoric acid, the polysilicon layer 3 is removed using hydrofluoric acid. Thereafter, the protective oxide layer 2 is removed using hydrofluoric acid. By this etching, the protective oxide layer 2 on the element regions A1, A2, and A3 is etched, and the upper portion of the Si oxide film 7 filling the element isolation trench 5 is also partially etched. By this etching, as shown in FIG. 3F, the upper surfaces (Si surfaces) of the element regions A1, A2, and A3 on the main surface of the Si substrate 1 are exposed.

  Next, the well 8 is formed in the element region by ion implantation. Of the well 8, ions of As (arsenic) and P (phosphorus) are implanted into the n-type well, and ions of B (boron) are implanted into the p-type well.

Thereafter, as shown in FIG. 5A, a selective growth mask material layer 9 having a thickness of about 10 to 30 nm is deposited. The selective growth mask material layer 9 is formed of, for example, a SiN or SiO ₂ film or a laminated film thereof. Next, as shown in FIG. 5B, the selective growth mask 10 is fabricated by patterning the selective growth mask material layer 9. This patterning is performed by lithography and etching techniques, but the etching is preferably performed by wet etching using a chemical solution. As the chemical solution, hot concentrated phosphoric acid can be used when the selective growth mask material layer 9 is made of SiN, and hydrofluoric acid is used when the selective growth mask material layer 9 is made of SiO _2. Can do. Note that a thermal oxide film having a thickness of about 5 nm may be formed on the exposed Si surface before the selective growth mask material layer 9 is formed.

  As shown in FIG. 5B, the opening of the selective growth mask 10 defines a region where a layer containing SiGe should be epitaxially grown. That is, the opening of the selective growth mask 10 is formed so as to include the element regions A2 and A3, and the element region A1 in which the Si element is formed is covered with the selective growth mask 10. The epitaxial growth of the layer containing SiGe does not occur on the selective growth mask 10 but occurs selectively on the surface of the element regions A2 and A3 located in the opening of the selective growth mask 10.

Next, as shown in FIG. 5C, the Si buffer layer 11 having a thickness of about 2 to 5 nm and a thickness of about 5 to 15 nm are formed only in the opening of the selective growth mask 10 by using the UHV-VCD method. The SiGe channel layer 12 and the Si cap layer 13 having a thickness of about 2 to 5 nm are sequentially grown. The growth temperature is set to about 500 to 600 ° C., and GeH ₄ and Si ₂ H ₆ are used as source gases. HCl gas may be added to increase the selectivity during crystal growth. As described above, in the present embodiment, a stacked structure including the Si layer and the SiGe layer is formed as the layer containing SiGe. A desired strain can be formed by adjusting the composition ratio of Ge in the SiGe layer. Carbon may be added to the SiGe layer.

  If the channel region of the MOS transistor is formed in the SiGe layer, the hole mobility can be improved about twice as compared with the case where the channel region is formed in the conventional silicon layer. In addition, when the channel region is formed in the strained Si layer, the electron mobility is improved by about 2.2 times and the hole mobility is improved by about 1.4 times compared with the case where the channel region is formed in the conventional silicon layer. Is feasible. Such a strained Si layer is obtained by growing a Si layer on a lattice-relaxed SiGe layer. Since SiGe has a slightly larger lattice spacing than Si (the lattice constant of the SiGe layer having a Ge composition of 30% is about 1% larger than the lattice constant of the silicon layer), it is pulled by the Si grown on SiGe. Distortion will occur.

When producing a MOS transistor having high mobility in the epitaxial layer, the Ge composition of SiGe is preferably set to about 15 to 50%. This is because if the Ge composition is lower than this range, the effect of improving the hole mobility is small, and if it is higher than this range, lattice relaxation tends to occur, which is not preferable. Next, as shown in FIG. 5D, the selective growth mask 10 is removed by wet etching. As the chemical solution for the wet etching, the same type of chemical solution as that used for patterning the selective growth mask 10 can be used. After the surface cleaning, the gate insulating film 14 is formed as shown in FIG. The gate insulating film 14 can be formed by thermally oxidizing the surface of the element region A1 and the epitaxial layer in a temperature range of 750 to 1050 ° C., or depositing an insulating film by another method. At this time, it is preferable to form the gate insulating film 14 at a relatively low temperature because generation of lattice relaxation due to lattice mismatch between Si and SiGe can be suppressed. Therefore, it is preferable to form the gate insulating film 14 in the range of 750 to 900 ° C. As the gate insulating film 14, a SiO ₂ film, a SiON film, or a laminated structure thereof is used. A high dielectric material such as ZrO ₂ or HfO ₂ may be used.

  Next, after a polysilicon layer is deposited to a thickness of about 150 to 250 nm using the CVD method, a gate electrode 15 is formed by lithography and dry etching, as shown in FIG. The patterning of the polysilicon can be performed by dry etching using an etching gas such as chlorine or hydrogen bromide.

  Next, a relatively low dose of impurity ion implantation is performed using the gate electrode 15 as an implantation mask, thereby forming an LDD (Lightly Doped Drain) 16 shown in FIG. 6B. Next, as shown in FIG. 6C, after the sidewall 17 is formed on the side wall of the gate electrode 15, an n-type source is formed in the semiconductor in the element region A1 and in the epitaxial layer grown on the element region A3. -Drain 18 is formed. At this time, the epitaxial layer grown on the element region A2 is covered with a resist mask or the like to prevent n-type impurity implantation. Thereafter, the p-type source / drain 18 is formed in the epitaxial layer grown on the element region A2.

The sidewall 17 is produced by depositing a SiO ₂ film, a SiN layer, or a laminated film thereof, and then etching the entire surface by dry etching with high anisotropy.

  Next, in order to lower the resistance of the gate electrode 15 and the source / drain 18 made of polysilicon, the surface of the gate electrode 15 and the surface of the source / drain 18 are silicided, and a silicide layer 19 is formed as shown in FIG. Form. The silicide layer 19 is preferably Co silicide, Ti silicide, Ni silicide, or the like.

Thereafter, as shown in FIG. 6E, an interlayer insulating film 20 is deposited by a CVD method. SiO ₂ can be used as the material of the interlayer insulating film 20. In order to lower the dielectric constant of the interlayer insulating film 20, fluorine may be added to SiO ₂ . Thereafter, contact holes are formed in the interlayer insulating film 20 using dry etching, and the formed contact holes are filled with metal to form plugs 21. When W (tungsten) is used as the material of the plug 21, it is easy to fill the contact hole by the CVD method. Further, after depositing an aluminum layer having a thickness of about 500 to 700 nm on the interlayer insulating film 20 by sputtering, the aluminum layer is patterned to form the wiring 22 made of aluminum.

  By the above method, a semiconductor device in which a Si element and a SiGe element are mixedly mounted on the same substrate can be manufactured. In particular, in this embodiment, as the SiGe element, a P-channel MOS transistor is formed in the epitaxial layer on the element region A2, and an N-channel MOS transistor is formed in the epitaxial layer on the element region A3. Further, an N-channel MOS transistor is formed in the relatively large element region A1 shown in the drawing.

  As described above, the channel length direction size of the element region A1 in this embodiment is larger than the channel length direction sizes of the element regions A2 and A3, and is 10 μm or more. The size in the channel length direction of the epitaxial layer grown on the element regions A2 and A3 in the present embodiment is in the range of 0.5 to 2 μm. Thus, in the small element region A3 having a channel length direction size of 2 μm or less, the channel region of the N-channel MOS transistor is not formed on the surface of the Si substrate 1, but is formed in the epitaxial layer on the element region A3. On the other hand, the channel region of the N-channel MOS transistor is formed on the surface of the Si substrate 1 in the relatively large element region A1 whose channel length direction size is 10 μm or more.

  Whether the channel region of the N-channel MOS transistor is formed on the Si substrate 1 or the epitaxial layer grown thereon is determined according to the size of the element region (channel length direction size). The

  When the channel region of the N-channel MOS transistor is formed in an element region surrounded by STI, when the size of the element region in the channel length direction becomes 10 μm or less, the characteristics of the N-channel MOS transistor are reduced as the size is reduced. It starts to deteriorate and deteriorates rapidly when it becomes 2 μm or less. On the other hand, when a channel region is formed in an epitaxial layer grown on a small element region, even if the size of the epitaxial layer in the channel length direction is 2 μm or less, the characteristics of the N-channel MOS transistor hardly deteriorate.

  On the other hand, when a P-channel MOS transistor is formed in an element region surrounded by STI, the characteristics of the P-channel MOS transistor deteriorate even when the size of the element region in the channel length direction is 10 μm or less. Rather, it gets better. For this reason, the channel region of the P-channel MOS transistor may be formed in the Si substrate 1 regardless of the size of the element region, or may be formed in an epitaxial layer grown thereon. In the case of a small-sized P-channel MOS transistor, it is preferable to form the channel region directly in the element region of the Si substrate 1 rather than forming the channel region in the epitaxial layer having a small size in the channel length direction.

[Other Embodiments]
Next, another embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 7 (a) and 7 (b). FIGS. 7A and 7B have the same configuration as that of the semiconductor device in the first embodiment, except that the configuration of the epitaxial layer is different.

  First, refer to FIG. In the example shown in this figure, the epitaxial layer 703 in which the N-channel MOS transistor 708 is formed has a single-layer structure of Si, but the epitaxial layer 705 in which the P-channel MOS transistor 711 is formed is , Si layer, SiGe layer, and Si layer. An N-channel MOS transistor 700 is formed on the element region of the Si substrate 1. On the other hand, in the semiconductor device shown in FIG. 7B, each of the epitaxial layers 703 and 705 has a single layer structure made of a Si layer. Instead of forming the Si epitaxial layers 703 and 705 as shown in FIG. 7B, a SiGe single layer epitaxial layer having a high carrier mobility may be formed. By forming the channel region in the SiGe layer having high carrier mobility, the transistor performance can be improved as compared with the case where the channel region is formed in the Si layer or the Si substrate.

  Thus, in the semiconductor device according to the present invention, the configuration of the epitaxial layer formed by selective growth is arbitrary.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device by which the characteristic degradation resulting from the stress which becomes a problem with the semiconductor device which has STI was suppressed is provided.

It is sectional drawing which shows the stress relief | release in the semiconductor device of this invention. (A) is a partial cross section figure of the semiconductor device in the 1st Embodiment of this invention, (b) is a figure which shows the upper surface. (A) to (f) are process cross-sectional views illustrating an embodiment of a method of manufacturing a semiconductor device according to the present invention. (A) is a top view which shows the example of arrangement | positioning of element area | region A1, A2, A3, (b) is the B-B 'sectional view taken on the line. (A) to (e) are process cross-sectional views illustrating an embodiment of a method of manufacturing a semiconductor device according to the present invention. (A) to (e) are process cross-sectional views illustrating an embodiment of a method of manufacturing a semiconductor device according to the present invention. (A) is sectional drawing which shows other embodiment of the semiconductor device by this invention, (b) is sectional drawing which shows other embodiment. It is sectional drawing which shows the stress in the conventional semiconductor device. It is a graph which shows the relationship between the parameter a which prescribes | regulates the channel length direction size of the element area | region enclosed by STI, and drain current. FIG. 5 is a plan layout diagram of a MOS transistor in which a parameter a that defines the channel length direction size of an element region is shown.

Explanation of symbols

A1 Element region A2 Element region A3 Element region 1 Si substrate 2 Protective oxide layer (SiO ₂ layer)
3 Polysilicon layer 3
4 SiN layer 5 Element isolation trench (trench)
6 Protective oxide layer 7 Si oxide film 9 Mask material layer for selective growth 10 Mask for selective growth 11 Si buffer layer 12 SiGe channel layer 13 Si cap layer 14 Gate insulating film 15 Gate electrode 16 LDD
17 Side wall 18 Source / drain 19 Silicide layer 20 Interlayer insulating film 21 Plug 22 Wiring

Claims (9)

A substrate having a semiconductor layer having a main surface, and having a trench isolation structure formed in an isolation region that divides the main surface into a plurality of element regions;
An epitaxial layer selectively grown on at least one element region of the plurality of element regions in the main surface of the semiconductor layer;
A semiconductor device comprising:
A first N-channel MOS transistor having a channel region formed in any of the plurality of element regions in the main surface of the semiconductor layer;
A second N-channel MOS transistor having a channel region formed in the epitaxial layer;
A P-channel MOS transistor having a channel region formed in any one of the plurality of element regions in the main surface of the semiconductor layer or in the epitaxial layer;
With
The channel length direction size of the epitaxial layer in which the channel region of the second N-channel MOS transistor is formed is the channel length direction size of the element region in which the channel region of the first N-channel MOS transistor is formed. Smaller than a semiconductor device.   2. The semiconductor device according to claim 1, wherein a channel length direction size of an epitaxial layer in which a channel region of the second N-channel MOS transistor is formed is 10 μm or less.   3. The semiconductor device according to claim 1, wherein a size in a channel length direction of an element region in which a channel region of the first N-channel MOS transistor is formed exceeds 10 μm.   4. The device according to claim 1, comprising a P-channel MOS transistor having a channel region in an element region having a channel length direction size of 10 μm or less among the plurality of element regions in the main surface of the semiconductor layer. The semiconductor device described.   The semiconductor device according to claim 1, wherein the trench isolation structure applies a compressive stress in a lateral direction to the element region in the semiconductor layer.   The semiconductor device according to claim 1, wherein the semiconductor layer is made of single crystal silicon.   The semiconductor device according to claim 1, wherein the epitaxial layer includes a layer containing silicon and germanium.   The semiconductor device according to claim 1, wherein a thickness of the epitaxial layer is not less than 1 nm and not more than 100 nm. Preparing a substrate including a semiconductor layer having a main surface (A);
Forming a separation groove in the main surface of the semiconductor layer for dividing the main surface of the semiconductor layer into a plurality of element regions;
A step (C) of forming an STI by filling the isolation groove of the semiconductor layer with an insulator;
A step (D) of growing an epitaxial layer on a part of element regions included in a plurality of element regions of the semiconductor layer;
Forming a MOS transistor having a channel region in any one of the plurality of element regions on the main surface of the semiconductor layer or in the epitaxial layer, and (E),
The step (E)
Forming a first N-channel MOS transistor having a channel region in any of the plurality of element regions in the main surface of the semiconductor layer;
Forming a second N-channel MOS transistor having a channel region in the epitaxial layer (e2);
Forming a P-channel MOS transistor having a channel region in any one of the plurality of element regions on the main surface of the semiconductor layer or in the epitaxial layer (e3),
The channel length direction size of the epitaxial layer in which the channel region of the second N-channel MOS transistor is formed is the channel length direction size of the element region in which the channel region of the first N-channel MOS transistor is formed. A manufacturing method of a semiconductor device smaller than the above.