JP2006023903A - Electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide electronic equipment where the number of slave parts is not restricted, and the efficiency of data transfer is made satisfactory at the time of transmitting one and the same data to a plurality of slave parts whose master part is connected to one and the same bus. <P>SOLUTION: This electronic equipment is provided with a master circuit 3, slave circuits 1 and 2, a bus for connecting the master circuit 3 and the slave circuits 1 and 2 and a normal reception signal processing circuit 11 arranged in the middle of the path of the bus. The address setting of the slave circuits 1 and 2 is made the same, and the same data are transmitted from the master circuit 3 to the slave circuits 1 and 2, and when the data have been normally received by the salve circuits 1 and 2, a normal reception signal showing that the data have been normally received is outputted. A normal reception signal processing circuit 11 inputs the normal reception signal, and returns the normal reception signal to the master circuit 3 only when both of the slave circuits 1 and 2 output the normal reception signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic device in which a master unit and a plurality of slave units are connected via a bus. In particular, the slave unit can be specified by address setting, and when the slave unit normally receives data, The present invention relates to an electronic device using a bus having a specification for returning a signal indicating that data has been received to a master unit.

The I ² C bus is a serial bus proposed by Philips, and supports data exchange between a plurality of devices using two signals of a serial clock and serial data. Details of I ² C-type bus omitted because it is described in the specifications or the like of the I ² C-type bus, which is issued by Philips. The acknowledge, which is one of the signals used in the I ² C system bus, is also described in detail in the I ² C system bus standard issued by Philips, but will be briefly described. .

In the I ² C system bus, data transfer is basically performed in units of 8 bits. Whether or not the data transfer is normally performed immediately after the 8-bit data transfer is confirmed by an acknowledge. When the data transfer is normally performed, the side that has received the data notifies the side that has transmitted the data that the data transfer has been normally performed by returning a 1-bit acknowledge to the side that has transmitted the data. On the other hand, if the data transfer is not normally performed, the data receiving side transmits the data indicating that the data transfer has not been performed normally by not returning the 1-bit acknowledge to the data transmitting side. Let the other side know.

  Here, the operation of returning the acknowledge is to pull the serial data to the low level immediately after the 8-bit data transfer.

In an electronic device using an I ² C system bus, the master unit can individually control the plurality of slave units by setting each of the plurality of slave units to different addresses, but the address setting is limited. In fact, the number of slave units controlled by the same bus line is limited.

Next, as an electronic apparatus having an I ² C system bus, here, a receiving apparatus that selects one of many signals transmitted from each TV broadcasting station and receives a desired program will be described as an example. . FIG. 9 shows a schematic configuration example of a conventional receiving apparatus. The conventional receiving apparatus shown in FIG. 9 includes an antenna 4, a tuner 5, a demodulation circuit 6, and a CPU 7. The tuner 5 includes an RF input terminal 5a, a band pass filter (BPF) 5b, an RF amplifier 5c, a band pass filter (BPF) 5d, a PLL circuit 5e, a voltage controlled oscillation circuit (VCO) 5f, and a mixer circuit. 5g and IF output terminal 5h. The RF input terminal 5a is connected to the antenna 4, the IF output terminal 5h is connected to the input terminal of the demodulation circuit 6, and the PLL circuit 5e is connected to the CPU 7 via the I ² C system bus. The I ² C system bus has a signal line for transmitting the serial clock SCL and a signal line for transmitting the serial data SDA.

  A large number of received signals received by the antenna 4 are input to the RF input terminal 5a. First, the band-pass filter 5b whose filter characteristics change according to the tuning voltage generated by the PLL circuit 5e is received from the large number of received signals. Only the desired signal is selected. The reception desired signal selected by the band pass filter 5b is amplified by the RF amplifier 5c.

  Thereafter, only the desired reception signal is further selected from the output signal of the RF amplifier 5c by the band-pass filter 5d whose filter characteristics change according to the tuning voltage generated by the PLL circuit 5e, and enters the mixer circuit 5g. Further, the local oscillation signal oscillated by the voltage controlled oscillation circuit 5f is also input to the mixer circuit 5g. The frequency of the local oscillation signal changes according to the tuning voltage generated by the PLL circuit 5e.

  The mixer circuit 5g performs frequency conversion by mixing the reception desired signal and the local oscillation signal, down-converts the reception desired signal into an intermediate frequency (IF) signal, and outputs it to the IF output terminal 5h. The frequency of the intermediate frequency signal is determined by the difference between the frequency of the local oscillation signal and the frequency of the desired reception signal. The PLL circuit 5e generates a tuning voltage having a different value for each desired reception channel according to data transmitted from the CPU 7. Thereby, the frequency of the local oscillation signal is changed in proportion to the frequency of the desired reception signal, and the intermediate frequency signal output from the mixer circuit 5g is always a constant frequency.

  The intermediate frequency signal sent from the IF output terminal 5 h to the demodulation circuit 6 is demodulated by the demodulation circuit 6. For example, when receiving a digital TV broadcast, a demodulating circuit that digitally demodulates the intermediate frequency signal to obtain a digital signal such as a transport stream is used as the demodulating circuit 6. When receiving an analog TV broadcast, a demodulator circuit that demodulates the intermediate frequency signal to obtain an analog signal such as a video signal or an audio signal is used as the demodulator circuit 6.

  By the way, in a vehicle-mounted TV, a portable TV, a portable radio, a cellular phone, and the like, the reception status may change remarkably due to a change in antenna position and orientation angle. For this reason, in an in-vehicle TV, a portable TV, a portable radio, a cellular phone, etc., the reception status is determined by using a plurality of antennas instead of the receiving device shown in FIG. It is common to use a receiving apparatus (diversity receiving apparatus) corresponding to the change of the above.

  Here, FIG. 10 shows a schematic configuration example of a conventional diversity receiver. 10 that are the same as those in FIG. 9 are given the same reference numerals, and detailed descriptions thereof are omitted. The conventional diversity receiving apparatus shown in FIG. 10 includes a first tuner 5 and a second tuner 5 '.

  The second tuner 5 ′ has the same configuration as the first tuner 5. That is, the RF input terminal 5′a is the RF input terminal 5a, the bandpass filter (BPF) 5′b is the bandpass filter 5b, the RF amplifier 5′c is the RF amplifier 5c, and the bandpass filter (BPF) 5 ′. d is a band-pass filter 5d, PLL circuit 5′e is a PLL circuit 5e, voltage-controlled oscillator circuit (VCO) 5′f is a voltage-controlled oscillator circuit 5f, mixer circuit 5′g is a mixer circuit 5g, and IF output The terminal 5′h is the same component as the IF output terminal 5h.

The RF input terminal 5a of the first tuner 5 is connected to the antenna 4, and the RF input terminal 5'a of the second tuner 5 'is connected to the antenna 4'. The IF output terminal 5h of the first tuner 5 is connected to the input terminal of the demodulation circuit 6, and the IF output terminal 5'h of the second tuner 5 'is connected to the input terminal of the demodulation circuit 6'. The PLL circuits 5e and 5'e are connected to the CPU 7 through the same I ² C bus. The I ² C system bus has a signal line for transmitting the serial clock SCL and a signal line for transmitting the serial data SDA. Then, the comparator 8 compares the demodulated signal output from the demodulating circuit 6 with the demodulated signal output from the demodulating circuit 6 ′, and the demodulated signal having the better quality (S / If N is the higher demodulated signal and the demodulated signal is a digital signal, the demodulated signal having the lower bit error rate is selected and output.

  In the conventional diversity receiver, the same broadcast is selected by the first tuner 5 and the second tuner 5 '. That is, the PLL circuit 5e and the PLL circuit 5'e receive the same data from the CPU 7 and generate the same tuning voltage according to the received data. Therefore, the voltage controlled oscillation circuit 5f and the voltage controlled oscillation circuit 5'f oscillate the same local oscillation signal. Therefore, the demodulated signal output from the demodulator circuit 6 and the demodulated signal output from the demodulator circuit 6 'have the same contents.

  For example, if the reception condition of the antenna 4 is deteriorated, the quality of the demodulated signal obtained by processing the signal received by the antenna 4 is also deteriorated. If the reception condition of the antenna 4 ′ is not deteriorated, the antenna 4 ′ is used. Since the quality of the demodulated signal obtained by processing the received signal is good, the comparator 8 discards the demodulated signal obtained by processing the signal received by the antenna 4 and received by the antenna 4 ′. A demodulated signal obtained by processing the signal is selected. As a result, the quality of the demodulated signal in the receiving apparatus as a whole can be kept good.

Even if the reception status of some of the plurality of antennas deteriorates as described above, the diversity reception device does not deteriorate the total reception status of the reception device if one or more reception statuses of the plurality of antennas are good. It is a receiving device.
JP-T-2002-518739

As described above, in the diversity receiver, all the PLL circuits that generate tuning voltages (hereinafter referred to as tuning PLL circuits) need to input the same data.

  Even though the data input to the tuning PLL circuit is the same, it is necessary to set an individual address for each tuning PLL circuit. This is because, if the same address is set for all the tuning PLL circuits, even if only one of the plurality of tuning PLL circuits receives data normally, the acknowledge returns to the data sending side. This is because there is a problem that even if the data cannot be normally received, the side that sent the data cannot recognize it.

  If the number of tuning PLL circuits connected by the same bus is small, there may be no problem even if individual addresses are set for each tuning PLL circuit. However, as described above, the address setting is limited (mostly four types). Therefore, the number of tuning PLL circuits connected by the same bus is practically limited, and the design margin is narrowed.

  In addition, since it is necessary for the data sending side to transmit the same data several times by changing the address, there is a lot of waste in terms of program and time.

  Note that the computer system disclosed in Patent Document 1 can satisfy the request for the lock-up operation, but cannot solve the above problems.

  In view of the above problems, the present invention provides an electronic device in which the number of slave units is not limited and data transfer efficiency is high when the master unit transmits the same data to a plurality of slave units connected to the same bus. The purpose is to provide equipment.

  In order to achieve the above object, an electronic apparatus according to the present invention includes a master unit, a plurality of slave units, a bus, and a normal reception signal processing unit provided in a path of the bus, and the master unit and the plurality of slaves Are connected to each other via the bus, the address settings of the plurality of slave units are made the same, the master unit sends the same data to the plurality of slave units, and each of the plurality of slave units normalizes the data When receiving, a normal reception signal indicating that the data has been normally received is output, the normal reception signal processing unit inputs the normal reception signal, and all of the plurality of slave units output the normal reception signal. Only the normal reception signal is returned to the master unit. Note that a slave unit in which an address different from the plurality of slave units is set may be connected to the bus.

  In the electronic device having the above-described configuration, the addresses of the plurality of slave units are set to be the same, so that the number of the plurality of slave units is not limited. In addition, since the addresses of the plurality of slave units are set to be the same, it is not necessary for the master unit to change the address and transmit the same data many times, and the efficiency of data transfer is improved.

Further, an I ² C bus may be used as the bus, and the normal reception signal may be a 1-bit Low level signal. In this case, the following eight examples are given as examples of the configuration of the normal reception signal processing unit.

  As a first example, the normal reception signal processing unit includes an OR circuit that inputs the outputs of the plurality of slave units. As a second example, the normal reception signal processing unit includes a negative OR circuit that inputs the outputs of the plurality of slave units, and a negative circuit that inputs the output of the negative OR circuit. . As a third example, the normal reception signal processing unit receives an output of each of the plurality of slave units, a negative circuit that inputs an output of the logical sum circuit, and an output of the negative circuit And an inverting transistor that is input to the control terminal. As a fourth example, the normal reception signal processing unit includes a negative OR circuit that inputs the outputs of the plurality of slave units, and an inverting transistor that inputs the output of the negative OR circuit to a control terminal. It is the composition which has. As a fifth example, the normal reception signal processing unit includes a plurality of negation circuits that individually input the outputs of the plurality of slave units, and a NAND circuit that inputs the outputs of the plurality of negation circuits, It is the structure which has. As a sixth example, the normal reception signal processing unit includes a plurality of negation circuits that individually input the outputs of the plurality of slave units, and an AND circuit that inputs the outputs of the plurality of negation circuits, And a second negation circuit for inputting the output of the AND circuit. As a seventh example, the normal reception signal processing unit includes a plurality of negation circuits that individually input the outputs of the plurality of slave units, and an AND circuit that inputs the outputs of the plurality of negation circuits, And an inverting transistor that inputs an output of the AND circuit to a control terminal. As an eighth example, the normal reception signal processing unit includes a plurality of negation circuits that individually input the outputs of the plurality of slave units, and a negative AND circuit that inputs the outputs of the plurality of negation circuits, And a second negation circuit that inputs the output of the NAND circuit, and an inverting transistor that inputs the output of the second negation circuit to a control terminal.

  Moreover, in the electronic device according to the present invention having any one of the above configurations, the normal reception signal processing unit may be integrated. Further, when the electronic apparatus according to the present invention includes a general-purpose integrated circuit, the normal reception signal processing unit is built in the general-purpose integrated circuit to form an integrated circuit, and serial data input / output terminals are provided in the general-purpose integrated circuit. It may be provided.

  The present invention can be applied to electronic devices for various uses. Specific examples of the electronic device according to the present invention include an electronic device (for example, an in-vehicle TV or a portable TV) including a diversity receiver having a plurality of tuners. And diversity receivers having a plurality of tuners). When the electronic device according to the present invention is an electronic device including a diversity receiver or the diversity receiver itself, the tuning PLL circuits in the plurality of tuners may be the plurality of slave units.

  According to the present invention, when the master unit transmits the same data to a plurality of slave units connected to the same bus, it is possible to realize an electronic device that has no limitation on the number of slave units and has high data transfer efficiency. it can.

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described. FIG. 1 shows the main configuration of an electronic apparatus according to the first embodiment of the present invention. The electronic device shown in FIG. 1 includes slave circuits 1 and 2 and a master circuit 3. Slave circuits 1 and 2 and master circuit 3 are connected via an I ² C bus. The I ² C bus has a signal line (hereinafter referred to as a serial clock line) for transmitting a serial clock SCL and a signal line (hereinafter referred to as a serial data line) for transmitting serial data SDA.

  The serial clock line connected to the master circuit 3 is distributed in two and connected to the slave circuits 1 and 2, and the serial data line connected to the master circuit 3 is distributed in two and connected to the slave circuits 1 and 2. A normal reception signal processing circuit 11 is provided at two distribution positions of the serial data line.

  The normal reception signal processing circuit 11 includes buffer amplifiers BUF1 and BUF2, and an OR circuit OR1. The input terminal of the buffer amplifier BUF1, the input terminal of the buffer amplifier BUF2, and the output terminal of the OR circuit OR1 are connected in common and connected to the master circuit 3 via a serial data line. The output terminal of the buffer amplifier BUF1 and the first input terminal of the OR circuit OR1 are connected in common and connected to the slave circuit 1 via the serial data line. The output terminal of the buffer amplifier BUF2 and the second input terminal of the OR circuit OR1 are connected in common and connected to the slave circuit 2 via a serial data line. The buffer amplifiers BUF1 and BUF2 may have any circuit configuration as long as they can accurately transmit the high level and low level of the serial data SDA. For example, the buffer amplifiers BUF1 and BUF2 may have a circuit configuration in which two negative circuits are connected in series.

  Next, the operation of the electronic device having the above configuration will be described. Since the serial data SDA transmitted from the master circuit 3 reaches the slave circuit 1 via the buffer amplifier BUF1, and reaches the slave circuit 2 via the buffer amplifier BUF2, the slave circuits 1 and 2 respectively receive the serial data SDA. Can be received normally.

  Further, the first input terminal of the OR circuit OR1 for inputting the acknowledge transmitted from the slave circuit 1 and the second input terminal of the OR circuit OR1 for inputting the acknowledge transmitted from the slave circuit 2 are both at the low level. Only when the output of the OR circuit OR1 becomes Low level. For this reason, only when each of the slave circuits 1 and 2 normally receives data transmitted from the master circuit 3, the output of the OR circuit OR1 becomes Low level, and the master circuit 3 receives an acknowledge.

  Here, since the acknowledge returned from the slave circuit 1 and the acknowledge returned from the slave circuit 2 are separated by the buffer amplifiers BUF1 and BUF2, they do not interfere with each other.

  Of course, if the addresses of the slave circuits 1 and 2 are not set to be the same, the above operation is incomplete. However, setting the addresses of the two slave circuits 1 and 2 to be the same is one of the features of the present invention. Therefore, there is no problem.

Since the addresses of the two slave circuits 1 and 2 are set to be the same, the number of slave circuits connected by the same I ² C system bus is not limited. Thus, the slave circuit connected with the same I ² C-type bus in the present embodiment has been be two, it may be three or more. In this case, it is preferable to increase the number of input terminals of the OR circuit OR1 and the number of buffer amplifiers by the increased number of slave circuits.

  Further, since the addresses of the two slave circuits 1 and 2 are set to be the same, it is not necessary for the master circuit 3 to change the address and transmit the same data many times, thereby improving the efficiency of data transfer.

  Next, a second embodiment of the present invention will be described. The principal part structure of the electronic device which concerns on 2nd Embodiment of this invention is shown in FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The electronic device shown in FIG. 2 has a configuration in which a normal reception signal processing circuit 12 is provided instead of the normal reception signal processing circuit 11 of the electronic device shown in FIG.

  The normal reception signal processing circuit 12 includes buffer amplifiers BUF1 and BUF2, a negative OR circuit NOR1, and a negative circuit INV1. The input terminal of the buffer amplifier BUF1, the input terminal of the buffer amplifier BUF2, and the output terminal of the negative circuit INV1 are connected in common and connected to the master circuit 3 via the serial data line. The output terminal of the buffer amplifier BUF1 and the first input terminal of the NOR circuit NOR1 are connected in common and connected to the slave circuit 1 through a serial data line. The output terminal of the buffer amplifier BUF2 and the second input terminal of the NOR circuit NOR1 are connected in common and connected to the slave circuit 2 via a serial data line. Further, the output terminal of the negative OR circuit NOR1 is connected to the input terminal of the negative circuit INV1. The buffer amplifiers BUF1 and BUF2 may have any circuit configuration as long as they can accurately transmit the high level and low level of the serial data SDA. For example, the buffer amplifiers BUF1 and BUF2 may have a circuit configuration in which two negative circuits are connected in series.

  Next, the operation of the electronic device having the above configuration will be described. Since the serial data SDA transmitted from the master circuit 3 reaches the slave circuit 1 via the buffer amplifier BUF1, and reaches the slave circuit 2 via the buffer amplifier BUF2, the slave circuits 1 and 2 respectively receive the serial data SDA. Can be received normally.

  The first input terminal of the NOR circuit NOR1 that inputs the acknowledge transmitted from the slave circuit 1 and the second input terminal of the NOR circuit NOR1 that inputs the acknowledge transmitted from the slave circuit 2 are both. Only when it becomes Low level, the output of the NOR circuit NOR1 becomes High level, and the output of the NOT circuit INV1 becomes Low level. For this reason, only when each of the slave circuits 1 and 2 normally receives data transmitted from the master circuit 3, the output of the negative circuit INV1 becomes low level, and the master circuit 3 receives an acknowledge.

  Here, since the acknowledge returned from the slave circuit 1 and the acknowledge returned from the slave circuit 2 are separated by the buffer amplifiers BUF1 and BUF2, they do not interfere with each other.

  Of course, if the addresses of the slave circuits 1 and 2 are not set to be the same, the above operation will be incomplete, but it is one of the features of the present invention that the addresses of the two slave circuits 1 and 2 are the same. There is no problem.

Since setting the two addresses of the slave circuits 1 and 2 in the same, the number of slave circuits connected in the same I ² C-type bus is not limited. Therefore, in the present embodiment, there are two slave circuits connected by the same I ² C system bus, but there may be three or more slave circuits. In this case, the number of input terminals of the NOR circuit NOR1 and the number of buffer amplifiers may be increased by the number of slave circuits.

  Further, since the addresses of the two slave circuits 1 and 2 are set to be the same, it is not necessary for the master circuit 3 to change the address and transmit the same data many times, thereby improving the efficiency of data transfer.

  The reason why the negative circuit and the negative OR circuit are used in the present embodiment is that these logic circuits are more widely used than the OR circuit and are often advantageous in terms of cost.

  Next, a third embodiment of the present invention will be described. FIG. 3 shows the main configuration of an electronic apparatus according to the third embodiment of the present invention. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The electronic device shown in FIG. 3 has a configuration in which a normal reception signal processing circuit 13 is provided instead of the normal reception signal processing circuit 11 of the electronic device shown in FIG.

  The normal reception signal processing circuit 13 includes buffer amplifiers BUF1 and BUF2, a logical sum circuit OR1, a negative circuit INV1, and an inverting amplifier. The inverting amplifier includes an inverting transistor Q1 and a pull-up resistor R1. The input terminal of the buffer amplifier BUF1, the input terminal of the buffer amplifier BUF2, and the output terminal of the inverting amplifier are connected in common and connected to the master circuit 3 via a serial data line. The output terminal of the buffer amplifier BUF1 and the first input terminal of the OR circuit OR1 are connected in common and connected to the slave circuit 1 via the serial data line. The output terminal of the buffer amplifier BUF2 and the second input terminal of the OR circuit OR1 are connected in common and connected to the slave circuit 2 via a serial data line. The output terminal of the OR circuit OR1 is connected to the input terminal of the negation circuit INV1, and the output terminal of the negation circuit INV1 is connected to the input terminal of the inverting amplifier. The buffer amplifiers BUF1 and BUF2 may have any circuit configuration as long as they can accurately transmit the high level and low level of the serial data SDA. For example, the buffer amplifiers BUF1 and BUF2 may have a circuit configuration in which two negative circuits are connected in series.

  Next, the operation of the electronic device having the above configuration will be described. Since the serial data SDA transmitted from the master circuit 3 reaches the slave circuit 1 via the buffer amplifier BUF1, and reaches the slave circuit 2 via the buffer amplifier BUF2, the slave circuits 1 and 2 respectively receive the serial data SDA. Can be received normally.

  Further, the first input terminal of the OR circuit OR1 for inputting the acknowledge transmitted from the slave circuit 1 and the second input terminal of the OR circuit OR1 for inputting the acknowledge transmitted from the slave circuit 2 are both at the low level. Only when the output of the OR circuit OR1 becomes Low level, the output of the NOT circuit INV1 becomes High level, and the output of the inverting amplifier becomes Low level. For this reason, only when each of the slave circuits 1 and 2 normally receives the data transmitted from the master circuit 3, the output of the inverting amplifier becomes the low level, and the master circuit 3 receives the acknowledge.

  Here, since the acknowledge returned from the slave circuit 1 and the acknowledge returned from the slave circuit 2 are separated by the buffer amplifiers BUF1 and BUF2, they do not interfere with each other.

  Of course, if the addresses of the slave circuits 1 and 2 are not set to be the same, the above operation will be incomplete, but it is one of the features of the present invention that the addresses of the two slave circuits 1 and 2 are the same. There is no problem.

Since the addresses of the two slave circuits 1 and 2 are set to be the same, the number of slave circuits connected by the same I ² C system bus is not limited. Therefore, in the present embodiment, there are two slave circuits connected by the same I ² C system bus, but there may be three or more slave circuits. In this case, it is preferable to increase the number of input terminals of the OR circuit OR1 and the number of buffer amplifiers by the increased number of slave circuits.

  Further, since the addresses of the two slave circuits 1 and 2 are set to be the same, it is not necessary for the master circuit 3 to change the address and transmit the same data many times, thereby improving the efficiency of data transfer.

  The reason why the inverting transistor is used in the present embodiment is that the current control of the transistor is closer to the conventional control method, and stable operation is easier. The inversion transistor Q1 may be a field effect transistor or the like without any operational problem and can be replaced with a bipolar transistor.

  Next, a fourth embodiment of the present invention will be described. FIG. 4 shows the main configuration of an electronic apparatus according to the fourth embodiment of the present invention. 4 that are the same as those in FIG. 3 are given the same reference numerals, and detailed descriptions thereof are omitted. The electronic device shown in FIG. 4 has a configuration in which a normal reception signal processing circuit 14 is provided instead of the normal reception signal processing circuit 13 of the electronic device shown in FIG.

  The normal reception signal processing circuit 14 has a configuration in which the logical sum circuit OR1 and the negative circuit INV1 of the normal reception signal processing circuit 13 of the electronic apparatus shown in FIG. 3 are replaced with a negative logical sum circuit NOR1. The electronic device shown in FIG. 4 is advantageous in terms of cost because it can reduce one part as compared with the electric device shown in FIG.

  The operation of the electronic device shown in FIG. 4 is substantially the same as the operation of the electric device shown in FIG.

  Next, a fifth embodiment of the present invention will be described. The principal part structure of the electronic device which concerns on 5th Embodiment of this invention is shown in FIG. 5 that are the same as those in FIG. 1 are assigned the same reference numerals, and detailed descriptions thereof are omitted. The electronic device shown in FIG. 5 has a configuration in which a normal reception signal processing circuit 15 is provided instead of the normal reception signal processing circuit 11 of the electronic device shown in FIG.

  The normal reception signal processing circuit 15 includes buffer amplifiers BUF1 and BUF2, negative circuits INV2 and INV3, and a negative logical product circuit NAND1. The input terminal of the buffer amplifier BUF1, the input terminal of the buffer amplifier BUF2, and the output terminal of the NAND circuit NAND1 are connected in common and connected to the master circuit 3 via a serial data line. The output terminal of the buffer amplifier BUF1 and the input terminal of the negation circuit INV2 are connected in common and connected to the slave circuit 1 via a serial data line. The output terminal of the buffer amplifier BUF2 and the input terminal of the NOT circuit INV3 are connected in common and connected to the slave circuit 2 via a serial data line. Further, the output terminal of the negative circuit INV2 is connected to the first input terminal of the negative logical product circuit NAND1, and the output terminal of the negative circuit INV3 is connected to the second input terminal of the negative logical product circuit NAND1. The buffer amplifiers BUF1 and BUF2 may have any circuit configuration as long as they can accurately transmit the high level and low level of the serial data SDA. For example, the buffer amplifiers BUF1 and BUF2 may have a circuit configuration in which two negative circuits are connected in series.

  Next, the operation of the electronic device having the above configuration will be described. Since the serial data SDA transmitted from the master circuit 3 reaches the slave circuit 1 via the buffer amplifier BUF1, and reaches the slave circuit 2 via the buffer amplifier BUF2, the slave circuits 1 and 2 respectively receive the serial data SDA. Can be received normally.

  The acknowledge transmitted from the slave circuit 1 is inverted by the negation circuit INV2 and then input to the first input terminal of the NAND circuit NAND1, and the acknowledge transmitted from the slave circuit 2 is inverted by the negation circuit INV3. This is input to the second input terminal of the NAND circuit NAND1. For this reason, only when each of the slave circuits 1 and 2 normally receives data transmitted from the master circuit 3, the output of the NAND circuit NAND1 becomes Low level, and the master circuit 3 receives an acknowledge.

  Here, since the acknowledge returned from the slave circuit 1 and the acknowledge returned from the slave circuit 2 are separated by the buffer amplifiers BUF1 and BUF2, they do not interfere with each other.

  Of course, if the addresses of the slave circuits 1 and 2 are not set to be the same, the above operation will be incomplete, but it is one of the features of the present invention that the addresses of the two slave circuits 1 and 2 are the same. There is no problem.

Since the addresses of the two slave circuits 1 and 2 are set to be the same, the number of slave circuits connected by the same I ² C system bus is not limited. Therefore, in the present embodiment, there are two slave circuits connected by the same I ² C system bus, but there may be three or more slave circuits. In this case, it is preferable to increase the number of input terminals of the NAND circuit NAND1 and the number of negation circuits and buffer amplifiers by the increased number of slave circuits.

  Further, since the addresses of the two slave circuits 1 and 2 are set to be the same, it is not necessary for the master circuit 3 to change the address and transmit the same data many times, thereby improving the efficiency of data transfer.

  Next, a sixth embodiment of the present invention will be described. The principal part structure of the electronic device which concerns on 6th Embodiment of this invention is shown in FIG. 6 that are the same as those in FIG. 5 are given the same reference numerals, and detailed descriptions thereof are omitted. The electronic device shown in FIG. 6 has a configuration in which a normal reception signal processing circuit 16 is provided instead of the normal reception signal processing circuit 15 of the electronic device shown in FIG.

  The normal reception signal processing circuit 16 has a configuration in which the negative logical product circuit NAND1 of the normal reception signal processing circuit 15 of the electronic device shown in FIG. 5 is replaced with a logical product circuit AND1 and a negative circuit INV4.

  The operation of the electronic device illustrated in FIG. 6 is substantially the same as the operation of the electric device illustrated in FIG.

  Next, a seventh embodiment of the present invention will be described. The principal part structure of the electronic device which concerns on 7th Embodiment of this invention is shown in FIG. In FIG. 7, the same parts as those in FIG. The electronic device shown in FIG. 7 has a configuration in which a normal reception signal processing circuit 17 is provided instead of the normal reception signal processing circuit 15 of the electronic device shown in FIG.

  The normal reception signal processing circuit 17 has a configuration in which the negative logical product circuit NAND1 of the normal reception signal processing circuit 15 of the electronic device shown in FIG. 5 is replaced with a logical product circuit AND1 and an inverting amplifier. The inverting amplifier includes an inverting transistor Q1 and a pull-up resistor R1.

  The operation of the electronic device illustrated in FIG. 7 is substantially the same as the operation of the electric device illustrated in FIG.

  The reason why the inversion transistor is used in the present embodiment is that the current control of the transistor is closer to the conventional control method, and stable operation is easier. The inversion transistor Q1 may be a field effect transistor or the like without any operational problem and can be replaced with a bipolar transistor.

  Next, an eighth embodiment of the present invention will be described. The principal part structure of the electronic device which concerns on 8th Embodiment of this invention is shown in FIG. In FIG. 8, the same parts as those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted. The electronic device shown in FIG. 8 has a configuration in which a normal reception signal processing circuit 18 is provided instead of the normal reception signal processing circuit 16 of the electronic device shown in FIG.

  The normal reception signal processing circuit 18 is configured by replacing the logical product circuit AND1 and the negative circuit INV4 of the normal reception signal processing circuit 16 of the electronic device shown in FIG. 6 with a negative logical product circuit NAND1, a negative circuit INV4, and an inverting amplifier. . The inverting amplifier includes an inverting transistor Q1 and a pull-up resistor R1.

  The operation of the electronic device shown in FIG. 8 is substantially the same as the operation of the electric device shown in FIG.

  The reason why the inverting transistor is used in the present embodiment is that the current control of the transistor is closer to the conventional control method, and stable operation is easier. The inversion transistor Q1 may be a field effect transistor or the like without any operational problem and can be replaced with a bipolar transistor.

  In the first to eighth embodiments of the present invention described above, each of the normal reception signal processing circuits 11 to 18 may be integrated. Since each of the normal reception signal processing circuits 11 to 18 is configured by a logic circuit, it is relatively easy to make an integrated circuit. Each of the normal reception signal processing circuits 11 to 18 may be integrated into a single integrated circuit. Each of the normal reception signal processing circuits 11 to 18 may be integrated into the general-purpose integrated circuit. And may be integrated. Since the normal reception signal processing circuits 11 to 18 have a small circuit scale, even if each of the normal reception signal processing circuits 11 to 18 is incorporated in the general-purpose integrated circuit, the chip size of the general-purpose integrated circuit is hardly affected. In addition, when each of the normal reception signal processing circuits 11 to 18 is built in a general-purpose integrated circuit to be integrated, the general-purpose integrated circuit is connected to a serial data line. Input / output terminals may be provided.

  In addition, the present invention can be applied to electronic devices for various purposes. Specific examples of the electronic device according to the present invention include an electronic device including a diversity receiver (for example, a vehicle-mounted TV, a portable TV, a portable device). Radio, mobile phone, etc.) and diversity receiver itself. When the electronic device according to the present invention is an electronic device provided with a diversity receiver or the diversity receiver itself, the slave circuits 1 and 2 in the first to eighth embodiments of the present invention described above are tuned PLL circuits in each tuner, The master circuit 3 is a CPU.

In the first to eighth embodiments of the present invention described above, the electronic device using the I ² C system bus has been described. However, the present invention is not limited to this, and the slave unit is designated by address setting. It can be applied to all electronic devices using a bus with a specification that returns a signal indicating that data has been received normally to the master unit when the slave unit has received data normally.

These are figures which show the principal part structure of the electronic device which concerns on 1st Embodiment of this invention. These are figures which show the principal part structure of the electronic device which concerns on 2nd Embodiment of this invention. These are figures which show the principal part structure of the electronic device which concerns on 3rd Embodiment of this invention. These are figures which show the principal part structure of the electronic device which concerns on 4th Embodiment of this invention. These are figures which show the principal part structure of the electronic device which concerns on 5th Embodiment of this invention. These are figures which show the principal part structure of the electronic device which concerns on 6th Embodiment of this invention. These are figures which show the principal part structure of the electronic device which concerns on 7th Embodiment of this invention. These are figures which show the principal part structure of the electronic device which concerns on 8th Embodiment of this invention. These are figures which show the example of schematic structure of the conventional receiver. These are figures which show the example of schematic structure of the conventional diversity receiver.

Explanation of symbols

1, 2 Slave circuit 3 Master circuit 11-18 Normal reception signal processing circuit AND1 AND circuit BUF1, BUF2 Buffer amplifier INV1-INV4 Negative circuit NAND1 NAND circuit NOR1 NOR circuit OR1 OR circuit Q1 Inverting transistor R1 Pull Up resistor SDA Serial data SCL Serial clock

Claims (14)

A master unit, a plurality of slave units, a bus, and a normal reception signal processing unit provided in the path of the bus,
The master unit and the plurality of slave units are connected via the bus,
The address settings of the plurality of slave units are the same, and the master unit sends the same data to the plurality of slave units,
When each of the plurality of slave units normally receives the data, it outputs a normal reception signal indicating that the data has been normally received,
The electronic apparatus wherein the normal reception signal processing unit inputs the normal reception signal and returns the normal reception signal to the master unit only when all of the plurality of slave units output the normal reception signal . The bus is an I ² C bus,
The electronic apparatus according to claim 1, wherein the normal reception signal is a 1-bit Low level signal.   The electronic apparatus according to claim 2, wherein the normal reception signal processing unit includes an OR circuit that inputs an output of each of the plurality of slave units.   The electronic apparatus according to claim 2, wherein the normal reception signal processing unit includes a negative logical sum circuit that inputs an output of each of the plurality of slave units, and a negative circuit that inputs an output of the negative logical sum circuit.   The normal reception signal processing unit inputs an output of each of the plurality of slave units, a NOT circuit that inputs the output of the OR circuit, and an inversion input that inputs the output of the NOT circuit to a control terminal The electronic device according to claim 2, further comprising a transistor.   3. The normal reception signal processing unit includes a negative OR circuit that inputs an output of each of the plurality of slave units, and an inverting transistor that inputs an output of the negative OR circuit to a control terminal. Electronics.   3. The normal reception signal processing unit includes a plurality of negation circuits that individually input outputs of the plurality of slave units, and a negative AND circuit that inputs outputs of the plurality of negation circuits. Electronic equipment.   The normal reception signal processing unit includes a plurality of negation circuits that individually input outputs of the plurality of slave units, an AND circuit that inputs outputs of the plurality of negation circuits, and an output of the AND circuit. The electronic device according to claim 2, further comprising a second negative circuit for inputting.   The normal reception signal processing unit includes a plurality of negation circuits that individually input outputs of the plurality of slave units, an AND circuit that inputs outputs of the plurality of negation circuits, and an output of the AND circuit. The electronic device according to claim 2, further comprising an inverting transistor that is input to the control terminal.   The normal reception signal processing unit includes a plurality of negation circuits that individually input outputs of the plurality of slave units, a negative logical product circuit that inputs outputs of the plurality of negative circuits, and a negative logical product circuit. The electronic apparatus according to claim 2, further comprising: a second negation circuit that inputs an output; and an inverting transistor that inputs an output of the second negation circuit to a control terminal.   The electronic device according to claim 1, wherein the normal reception signal processing unit is integrated. Equipped with general-purpose integrated circuits,
12. The electronic apparatus according to claim 11, wherein the normal reception signal processing unit is built in the general-purpose integrated circuit to be integrated, and an input / output terminal for serial data is provided in the general-purpose integrated circuit. A diversity receiver having a plurality of tuners,
The electronic device according to claim 1, wherein tuning PLL circuits in the plurality of tuners are the plurality of slave units. An electronic device including a diversity receiver having a plurality of tuners,
The electronic device according to claim 1, wherein tuning PLL circuits in the plurality of tuners are the plurality of slave units.

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