JP2006020072A - Radio receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a radio receiver capable of constituting an MB-OFDM receiver circuit without using a high speed analog switch. <P>SOLUTION: Three base band demodulators DEMO1-3 in a BB 2 are provided corresponding to local frequencies f1, f2, f3 suited to a frequency hopping pattern for demodulating signals received by an RF unit 1 using corresponding local frequencies. A selector SEL1 switches over outputs I of the base band demodulators DEMO1-3 to output through AD converters ADI1-3 according to the timing of the frequency hopping of the received signals. A selector SEL2 switches over outputs Q of the base band demodulators DEMO1-3 to output through AD converters ADQ1-3 according to the switching timing by the selector SEL1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multiband orthogonal frequency division multiplexing wireless receiver.

  In recent years, ultra-wideband (hereinafter referred to as UWB) communication has attracted attention as short-range and large-capacity wireless communication. In particular, the proposal of a UWB system of a multiband orthogonal frequency division multiplexing (hereinafter referred to as MB-OFDM) system is most supported. This method is being standardized by TG3a of the IEEE802.15 committee, and details thereof are described in IEEE P802.15-03 / 268r1 and IEEE P802.15-03 / 267r6.

  In the proposed system, frequency hopping is performed for each symbol of an orthogonal frequency division multiplexing (OFDM) signal, IFFT / FFT time is about 242.4 ns, zero (padded) prefix time is about 60.6 ns, and hopping is performed. The allowable time for switching frequency (guard interval) is about 9.5 ns.

  In the transmitter using the above proposed scheme, no signal is transmitted during the period of about 60.6 ns of the zero (padded) prefix time, so this time may be used as the frequency switching time. However, on the receiver side, the zero (padded) prefix time is divided by the time for taking in the multipath delayed wave, so this time cannot be used for the switching time of the hopping frequency.

  A compensation method in the case where a multipath delayed wave is generated is described in Slide 15 of IEEE P802.15-03 / 267r6. The concept of the delay wave compensation method is shown in FIG.

As shown in FIG. 7, the delayed wave that is later than the FFT interval is added to the head of the FFT interval. As a result, delay wave compensation can be performed. In the proposed MB-OFDM system, about 60.6 ns of the zero (padded) prefix time is set as the compensation range of the delayed wave, and this time is used as the frequency switching time. However, it is necessary to switch the frequency during the period of about 9.5 ns of the guard interval. However, since it is impossible to reset the local frequency during such a short time period, in the above proposal, all frequencies used for frequency hopping are held as local frequencies, and their local frequencies are Frequency hopping is enabled by selecting the frequency with a switch.
IEEE P802.15-03 / 268r1 IEEE P802.15-03 / 267r6

  In IEEE P802.15-03 / 267r6, Slide21, the MB-OFDM system proponent showed experimental results that the switching time of the local frequency is completed in about 2 ns. Therefore, it is generally difficult to switch the local frequency with an analog switch within a time of 9.5 ns.

  An object of the present invention is to provide a radio receiving apparatus that can configure an MB-OFDM receiving circuit without using a high-speed analog switch.

  In order to achieve the above object, the present invention provides a multiband orthogonal frequency division multiplexing radio receiving apparatus that oscillates a plurality of local frequencies in accordance with a frequency hopping pattern of a received signal; A plurality of baseband demodulating units that are provided in association with local frequencies and that demodulate received signals using the associated local frequencies, and the baseband demodulating units according to the timing of frequency hopping of the received signals I output switching means for switching and outputting the respective I outputs, Q output switching means for switching and outputting the respective Q outputs of the baseband demodulation means in synchronization with the switching timing of the I output switching means, Each of the output of the I output switching means and the output of the Q output switching means To provide a radio receiving apparatus characterized by comprising a data demodulation means for demodulating the data on the basis of.

  In order to achieve the above object, the present invention provides a multiband orthogonal frequency division multiplexing radio receiving apparatus, which is provided with local oscillating means for oscillating a plurality of local frequencies in accordance with a frequency hopping pattern of a received signal. Two baseband demodulating means for demodulating a received signal using a local frequency, and the baseband demodulating means alternately demodulate received signals having different hopping frequencies from among the plurality of local frequencies. Frequency selecting means for selecting a local frequency to be given to each of the baseband demodulating means, I output switching means for switching and outputting each I output of the baseband demodulating means according to the frequency hopping timing of the received signal, , In synchronism with the switching timing of the I output switching means. Q output switching means for switching and outputting each Q output of the band demodulating means, and data demodulating means for demodulating data based on each of the output of the I output switching means and the output of the Q output switching means Provided is a wireless receiver characterized by comprising:

  According to the present invention, an MB-OFDM receiving circuit can be configured without using a high-speed analog switch.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a basic configuration of the radio receiving apparatus according to the first embodiment of the present invention, and FIG. 2 is a block diagram showing a circuit configuration of the first stage of the digital signal processing unit of FIG.

  As shown in FIG. 1, the radio reception apparatus according to the present embodiment includes a radio reception apparatus using the MB-OFDM method, and the radio reception apparatus includes an RF (radio frequency) unit 1 and a BB (baseband). Unit 2 and a digital signal processing unit 3.

  The RF unit 1 includes a transmission / reception changeover switch T / RSW for outputting a signal received by the antenna ANT to the reception side, a bandpass filter BPF, a low noise amplifier LNA, and three local frequencies f1, f2, and f3. And an oscillating oscillator Synth. Here, the local frequencies f1, f2, and f3 are frequencies according to the frequency hopping pattern of the received signal, respectively. The number of local frequencies f1, f2, and f3 is equal to the basic hopping number, and in the present embodiment, the number is three.

  The BB unit 2 includes three baseband demodulators DEMO1 to DEMO3 for demodulating the reception signal received by the RF unit 1 using the corresponding local frequencies f1, f2, and f3. AD converters ADI1 to ADI3 are connected to I outputs of the baseband demodulators DEMO1 to DEMO3 through low pass filters LPF, respectively. AD converters ADQ1 to ADQ3 are connected to Q outputs of the baseband demodulators DEMO1 to DEMO3 through low pass filters LPF, respectively.

  The digital signal processing unit 3 includes a selector SEL1 that switches the outputs of the AD converters ADI1 to ADI1 and a selector SEL2 that switches the outputs of the AD converters ADQ1 to ADQ1 simultaneously with the I channel. The selectors SEL1 and SEL2 switch the outputs of the corresponding AD converters ADI1 to ADI3 and ADQ1 to AD3 in accordance with the frequency hopping timing of the received signal by a synchronization circuit (not shown), and the signal of the next symbol is input. Until just before the operation, it operates so as to connect to the output of the AD converter that inputs the reception signal of the previous frequency.

  In the first stage circuit configuration of the digital signal processing unit 3, specifically, as shown in FIG. 2, a frequency correction rotator ROT1 is connected to the outputs of the selectors SEL1 and SEL2, and the frequency correction rotator ROT1 For the outputs of the selectors SEL1 and SEL2, the phase rotation due to the difference between the frequency of the received signal and the corresponding local frequency of the local oscillator Synth is corrected. Each shift register SF1, 2 consists of a shift register having 165 columns, holds data in the data section in the first to 128th columns, and further from the zero (padded) prefix section to the guard interval section. The delayed wave component is held in the 129th to 165th columns. Here, the data of each column from the 129th to the 165th is added to the data of each column from the 1st to the 37th, respectively, and the data after this addition is passed to the signal demodulator 4 to perform FFT (high speed). Fourier transform) process.

  In this embodiment, a shift register having 165 columns is used to store all data from the data interval to the guard interval interval in the shift register, but instead, data is stored. A 37-column shift register can also be used as the shift register. In this case, the 1st to 37th data are stored in the shift register, and the 38th data and subsequent data are sequentially output to the signal demodulator 4. When the 129th to 165th data is output to the signal demodulator 4, the 129th to 165th data is added to the data of the 1st to 37th columns stored in the shift register. However, the signal is output to the signal demodulator 4.

  As described above, according to the present embodiment, the output of each AD converter is switched by the selectors SEL1 and SEL2 so that high-speed switching is possible, and the MB-OFDM reception circuit is used without using a high-speed analog switch. Can be configured.

  Further, it is possible to compensate for the multipath delay wave for a time that is equal to or longer than the sum of the zero padded prefix interval and the guard interval interval.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a block diagram showing a basic configuration of a radio reception apparatus according to the second embodiment of the present invention, and FIG. 4 is a block diagram showing a circuit configuration of the first stage of the digital signal processing unit of FIG. Here, the same devices and blocks as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  As shown in FIG. 3, the wireless reception device according to the present embodiment includes an RF unit 1, a BB unit 2, and a digital signal processing unit 3. The RF unit 1 includes an oscillator Synth that oscillates three local frequencies f1, f2, and f3, and a local switch Lo.1 that selects and outputs two of the three local frequencies f1, f2, and f3. SW. Here, the local frequencies f1, f2, and f3 are frequencies according to the frequency hopping pattern of the received signal, respectively, and the number thereof is set equal to the basic hopping number.

  The BB unit 2 includes two baseband demodulators DEMO1 and 2 for demodulating the reception signal received by the RF unit 1 using the corresponding local frequencies f1, f2, and f3. The AD converters ADI 1 and 2 are connected to the I outputs of the baseband demodulators DEMO 1 and 2 via low pass filters LPF, respectively. AD converters ADQ1 and ADQ2 are connected to the Q outputs of the baseband demodulators DEMO1 and DEMO2 through low-pass filters LPF, respectively.

  The digital signal processing unit 3 includes a selector SEL1 that switches the outputs of the AD converters ADI1 and 2, and a selector SEL2 that switches the outputs of the AD converters ADQ1 and AD2 in accordance with the output switching timing of the AD converters ADI1 and ADI2. . Each selector SEL1, 2 switches the output of the corresponding AD converters ADI1, 2 and ADQ1, 2 in accordance with the frequency hopping timing of the received signal by a synchronizing circuit (not shown), and the signal of the next symbol is input. Until just before the operation, it operates so as to connect to the output of the AD converter that inputs the reception signal of the previous frequency.

  In such a configuration, the local switch Lo. The SW performs a switching operation in accordance with the frequency hopping timing of the received signal by the synchronization circuit. By this switching operation, the local frequency signal corresponding to the center frequency of the currently received signal is transferred to one baseband demodulator. Then, a local frequency signal corresponding to the center frequency of the signal to be received is output to the other baseband demodulator.

  In this way, the local switch Lo. By operating the SW so as to switch the local frequency of the other baseband demodulator while one baseband demodulator is receiving a signal, the data interval from one symbol to the guard interval is reached. The time, that is, the time of about 312.5 ns including the data section of about 242.4 ns, the zero (padded) prefix section of about 60.6 ns, and the guard interval section of about 9.5 ns can be divided into the local frequency switching time. This time is sufficient for the switching time of the high frequency switch.

  In the first stage circuit configuration of the digital signal processing unit 3, specifically, as shown in FIG. 4, a frequency correction rotator ROT1 is connected to the outputs of the selectors SEL1 and SEL2, and the rotator ROT1 is connected to each selector SEL1. , 2, the phase rotation due to the frequency difference between the frequency of the received signal and the corresponding frequency of the local oscillator Synth is corrected. Each shift register SF1, 2 consists of a shift register having 165 columns, holds data in the data section in the first to 128th columns, and further from the zero (padded) prefix section to the guard interval section. The delayed wave component is held in the 129th to 165th columns. Here, the data of each column from the 129th to the 165th is added to the data of each column from the 1st to the 37th, respectively, and the data after this addition is passed to the signal demodulator 4 to perform FFT (high speed). Fourier transform) process.

  As in the first embodiment, a 37-column shift register can be used instead of the shift register.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing a circuit configuration of the first stage of the digital signal processing unit in the wireless reception apparatus according to the third embodiment of the present invention.

  This embodiment is different from the first embodiment in that the digital signal processing unit 3 having a different configuration is provided. Specifically, as shown in FIG. 5, the digital signal processing unit 3 includes three frequency correction rotators ROT1 to ROT3, three shift registers SFI1 to SFI3, three shift registers SFQ1 to 2, And selectors SEL3 and SEL4.

  Each rotator ROT1 to ROT3 inputs the I output and Q output of the corresponding AD converter, and corrects the phase rotation due to the frequency difference between the frequency of the received signal and the corresponding local frequency with respect to the I output and Q output. . The shift registers SFI1 to SFI3 are composed of 192 column shift registers for storing I channel signals of each hopping frequency of the received signal. Similarly, the shift registers SFQ1 to SFQ1 are made up of 192 column shift registers that accumulate Q channel signals of each hopping frequency of the received signal. SEL3 operates to switch to the shift register of the next hopping frequency signal when the head of the I channel signal of each hopping frequency reaches the first column of the shift registers SFI1 to SFI3. When the head of the Q channel signal of the frequency reaches the first column of the shift registers SFQ1 to 3, the operation is performed so as to switch to the shift register of the signal of the next hopping frequency.

  The shift registers SFI1-3 and SFQ1-3 continue to take in signals of each hopping frequency. Here, the shift registers SFI 1 to 3 and SFQ 1 to 3 can also receive a delayed wave after hopping from one frequency to the next frequency unless another piconet performing another hopping exists. Is possible. Further, the shift registers SFI1 to 3 and SFQ1 to 3 can perform compensation up to a delay wave of 64 columns (chips) including the zero (padded) prefix section and the guard interval section, that is, a delay wave of about 121.2 ns. .

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a circuit configuration of the first stage of the digital signal processing unit in the wireless reception apparatus according to the fourth embodiment of the present invention.

  The present embodiment is different from the second embodiment in that a digital signal processing unit 3 having a different configuration is provided. Specifically, as shown in FIG. 6, the digital signal processing unit 3 includes two frequency correction rotators ROT 1 and 2, two selectors SEL 1 and 2, three shift registers SFI 1 to 3, and three shifts. Registers SFQ 1 to 3 and two selectors SEL 3 and 4 are provided.

  Each rotator ROT1, 2 corrects the phase rotation due to the frequency difference between the frequency of the received signal and the corresponding local frequency with respect to the I output and Q output of the corresponding AD converter. Each of the selectors SEL1 and SEL2 performs a switching operation in accordance with the frequency hopping timing of the received signal by a synchronization circuit (not shown) and immediately before the next symbol signal is output to the output of the AD converter. Is connected to the output of the AD converter.

  Each of the shift registers SFI1 to SFI3 is composed of a 192-column shift register that accumulates an I channel signal of each hopping frequency of the received signal. Similarly, the shift registers SFQ1 to SFQ1 are made up of 192 column shift registers that accumulate Q channel signals of each hopping frequency of the received signal. SEL3 operates to switch to the shift register of the next hopping frequency signal when the head of the I channel signal of each hopping frequency reaches the first column of the shift registers SFI1 to SFI3. When the head of the Q channel signal of the frequency reaches the first column of the shift registers SFQ1 to 3, the operation is performed so as to switch to the shift register of the signal of the next hopping frequency.

  Since each of the shift registers SFI1 to 3 and SFQ1 to 3 continues to take in signals of each hopping frequency for 27 columns (chips) after the guard interval, unless there is another piconet performing another hopping, After hopping the received signal from one frequency to the next, it is possible to capture a delayed wave of 27 columns (chips) that is longer than the guard interval interval. Therefore, the shift registers SFI1 to 3 and SFQ1 to 3 can compensate for the influence up to a delay wave of about 121.2 ns, that is, 64 columns (chips) including the zero (padded) prefix period and the guard interval period. . In this case, the local switch Lo. The SW needs to perform switching operation (switching) within about 121.2 ns, but this time is sufficiently longer than the guard interval interval of about 9.5 ns, so switching is surely performed within the above time. It can be performed.

It is a block diagram which shows the basic composition of the radio | wireless receiver which concerns on the 1st Embodiment of this invention. FIG. 2 is a block diagram illustrating a circuit configuration of a first stage of the digital signal processing unit in FIG. 1. It is a block diagram which shows the basic composition of the radio | wireless receiver which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the circuit structure of the first stage of the digital signal processing part of FIG. It is a block diagram which shows the circuit structure of the first stage of the digital signal processing part in the radio | wireless receiver which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the circuit structure of the first stage of the digital signal processing part in the radio | wireless receiver which concerns on the 4th Embodiment of this invention. It is a conceptual diagram which shows the compensation method of a multipath delay wave.

Explanation of symbols

T / R SW transmission / reception switch BPF RF band bandpass filter LNA amplifier Lo.SW local switch Synth oscillator DEMO1-3 baseband demodulator LPF lowpass filter ADI1-3, ADQ1-3 AD converter SEL1-4 selector SF1-2 SFI 1-3, SFQ 1-3 Shift register

Claims (6)

A wireless receiver of a multiband orthogonal frequency division multiplexing system,
Local oscillation means for oscillating a plurality of local frequencies according to the frequency hopping pattern of the received signal;
A plurality of baseband demodulation means provided in association with the plurality of local frequencies, respectively, for demodulating a received signal using the associated local frequencies;
I output switching means for switching and outputting the respective I outputs of the baseband demodulation means according to the timing of frequency hopping of the received signal;
Q output switching means for switching and outputting the respective Q outputs of the baseband demodulation means in synchronization with the switching timing of the I output changing means;
A radio receiving apparatus comprising: data demodulating means for demodulating data based on each of the output of the I output switching means and the output of the Q output switching means. A wireless receiver of a multiband orthogonal frequency division multiplexing system,
Local oscillation means for oscillating a plurality of local frequencies according to the frequency hopping pattern of the received signal;
Two baseband demodulation means for demodulating the received signal using a given local frequency;
Frequency selecting means for selecting a local frequency to be given to each of the baseband demodulating means from among the plurality of local frequencies so that each of the baseband demodulating means alternately demodulates received signals of different hopping frequencies;
I output switching means for switching and outputting the respective I outputs of the baseband demodulation means according to the timing of frequency hopping of the received signal;
Q output switching means for switching and outputting the respective Q outputs of the baseband demodulation means in synchronization with the switching timing of the I output switching means;
A radio receiving apparatus comprising: data demodulating means for demodulating data based on each of the output of the I output switching means and the output of the Q output switching means.   When the frequency selection means selects a local frequency corresponding to the received signal of the current hopping frequency as the local frequency to be given to one of the baseband demodulation means, the next hopping is given as the local frequency to be given to the other of the baseband demodulation means When a local frequency corresponding to the received signal of the frequency is selected and demodulation of the received signal of the next hopping frequency is started by the other of the baseband demodulating means, the local frequency given to one of the baseband demodulating means is further 3. The radio receiving apparatus according to claim 2, wherein a local frequency corresponding to a received signal having a hopping frequency is selected. A plurality of first analog / digital conversion means respectively connected to the respective I outputs of the baseband demodulation means;
A plurality of second analog / digital conversion means respectively connected to the respective Q outputs of the baseband demodulation means;
The I output switching unit switches and outputs each output of the first analog / digital conversion unit, and the Q output switching unit switches and outputs each output of the second analog / digital conversion unit. The wireless reception device according to claim 1, wherein the wireless reception device is a wireless communication device. I output accumulation means for accumulating the output of the I output switching means for at least the time obtained by adding the zero padded prefix interval and the guard interval interval;
Q output accumulating means for accumulating the output of the Q output switching means for at least the time obtained by adding the zero padded prefix interval and the guard interval interval;
Of the outputs from the I output switching means, the outputs corresponding to at least the zero padded prefix interval and the guard interval interval are added to the output accumulated in the I output accumulation means and output to the data demodulation means. I output addition means;
Of the outputs of the Q output switching means, the outputs corresponding to at least the zero padded prefix interval and the guard interval interval are added to the output accumulated in the Q output accumulation means and output to the data demodulation means. 5. The radio receiving apparatus according to claim 4, further comprising Q output adding means. A plurality of first analog / digital conversion means respectively connected to the respective I outputs of the baseband demodulation means;
A plurality of second analog / digital conversion means respectively connected to the respective Q outputs of the baseband demodulation means;
A plurality of I output accumulation means for accumulating outputs corresponding to at least the data interval, the zero padded prefix interval, and the guard interval interval among the respective outputs of the first analog / digital conversion means;
A plurality of Q output accumulation means for accumulating outputs corresponding to at least the data interval, the zero padded prefix interval, and the guard interval interval among the outputs of the second analog / digital conversion means;
The I output switching unit switches and outputs each output of the I output accumulation unit, and the Q output switching unit switches and outputs each output of the Q output accumulation unit. 3. The wireless receiving device according to 1 or 2.

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