JP2006018656A - Microcomputer system, semiconductor device and wireless tag - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer system capable of satisfying demands for microcomputer systems used for ubiquitous computing, or ensuring security as well as reduction in power consumption. <P>SOLUTION: This system comprises a processing unit 101 performing system control, a RAM block 103 storing programs and data, a ROM 102 storing fixed programs for system control, an input exclusive port 106 for fetching an application program stored in the RAM block 103, an input and output port 107 for transmitting and receiving data and control signals to and from an external device 110, and a built-in battery 108 for supplying power to at least the processing unit 101, the RAM block 103 and the ROM 102. The processing unit 101 prohibits the operation of the input exclusive port 106 after fetching the application program to the RAM block 103. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a low power consumption microcomputer system incorporating a battery that can be used in a small electronic device such as a wireless tag, and more particularly to a microcomputer system with enhanced security functions for application programs and data held in the system. .

  Ubiquitous computing is attracting attention as a next-generation information technology. It is expected that a miniaturized microcomputer system will be incorporated into everything around us. As one form of this, a wireless tag for identifying an object without contact has been developed.

  A wireless tag is a tag that is attached to a product or the like, and stores attribute information such as an identification number (ID) and price of the product in a built-in nonvolatile memory. In addition, a name, an address, sex, etc. may be recorded in the nonvolatile memory as personal information data. In recent years, application programs can be stored in a non-volatile memory and executed to improve convenience. The wireless tag has an advantage that it does not require a complicated protocol or encryption processing with high power consumption and can easily reduce power consumption.

  As an example of the wireless tag, a schematic block configuration of the wireless tag disclosed in Patent Document 1 shown below is shown in FIG. In addition, this wireless tag transmits and receives data and the like by non-contact communication using electromagnetic induction. FIG. 7 shows an ASK (Amplitude Shift Keying) modulation communication waveform used in the wireless tag. As shown in FIG. 6, the wireless tag unit 610 disclosed in Patent Document 1 includes a CPU 601, a nonvolatile memory 602, a power supply circuit 605, an I / O unit 608, and an RF antenna 609. The I / O unit 608 includes a modulation circuit 603, a demodulation circuit 604, and a radio frequency (RF) circuit 606, and circuit portions other than the RF antenna 609 of the wireless tag unit 610 are configured by a semiconductor device 607. Yes. The radio communication wave used for data transmission / reception has a 13.56 MHz carrier wave, and the communication data is superimposed on the carrier wave by ASK amplitude modulation. The modulation degree of ASK amplitude modulation is as low as about 10%.

  When the wireless tag is placed in a magnetic field generated by an external device such as a reader / writer device, AC power is generated by the resonance action of the RF antenna 609. This AC power is rectified by a rectifier circuit in the power supply circuit 605 and supplied to an internal circuit in the semiconductor device 607.

  In the I / O unit 608, when the communication data generated by the processing of the CPU 601 is transmitted to an external device, the communication data is load-modulated by the modulation operation of the modulation circuit 603 and output. Conversely, when communication data is received from the RF antenna 609, the demodulation waveform of the demodulation circuit 604 detects the amplitude of the communication waveform. When the modulation degree is 10%, “1” is set if the amplitude is 100%. If 90%, communication data is demodulated by assigning “0”. A radio frequency (RF) circuit 606 switches data communication input / output.

  Data demodulated by the demodulation circuit 604 (including application program data) is stored in the nonvolatile memory 602 by processing of the CPU 601.

  However, a wireless tag cannot always receive stable power because it receives power supply via a medium called radio waves. In addition, since the power supply voltage obtained from the RF antenna 609 depends on the distance to the external device (reader / writer), there is a possibility that the power becomes weak when the distance is increased. Therefore, the system used for the wireless tag and its components need to have low power consumption so that it can operate even with somewhat unstable and weak power.

At the same time, it is necessary to secure the attribute information such as the identification number (ID) and price of the item stored in the wireless tag, personal information such as name, address and sex, and the security of the application program written in the wireless tag. There is.
JP 2002-197429 A

  A microcomputer system used for ubiquitous computing typified by the above-described wireless tag has a demand for low power consumption and security, and a microcomputer system that satisfies these requirements at the same time is required.

  However, the current microcomputer system has the following problems. First, the non-volatile memory used in these microcomputer systems can be made to be non-operating during standby so that its power consumption can be close to “0” and retain written data. Is possible. However, there is a problem that power consumption during writing or reading is relatively large. In a flash memory widely used as a nonvolatile memory, the peak current is about several tens of mA. When used in a wireless tag, operation under weak power is a problem. Further, the communication distance of the wireless tag varies depending on the power consumption, and there is a problem that the communication distance is shortened when the power consumption is large.

  Secondly, as a security problem, when a product is discarded, the discarded product may be used by a third party. These products may be used for other purposes by rewriting application programs and data, or may be abused in some cases.

  Third, when the product is discarded, there is a problem that the application program remains in the product. In this case, the application program and data may be leaked or leaked, which is not preferable in terms of security. Therefore, when the product is discarded, there is a problem that an appropriate measure for ensuring security (hereinafter referred to as “reject processing”) must be performed.

  In the wireless tag disclosed in Patent Document 1 described above, these problems are not considered at all, and the problems exist.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a microcomputer system used for ubiquitous computing, that is, a microcomputer system capable of ensuring security while reducing power consumption. The point is to provide.

  In order to achieve the above object, a microcomputer system according to the present invention includes a processing unit that performs system control, a RAM block that stores programs and data, a ROM that stores fixed programs for system control, and the RAM block. An input-only port for capturing an application program to be stored, an input / output port for transmitting / receiving data and control signals to / from an external device, and for supplying power to at least the processing unit, the RAM block, and the ROM And a built-in battery, wherein the processing unit prohibits the operation of the input-only port after fetching the application program.

  With the configuration of the first feature described above, the application program is written into the program storage RAM through the input-only port at the time of manufacturing, and after the processing is performed, the processing unit sets the operation of the input-only port to the prohibited state. By blocking the access path from the application program to the application program, the application program can be prevented from being rewritten, leaked or leaked.

  In the first feature, a RAM block driven by a built-in battery is used as a means for storing a program and data, so that a large amount of power is consumed during writing or erasing as in a conventionally used flash memory. In addition, it is possible to simultaneously satisfy the requirements of the non-volatility and low power consumption of stored data.

  Further, by adopting a configuration in which the application program is written in the RAM block, the system can be given flexibility and the program can be easily changed at the manufacturing stage. Even if the contents of the application program are not decided at the beginning of the manufacturing stage, it is possible to write the application program in the final process of manufacturing, and manufacturing and application program development proceed in parallel, resulting in a shorter product delivery time. Is possible.

  In recent years, batteries built in and utilized in microcomputer systems have become smaller and thinner (thickness: about 1.5 mm). Some of them have a power capacity exceeding 500 mAh (2.5 V termination voltage) in the 3.0 V specification despite being small. These batteries can be used for small electronic devices such as wireless tags, and since there is no wireless power supply from the outside, the communication distance can be stably increased. Therefore, in the first feature, the problem of the communication distance at the time of wireless power supply can be solved by using the built-in battery.

  The input / output port in the configuration of the first feature is configured by a combination of at least two types of input / output terminals, input terminals, and output terminals, or configured by only the input / output terminals. Is assumed.

  In the microcomputer system according to the present invention, in addition to the first feature, after the processing unit fetches the application program, at least the storage area of the RAM block storing the application program is in a write-inhibited state. The second feature is to make it.

  According to the configuration of the second feature, writing of the application program can be performed according to the use by prohibiting writing of at least the storage area storing the application program in the RAM block, and read-only after writing. It becomes possible to function as a memory, and the application program written in the RAM block can be more reliably protected. For example, it is possible to protect the program from being tampered with by a malicious third party, and furthermore, an application program against inadvertent writing such as when the power supply voltage becomes unstable due to exhaustion of the built-in battery, etc. Can be safe. In addition, during the period when power is supplied from the built-in battery, at least the storage area of the RAM block storing the application program can be functionally used as a read-only memory. In order to execute the application program, the CPU control can be transferred from the ROM to the program storage RAM and executed. By adopting the configuration of the second feature, it is possible to reduce the power consumption as described above as compared with the case where a nonvolatile memory such as a flash memory is employed. Furthermore, the use of the ROM is limited to the storage of the control program of the microcomputer system such as the execution control of the application program, and the application program is stored in the RAM block. Can be changed and flexible application is possible depending on the application.

  In the microcomputer system according to the present invention, in addition to the first feature, the RAM block includes at least a first RAM and a second RAM, and the processing unit responds to a request from the first external device. The first processing program forming a part of the fixed program is executed, the application program is fetched via the input dedicated port and stored in the first RAM, and then the operation of the input dedicated port and the first RAM are performed. The first RAM operates as a read-only program memory after the write operation is prohibited, and the processing unit loads the first RAM in response to a request from the second external device. Executing the stored application program and storing the data generated by the execution in the second RAM; And butterflies.

  According to the configuration of the third feature, the configuration of the second feature can be more specifically realized, and the effects of the first and second features can be achieved.

  In the microcomputer system according to the present invention, in addition to the third feature, the processing unit executes a second processing program forming a part of the fixed program, and the number of times the application program is used is The program and data stored in the first RAM and the second RAM just before or just after reaching the life cycle derived from the accumulated power consumption of the entire system determined from the number of times and the power capacity of the built-in battery. The fourth feature is to forcibly reset by means.

  According to the configuration of the fourth feature, the life cycle of the microcomputer system according to the present invention can be grasped, and the system can be safely discarded after the rejection process for ensuring security. In addition, when creating an application program by incorporating a program that calculates the life cycle into the second processing program that forms part of the fixed program, the application program creator must create the program without worrying about the life cycle calculation process. Can do.

  By the way, in the case where the first RAM and the second RAM are configured by a static random access memory, which will be described later, when the built-in battery is consumed and the output voltage is lowered, the processing unit such as the CPU becomes inoperable. In some cases, the first RAM and the second RAM can hold stored data in the low power supply voltage state. Therefore, even if the life cycle of the system is completed, there is a high possibility that the first RAM and the second RAM still function as nonvolatile memories. According to the configuration of the fourth feature, the reject process for the first RAM and the second RAM can be reliably executed during the life cycle period in which the processing unit can operate. It can be surely prevented.

  In addition to any of the above features, the microcomputer system according to the present invention forms the processing unit, the RAM block, the ROM, the input-only port, and the input / output port on a single semiconductor substrate. This is a fifth feature.

  According to the configuration of the fifth feature, the microcomputer system can be constructed as a small electronic device by configuring functional blocks such as processing units as semiconductor devices. Furthermore, the RAM block can be used as a writable memory that consumes very little power while being nonvolatile.

  The microcomputer system according to the present invention is characterized in that, in addition to any of the above features, the RAM block comprises a static random access memory.

  According to the configuration of the sixth feature, a large power consumption is not required at the time of writing or erasing operation, and furthermore only a leakage current is generated in the standby state, so that the power consumption at the standby time is substantially eliminated. Therefore, the RAM block can be used as a writable memory with extremely low power consumption while being nonvolatile.

  In the microcomputer system according to the present invention, in addition to any one of the features described above, the input / output port is configured to be capable of wirelessly transmitting and receiving data and control signals to and from the external device. Features.

  According to the configuration of the seventh feature, the microcomputer system according to the present invention can be constructed as a wireless tag.

  According to another aspect of the present invention, there is provided a semiconductor device including: the processing unit, the RAM block, the ROM, the input-only port, and the input / output port in a microcomputer system having any one of the above features on a single semiconductor substrate. It is formed by the following. Furthermore, a wireless tag according to the present invention includes the microcomputer system having the seventh feature.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a microcomputer system according to the present invention (hereinafter referred to as “the present system” as appropriate) will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 schematically shows the basic configuration of the system of the present invention. As shown in FIG. 1, the system 100 of the present invention is battery driven by a built-in battery 108, and the battery 108 is built (sealed) in a housing (package) of the system 100 of the present invention. The power of the system 100 of the present invention is not supplied from other than the battery 108, and there is no means for replacing the battery 108. In addition to loading the battery 108 in the manufacturing stage, there is no charging by a charger or the like, or power supply by a solar cell or the like, that is, no energy supply from the outside. In the system 100 of the present invention, electric power is constantly supplied from the built-in battery 108 during its life cycle. As described above, the battery 108 is preferably sealed inside the system as described above in order to prevent malicious reuse due to external power supply after the battery is replaced or removed.

  As shown in FIG. 1, the system 100 of the present invention includes, as functional blocks, a processing unit 101 such as a CPU that controls the system 100 of the present invention, and a ROM 102 that stores a fixed program for system control executed on the processing unit 101. And a RAM block 103 for storing application programs and data to be executed on the processing unit 101. Accordingly, the processing unit 101 is controlled for system control by a fixed program stored in the ROM 102, and the processing unit 101 is controlled for a specific application by an application program stored in the RAM block 103. Yes.

  The RAM block 103 is divided into a first RAM 104 that stores application programs and a second RAM 105 that stores data of processing results of the application programs. The first RAM 104 has a function of prohibiting writing, and can be functionally operated as a read-only memory by constantly supplying current from the built-in battery 108. Further, the stored content can be erased by a reset signal connected to the RAM block 103.

  Furthermore, the system 100 of the present invention transmits and receives data and control signals between the input external port 106 for taking in the application program stored in the RAM block 103 from the first external device 109 and the second external device 110. For this purpose, an input / output port 107 is provided. The first external device 109 is an external device that assumes general-purpose tester evaluation at the time of manufacture and evaluation with a PROM writer, and the second external device 110 has a use environment (transmission / reception device etc.) of the system 100 of the present invention. This is an assumed external device. The functional blocks 101 to 103, the input dedicated port 106, and the input / output port 107 are connected to each other via the data bus 111. In FIG. 1, description of an address bus, a control signal bus, and the like between the functional blocks 101 to 103 is omitted.

  The input dedicated port 106 and the input / output port 107 are not particularly limited in the form of an interface such as serial or parallel (in some cases, there is an analog input / output or a non-contact communication form). Adopt the interface shown.

  In this embodiment, the functional blocks 101 to 103 other than the battery 108 of the system 100 of the present invention, the input dedicated port 106, and the input / output port 107 are formed on a single semiconductor substrate and configured as a semiconductor device. If a part other than the battery 108 of the system 100 of the present invention is configured in a semiconductor device, there is no extra power consumption in the connection between the functional blocks, and the power consumption can be further reduced, and a small electronic device can be configured. In addition, you may be the form which comprises parts other than the battery 108 of this invention system 100 on board | substrates, such as a printed circuit board.

  The input-only port 106 is an interface for reading an application program into the first RAM 104 by using a general-purpose tester or the like at the time of manufacture. When the system 100 of the present invention has restrictions on terminals, a UART or the like having only a reception function is used. The serial communication port can be used. From the first external device 109 such as a general-purpose tester, application program data is serially transmitted in accordance with the UART communication format, and is sequentially written into the internal register (internal buffer) of the input-only port 106. The processing unit 101 executes the first processing program (part of the fixed program) recorded in the ROM 102 to sequentially transfer the internal register data (application program) of the input-only port 106 to the first RAM 104. Store.

  As described above, the ROM 102 stores control programs such as data input, writing to the RAM block 103, and erasure. Furthermore, by adopting a configuration in which the application program is input from an external device, the application (use) of the system 100 of the present invention is not fixed.

  When the application program data is completely written to the first RAM 104, the control register 112 is set to the operation prohibited state from the processing unit 101, and the input dedicated port 106 is set by the operation prohibition signal output from the control register 112. It is possible to prohibit the operation of

  The input / output port 107 is used as a port for performing communication with the second external device 110 such as a transmission / reception device. When the second external device 110 requires serial communication, a serial communication port such as UART is used. Is available. By executing the application program, it is possible to control the input / output port 107 from the processing unit 101, perform data communication with the second external device 110, and store data as a result of the data communication in the second RAM 105. Is possible.

  FIG. 2 shows a procedure for writing an application program at the time of manufacture. The writing process is preferably incorporated into the final process of the hardware test at the time of manufacture. By describing the operation of the system 100 of the present invention along the write processing procedure, the functions and operations of the respective functional blocks 101 to 103 in the system 100 of the present invention will become clearer.

  In the processing procedure shown in FIG. 2, from the initial setting mode (steps S11 to S16) for storing the application program in the first RAM 104, the standby mode (step S11 to S16) is completed and the system 100 of the present invention is shifted to the standby state. The description up to S17) will be made.

  In step S11, a clock is supplied from the first external device 109 via a clock terminal. Next, the test mode is entered by setting the TEST terminal to “H” (high level). At this time, the input-only port 106 is activated.

  In step S12, the system 100 of the present invention performs a predetermined test in the test mode. These are equivalent to a general hardware test, and the functional blocks of the processing unit 101, the ROM 102, the RAM block 103, the input dedicated port 106, and the input / output port 107 are tested by a self test. Since the details of the test are not directly related to the purpose of the present application, the description is omitted here.

  In step S13, a command indicating the start of application program transfer is transmitted from the first external device 109 such as a general-purpose tester. When the processing unit 101 receives this command through the input-only port 106, the processing unit 101 starts executing the first processing program stored in the ROM 102 and prepares to receive the application program to be transferred stored in the first RAM 104. .

  In step S14, the application program data is sequentially transmitted from the first external device 109 such as a general-purpose tester in accordance with the UART format and is temporarily stored in a register (internal buffer) in the input-only port 106. The application program data stored in the register by the first processing program in the ROM 102 is sequentially written to a predetermined address in the first RAM 104. When the writing of the application program is completed, the first processing program in the ROM 102 executes the following steps S15, S16, and S17.

  In step S15, the operation of the input-only port 106 is prohibited. The input-only port 106 is deactivated by register control from the processing unit 101.

  In step S16, the writing function to the first RAM 104 is prohibited. At this point, the first RAM 104 becomes a read-only memory.

  In step S17, the system 100 of the present invention is set to the standby mode.

  In step S18, by setting the TEST terminal = “L” (low level), the system 100 of the present invention is released from the test mode and enters the normal operation mode.

  Next, a rejection process of an electronic device (product) configured by the system 100 of the present invention will be described.

  FIG. 4 shows a power consumption model in the system 100 of the present invention. In this power consumption model, P1 is defined as the power consumption amount in the initial setting mode, P2 is defined as the power consumption amount in the standby (HALT) mode, and P3 is defined as the power consumption amount for one operation of the system 100 of the present invention. Yes.

The total power consumption _PT consumed by the system 100 of the present invention during the life cycle period can be expressed by the following formula 1. Note that N in Equation 1 represents the total number of operations (life cycle) of the system 100 of the present invention.

(Equation 1)
P _T = P1 + P2 × N + P3 × N

  Here, the power consumption amount P1 in the initial setting mode and the power consumption amount P3 required for one operation of the system 100 of the present invention can be determined depending on the actual use situation through product evaluation or the like.

  The power consumption P2 in the standby (HALT) mode is sufficiently small with respect to the power capacity (Wh) converted from the current capacity (Ah) of the battery 108 in today's low-consumption microcomputer. When a static random access memory is used, only the leakage current contributes to power consumption in the standby mode, so that it can be handled as P2 = 0 substantially.

From the above, when the total power consumption _PT consumed during the life cycle period given by Equation 1 becomes equal to the initial power capacity P _B of the battery 108, the life cycle period ends. N is given by Equation 2 below.

(Equation 2)
N = (P _B −P1) / P3

  Therefore, the life cycle N can be determined depending on the actual use situation from the evaluation of the allowable current capacity of the battery 108 and the power consumption amounts P1 and P3 of the system 100 of the present invention. In this processing, a program for counting the number n of times the application program has been used is incorporated in the second processing program that forms part of the fixed program stored in the ROM 102, and the number n is equal to the life cycle N. Alternatively, when it becomes larger, the end of the life cycle period is determined, and an application program stored in the first RAM 104 and the second RAM 105 and an erase program for erasing data as a result of the execution are executed.

  FIG. 3 shows a processing procedure for determining the life cycle N and erasing the application program and the data that is the result of the execution.

  In step S21, the application program is executed by being connected to the second external device 110.

  In step S22, a program corresponding to the specification of the application program stored in the first RAM 104 is executed.

  In step S23, when the application program ends, the control of the processing unit 101 is transferred from the first RAM 104 to the ROM 102, and the second processing program is executed.

  In step S24, the number of uses n is counted. The count number is stored in a register in the processing unit 101 and is counted up each time it is used.

  In step S25, the life cycle number N determined in advance and recorded in the application program is compared with the counted number n of use. If the use count n value is less than or equal to the life cycle number N, the control of the processing unit 101 is returned from the ROM 102 to the first RAM 104 in step S27 to enter the standby mode (HALT) state, and the next request from the second external device 110 Wait for. If the use count n is larger than the life cycle number N, the RAM block 103 (including the first RAM 104 and the second RAM 105) is erased using a reset signal in step S26.

  As described above, by erasing the data in the RAM block 103 before discarding the product, a rejection process can be performed and security can be ensured.

Second Embodiment
Next, a second embodiment of the system of the present invention will be described. In the second embodiment, the system of the present invention is applied to a wireless tag. Further, the effectiveness when the system of the present invention is used for a wireless tag will be described together.

  The wireless tag is used for a tag or the like, and for example, personal information such as name, address, and gender is recorded. In addition, a record of the transportation route of the luggage, for example, a transportation time, a transportation route, and transportation means are recorded. Such information (confidential data) is transmitted and received between the handheld or stationary reader / writer device (corresponding to the second external device 110 in FIG. 1) and the wireless tag. Since it is difficult to bring the wireless tag attached to the luggage and the reader / writer device close to each other, it is preferable that the communication distance is long. In addition, security is important in the wireless tag, and management of personal information recorded in the wireless tag memory (corresponding to the second RAM 105 in FIG. 1), falsification of the transportation route, etc., and wireless tag memory (in FIG. It is necessary to protect the application program written in 1 RAM 104).

  FIG. 5 shows a schematic configuration of a system 500 of the present invention in a second embodiment suitable for a wireless tag. In FIG. 5, the same components as those in the first embodiment are described with the same reference numerals.

  In the second embodiment, instead of the input / output port 107 in the first embodiment shown in FIG. 1, a wireless communication using, for example, ASK amplitude modulation, which includes a modulation circuit 501, a demodulation circuit 502, a communication circuit 503, and an RF antenna 504. I / O port 507 is provided. Here, since the system 500 of the present invention incorporates the battery 108 as in the first embodiment, it is not necessary to provide a power supply circuit for power supply by electromagnetic induction at the input / output port 507.

  As shown in FIG. 5, the system 500 of the present invention includes, as functional blocks, a processing unit 101 such as a CPU that controls the system 500 of the present invention, and a ROM 102 that stores a fixed program for system control executed on the processing unit 101. And a RAM block 103 for storing application programs and data to be executed on the processing unit 101. Accordingly, the processing unit 101 is controlled for system control by a fixed program stored in the ROM 102, and the processing unit 101 is controlled for a specific application by an application program stored in the RAM block 103. Yes.

  The RAM block 103 is divided into a first RAM 104 that stores application programs and a second RAM 105 that stores data of processing results of the application programs. The first RAM 104 has a function of prohibiting writing, and can be functionally operated as a read-only memory by constantly supplying current from the built-in battery 108. Further, the stored content can be erased by a reset signal connected to the RAM block 103.

  The input-only port 106 is an interface for writing an application program to the first RAM 104 using a general-purpose tester or the like at the time of manufacture, and is a serial communication port such as UART having only a reception function.

  The power supply voltage of the system 500 of the present invention is supplied from the battery 108. The electric power from the battery 108 is constantly supplied to the system 500 of the present invention including the RAM block 103. Thereby, the application program written at the time of manufacture is not erased. In addition, since the power supply by electromagnetic induction is not received, the communication distance can be as long as the radio waves for data communication reach. Accordingly, it is possible to secure a communication distance between the wireless tag attached to the luggage and the reader / writer device (second external device 110).

  When transmitting communication data, the processing unit 101 sets data in the communication circuit 503. The transmission data is load-modulated by the modulation circuit 501 and output from the antenna 609. When receiving communication data from the RF antenna 504, the communication data is demodulated by detecting the amplitude of the communication waveform by the demodulation operation of the demodulation circuit 502. As shown in FIG. 7, in the case of binary assignment, “1” is assigned if the amplitude is 100%, and “0” is assigned if the amplitude is 90%. The demodulated data is received by the communication circuit 503 and then transferred and stored in the second RAM 105 of the RAM block 103 by the processing unit 101 under the control of the application program stored in the first RAM 104. The above modulation / demodulation method is based on the ISO 14443 standard.

  Since writing to the second RAM 105 consumes less power than writing to the nonvolatile memory, voltage stabilization is achieved and the system is further stabilized. When the RAM block 103 is a static random access memory, a large amount of power is not consumed at the time of writing and erasing, and only a leakage current is generated at the time of standby. It can be set to “0”. As a result, the life cycle of the system can be easily grasped and the rejection process can be performed.

  FIG. 8 shows a classification based on events that occur during the life cycle of the wireless tag. The period from manufacture to reject processing is divided into four stages of manufacture (T1), shipment (T2), operation (T3), and reject processing (T4).

  In the manufacturing stage (T1), a hardware test after manufacturing and writing of an application program are performed. In this process, the application program can be written by the processes from step S11 to step S18 shown in FIG. Further, after the application program is written, the operation of the input-only port 106 is prohibited to improve the security, and further, the application program can be surely protected by prohibiting the writing to the first RAM 104. .

  In the shipping stage (T2), the battery is sealed, and power is constantly supplied to the system 500 of the present invention.

  In the operation stage (T3), the number of times the wireless tag is used is determined from the number of times of writing from the reader / writer device in the transport route. The number of times of writing is determined at the installation location of the reader / writer device in the transport route.

  In the reject processing stage (T4), when the transportation is completed, the reject processing is performed. The reject process can be executed by the processing procedure shown in FIG. Since the application program and confidential data can be erased when the number of writes exceeds the number of times when the transportation is completed, security is ensured.

1 is a block diagram schematically showing a basic configuration of a microcomputer system according to the present invention. 6 is a flowchart showing a procedure for writing an application program when manufacturing the microcomputer system according to the present invention. The flowchart which shows the process sequence which determines the end time of the life cycle period in the microcomputer system based on this invention, and erase | eliminates the memory data of RAM block The figure which shows the time transition of the power consumption model and power consumption in the microcomputer system which concerns on this invention The block diagram which shows schematically the structure at the time of applying the microcomputer system which concerns on this invention to a wireless tag Block diagram showing a configuration example of a conventional wireless tag Waveform diagram showing ASK modulation communication waveform used in wireless tag The figure explaining the life cycle at the time of applying the microcomputer system concerning this invention to a wireless tag

Explanation of symbols

100 Microcomputer System 101 Processing Unit 102 ROM According to the Present Invention
103 RAM block 104 First RAM
105 Second RAM
106 Input Dedicated Port 107 Input / Output Port 108 Battery 109 First External Device 110 Second External Device 111 Data Bus 112 Control Register 500 Wireless Tag (Microcomputer System According to the Present Invention)
501 Modulation circuit 502 Demodulation circuit 503 Communication circuit 504 RF antenna 507 Input / output port 601 CPU
602 Nonvolatile memory 603 Modulation circuit 604 Demodulation circuit 605 Power supply circuit 606 Radio frequency (RF) circuit 607 Semiconductor device
608 I / O unit 609 RF antenna 610 Wireless tag unit

Claims (9)

A processing unit for system control;
A RAM block for storing programs and data;
ROM for storing fixed programs for system control;
An input-only port for capturing an application program stored in the RAM block;
An input / output port for transmitting and receiving data and control signals to and from an external device;
At least the processing unit, the RAM block, and a built-in battery for supplying power to the ROM,
The microcomputer system, wherein the processing unit prohibits the operation of the input-only port after taking in the application program.   2. The microcomputer system according to claim 1, wherein the processing unit further sets at least a storage area storing the application program in the RAM block to a write-inhibited state after taking in the application program. The RAM block includes at least a first RAM and a second RAM,
The processing unit executes a first processing program forming a part of the fixed program in response to a request from the first external device, and takes in the application program via the input-only port. , The operation of the input-only port and the write operation to the first RAM are prohibited,
The first RAM operates as a read-only program memory after the write operation is prohibited,
The processing unit executes the application program stored in the first RAM in response to a request from a second external device, and stores data generated by the execution in the second RAM. Item 2. The microcomputer system according to Item 1.   The processing unit executes a second processing program that forms part of the fixed program, and the number of uses of the application program is determined from the number of uses. 4. The program and data stored in the first RAM and the second RAM are forcibly reset by hardware means immediately before or after the life cycle derived from the capacity is reached. Microcomputer system.   5. The processing unit, the RAM block, the ROM, the input-only port, and the input / output port are formed on a single semiconductor substrate. A microcomputer system according to 1.   6. The microcomputer system according to claim 1, wherein the RAM block includes a static random access memory.   The microcomputer system according to claim 1, wherein the input / output port is configured to be able to wirelessly transmit and receive data and control signals to and from the external device.   The processing unit, the RAM block, the ROM, the input-only port, and the input / output port in the microcomputer system according to claim 1 are formed on a single semiconductor substrate. A semiconductor device characterized by comprising:   A wireless tag comprising the microcomputer system according to claim 7.

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