JP2006018610A - Digital data processing card and method for controlling digital data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital data processing card that transmits an interrupt signal to a digital data processing host device in response to some cause of an interruption generated depending on an application program, thereby processing the cause of the interrupt. <P>SOLUTION: The digital data processing card includes a host interface control part in communication with the host device; at least one application module that generates the cause of an interruption requesting an interruption process; an interruption cause selecting part for setting at least one interruption cause selection register to set whether or not the interruption process based on the cause of the interruption is permitted; and an interruption signal control part that outputs an interruption signal to the host device through a host interface according to the occurrence of the cause of the interruption and the set condition of the interruption cause selection register that corresponds to the cause of the interruption. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital data processing card and a control method for a digital data processing system.

In recent years, digital devices such as personal computers and AV (Audio Visual) devices have become widespread. Digital data processing cards that add various functions to these digital data devices have become widespread and common. For example, digital audio data or the like can be recorded in a semiconductor memory built in a digital data processing card and can be reproduced by a portable digital data processing host device.
In addition, digital data processing cards having expanded functions have been introduced by incorporating various applications into the digital data processing card. As the functions of the digital data processing card are diversified, various kinds of information are transmitted and received between the digital data host device and the digital data processing card.

A conventional digital data processing system having a digital data processing host device 200 and a digital data processing card 900 will be described with reference to FIG. FIG. 9 is a functional block diagram of a conventional digital data processing system.
The digital data processing system of FIG. 9 performs master-slave communication using the digital data processing host device 200 as a master and the digital data processing card 900 as a slave in a synchronous method. The digital data processing card 900 and the digital data processing host device 200 send and receive data (command, response, partial data) for controlling the digital data processing card 900, such as application data. Connected by signal lines composed of four data signal lines (DATA [3: 0]) for transmitting and receiving data and a clock signal line (CLK) for transmitting a clock serving as a reference signal such as a command signal or a data signal The application data is transmitted and received.

In FIG. 9, the digital data processing host device 200 includes a card interface control unit 151, an interrupt signal receiving unit 152, a host control unit 153, an application data processing unit 154, and an interrupt release signal generating unit 155.
The digital data processing card 900 includes an application module 110, a card control unit 111, an application data control unit 112, an interrupt signal control unit 913, a host interface control unit 115, a data storage control unit 118, and a data storage unit 119.

Each functional block of the digital data processing host device 200 will be described. The host control unit 153 controls the entire digital data processing host device 200. The application data processing unit 154 controls the entire digital data processing system with respect to execution of applications. The application data processing unit 154 transmits a command and data to be processed (referred to as “processed application data”) to the digital data processing card 900 through a signal line such as a command signal line. The processing result (referred to as “processing result application data”) is acquired. The application data to be processed may be input to the digital data processing card 900 from another external device.
The card interface control unit 151 communicates with the digital data processing card 900 through a signal line such as a command signal line. The interrupt signal receiving unit 152 detects the interrupt signal transmitted from the digital data processing card 900 and transmits it to the host control unit 153. The interrupt release signal generation unit 155 generates an interrupt release signal after the digital data processing host device 200 acquires the processing result application data from the digital data processing card 900.

Each functional block of the digital data processing card 900 will be described. The card control unit 111 controls each block in the digital data processing card 900. The host interface control unit 115 communicates with the digital data processing host device 200 through a signal line such as a command signal line. The interrupt signal control unit 913 generates an interrupt signal based on a command from the application data control unit 112.
The application module 110 inputs and processes application data to be processed based on a command from the card control unit 111, and outputs processing result application data.
The application data control unit 112 transmits the processed application data transmitted from the digital data processing host device 200 to the application module 110, stores the processing result application data generated by the application module 110 in the data storage unit 119, and stores the data The processing result application data read from the unit 119 is transmitted to the digital data processing host device 200. The data accumulation control unit 118 performs input / output control of the data accumulation unit 119. The data storage unit 119 stores various data.

Next, the operation of the digital data processing system configured as described above will be described. An operation in which the digital data processing card 900 receives processed application data corresponding to the built-in application module 110 and transmits processing result application data to the digital data processing host device 200 will be described.
When the card control unit 111 receives the processed application data corresponding to the built-in application module 110, the card control unit 111 transmits the received processed application data to the application module 110. The application module 110 inputs and processes corresponding application data to be processed, and generates processing result application data.

The application data control unit 112 inquires of the data storage control unit 118 whether the data storage unit 119 can store the processing result application data. When the data storage unit 119 can store the processing result application data, the data storage control unit 118 generates a data write control signal and stores the processing result application data in the data storage unit 119 using the data write control signal. To do.
The application data control unit 112 accumulates the application data to be processed in the data accumulation unit 119, and then sends a command to the interrupt signal control unit 913 to activate interrupt processing. The interrupt signal control unit 913 sets a built-in host interrupt register, generates and outputs a host interrupt signal. The host interface controller 114 receives the host interrupt signal, converts it into a prescribed transmission format, and transmits it to the digital data processing host device 200 via the data signal line (DATA1). “Prescribed transmission format” means a communication standard between a digital data processing host device and a digital data processing card.

In the digital data processing host device 200, the card interface control unit 151 receives the host interrupt signal sent from the digital data processing card 900, and converts the specified transmission format data into data for internal transmission. The interrupt signal receiving unit 152 receives the host interrupt signal after data conversion, detects an interrupt request from the digital data processing card 900, and notifies the host control unit 153 of the interrupt request.
The request content of the host interrupt signal is determined according to the application module 110. In the conventional example of FIG. 9, it is a transmission request for processing result application data. The host control unit 153 instructs the application data processing unit 154 to generate a command for requesting transmission of processing result application data. The application data processing unit 154 generates a processing result application data transmission request command. The card interface control unit 151 converts the processing result application data transmission request command into a prescribed transmission format and transmits it to the digital data processing card 900 via the command signal line (CMD). The processing result application data transmission request command is also transmitted to the interrupt cancellation signal generation unit 155.

The host interface control unit 114 of the digital data processing card 900 receives the processing result application data transmission request command sent from the digital data processing host device 200, converts the specified transmission format data into data for internal transmission, The data is sent to the data control unit 112. Upon receiving the processing result application data transmission request command, the application data control unit 112 reads out the processing result application data stored in the data storage unit 115. The host interface control unit 115 inputs the processing result application data read from the data storage unit 115, converts it into a specified transmission format, and passes through four or one data signal line (DATA) of the transmission data bus. To the digital data processing host device 200.
The card interface control unit 151 of the digital data processing host device 200 receives the processing result application data sent from the digital data processing card 900, converts the specified transmission format data into data for internal transmission, and performs application data processing. To the unit 154. The application data processing unit 154 processes the processing result application data.

After the digital data processing host device 200 transmits the processing result application data transmission request command, the interrupt cancellation signal generation unit 155 that has received the processing result application data transmission request command generates an interrupt cancellation command. The card interface control unit 151 inputs an interrupt cancel command, converts it into a prescribed transmission format, and transmits it to the digital data processing card 900 via a command signal line (CMD).
The host interface control unit 114 receives the interrupt release command sent from the digital data processing host device 200, converts the specified transmission format data into data for internal transmission, and sends it to the interrupt signal control unit 913. The interrupt signal control unit 913 inputs an interrupt cancel command, and cancels the host interrupt register in the set state.
JP 11-298450 A

Various application functions for function expansion can be added to the digital data processing card.
However, when developing a digital data processing card that adds new application functions or improves the functions of existing applications, depending on the application, the digital data processing card may digitalize new interrupt processing specific to the application. Sometimes you want to send an interrupt signal to a data processing host device. However, for example, a conventional interrupt signal control unit incorporated in an IC transmits an interrupt signal only based on a certain interrupt factor. If the interrupt signal control unit of the digital data processing card is newly designed, human and financial development investment and a development period are required, and there is a problem that the release time of a new product is delayed.

The present invention has been made in view of the above-described problems, and transmits an interrupt signal to a digital data processing host device by an arbitrary interrupt factor generated according to an application program, and processes the interrupt factor. The object is to provide a data processing card.
The present invention relates to a method for controlling a digital data processing system having a digital data processing card and a digital data processing host device for transmitting / receiving an interrupt signal by an arbitrary interrupt factor generated according to an application program and processing the interrupt factor The purpose is to provide.
It is an object of the present invention to provide a digital data processing card and a digital data processing system having a scalable interrupt processing function.
An object of the present invention is to provide a digital data processing card and a control method for a digital data processing system in which an interrupt processing function can be arbitrarily set at an application level.

  In order to solve the above problems, the present invention has the following configuration. According to a first aspect of the present invention, there is provided a digital data processing card comprising: a host interface controller that communicates with a host device; at least one application module that generates an interrupt factor that requests interrupt processing; A rewritable memory having at least one interrupt factor selection register for setting whether or not to allow interrupt processing based on an interrupt factor, the generation of the interrupt factor, and the interrupt factor corresponding to the interrupt factor And an interrupt signal control unit that outputs an interrupt signal to a host device through the host interface based on a setting state of a selection register.

Conventional digital data processing cards execute interrupt processing based on certain factors, and do not have the flexibility to change interrupt factors depending on the application.
The digital data processing card of the present invention can permit or prohibit interrupt processing for any interrupt factor depending on the application by rewriting data stored in a rewritable memory. You may rewrite the permission / prohibition setting of interrupt processing by executing a program built in the digital data processing card, and the host device attached rewrite data of permission / prohibition setting of interrupt processing to the digital data processing card. The setting may be rewritten by sending a rewrite command.
The “rewritable memory” is, for example, a RAM, a flash memory, an S-R flip-flop, or the like.

  According to a second aspect of the present invention, there is provided a digital data processing card comprising: a host interface controller that communicates with a host device; at least one application module that generates an interrupt factor that requests an interrupt process; A rewritable memory having an interrupt factor register set to each address based on each interrupt factor, an address value storage unit for storing an address value, and an address stored in the address value storage unit And an interrupt signal control unit that outputs an interrupt signal to a host device through the host interface when the interrupt factor register designated by a value is set.

In the conventional digital data processing card, for example, if the interrupt signal control unit has eight interrupt factor registers, the eight interrupt factor registers respond to only eight constant interrupt factors. The interrupt signal control unit could not output an interrupt signal based on other interrupt factors.
In the digital data processing card of the present invention, for example, the interrupt signal control unit responds to an interrupt factor designated by eight addresses stored in the address value storage unit. By rewriting the address stored in the address value storage unit, an interrupt signal can be output based on an arbitrary factor.
The digital data processing card of the present invention can perform an interrupt process based on an arbitrary interrupt factor according to an application by rewriting data stored in a rewritable memory. The interrupt factor may be rewritten by executing the program built in the digital data processing card, or the interrupt factor may be rewritten by the host device sending a rewrite command with the interrupt factor rewrite data attached to the digital data processing card. good.
Typically, the “address value” is the address value of the selected interrupt factor register, but may be a value that specifies the address value of the indirectly selected interrupt factor register.

The digital data processing card according to claim 3 of the present invention, wherein the rewritable memory sets whether or not to permit interrupt processing based on each interrupt factor to a plurality of addresses. And when the interrupt factor selection register specified by the address value stored in the address value storage unit prohibits the interrupt, even if the corresponding interrupt factor occurs, The digital data processing card according to claim 2, wherein the interrupt signal control unit does not output an interrupt signal to a host device.
If the interrupt factor selection register disables interrupts, the interrupt factor register may not be set when an interrupt factor is generated, and the interrupt signal control unit will not interrupt even if the interrupt factor register is set. The output signal may not be output.

In the digital data processing card according to claim 4 of the present invention, the rewritable memory having the interrupt factor selection register or the interrupt factor register and the address value storage unit is a RAM or a flash memory. The digital data processing card according to claim 1, wherein the digital data processing card is a digital data processing card.
Conventionally, only a limited number of interrupt factor registers can be provided in the interrupt signal control unit. By providing an interrupt factor register in the RAM or flash memory (the number of bits (capacity) of the RAM or flash memory is generally much larger than the number of dedicated interrupt factor registers), any number of interrupt factors A register can be provided.

The digital data processing card according to claim 5 of the present invention is such that the rewritable memory has at least one initial value of an address value stored in the address value storage unit and a set value of the interrupt factor selection register. The initial value is automatically read from the rewritable memory when the digital data processing card is activated, and the set value of the address value storage unit is set as an address value, or The digital data processing card according to any one of claims 1 to 4, wherein a set value of the interrupt factor selection register is set to an initial value.
By storing the initial value in a nonvolatile memory and setting the initial value in a register or the like at startup (when the power is turned on), the set value of the register or the like can be maintained even when the power is turned off. Preferably, the initial value and the current set value can be arbitrarily rewritten separately.

In the digital data processing card according to claim 6 of the present invention, when the host interface receives a command for inquiring about interrupt factor information transmitted from the host device, the digital data processing card is set to the address of the interrupt factor register set. 3. The digital data processing card according to claim 2, wherein a response including interrupt factor information generated based on the response is transmitted to the host device.
Since the host device can acquire the interrupt factor information from the digital data processing card, even when an interrupt signal is transmitted based on a number of interrupt factors, the host device executes an appropriate process according to the interrupt factor. I can do it.

The digital data processing card according to claim 7 of the present invention further includes a password verification unit, wherein the rewritable memory stores a first password that is a unique value and is transmitted from the host device. Password, the initial value, the set value of the interrupt factor selection register, and the rewrite data of any of the address values stored in the address value storage unit, and the rewrite data write command, The password verification unit compares the first password and the second password when a command including the command is received, and writes the rewritten data in the rewritable memory when they match. A digital data processing card according to any one of claims 1 to 6.
With the above configuration, it is possible to prevent the digital data processing card from malfunctioning due to a third party rewriting the settings without permission.
Preferably, the first password is a dedicated password for rewriting the set value or the like. The first password is notified only to a manufacturer who has received a predetermined certification.

In the digital data processing card according to claim 8 of the present invention, the password verification unit further includes a random number generation unit, and each time the password verification unit compares the first password and the second password. The digital data processing card according to claim 7, wherein the random number generator rewrites the first password.
According to the present invention, it is possible to further prevent a third party from rewriting the settings without permission.

According to a ninth aspect of the present invention, there is provided a digital data processing system control method comprising: a host device that communicates with each other; and a digital data processing card having one or more application modules that generate interrupt factors. A control method for a digital data processing system, wherein the digital data processing card sets an interrupt state based on an interrupt factor generated by the application module, and the digital data processing card, A first transmission step of transmitting an interrupt signal to the host device; and an interrupt factor inquiry step of transmitting a command for inquiring an interrupt factor based on the received interrupt signal to the digital data processing card. And the digital data processing card issues an inquiry command for the interrupt factor. , A second transmission step of generating a response including interrupt factor information based on the interrupt status and transmitting the response to the host device, and the interrupt factor information received by the host device A data processing request step for transmitting a data processing command generated based on the response including the response to the digital data processing card; a data processing step for executing data processing specified by the command by the digital data processing card; The host device receives an interrupt cancel request step for transmitting a command for canceling the interrupt state to the digital data processing card, and the digital data processing card receives a command for canceling the interrupt state. And an interrupt state canceling step for canceling the interrupt state.
The present invention realizes a control method of a digital data processing system in which, when an interrupt factor occurs, the digital data processing card and the host device appropriately exchange information regarding the interrupt processing and execute the interrupt processing.

According to the present invention, for example, according to the purpose of use of the digital data processing card, the interrupt signal control function can be expanded according to the function of the built-in application module for expanding the function. The address for accessing the control function and the number of extended interrupt factors can be set arbitrarily. This has the advantage of being able to cope with changes and updates to application standards for digital data processing cards.
In addition, according to the present invention, for example, according to the purpose of use of the digital data processing card, it is possible to arbitrarily set the register function setting data according to the function of the built-in application module for extending the function. Even in a digital data processing card that does not include a control element such as a microcomputer, the digital data processing card has an advantage that it can cope with a change or update of application standards of the digital data processing card.

  Further, according to the present invention, for example, according to the purpose of use of the digital data processing card, it is possible to rewrite the stored address data and register setting data according to the function of the built-in application module for expanding the function. . In addition, it is possible to limit the rewriting of the stored data, and it has an advantage that it can cope with a change or update of the application standard and an advantage that it can correspond to the protection of the stored data.

According to the present invention, it is possible to realize a digital data processing card that transmits an interrupt signal to a digital data processing host device by an arbitrary interrupt factor generated according to an application program, and processes the interrupt factor. Is obtained.
According to the present invention, there is provided a digital data processing system having a digital data processing card and a digital data processing host device for transmitting and receiving an interrupt signal by an arbitrary interrupt factor generated according to an application program and processing the interrupt factor. An advantageous effect of realizing the control method is obtained.
According to the present invention, it is possible to obtain an advantageous effect that a digital data processing card and a digital data processing system having a scalable interrupt processing function can be realized.
According to the present invention, it is possible to obtain an advantageous effect that a digital data processing card and a digital data processing system control method capable of arbitrarily setting an interrupt processing function at an application level can be realized.

  Embodiments of a digital data processing card of a digital data processing system according to the present invention will be described below with reference to the drawings.

Example 1
A digital data processing system having a digital data processing host device and a digital data processing card according to a first embodiment of the present invention will be described with reference to FIGS.
The digital data processing system includes a digital data processing card 100 (FIG. 1) and a digital data processing host device 200. Master / slave communication is performed in a synchronous manner using the digital data processing host device 200 as a master and the digital data processing card 100 as a slave. The digital data processing card 100 and the digital data processing host device 200 have a command signal line (CMD) for transmitting / receiving data (command, response, partial data) for controlling the digital data processing card 100, such as application data. Connected by signal lines composed of four data signal lines (DATA [3: 0]) for transmitting and receiving data and a clock signal line (CLK) for transmitting a clock serving as a reference signal such as a command signal or a data signal The application data is transmitted and received.

The configuration of the digital data processing card according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a functional block diagram showing the configuration of the digital data processing card 100 according to the first embodiment of the present invention.
The digital data processing card 100 is an application module 110 (a wireless communication module in the embodiment), a card control unit 111, an application data control unit 112, an interrupt signal control unit 113, a register control unit 114, and a host interface control unit. 115, a card initialization control unit 116, a password control unit 117, a data storage control unit 118, and a data storage unit 119.
Compared with the conventional example, the digital processing card 100 according to the embodiment determines whether to generate an interrupt signal based on an arbitrary interrupt factor according to the application module 110 and whether to permit the output of the interrupt signal. It can be set for each interrupt factor. The digital data processing card of the embodiment has a data storage unit 119 that is a flash memory, and is also a memory card.

In the digital data processing system of the present invention, the digital data processing host device 200 is the same in hardware as the conventional example except that it transmits / receives information not in the conventional example to / from the digital data processing card of the present invention. . The digital data processing card of the present invention has an interrupt signal control unit 113 instead of the interrupt signal control unit 913 of the conventional example, and a card initialization control unit 116 and a password control unit 117 (both of which are conventional). (Not shown in the example (FIG. 9)) and a register control unit 114 that is not in the conventional example. In other respects, the digital data processing card 100 of the embodiment has the same configuration as the digital data processing card 900 of the conventional example. The same reference numerals are assigned to the same functional blocks.
In the digital data processing card 100 of the embodiment, the interrupt signal control unit 113 executes the function executed by the interrupt signal control unit 913 in the digital data processing card 900 of the conventional example. A description of the same functional blocks and operations as in the conventional example is omitted.

The interrupt signal control unit 113 of the digital data processing card 100 of the embodiment will be described. FIG. 2 is a functional block diagram illustrating the configuration of the interrupt signal control unit 113 according to the embodiment of this invention.
The interrupt signal control unit 113 includes a standard interrupt signal control unit 201, an extended interrupt signal control unit 202, an interrupt factor switching control unit 203, and an interrupt signal generation unit 204.
The interrupt signal control unit 113 generates an interrupt signal based on a command from the application data control unit 112 as in the conventional example. The interrupt signal control unit 113 according to the present invention generates an interrupt signal based on various interrupt factors according to the application module, and whether to permit generation of an interrupt signal for each of various interrupt factors. Can be set. Further, the interrupt signal control unit 113 of the present invention is an interrupt factor set so as to be compatible at the time of IC (abbreviation of Integrated Circuit; including the interrupt signal control unit 113) according to the application module. Whether an interrupt signal can be generated based on a new factor (extended interrupt factor) other than (standard interrupt factor), and whether to actually generate an interrupt signal for each new factor Can be set.

The standard interrupt signal control unit 201 generates an interrupt signal based on an interrupt factor (standard interrupt factor) designed so that the IC can cope from the beginning. The extended interrupt signal control unit 202 is an interrupt factor (an interrupt factor arbitrarily added by the manufacturer after the completion of the IC) other than the interrupt factor (standard interrupt factor) designed so that the IC can cope from the beginning. An interrupt signal is generated based on the extended interrupt factor.
The standard interrupt signal control unit 201 will be described. The standard interrupt signal control unit 201 includes an interrupt address control unit 211, an interrupt factor setting control unit 212, an interrupt factor selection control unit 213, and an interrupt factor release control unit 214.

When the application data control unit 112 instructs the interrupt signal control unit 113 to generate an interrupt signal, it sets an interrupt address corresponding to the interrupt factor in the interrupt address control unit 211 and designates it by the interrupt address. The interrupt factor register (interrupt factor setting control unit 212) is set. The interrupt address control unit 211 outputs the set address to the interrupt factor setting control unit 212, the interrupt factor selection control unit 213, and the interrupt factor release control unit 214.
When resetting the interrupt factor register of the interrupt signal control unit 113, the application data control unit 112 sets an interrupt address corresponding to the interrupt factor in the interrupt address control unit 211, and Input a reset command. The interrupt release control unit 214 resets the interrupt factor register (interrupt factor setting control unit 212) designated by the interrupt address.

The interrupt factor setting control unit 212 has a plurality (eight in the embodiment shown in FIG. 5) of interrupt factor registers specified by interrupt addresses. Each interrupt factor register addressed by the interrupt address control unit 211 has an application data control unit when the interrupt factor selection control unit 213 allows the interrupt factor register to output an interrupt signal. It is set by a command from 112, and is reset (set to 0) by the interrupt factor release control unit 214. When any interrupt factor register is set, the interrupt factor setting control unit 212 instructs the interrupt signal generation unit 204 to generate and output an interrupt signal. If an interrupt factor register having an interrupt factor selection control unit 213 prohibits the output of an interrupt signal, the interrupt factor register (interrupt factor setting control unit 212) cannot be set.
Instead, when an interrupt factor register having an interrupt factor selection control unit 213 prohibits output of an interrupt signal, the interrupt factor register (interrupt factor setting control unit 212) is set. It is possible to make it impossible to output an interrupt signal.

The register control unit 114 has a plurality of interrupt factor selection registers, and each interrupt factor selection register is associated with each interrupt factor register (interrupt factor setting control unit 212). Each interrupt factor selection register sets the interrupt factor register when an interrupt factor is generated for the interrupt factor register (interrupt factor setting control unit 212) associated with the interrupt factor selection register. It is determined whether to permit (inhibit) (to generate an interrupt signal based on the interrupt factor) (allow if the value is 1 and prohibit if the value is 0). The card control unit 111 of the digital data processing card 100 executes an internal ROM program (typically executes an initialization program), and sets each interrupt factor selection register of the register control unit 114 (1 Interrupt enable) or reset (set to 0. interrupt prohibited). The digital data processing host device 200 can set or reset each interrupt factor selection register of the register control unit 114 by transmitting a command to the card control unit 111 of the digital data processing card 100.
The interrupt factor selection control unit 213 inputs an output signal from each interrupt factor selection register of the register control unit 114, and an interrupt factor register (interrupt factor setting control unit 212) designated by the interrupt address is input. Allow or prohibit to be set.

  The interrupt factor cancellation control unit 214 is composed of a logic circuit. The interrupt factor release control unit 214 inputs an interrupt address output from the interrupt address control unit 211 and an interrupt release command output from the application data control unit 112, and is specified by the interrupt address. Reset the factor register (interrupt factor setting control unit 212).

  The extended interrupt signal control unit 202 will be described. The extended interrupt signal control unit 202 includes an extended interrupt address control unit 221, an extended interrupt factor setting control unit 222, an extended interrupt factor selection control unit 223, and an extended interrupt factor release control unit 224. The manufacturer can arbitrarily associate a new interrupt factor with an extended interrupt address.

When the application data control unit 112 instructs the interrupt signal control unit 113 to generate an interrupt signal based on a new interrupt factor (extended interrupt factor), the application data control unit 112 sets the extended interrupt address control unit 221 as an extension interrupt factor. The corresponding interrupt address is set, and the extended interrupt factor register (extended interrupt factor setting control unit 222) designated by the interrupt address is set. The extended interrupt address control unit 221 outputs the set address to the extended interrupt factor setting control unit 222, the extended interrupt factor selection control unit 223, and the extended interrupt factor release control unit 224.
When the application data control unit 112 resets the extended interrupt factor register of the interrupt signal control unit 113, the application data control unit 112 sets an interrupt address corresponding to the interrupt factor in the extended interrupt address control unit 221, and performs extended interrupt release control. A reset command is input to the unit 224. The extended interrupt release control unit 224 resets the extended interrupt factor register (extended interrupt factor setting control unit 222) designated by the interrupt address.

The extended interrupt factor setting control unit 222 has a plurality of extended interrupt factor registers specified by interrupt addresses. For each extended interrupt factor register addressed by the extended interrupt address control unit 221, if the extended interrupt factor selection control unit 223 allows the extended interrupt factor register to output an interrupt signal, It is set by a command from the application data control unit 112, and is reset (set to 0) by the extended interrupt factor release control unit 224. When set, the extended interrupt factor setting control unit 222 instructs the interrupt signal generation unit 204 to generate and output an interrupt signal. If the extended interrupt factor selection control unit 223 prohibits the output of an interrupt signal at a certain interrupt address, the extended interrupt factor register (extended interrupt factor setting control unit 222) at that interrupt address is set. I can't do that.
Instead, when the extended interrupt factor register having the extended interrupt factor selection control unit 223 prohibits the output of an interrupt signal, the extended interrupt factor register (extended interrupt factor setting control unit 222) ) Can be set, but the interrupt signal may not be output.

The register control unit 114 further includes a plurality of extended interrupt factor selection registers, and each extended interrupt factor selection register is associated with each extended interrupt factor register (extended interrupt factor setting control unit 222). Each extended interrupt factor selection register, when an interrupt factor is generated for the extended interrupt factor register (extended interrupt factor setting control unit 222) associated with the extended interrupt factor selection register, Determines whether or not to set the register (to generate an interrupt signal based on the interrupt factor) (whether it is prohibited) (if the value is 1, permit it, if the value is 0) Ban.). The card control unit 111 of the digital data processing card 100 executes a program in a built-in ROM (typically executes an initialization program), and sets each extended interrupt factor selection register of the register control unit 114 ( It can be set to 1. Interrupt enabled) or reset (set to 0. Interrupt disabled). The digital data processing host device 200 can set or reset each extended interrupt factor selection register of the register control unit 114 by transmitting a command to the card control unit 111 of the digital data processing card 100.
The extended interrupt factor selection control unit 223 is composed of a logic circuit. The extended interrupt factor selection control unit 223 receives the interrupt address output from the extended interrupt address control unit 221 and the output signal from each extended interrupt factor selection register of the register control unit 114, and receives the interrupt address. Enable or disable setting of the extended interrupt factor register (extended interrupt factor setting control unit 222) specified by.

  The extended interrupt factor cancellation control unit 224 is composed of a logic circuit. The extended interrupt factor release control unit 224 receives the interrupt address output from the extended interrupt address control unit 221 and the interrupt release command output from the application data control unit 112, and is specified by the interrupt address. The extended interrupt factor register (extended interrupt factor setting control unit 222) is reset.

In response to a command from the card control unit 111, the interrupt factor switching control unit 203 receives an interrupt signal output command transmitted from the interrupt factor setting control unit 212 or an interrupt transmitted from the extended interrupt factor setting control unit 222. The interrupt signal output command is selectively transmitted to the interrupt signal generation unit 204. Specifically, when the interrupt factor switching control unit 203 receives a command to output an interrupt signal based on the standard interrupt factor from the card control unit 111, the interrupt factor setting control unit 212 outputs the interrupt signal. The command is permitted to be output, and the interrupt signal output command transmitted from the extended interrupt factor setting control unit 222 is not passed. When the interrupt factor switching control unit 203 receives a command to output an interrupt signal based on the extended interrupt factor from the card control unit 111, the interrupt factor setting control unit 212 outputs an interrupt signal output command. The interrupt signal output command transmitted from the extended interrupt factor setting control unit 222 is transmitted to the interrupt signal generation unit 204.
The interrupt signal generation unit 204 generates and outputs an interrupt signal according to the interrupt signal output command transmitted from the interrupt factor setting control unit 212 or the extended interrupt factor setting control unit 222.

In the digital data processing system having the above-described configuration, an operation when the digital data processing card 100 receives processed application data corresponding to the application module 110 incorporated therein and transmits processing result application data to the digital data processing host device 200. Is described below. In the embodiment, the application module 110 that is a wireless communication module receives data (processed application data) transmitted from an external device, and transmits the received data (processing result application data) to the digital data processing host device 200. .
When receiving the corresponding processed application data, the application module 110 of the card control unit 111 processes the processed application data and generates processing result application data.

  The application data control unit 112 stores the processing result application data generated by the application module 110 in the data storage unit 119. The application data control unit 112 selects an interrupt factor (processing result application data transmission request in the embodiment) corresponding to the processing result application data, and sends it to the interrupt address control unit 211 (or the extended interrupt address control unit 221). Write the interrupt address corresponding to the interrupt factor. The application data control unit 112 sets the interrupt factor register (or the extended interrupt factor register) of the interrupt factor setting control unit 212 (or the extended interrupt factor setting control unit 222) designated by the interrupt address. If the interrupt factor selection register (or extended interrupt factor selection register, included in the register control unit 114) corresponding to the interrupt factor register (or extended interrupt factor register) is in the interrupt enabled state (set state) For example, the interrupt factor register (or extended interrupt factor register) designated by the interrupt address is set. If the interrupt factor selection register (or extended interrupt factor selection register) corresponding to the interrupt factor register (or extended interrupt factor register) is in the interrupt disabled state (reset state), the interrupt address is specified. The interrupt factor register (or extended interrupt factor register) is not set.

  When the interrupt factor register (or extended interrupt factor register) is set, the interrupt factor setting control unit 212 (or extended interrupt factor setting control unit 222) generates an interrupt signal to the interrupt signal generation unit 204. Command. The interrupt signal generation unit 204 generates and outputs an interrupt signal. The host interface control unit 115 receives an interrupt signal, converts the interrupt signal into a prescribed transmission format, and transmits it to the digital data processing host device 200 via the data signal line (DATA1).

  The digital data processing host device 200 receives the interrupt signal transmitted from the digital data processing card 100. At this point, the digital data processing host device 200 knows that an interrupt processing request has been sent from the digital data processing card 100, but the digital data processing host device 200 is requested because the interrupt signal is not accompanied by data. I do not know the specific contents of interrupt processing (interrupt factor). The digital data processing host device 200 generates an interrupt factor identification information request command in order to know the interrupt factor generating the interrupt signal. The interrupt factor identification information request command is converted into a prescribed transmission format and transmitted to the digital data processing card 100 via a command signal line (CMD).

  The host interface control unit 115 of the digital data processing card 100 receives the interrupt factor identification information request command sent from the digital data processing host device 200, converts it into data for internal transmission, and transmits it to the application data control unit 112. To do. In response to the interrupt factor identification information request command, the interrupt factor set in the interrupt factor setting control unit 212 (or the extended interrupt factor setting control unit 222) (processing result application data transmission request in the embodiment) is detected. To do. The interrupt factor can be detected by the address of the set interrupt factor register (or extended interrupt factor register). The application data control unit 112 sends interrupt factor identification information including information on the detected interrupt factor to the host interface control unit 115. The host interface control unit 115 converts the response including the interrupt factor identification information into a prescribed transmission format and transmits the response to the digital data processing host device 200 via the command signal line (CMD).

  The digital data processing host device 200 receives a response including interrupt factor identification information sent from the digital data processing card 100. The digital data processing host device 200 knows the interrupt factor. When the interrupt factor identification information includes, for example, an interrupt factor requesting that the digital data processing card 100 transmits the processing result application data, the digital data processing host device 200 transmits the processing result application data to the digital data processing. A processing result application data request command requested to the card 100 is generated. The processing result application data request command is converted into a prescribed transmission format and transmitted to the digital data processing card 100 via the command signal line (CMD) of the transmission data bus.

  The digital data processing card 100 receives the processing result application data request command sent from the digital data processing host device 200. The processing result application data request command is converted into data for internal transmission by the host interface control unit 115 and sent to the application data control unit 112. The application data control unit 112 commands reading of the processing result application data stored in the data accumulation control unit 118. The data accumulation control unit 118 reads out the processing result application data accumulated in the data accumulation unit 119 (in the embodiment, data transmitted from an external device through wireless communication). The read processing result application data is sent to the host interface control unit 115. The host interface control unit 115 converts the processing result application data into a prescribed transmission format, and transmits it to the digital data processing host device 200 via four or one data signal line (DATA) included in the transmission data bus. To do.

  The digital data processing host device 200 receives the processing result application data. The digital data processing host device 200 receives the processing result application data, performs a predetermined process (for example, after outputting the processing result application data from the digital data processing host device 200), and then interrupts the digital data processing card 100. Generate interrupt factor release command to release the status. The card interface control unit 151 of the digital data processing host device 200 converts the interrupt factor release command into a prescribed transmission format and transmits it to the digital data processing card 100 via the command signal line (CMD).

  The host interface control unit 115 of the digital data processing card 100 receives the interrupt factor release command, converts it into data for internal transmission, and transmits it to the application data control unit 112. The application data control unit 112 receives the interrupt factor register (or extended interrupt factor setting control unit) of the interrupt factor setting control unit 212 via the interrupt factor cancellation control unit 214 (or extended interrupt factor release control unit 224). 222 (extended interrupt factor register) 222 is reset. As a result, the host interrupt state of the digital data processing card 100 is released.

Next, in the digital data processing system configured as described above, an operation when the digital data processing host device 200 generates processed application data and transmits the processed application data to the digital data processing card 100 will be described. In the embodiment, the application data to be processed is data that the application module 110 that is a wireless communication module transmits to an external device.
The digital data processing host device 200 generates application data to be processed (transmission data for wireless communication). The digital data processing host device 200 generates a processed application data reception request command for requesting the digital data processing card 100 to receive the generated processed application data. The card interface control unit 151 of the digital data processing host device 200 converts the processed application data reception request command into a prescribed transmission format, and sends it to the digital data processing card 100 via the command signal line (CMD) of the transmission data bus. Send. The card interface control unit 151 converts the generated processed application data into a specified transmission format following the processed application data reception request command, and transmits four or one data signal lines (DATA) of the transmission data bus. To the digital data processing card 100.

The host interface control unit 115 of the digital data processing card 100 receives the processed application data reception request command sent from the digital data processing host device 200, converts it into data for internal transmission, and sends it to the application data control unit 112. . When receiving the processed application data reception request command, the application data control unit 112 inquires of the data storage control unit 118 whether the data storage unit 119 can store the processed application data. When the data storage unit 119 can store the processed application data, the data storage control unit 118 generates a data write control signal and prepares to store the processed application data.
Subsequently, the host interface control unit 115 receives the application data to be processed sent from the digital data processing host device 200, converts it into data for internal transmission, and sends it to the application data control unit 112. The application data control unit 112 transmits the processed application data to the data accumulation control unit 118. When the data storage unit 119 can store the processed application data, the data storage control unit 118 outputs a data write control signal and stores the processed application data in the data storage unit 119.
The application module 110, which is a wireless communication module, sequentially reads out the application data to be processed (transmission data for wireless communication) stored in the data storage unit 119, and outputs it by wireless communication.

When the application module 110 sequentially outputs the processed application data and the unprocessed processed application data stored in the data storage unit 119 falls below a certain amount, the application data control unit 112 interrupts the interrupt signal control unit 113. Command output of the self-contained signal. More specifically, the application data control unit 112 extends the interrupt factor register (or the extended interrupt factor setting control unit 222) of the interrupt factor setting control unit 212 corresponding to the interrupt factor requesting transmission of the processed application data. Set the interrupt factor register.
If the interrupt factor selection register (or extended interrupt factor selection register) corresponding to the interrupt factor register (or extended interrupt factor register) is in the interrupt enabled state (set state), the interrupt factor register (or The extended interrupt factor register) is set. The interrupt signal control unit 113 outputs an interrupt signal.
The host interface control unit 115 transmits an interrupt signal to the digital data processing host device 200.

  The digital data processing host device 200 receives an interrupt signal from the host interface control unit 115. At this point, the digital data processing host device 200 knows that an interrupt processing request has been sent from the digital data processing card 100. However, since the host interrupt signal is not accompanied by data, the digital data processing host device 200 requests I don't know the specific contents of interrupted interrupt processing (host interrupt factor). The digital data processing host device 200 generates an interrupt factor identification information request command and transmits it to the digital data processing card 100 in order to know the interrupt factor generating the interrupt signal.

  The digital data processing card 100 receives the interrupt factor identification information request command sent from the digital data processing host device 200. The digital data processing card 100 detects an interrupt factor (processed application data transmission request in the embodiment) set by the interrupt factor setting control unit 212 (or the extended interrupt factor setting control unit 222). The application data control unit 112 sends interrupt factor identification information including information on the detected interrupt factor to the host interface control unit 115. The digital data processing card 100 transmits a response including interrupt factor identification information to the digital data processing host device 200.

  The digital data processing host device 200 receives a response including interrupt factor identification information sent from the digital data processing card 100. The digital data processing host device 200 knows the interrupt factor. When the interrupt factor identification information includes, for example, an interrupt factor requesting that the digital data processing card 100 transmits the processed application data, the digital data processing host device 200 receives the processed application data by digital data processing. A processing application data reception request command to be requested to the card 100 is generated, and the processing application data reception request command and the processing application data are transmitted to the digital data processing card 100.

The digital data processing card 100 receives the processing application data reception request command and the processing application data transmitted from the digital data processing host device 200. The application data to be processed is stored in the data storage unit 119. The digital data processing card 100 transmits a processed application data reception request command and a response notifying that the processed application data has been received to the digital data processing host device 200.
When the digital data processing host device 200 receives the above response, the digital data processing host device 200 generates a host interrupt factor cancel command for canceling the interrupt state of the digital data processing card 100 and transmits it to the digital data processing card 100.
The digital data processing card 100 receives the interrupt factor release command. The application data control unit 112 receives the interrupt factor register (or extended interrupt factor setting control unit) of the interrupt factor setting control unit 212 via the interrupt factor cancellation control unit 214 (or extended interrupt factor release control unit 224). 222 (extended interrupt factor register) 222 is reset. As a result, the host interrupt state of the digital data processing card 100 is released.

Example 2
Next, the operation for generating an interrupt signal by controlling an interrupt factor (extended interrupt factor) specific to the application module 111 built in the digital data processing card 100 will be described in detail with reference to FIG. To do.
FIG. 3 is a functional block diagram showing detailed configurations of the extended interrupt signal control unit 202, the register control unit 114, and the card initialization control unit 116 of the interrupt signal control unit 113 (FIG. 1) according to the embodiment of the present invention. is there.
The extended interrupt signal control unit 202 includes an extended interrupt address control unit 221, an extended interrupt factor setting control unit 222, an extended interrupt factor selection control unit 223, and an extended interrupt factor release control unit 224. The extended interrupt address control unit 221 includes an extended interrupt address setting unit 301 and an address data storage unit 302. The register control unit 114 includes a register setting unit 303, a register data storage unit 304, and a register function control unit 305. The card initialization control unit 116 includes a card initialization function unit 306, a data download control unit (hereinafter abbreviated as “data DL control unit”) 307, a CIS storage unit 308, and a CSA storage unit 309.

  When the digital data processing host device 200 is activated, when the digital data processing card 100 is inserted, or with the digital data processing card 100 inserted into the digital data processing host device 200, the digital data processing host device 200 Is activated, the digital data processing host device 200 generates a digital data processing card initialization command. The card interface control unit 151 converts the digital data processing card initialization command into a prescribed transmission format, and transmits the command to the digital data processing card 100 via the command signal line (CMD) of the transmission data bus.

  The host interface control unit 115 of the digital data processing card 100 receives the digital data processing card initialization command sent from the digital data processing host device 200, converts it into data for internal transmission, and the card initialization control unit 116 The data is sent to the card initialization function unit 306. The card initialization function unit 306 initializes each functional block of the digital data processing card 100. When the card initialization function unit 306 initializes the digital data processing card 100, the data DL control unit 307 controls the data accumulation control unit 118, and controls the extended interrupt signal stored in the data accumulation unit 119 in advance. The address data of each extended interrupt factor register of the unit 202 is downloaded. The downloaded address data is stored in the address data storage unit 302.

  Each interrupt factor register of the standard interrupt signal control unit 201 has its interrupt address and its interrupt factor determined, but each extended interrupt factor register of the extended interrupt signal control unit 202 has its interrupt An address and its interrupt factor can be arbitrarily determined. By storing arbitrary address data in the data storage unit 119 and associating an arbitrary interrupt factor with each address data (these data can be arbitrarily set by a program stored in the memory), an extended interrupt. Each extended interrupt factor register of the signal control unit 202 can be used for any interrupt factor.

As described above, the data storage unit 119 is a flash memory that is a rewritable nonvolatile memory. The extension interrupt factor register and extension interrupt address setting unit 301 of the extension interrupt signal control unit 202 and the extension interrupt factor selection register and register setting unit 303 of the register control unit 114 are a flash memory (memory device). It is provided in a part of the data storage unit 119).
The lower 4 bits bn (0 ≦ bn ≦ 3) (64B × 4 bits = 256 bits) of the addresses F20H to F5FH (each address has 8-bit data) of the flash memory (data storage unit 119) are respectively specified. This is an extended interrupt factor register that is set based on the interrupt factor. The upper 4 bits bn (4 ≦ bn ≦ 7) of the same address (F20H to F5FH) are respectively extended interrupt factor selection registers. The extended interrupt factor register of bit bn (0 ≦ bn ≦ 3) corresponds to the extended interrupt factor select register of bit (bn + 4).

  The addresses F00H to F1FH store 16 addresses (the extended interrupt address setting unit 301 and the register setting unit 303). Stored data at two addresses (for example, stored data at addresses F00H and F01H) specify the address of a specific extended interrupt factor register. For example, in the set of the addresses F00H and F01H, the bit number (0 to 3) of the extended interrupt factor register is stored in the address F00H (lower address), and the extended interrupt factor register in the address F01H (upper address). Stored is a value (20H to 50H) obtained by subtracting a predetermined offset value (F00H) from the address value (F20H to F5FH). Addresses of any 16 extended interrupt factor registers in the above 256 bits are stored in addresses F00H to F1FH.

When an interrupt factor corresponding to the 16 extended interrupt factor registers specified by addresses F00H to F1FH is generated, the interrupt signal control unit 113 outputs an interrupt signal.
When the digital data processing host device 200 transmits a command for writing the addresses of 16 extended interrupt factor registers corresponding to arbitrary interrupt factors to the addresses F00H to F1FH, for example, to the digital data processing card 100 (or so) An initialization program of the digital data processing card 100 containing a simple command is executed), and interrupt processing can be executed by an arbitrary factor according to the application.
Initial values of the upper 4 bits of the addresses F00H to F1FH and F20H to F5FH may be stored in a predetermined area (for example, F60H to 1BFH) of the memory (the address data storage unit 302 and the register data storage unit 304). ).
When the digital data processing card 100 is activated, the data storage unit 119 reads the initial values stored in the addresses F60H to F7FH and writes them in the addresses F00H to F1FH. The data storage unit 119 reads the initial value stored in the upper 4 bits of F80H to FBFH and writes it in the upper 4 bits of F20H to F5FH. The lower 4 bits of F20H to F5FH are reset (value 0) at the time of initial setting.
If the initial value is stored in the non-volatile memory, for example, the extended interrupt factor register and extended interrupt address setting unit 301 of the extended interrupt signal control unit 202 and the extended interrupt factor selection register and register setting of the register control unit 114 are set. The unit 303 may be provided in the RAM.

Assume that an interrupt factor (extended interrupt factor) specific to the application module 110 built in the digital data processing card 100 occurs. The card control unit 111 interrupts an interrupt signal output by the extended interrupt signal control unit 202 by executing a program built in the digital data processing card 100 or in response to a command from the digital data processing host device 200 The interrupt factor switching control unit 203 is set so as to be transmitted to the signal generation unit 204, and the extended interrupt signal control unit 202 is caused to function. The application data control unit 112 writes the interrupt address corresponding to the generated extended interrupt factor into the extended interrupt address setting unit 301 and sets the extended interrupt factor register of the extended interrupt factor setting control unit 222. If the extended interrupt factor selection register (register control unit 114) corresponding to the extended interrupt factor register is in the interrupt enabled state (set state), the extended interrupt factor register is set.
Based on the instruction from the set extended interrupt factor register (extended interrupt signal control unit 202), the interrupt signal generation unit 204 generates a host interrupt signal. The host interface control unit 115 receives the host interrupt signal, converts it into a prescribed transmission format, and transmits it to the digital data processing host device 200 via the data signal line (DATA1).

  Thereafter, the same processing as described above is performed. That is, the digital data processing host device 200 receives the host interrupt signal transmitted from the digital data processing card 100. The digital data processing host device 200 transmits an interrupt factor identification information request command to the digital data processing card 100 and receives interrupt factor identification information from the digital data processing card 100. The digital data processing host device 200 transmits a command corresponding to the interrupt factor identification information to the digital data processing card 100 and executes the interrupt processing. When the interrupt process is completed, the digital data processing host device 200 transmits an interrupt factor cancel command to the digital data processing card 100 to cancel the interrupt state.

Example 3
Next, an operation for setting an initial set value of the register control unit 114 of the digital data processing card 100 will be described with reference to FIG.
FIG. 5 is a register table showing an interrupt factor selection register (8 bits) set by the register control unit 114 (FIG. 1) of the digital data processing card 100 according to the embodiment of the present invention. The interrupt factor selection register in FIG. 5 corresponds to each interrupt factor register of the interrupt factor setting control unit 212 (standard interrupt signal control unit 201). In FIG. 5, MSEL and Address “00014” are addresses of the interrupt factor selection register. b00 to b07 indicate each bit. A line in which EXTENTEN or the like is written indicates an interrupt factor. The initial value row indicates whether output of an interrupt signal by each factor is permitted (1) or prohibited (0) in the initial setting (setting value of the interrupt factor selection register). For example, in the register table shown in FIG. 5, in the state in which the digital data processing card 100 is initialized, the bit 1 PRINTEN (interrupt permission register related to the printer application) and the bit 3 MDINTEN (interrupt permission related to the MD disk application) Register) is set to "1". “1” means that interrupt is permitted. The other bits (interrupt enable registers for other applications) are set to “0” indicating that interrupts are prohibited.

The Read / Write line indicates whether or not the card control unit 111 can rewrite the set value of each interrupt factor selection register. When “R / W” is written, it indicates that rewriting and reading of a set value are possible (in the register table of FIG. 5, all registers are rewritable), and “R” is written. (Not shown in FIG. 5) indicates that reading is possible but rewriting is not possible.
In addition to the interrupt factor selection register shown in FIG. 5, the register control unit 114 extends the extended interrupt factor corresponding to each extended interrupt factor register of the extended interrupt factor setting control unit 222 (extended interrupt signal control unit 202). It also has a selection register.

  When the digital data processing host device 200 is activated and the digital data processing card 100 is inserted, or when the digital data processing card 100 is inserted into the digital data processing host device 200, the digital data processing host device 200 When activated, the digital data processing host device 200 generates a digital data processing card initialization command. The card interface control unit 151 of the digital data processing host device 200 converts the digital data processing card initialization command into a prescribed transmission format, and sends it to the digital data processing card 100 via the command signal line (CMD) of the transmission data bus. Send.

  The host interface control unit 115 of the digital data processing card 100 receives the digital data processing card initialization command sent from the digital data processing host device 200, converts it into data for internal transmission, and sends it to the card initialization function unit 306. To transmit. The card initialization function unit 306 initializes each functional block of the digital data processing card 100. When the card initialization function unit 306 initializes the digital data processing card 100, the data DL control unit 307 controls the data storage control unit 118, and the register control unit 114 stored in the data storage unit 119 in advance. Download the initial setting data of each interrupt factor selection register and each extended interrupt factor selection register. The downloaded register initial setting data is stored in the register data storage unit 304 and the register setting unit 303.

The register data storage unit 304 stores initial setting data of each interrupt factor selection register and each extended interrupt factor selection register. The register setting unit 303 includes a plurality of interrupt factor selection registers and an extended interrupt factor selection register. The interrupt factor selection register and the extended interrupt factor selection register of the register setting unit 303 are set to initial setting data at the time of initialization. Thereafter, the card control unit 111 (including the case where the card control unit 111 operates based on a command from the digital data processing host device 200) sends a command to the register control unit 114 to cause an interrupt factor of the register setting unit 303. The set value of the selection register or extended interrupt factor selection register can be changed.
The register function control unit 305 outputs each output signal of the interrupt factor selection register of the register setting unit 303 to the interrupt factor selection control unit 213 of the standard interrupt signal control unit 201, and the extended interrupt factor of the register setting unit 303 Each output signal of the selection register is output to the extended interrupt factor selection control unit 223 of the extended interrupt signal control unit 202.

The card control unit 111 or the digital data processing host device 200 initializes the value of the interrupt factor selection register or the extended interrupt factor selection register of the register setting unit 303, and controls the output signal of the register function control unit 305.
During operation, the digital data processing card 100 and the digital data processing host device 200 can write new values to the register setting unit 303 through the card control unit 111 and rewrite the initial setting values.

  Conventionally, a user inputs (generally, an application program started on the digital data processing host device) from the digital data processing host device, or the user sets a digital data processing card and arbitrarily selects digital data for each interrupt factor. The interrupt function of the processing card could not be permitted or prohibited. The digital data processing card of the present invention can arbitrarily permit or prohibit the interrupt function for each interrupt factor depending on the application. The digital data processing host device of the present invention can send a command to the digital data processing card to enable or disable the interrupt function of the digital data processing card for each interrupt factor. By combining the digital data processing card and the digital data processing host device of the present invention, a digital data processing system for executing an interrupt suitable for each application can be realized.

Example 4
Next, password control when rewriting data unique to the digital data processing card 100 stored in the data storage unit 119 of the digital data processing card 100 (setting values of the interrupt factor selection register and the extended interrupt factor selection register) This will be described with reference to FIGS. 4 and 6 as well. In the digital data processing card 100 of the embodiment, when rewriting the set values of the interrupt factor selection register and the extended interrupt factor selection register, verification is performed using a dedicated password.
FIG. 4 is a functional block diagram illustrating the configuration of the password control unit 117 (FIG. 1) according to the embodiment of this invention. FIG. 6 is a list showing the data arrangement of the initial data area IVA of the data storage unit 119 (FIG. 1) according to the embodiment of the present invention.
The password control unit 117 includes a password verification unit 140, a card password storage unit 141, and a host password storage unit 142.

  When the digital data processing host device 200 is activated and the digital data processing card 100 is inserted, or when the digital data processing card 100 is inserted into the digital data processing host device 200, the digital data processing host device 200 When activated, the digital data processing host device 200 generates a digital data processing card initialization command. The digital data processing card initialization command is converted into a prescribed transmission format and transmitted to the digital data processing card 100 via the command signal line (CMD) of the transmission data bus.

  The host interface control unit 115 of the digital data processing card 100 receives the digital data processing card initialization command sent from the digital data processing host device 200, converts it into data for internal transmission, and the card initialization function unit 306 ( Included in the card initialization control unit 116). The card initialization function unit 306 initializes each functional block of the digital data processing card 100. When the card initialization function unit 306 initializes the digital data processing card 100, the data DL control unit 307 controls the data storage control unit 118, and the card password storage data PSWD0 stored in the data storage unit 119 in advance. And PSWD1 are downloaded. The downloaded card password storage data PSWD0 and PSWD1 are stored in the card password storage unit 141. One of the card password accumulation data PSWD0 and PSWD1 is sent to the password verification unit 140 as the card password data CPSWD.

When the digital data processing host device 200 rewrites the data stored in the data storage unit 119, the stored data address control signal (the data storage control unit 118 is designated with the address of the data storage unit 119 and the data stored in the address is stored). A command for instructing rewriting) and rewrite accumulation data (setting values of the interrupt factor selection register and the extended interrupt factor selection register) and a password setting control signal (including the password HPSWD).
First, the card interface control unit 151 of the digital data processing host device 200 converts the password setting control signal into a prescribed transmission format and transmits it to the digital data processing card 100 via the command signal line (CMD) of the transmission data bus. To do. Next, the card interface control unit 151 of the digital data processing host device 200 converts the stored data address control signal and the rewritten stored data into a specified transmission format, respectively, and transmits four or one data signal lines ( (DATA) to the digital data processing card 100.

  The host interface control unit 115 of the digital data processing card 100 converts the password setting control signal sent from the digital data processing host device 200 into data for internal transmission and sends it to the register control unit 114. The register control unit 114 extracts the host password data HPSWD from the password setting control signal and stores it in the host password storage unit 142. Next, the register control unit 114 requests the password verification unit 140 to perform password verification. Upon receiving the password verification request, the password verification unit 140 compares the card password data CPSWD stored in the card password storage unit 141 with the host password data HPSWD stored in the host password storage unit 142, and if they match, The accumulated data write permission signal WROK is output to the data accumulation control unit 118.

  The host interface control unit 115 receives the storage data address control signal and the rewrite storage data sent from the digital data processing host device 200 following the password setting control signal, converts them into data for internal transmission, and the application data control unit 112. The application data control unit 112 generates an address data control signal FSMA (write address information) from the stored data address control signal, generates write data FSMD from the rewritten stored data, and transmits it to the data storage control unit 118. When the stored data write permission signal WROK is received from the password verification unit 140, the data storage control unit 118 receives the chip selection control signal XFMCE and the data write control signal XFSMWE (memory chip select signal) from the address data control signal FSMA. And the write data FSMD are transmitted to the data storage unit 119 in synchronization with the address data control signal FSMA, and the write data FSMD is stored at each address.

  As a result of the verification by the password verification unit 140, even if the host password data HPSWD and the card password data CPSWD do not match, the application data control unit 112 generates the address data control signal FSMA and the write data FSMD, and stores the data The data is transmitted to the control unit 118. However, if the host password data HPSWD and the card password data CPSWD do not match, the data accumulation control unit 118 does not generate the chip selection control signal XFMCE and the data write control signal XFSMWE, and does not rewrite the data in the data accumulation unit 119.

Here, the operation of the card initialization control unit 116 of the digital data processing card 100 in the embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a data arrangement diagram showing the data arrangement of the data storage unit 119 (FIG. 1) according to the embodiment of the present invention.
FIG. 8 is a timing chart showing the timing of downloading data from the data storage unit 119 when the digital data processing card 100 according to the embodiment of the present invention is initialized. In FIG. 8, the initial data MIER1 and MIER2 of the interrupt factor selection register and the extended interrupt factor selection register and the data of the interrupt addresses (addresses of the interrupt factor register and the extended interrupt factor register) RFU0 and RFU1 are downloaded. Timing is shown.

  The digital data processing host device 200 is inserted when the digital data processing host device 200 is activated or the digital data processing card 100 is inserted into the digital data processing host device 200. When 200 is activated, the digital data processing host device 200 generates a digital data processing card initialization command. The card interface control unit 151 of the digital data processing host device 200 converts the digital data processing card initialization command into a prescribed transmission format, and sends it to the digital data processing card 100 via the command signal line (CMD) of the transmission data bus. Send.

The card password may be a fixed value, but each time the card password is verified from the digital data processing host device 200 to the digital data processing card 100 using a predetermined random number generator, the value of the card password may be updated. good.
Each time the digital data processing host device 200 and the digital data processing card 100 have the same random number generator and the card password is verified, for example, the current card password value is input to the random number generator in each device. The random number generator generates a new card password using the current card password value as a parameter. In the correct combination of the digital data processing host device 200 and the digital data processing card 100, the two values match, so the digital data processing host device 200 can rewrite a predetermined initial value of the data storage unit 119.

  The host interface control unit 115 of the digital data processing card 100 receives the digital data processing card initialization command sent from the digital data processing host device 200, converts it into data for internal transmission, and sends it to the card initialization function unit 306. To transmit. The card initialization function unit 306 initializes each functional block of the digital data processing card 100. When the card initialization control unit 306 starts initialization of each functional block of the digital data processing card 100, the card initialization signal CARDINI (the interrupt factor selection register and the extended interrupt factor selection register of the register control unit 114). A signal instructing to download the initial value is generated and sent to the data DL control unit 307. When the data DL control unit 307 receives the card initialization signal CARDINI, the data DL control unit 307 generates an address data control signal FSMA (read address information) for reading data stored in the card storage unit 119, and sends it to the data storage control unit 118. send.

  Upon receiving the address data control signal FSMA, the data accumulation control unit 118 generates a chip selection control signal XFMCE and a data read control signal XFSMOE (a memory chip select signal and a read control signal from the memory), and an address data control signal FSMA. In synchronization with this, a chip selection control signal XFMCE and a data read control signal XFSMOE are sent to the data storage unit 119. When the data storage unit 119 receives the chip selection control signal XFMCE or the like, the data FSMD stored in each area corresponding to the address data control signal FSMA is sent to the data DL control unit 307 via the data storage control unit 118. Output. The data DL control unit 307 includes each read accumulation data FSMD (address data, initial values of the interrupt factor selection register and extended interrupt factor selection register, card password accumulation data PSWD0 and PSWD1 corresponding to the address data control signal FSMA. Are stored in the address data storage unit 302, the register data storage unit 304, and the card password storage unit 141, respectively.

An operation in which the data storage control unit 118 reads stored data from the data storage unit 119 during the initialization operation of the digital data processing card 100 will be described in detail.
The data DL control unit 307 that has received the card initialization signal CARDINI from the card initialization control unit 306 generates an address data control signal FSMA of the address “0” and sends it to the data accumulation control unit 118. When receiving the address data control signal FSMA (read address information) of the address “0”, the data accumulation control unit 118 generates a chip selection control signal XFMCE and a data read control signal XFSMOE, and generates an address data control signal of the address “0”. These signals are sent to the data storage unit 119 in synchronization with FSMA, and the stored data FSMD (IVA_P) (value is set to “α”) in the address “0” area is read from the data storage unit 119. The data DL control unit 307 inputs the storage data FSMD (IVA_P) (value is “α”) in the address “0” area via the data storage control unit 118 and controls the address data of the address {α, 0}. A signal FSMA is generated.

  The data storage unit 118 receives the address data control signal FSMA at the address {α, 0}, and sends the generated chip selection control signal XFMCE, data read control signal XFSMOE, and address data control signal FSMA to the data storage unit 119, The accumulated data FSMD (CCCR / SDIO, SD) stored in the address {α, 0} area is read. The data DL control unit 307 inputs the stored data FSMD (CCCR / SDIO, SD) in the address {α, 0} area via the data storage control unit 118 and transmits these data to the register data storage unit 304. . The register data storage unit 304 stores these data as initial values.

Next, the data DL control unit 307 generates an address data control signal FSMA of the address {α, 1}. The data storage unit 118 receives the address data control signal FSMA at the address {α, 1}, and sends the generated chip selection control signal XFMCE, data read control signal XFSMOE, and address data control signal FSMA to the data storage unit 119. The data storage unit 119 reads the stored data FSMD (C_CAP, CIS_COM_P (L)) in the address {α, 1} area. The data DL control unit 307 receives the stored data FSMD (C_CAP, CIS_COM_P (L)) in the address {α, 1} region and stores it in the register data storage unit 304.
Thereafter, similarly, the data DL control unit 307 receives the storage data FSMD (UAOFST) of the address {α, 2} to {α, 9} region via the data storage control unit 118, and sends it to the register data storage unit 304. Store.

  Subsequently, the data DL control unit 307 generates an address data control signal FSMA of the address {α, A}. The data storage unit 118 receives the address data control signal FSMA of the address {α, A}, and reads the stored data FSMD (RFU0 / RFU1) in the address {α, A} area in the same manner as described above. When the data DL control unit 307 receives the storage data FSMD (RFU0 / RFU1) in the address {α, A} area via the data storage control unit 118, the data DL control unit 307 transmits the data to the address data storage unit 302. The address data storage unit 302 stores the stored data FSMD (RFU0 / RFU1) as an initial value.

Subsequently, the data DL control unit 307 generates an address data control signal FSMA of the address {α, B}. The data storage unit 118 receives the address data control signal FSMA of the address {α, B}, and reads the stored data FSMD (RFU2 / RFU3) in the address {α, B} area in the same manner as described above. The address data storage unit 302 stores the stored data FSMD (RFU2 / RFU3) as an initial value.
Hereinafter, similarly, the data DL control unit 307 receives the accumulated data FSMD (RFU6 / RFUEN) stored in the address {α, C} and {α, D} areas via the data accumulation control unit 118, The data is transmitted to the address data storage unit 302. The address data storage unit 302 stores these data as initial values.

  Subsequently, the data DL control unit 307 generates an address data control signal FSMA of the address {α, E}. Similarly, the data DL control unit 307 reads the stored data FSMD (PSWD0 / PSWD1) in the address {α, E} area via the data storage control unit 118. The data DL control unit 307 transmits the stored data FSMD (PSWD0 / PSWD1) to the card password storage unit 141. The card password storage unit 141 stores card passwords PSWD0 and PSWD1.

Subsequently, the data DL control unit 307 generates an address data control signal FSMA of the address “1”. The data storage unit 118 receives the address data control signal FSMA of the address “1”, and reads the storage data FSMD (CSA_P) (value is “β”) in the address “1” area.
When the data DL control unit 307 receives the storage data FSMD (CSA_P) (value is “β”) in the address “1” area via the data storage control unit 118, the address data of the address “{β, 0}” A control signal FSMA is generated. The data storage unit 118 receives the address data control signal FSMA of the address “{β, 0}” and reads the stored data FSMD (CSA region data) in the address “{β, 0}” region. When the data DL control unit 307 receives the accumulation data FSMD (CSA area data) in the address “{β, 0}” area, the data DL control part 307 transmits it to the CSA accumulation unit 309. The CSA accumulation unit 309 stores accumulated data FSMD (CSA area data) as an initial value.

  Next, the data DL control unit 307 generates an address data control signal FSMA of the address “{β, 1}”. The data storage unit 118 receives the address data control signal FSMA of the address “{β, 1}” and reads the address data FSMD (CSA area data) in the address “{β, 1}” area. The CSA accumulation unit 309 stores accumulated data FSMD (CSA area data) as an initial value. Thereafter, similarly, the data DL control unit 307 sequentially receives the address data FSMD (CSA area data) up to the address “{(α−1), F}” area via the data accumulation control unit 118, and accumulates the CSA. To the unit 309. The CSA storage unit 309 stores these values as initial values.

Next, the data DL control unit 307 generates an address data control signal FSMA of the address “2”. The data storage unit 118 receives the address data control signal FSMA of the address “2”, and reads the stored data FSMD (CIS area data) in the address “2” area. When the data DL control unit 307 receives the storage data FSMD (CIS region data) in the address “2” region, the data DL control unit 307 transmits it to the CIS storage unit 308. The CIS accumulation unit 308 stores these values as initial values.
Next, the data DL control unit 307 generates an address data control signal FSMA of address “3”. The data storage unit 118 receives the address data control signal FSMA of the address “3”, and reads the stored data FSMD (CIS region data) in the address “3” area. The CIS accumulation unit 308 stores these values as initial values. Thereafter, similarly, the data DL control unit 307 sequentially receives the address data FSMD (CSA area data) up to the address {(β−1), F} area, and transmits it to the CIS accumulation unit 308.

  As described above, in the present invention, some initial values are set by indirect addressing (all initial values may be set by indirect addressing). By rewriting the indirect addressing addresses (“α” and “β” in the above example), the setting can be easily changed.

  In the above-described embodiment, the extended interrupt address control unit 221 includes the address data storage unit 302 and the extended interrupt address setting unit 301, and stores the data in the data storage unit 119 when the digital data initial card 100 is initialized. Since the extended interrupt signal processing address data is downloaded, the control units of the extended interrupt factor setting control unit 222, the extended interrupt factor selection control unit 223, and the extended interrupt factor release control unit 224 operate. Is stored in the extended interrupt address setting unit 301 as address data. Similarly, the register control unit has a register data storage unit 304 and a register setting unit 303, and downloads the register address data stored in the data storage unit 119 when the digital data initial card 100 is initialized. And stored in the register setting unit 304 as address data of the interrupt factor selection register.

In the above-described embodiment, the register control unit 114 includes the register data storage unit 304 and the register setting unit 303, and registers control stored in the data storage unit 119 during the initialization operation of the digital data initial card 100. The initial setting data of the unit 114 is downloaded and stored in the register setting unit 303 as register setting data for determining the operation of the register function control unit 305. The control unit 111 of the embodiment card has a function of controlling (including the case where the digital data processing host device 200 sends a command to the card control unit 111) and rewriting the register setting data stored in the register data storage unit 304. ing. For example, the initial setting data of the register control unit 114 may be stored as setting data for a read-only register that cannot be rewritten.
The application module 110 is assumed to be a module that performs wired or wireless communication, but may be another application.
Needless to say, some of the functional blocks such as the interrupt signal control unit and the register control unit can be replaced with software implemented by the CPU executing the program.

  The present invention is useful, for example, as a control method for a digital data processing system having a digital data processing card, a digital data processing card, and a digital data processing host device used in a digital data device.

1 is a functional block diagram showing the configuration of a digital data processing card of a digital data processing system according to an embodiment of the present invention. The functional block diagram which shows the structure of the interruption signal control part of the digital data processing card | curd of the Example of this invention. The functional block diagram which shows the structure of the extended interrupt signal control part of the interrupt signal control part of an Example of this invention, a register control part, and a card initialization control part The functional block diagram which shows the structure of the password control part of the Example of this invention Register table showing set values of the interrupt factor selection register of the register control unit of the digital data processing card of the embodiment of the present invention The table | surface which shows the data arrangement | positioning of the initial data area IVA of the data storage part of the Example of this invention Data arrangement diagram showing data arrangement of data storage unit of embodiment of the present invention FIG. 3 is a timing chart showing timing for downloading initialization data from the data storage unit when the digital data processing card of the embodiment of the present invention is initialized. Functional block diagram showing the configuration of a conventional digital data processing system

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Digital data processing card 110 Application module 111 Card control part 112 Application data control part 113 Interrupt signal control part 114 Register control part 115 Host interface control part 116 Card initialization control part 117 Password control part 118 Data accumulation control part 119 Data accumulation Unit 140 password verification unit 141 card password storage unit 142 host password storage unit 151 card interface control unit 152 interrupt signal reception unit 153 host control unit 154 application data processing unit 155 interrupt release signal generation unit 200 digital data processing host device 201 standard Interrupt signal control unit 202 Extended interrupt signal control unit 203 Interrupt factor switching control unit 204 Interrupt signal generation unit 211 Interrupt address control unit 12 Interrupt factor setting control unit 213 Interrupt factor selection control unit 214 Interrupt factor release control unit 221 Extended interrupt address control unit 222 Extended interrupt factor setting control unit 223 Extended interrupt factor selection control unit 224 Extended interrupt factor release Control unit 301 Extended interrupt address setting unit 302 Address data storage unit 303 Register setting unit 304 Register data storage unit 305 Register function control unit 306 Card initialization function unit 307 Data download control unit 308 CIS storage unit 309 CSA storage unit

Claims (9)

A host interface controller that communicates with the host device;
At least one application module that generates an interrupt factor that requests interrupt processing; and
An interrupt factor selection unit that sets at least one interrupt factor selection register that sets whether or not to allow interrupt processing based on the interrupt factor;
Based on the generation of the interrupt factor and the setting state of the interrupt factor selection register corresponding to the interrupt factor, an interrupt signal control unit that outputs an interrupt signal to the host device through the host interface;
A digital data processing card comprising: A host interface controller that communicates with the host device;
At least one application module that generates an interrupt factor that requests interrupt processing; and
A rewritable memory having an interrupt factor register that is set to a plurality of addresses based on each interrupt factor, and an address value storage unit that stores an address value,
An interrupt signal control unit that outputs an interrupt signal to the host device through the host interface when the interrupt factor register specified by the address value stored in the address value storage unit is set;
A digital data processing card comprising: The rewritable memory further includes an interrupt factor selection register for setting whether or not to allow interrupt processing based on each interrupt factor to a plurality of addresses,
Even if the corresponding interrupt factor occurs when the interrupt factor selection register specified by the address value stored in the address value storage unit prohibits the interrupt, the interrupt signal control Does not output an interrupt signal to the host device.
The digital data processing card according to claim 2.   4. The rewritable memory including the interrupt factor selection register or the interrupt factor register and the address value storage unit is a RAM or a flash memory. The digital data processing card according to item. The rewritable memory includes a nonvolatile memory that stores at least one initial value of an address value stored in the address value storage unit and a setting value of the interrupt factor selection register,
When the digital data processing card is activated, the initial value is automatically read from the rewritable memory, the set value of the address value storage unit is set as an address value, or the set value of the interrupt factor selection register is set. Set to the initial value,
5. The digital data processing card according to claim 1, wherein the digital data processing card is a digital data processing card.   When the host interface receives a command for inquiring about interrupt factor information transmitted from the host device, a response including the interrupt factor information generated based on the set address of the interrupt factor register, The digital data processing card according to claim 2, wherein the digital data processing card is transmitted to the host device. A password verification unit;
The rewritable memory stores a first password which is a unique value;
A second password transmitted from a host device, the initial value, the set value of the interrupt factor selection register, and the rewrite data of any of the address values stored in the address value storage unit; When the command including the rewrite data write command is received, the password verification unit compares the first password and the second password, and if the two match, the rewrite data can be rewritten. 7. The digital data processing card according to claim 1, wherein the digital data processing card is written in a memory. The password verification unit further includes a random number generation unit,
8. The digital data processing card according to claim 7, wherein the random number generator rewrites the first password every time the password verification unit compares the first password and the second password. . A method for controlling a digital data processing system, comprising: a host device that communicates with each other; and a digital data processing card having one or more application modules that generate interrupt factors,
An interrupt state setting step in which the digital data processing card sets an interrupt state based on an interrupt factor generated by the application module;
A first transmission step in which the digital data processing card transmits an interrupt signal to the host device;
An interrupt factor inquiry step in which the host device transmits a command for inquiring an interrupt factor based on the received interrupt signal to the digital data processing card;
A second transmission step in which the digital data processing card receives the interrupt factor inquiry command, generates a response including interrupt factor information based on the interrupt status, and transmits the response to the host device; ,
A data processing request step in which the host device transmits a data processing command generated based on the response including the received interrupt factor information to the digital data processing card;
A data processing step in which the digital data processing card executes data processing specified by the command;
An interrupt release request step in which the host device transmits a command to release the interrupt state to the digital data processing card;
The digital data processing card receives a command for instructing the cancellation of the interrupt state, and cancels the interrupt state.
A control method for a digital data processing system, comprising:

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