JP2006018577A - Circuit constitution specification preventing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit constitution specification preventing method capable of preventing the specification of a constituting circuit by a simple means and evading physical concealment which causes difficulties when required work is generated. <P>SOLUTION: To an internal register group for setting operations inside an FPGA 12, address signals and data signals are supplied from an MPU and selection signals are inputted through a gate circuit 22. A permission key is set by the external circuit of the MPU or the like to a permission key setting register 23 inside the FPGA 12 and an authentication key is set by the MPU to an authentication key setting register 24. A key match detection circuit 25 compares the permission key set to the permission key setting register 23 and the authentication key set to the authentication key setting register 24 and closes the gate circuit 22 and inhibits the access of the internal register group 21 in the case that they do not match. Thus, the operation specification of the circuit by a third party is made difficult and the specification and unauthorized copying of the circuit constitution are prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a circuit configuration specifying prevention method for preventing specification of a circuit configuration of a manufactured semiconductor integrated circuit or the like.

  In recent years, the number of functions allocated to fields that use programmable development methods such as software and FPGA (Field Programmable Gate Array), which are relatively easy to change functions, has increased in the semiconductor integrated circuit, realizing the system function requirements. ing. In this case, since a commercially available device such as MPU or FPGA is used, a technique for protecting the program and preventing the specification of the circuit configuration is required.

  As a method for preventing the protection of the program and the specification of the circuit configuration in the semiconductor integrated circuit, conventionally, a method of protecting configuration data by encryption has been generally used (for example, see Patent Documents 1 and 2).

Further, in terms of difficulty in specifying the circuit configuration, it has been realized by means such as erasing the part type name of the device and physically concealing the substrate specifying portion with silicon or the like.
JP 2001-256114 A JP 2003-84853 A

  As described above, when using a method based on encryption as a method for preventing program protection and circuit configuration specification in a semiconductor integrated circuit, encryption information must be stored in an internal circuit, and its design is very There is a problem of complexity. In addition, when the encryption method is used, there is a problem that it takes time for decryption and the activation becomes slow.

In addition, when using means such as erasing the part type name of the device or physically concealing the silicon specific part of the substrate, etc.
1. A malicious third party can remove the concealed material to identify the circuit configuration relatively easily.

2. There are two major problems in the manufacturer, which obstruct the necessary work such as repair and repair due to the concealed material.

  The present invention has been made to solve the above-mentioned problems, and it is possible to reliably prevent the identification of constituent circuits by simple means and to avoid physical concealment that causes difficulty when necessary work occurs. An object is to provide a prevention method.

  The circuit configuration specifying prevention method according to the present invention includes a gate circuit for controlling access from an external circuit to an internal logic in a field programmable gate array, and a permission key set in an internal permission key setting register in advance. The gate key circuit is unlocked and access from the external circuit to the internal logic is permitted by comparing with a permission key input from the external circuit.

  According to the present invention, it becomes difficult for a third party to specify the operation of the circuit, and even if the program of the programmable device itself leaks, the program operates unless all the device programs and the board structure are configured to be the same. Therefore, it is possible to reliably prevent the circuit configuration from being specified. Further, it is not necessary to cover the entire circuit configuration formed on the substrate as in the conventional case, and when it is necessary to actually verify the operation of the substrate, the operation can be easily confirmed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows a schematic configuration example when a circuit configuration specifying prevention method according to the present invention is implemented in a semiconductor integrated circuit. In FIG. 1, reference numeral 10 denotes a substrate for printing. On this substrate 10, for example, an MPU (Micro Processing Unit) 11, an FPGA (Field Programmable Gate Array: Programmable Gate Array Element) 12, a peripheral circuit 13, An MPU peripheral circuit 14 and a CPLD (factory programmed logic element) 15 are provided.

  The MPU 11 operates based on predetermined software, and outputs an address, data, and a selection signal to the FPGA 12. The FPGA 12 is an integrated circuit that can be programmed in the field after manufacture using a program for the FPGA element that determines the function. The FPGA 12 is provided with an operation setting register group inside, and controls the peripheral circuit 13 based on an instruction from the MPU 11 which is an external circuit.

  The MPU 11, FPGA 12, and peripheral circuit 13 are realized by dividing them into one or a plurality of substrates 10 by examining the optimum implementation means for each functional block in order to satisfy the system function requirements.

  And in this embodiment, it is set as the structure which operate | moves by the key confirmation between the at least 1 or more combination of the said structure device. The key expression used here is a value (or level) specific to the product or the board, and is not a fixed value in general. In addition, at least one key is used because the more keys there are, the more difficult it is for a third party to specify the circuit configuration. It can be used in combination. Similarly to the number of keys, one key itself can be configured from 1 bit to a plurality of bits, and the secrecy achievement level increases in proportion to the increase in the number of bits.

  Here, a method for realizing a product request function using a general component generally controls and operates the peripheral circuit 13 by writing an operation request and a set value from the MPU 11 to a register in the FPGA 12. It is. Therefore, according to the present invention, unless all correct components are available, access to the registers in the FPGA 12 is prohibited, and the circuit does not operate normally, so that the circuit configuration (including only a part) can be specified. This prevents unauthorized copying.

  In the following description, an externally set key that is used to apply for operation permission is used as an authentication key, and a key that serves as a criterion for determining whether or not operation is permitted for the key is described as an allowed key. Basically, these keys are basically set using separate paths.

  In the circuit shown in FIG. 1, the MPU 11 gives a trigger to the CPLD 15 to generate a permission key, and this permission key is set in the permission key register inside the FPGA 12. The FPGA 12 compares the permission key set in the permission key register with the authentication key output from the MPU 11, and permits access to the internal register group only when they match, thereby identifying the circuit configuration and accompanying illegality. Prevent copying.

  FIG. 2 shows the secrecy when the authentication key and the permission key are set in parallel and the specific difficulty level of the circuit configuration. The horizontal axis indicates the number of bits / key, and the vertical axis indicates the number of keys. As the number of keys and the number of keys increase, confidentiality increases. Therefore, one key using the A bit can be regarded as the same as A one-bit key. Therefore, when the FPGA pins allocated to a certain circuit configuration are the same, it is possible to realize stronger confidentiality by configuring one key with a plurality of bits and setting the key serially.

FIG. 3 shows a specific circuit configuration example of the FPGA 12.
In FIG. 3, reference numeral 21 denotes an operation setting internal register group configured in the FPGA 12, and an address signal and a data signal are given from the MPU 11. Further, a selection signal output from the MPU 11 is input to the internal register group 21 via the gate circuit 22.

  Further, the FPGA 12 is provided with a permission key setting register 23 and an authentication key setting register 24, and the permission key set in the permission key setting register 23 matches the authentication key set in the authentication key setting register 24. A key coincidence detection circuit 25 is provided for comparing and controlling the gate circuit 22 based on the comparison result. A permission key is set in the permission key setting register 23 by an external circuit, for example, the MPU 11, and an authentication key is set in the authentication key setting register 24 by the MPU 11.

  The key match detection circuit 25 compares the permission key set in the permission key setting register 23 with the authentication key set in the authentication key setting register 24, and if they match, opens the gate circuit 22, that is, the gate circuit. 22 is unlocked and access to the internal register group 21 is permitted, and in the case of a mismatch, the gate circuit 22 is closed and access to the internal register group 21 is prohibited. The internal register group 21 controls the peripheral circuits 13a to 13n based on the operation request and the set value written by the MPU 11.

  Since most of the system function request operations are set via the internal register group 21 in the FPGA 12, the original function is realized by restricting access to the internal register group 21 when the authorization key and the authentication key do not match. The peripheral devices including the FPGA 12 do not operate correctly. This makes it difficult for a third party to specify the circuit configuration and operation. In addition, even if the program of the programmable device itself leaks, the program cannot operate unless all the device programs and the board structure are configured identically, so that it is possible to reliably prevent the specification of the circuit configuration. it can. Further, since it is not necessary to cover the entire circuit configuration formed on the substrate as in the prior art, the operation can be easily confirmed when it is necessary to actually verify the operation of the substrate.

Next, a configuration example when keys are set in the permission key setting register 23 and the authentication key setting register 24 will be described.
FIG. 4 shows a case where the permission key is set in the permission key setting register 23 and the authentication key is set in the authentication key setting register 24 using parallel data by the data bus of the MPU 11.

  As an operation of the MPU 11, first, the boot process is performed, then the internal initial process is executed, and then the permission key that is not gated, that is, the permission key setting register 23 that is normally accessible is set in advance. Thereafter, an authentication key is issued and set in the authentication key setting register 24.

  Since the authentication key is a key that is set when the software operation starts after the boot process, the authentication key is basically set by the MPU 11. The authentication key is set in the authentication key setting register 24 in the FPGA 12 after executing the boot process of the MPU 11 and executing the internal initial process of the MPU 11.

  When the MPU 11 sets an authentication key in the authentication key setting register 24, the key match detection circuit 25 detects the match between the permission key and the authentication key. When the key match detection circuit 25 detects a match between the permission key and the authentication key, the gate circuit 22 is unlocked, the internal register group 21 can be accessed, and a transition is made to a normal operation state. However, if the key match detection circuit 25 determines that the permission key and the authentication key do not match, the gate circuit 22 remains locked and access to the internal register group 21 is prohibited.

  Note that the method for setting the permission key for the permission key setting register 23 is not limited to the setting from the MPU 11, and any method for obtaining (setting) it may be used. However, in the present embodiment, the configuration is described in which both the authorization key and the authentication key are set from the MPU 11, but in actual operation, it is recommended from the viewpoint of confidentiality to use the same means and the same route setting. It is not something.

  FIG. 5 shows a serial key setting method, in which a permission key is set in the permission key setting register 23 using the serial port of the MPU 11. That is, a signal output from the serial port of the MPU 11 is converted into a parallel address signal and data signal by the serial / parallel (S / P) conversion circuit 26 and set in the permission key setting register 23. This setting method is the same as the parallel setting method except that a serial communication method is used as setting means.

  On the other hand, the authentication key is set in the authentication key setting register 24 in the FPGA 12 after executing the boot process of the MPU 11 and executing the internal initial process of the MPU 11 as in the case of the setting by the parallel data.

  Note that the key setting method in the permission key setting register 23 is not limited to the setting from the MPU 11 as in the case of the setting using the parallel data, and any acquisition (setting) method may be used. good.

  When the permission key is set in the permission key setting register 23 as described above, there are methods for realizing parallel setting and serial setting. However, in the case of parallel setting, the number of pins to be used is equal to the key length (number of bits). In this case, it can be realized with about 3 pins. Concealment is the same as the parallel setting of 1-bit keys in the parallel setting, but in the serial setting, there are multiple keys with one pin. When it is realized with the same number of pins, the configuration is extremely strong.

  Next, another embodiment for setting a permission key in the permission key setting register 23 will be described with reference to FIGS.

(Second Embodiment)
FIG. 6 is a circuit configuration diagram showing a setting example of the permission key according to the second embodiment of the present invention. The second embodiment shows an example in which a permission key is set inside the FPGA 12.
That is, the initial value of the permission key setting register 23 is set in the Boot memory 31 of the FPGA 12 in advance, and the permission key is set in the permission key setting register 23 by executing the FPGA Boot process. Therefore, after the FPGA Boot process is completed, the setting of the permission key is completed.

  After that, when the authentication key is set in the authentication key setting register 24 by the MPU 11, the key match detection circuit 25 detects the match between the permission key and the authentication key, and the gate of the gate circuit 22 according to the detection result. Is controlled on / off.

  With the above configuration, the permission key has already been booted from the FPGA Boot data as the initial value of the permission key setting register 23, so it is not necessary to set the permission key again.

(Third embodiment)
FIG. 7 is a circuit configuration diagram showing a key setting example according to the third embodiment of the present invention. In the third embodiment, an example in which a permission key is set from the board 10 on which the FPGA 12 is mounted is shown.
That is, the key circuit 32 is provided on the substrate 10, and a key is assigned bit by bit to an unused I / O pin of the FPGA 12 to set a permission key for the permission key setting register 23. Then, after booting the FPGA 12, the input level from the I / O pin is read and set in the permission key setting register 23.

  According to the above configuration, by connecting the key setting for the I / O pin from directly below the FPGA device mounting, the connection state cannot be confirmed from the outside, and the secrecy can be improved.

(Fourth embodiment)
FIG. 8 is a circuit configuration diagram showing a key setting example according to the fourth embodiment of the present invention. In the fourth embodiment, an example in which the permission key is set by the MPU 11 is performed via the CPLD 15.

  In the fourth embodiment, the CPLD 15 is provided on the substrate 10 and is activated by giving a permission key or the like to the CPLD 15 from the serial port of the MPU 11. The CPLD 15 operates in response to a command from the MPU 11 and outputs a permission key to the FPGA 12 as serial data. The FPGA 12 converts the serial permission key sent from the CPLD 15 into a parallel data signal by the serial / parallel conversion circuit 26 and sets it in the permission key setting register 23.

  The MPU 11 sets a command for setting a permission key, a permission key, or a permission key type to the CPLD 15. This kind of permission key is, for example, a data string obtained by inverting “1” or “0”, or a data string that has been determined as a permission key. In this case, parallel / serial settings can be made between the MPU 11 and the CPLD 15 and between the CPLD 15 and the FPGA 12 in the same manner as in the above embodiment. It is.

(Fifth embodiment)
FIG. 9 is a circuit configuration diagram showing a key setting example according to the fifth embodiment of the present invention, and shows an example in which the permission key is set by the CPLD 15.
In the present embodiment, the CPLD 15 is provided on the substrate 10 as in the fourth embodiment. However, the CPLD 15 is configured to be able to monitor other boot situations, and the boot end signal (Boot Done) of the FPGA 12 is used as a trigger. The predetermined permission key is set in the FPGA 12. The FPGA 12 converts the serial permission key sent from the CPLD 15 into a parallel data signal by the serial / parallel conversion circuit 26 and sets it in the permission key setting register 23.
According to the fifth embodiment, the permission key can be set in the permission key setting register 23 by the CPLD 15.

  Also in the fifth embodiment, parallel / serial settings can be made between the MPU 11 and the CPLD 15 and between the CPLD 15 and the FPGA 12 as in the above embodiments, and can be selected depending on the implementation status. .

Next, operations and key setting procedures after power-on in each of the above embodiments will be described with reference to the flowchart shown in FIG.
When the power of the target device is turned on, the Boot control operation by CPLD is performed (step A1). First, “permission key setting 0” is performed by FPGA Boot processing (step A2). This “permission key setting 0” is a case where the permission key setting register 23 is set using the permission key incorporated as an initial value in the Boot data of the FPGA 12, as shown in the second embodiment of FIG. .

Next, “permission key setting 1” is performed by FPGA Boot processing (step A3). This "permission key setting 1"
(1) As shown in the third embodiment of FIG. 7, a key circuit 32 provided on the substrate 10 inputs a signal directly to the I / O pin of the FPGA 12 and uses it as a permission key as a permission key setting register 23. If set to
(2) As shown in the fifth embodiment of FIG. 9, when the CPLD 15 provided on the substrate 10 operates in response to the Boot end signal (Boot Done) of the FPGA 12 and the permission key is automatically set in the permission key setting register 23. is there.
Thereafter, the boot process of the MPU 11 is executed (step A4).

The processes in steps A2 to A4 are executed by boot control by CPLD.
After the boot process of the MPU 11 is completed, the “permission key setting 2” process is performed (step A5). As shown in the first embodiment of FIG. 4 and FIG. 5 and the third embodiment of FIG. 8, when the permission key is set when the MPU 11 is activated, the timing of “permission key setting 2” in step A5. Executed.

  Next, an internal initial process is executed by the MPU 11 (step A6). After the initial process is completed, the MPU 11 sets an authentication key in the authentication key setting register 24 in the FPGA 12 (step A7).

  Next, the FPGA 12 determines in the key match detection circuit 25 whether or not the permission key set in the permission key setting register 23 matches the authentication key set in the authentication key setting register 24, that is, key authentication. (Step A8).

  When the key match detection circuit 25 detects a match between the permission key and the authentication key in the key authentication, the key match detection circuit 25 opens the gate circuit 22 to permit access to the internal register group 21 (step A9), and shifts to a normal operation operation. (Step A10).

  In step A8, if the key match detection circuit 25 determines that the permission key and the authentication key do not match, the gate circuit 22 is held closed, and the internal register group 21 is accessed. It is forbidden. For this reason, peripheral devices including the FPGA 12 do not operate correctly, and the circuit configuration cannot be specified.

  As described above, various setting examples of the permission key have been shown. However, the present invention can realize the secrecy only by one setting method, and can also have a method configuration that maximizes the secrecy using all. . This makes it possible to configure according to the required confidentiality requirements in accordance with the system to be provided.

  Similarly, the key code itself can have any configuration from 1 bit to a plurality of bits depending on conditions such as the bus width of the MPU 11 to be used and the number of empty pins of the FPGA 12.

  In addition, the number of keys and key codes with a high degree of freedom can be used, and even in the match detection, from the match detection using the same key code for all keys to the one using the key code for all keys individually It can be set freely.

  Furthermore, considering the construction of the serial key setting between the CPLD 15 and the FPGA 12, the package of both devices at the present time is generally BGA (Ball Grid Array). By using the connection, it is possible to eliminate the means for signal monitoring from the outside, and it is possible to further improve the secrecy.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage.

It is a figure which shows the schematic structural example of the semiconductor integrated circuit using the circuit structure specific prevention method which concerns on 1st Embodiment of this invention. It is a figure which shows the confidentiality at the time of setting the authentication key and permission key in the embodiment in parallel, and the specific difficulty of a circuit structure. It is a figure which shows the specific circuit structural example of FPGA in the same embodiment. 5 is a diagram illustrating a configuration example in the case where the setting of the permission key in the permission key setting register and the setting of the authentication key in the authentication key setting register are performed using parallel data in the embodiment. FIG. 4 is a diagram illustrating a configuration example in the case where the permission key is set in the permission key setting register by serial data in the embodiment. FIG. It is a figure which shows the structural example of the semiconductor integrated circuit using the circuit structure specific prevention method which concerns on 2nd Embodiment of this invention. It is a figure which shows the structural example of the semiconductor integrated circuit using the circuit structure specific prevention method which concerns on 3rd Embodiment of this invention. It is a figure which shows the structural example of the semiconductor integrated circuit using the circuit structure specific prevention method which concerns on 4th Embodiment of this invention. It is a figure which shows the structural example of the semiconductor integrated circuit using the circuit structure specific prevention method which concerns on 5th Embodiment of this invention. It is a flowchart which shows the operation | movement after power activation in each embodiment of this invention, and a key setting procedure.

Explanation of symbols

  10 ... Substrate, 11 ... MPU, 11. FPGA12 ... MPU11, 12 ... FPGA, 13, 13a to 13n ... peripheral circuit, 14 ... MPU peripheral circuit, 15 ... CPLD, 21 ... internal register group, 22 ... gate circuit, 23 ... permission key setting register, 24 ... authentication key setting Registers 25... Key coincidence detection circuit 26... Serial / parallel (S / P) conversion circuit 31... Boot memory 32.

Claims (1)

  A gate circuit for controlling access from the external circuit to the internal logic is provided in the field programmable gate array, and the permission key preset in the internal permission key setting register and the permission key input from the external circuit are provided. A circuit configuration identification preventing method comprising: comparing the matching, and releasing the lock of the gate circuit and permitting access from the external circuit to the internal logic when matching occurs.

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