JP2006014113A - Image decoding device and image encoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain high throughput without increasing an operating frequency with regard to an image decoding device such as an MPEG decoder. <P>SOLUTION: A bit stream analytic section 17 distributes a VOP in a bit stream to VOP decoders 18-0 to 18-3 so that the decode processing start timing of each macro-block in the VOP decoders 18-0 to 18-3 can be after the decoding completion of a reference image region required for each macro-block is completed, and makes the VOP decoders 18-0 to 18-3 execute parallel processings of four VOPs. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image decoding apparatus and an image encoding apparatus such as an MPEG decoder and an MPEG encoder used in an MPEG (Moving Picture Experts Group) system. Specifically, the present invention relates to a technique for improving processing performance of an image decoding device and an image encoding device.

  For example, MPEG decoders and MPEG encoders are required to improve processing performance as the screen size of images handled increases, such as digital high-definition broadcasting. As a technique for improving the processing performance of the MPEG decoder and the MPEG encoder, “speeding up the operating frequency”, “parallel processing”, etc. are conceivable. An operable circuit or the like is necessary.

  On the other hand, with regard to “parallelization of processing”, in the case of an MPEG decoder, prediction processing between frames (pictures) and variable length decoding processing are required, so it is necessary to process code-compressed bitstreams sequentially from the front. Therefore, it is difficult to parallelize simple processes, and various ideas have been made for parallelizing processes.

  FIG. 7 is a diagram showing the structure of a frame image in MPEG-2. As shown in FIG. 7, a frame 1 in MPEG-2 is composed of a plurality of slices 2 which are horizontally long strip-like regions, and the slice 2 is composed of a plurality of macroblocks 3, and the macroblock 3 is composed of four It is composed of luminance blocks 4 to 7 and two color difference blocks 8 and 9.

  Therefore, as a parallel processing technique in an MPEG decoder, conventionally, parallel processing at a block level (a technique for processing a plurality of blocks in parallel with a block as a processing unit) or parallel processing at a slice level (a plurality of processing with a slice as a processing unit) A method for processing slices in parallel) has been proposed.

  FIG. 8 is a configuration diagram of a main part of an example of a conventional MPEG decoder. The conventional MPEG decoder shown in FIG. 8 performs parallel processing at the block level in 6 parallels, and 10 is a variable length decoding unit that inputs a bit stream of an MPEG digital image and performs variable length decoding. 11-0 Reference numeral 11-5 denotes a block processing unit that performs inverse quantization and inverse discrete cosine transform using blocks as processing units, 12 denotes a motion compensation unit, and 13 denotes a frame memory.

FIG. 9 is a block diagram of the main part of another example of a conventional MPEG decoder. The conventional MPEG decoder shown in FIG. 9 performs parallel processing at the slice level in four parallel processes. 14-0 to 14-3 are slice detectors for detecting a slice from the bit stream of the MPEG digital image. Reference numerals 0 to 15-3 denote slice processing units that perform variable length decoding, inverse quantization, inverse discrete cosine transform, and motion compensation using a slice as a processing unit, and reference numeral 16 denotes a frame memory.
Japanese Patent Laid-Open No. 9-261642 JP 2001-285876 A

  In the conventional MPEG decoder shown in FIG. 8, the variable length decoding unit 10 performs bit stream analysis and distributes the blocks Y0 to Y3, Cb, and Cr to the block processing units 11-0 to 11-5. Since the long decoding process needs to be performed by serial processing, the variable-length decoding unit 10 has to be operated at high speed and has a problem that the operating frequency has to be increased.

  The conventional MPEG decoder shown in FIG. 9 uses the fact that a unique code called a slice header exists for each macroblock line in the MPEG-2 standard, but in the MPEG-4 standard, a VOP (video object plane) is used. However, since there is no such unique code, parallel processing equivalent to the slice level cannot be performed.

  In view of the above, an object of the present invention is to provide an image decoding apparatus and an image encoding apparatus that can realize high processing performance without increasing the operating frequency.

  The image decoding apparatus of the present invention has a plurality of picture decoding processing units for decoding a plurality of pictures in parallel, and refers to each macroblock for the decoding processing start timing of each macroblock of each picture decoding processing unit This is after the decoding of the image area is completed.

  The image encoding apparatus of the present invention has a plurality of picture encoding processing units for encoding a plurality of pictures in parallel, and the encoding processing start timing of each macroblock of each picture encoding processing unit is set for each macroblock. This is after the encoding of the reference image area is completed.

  In the image decoding apparatus of the present invention, since the decoding processing start timing of each macroblock of each picture decoding processing unit is after the decoding of the reference image area of each macroblock, a plurality of pictures are decoded in parallel. Can do. Therefore, high processing performance can be realized without increasing the operating frequency.

  In the image encoding device of the present invention, since the encoding process start timing of each macroblock of each picture encoding processing unit is after the encoding of the reference image area of each macroblock is completed, a plurality of pictures are encoded in parallel. be able to. Therefore, high processing performance can be realized without increasing the operating frequency.

  1 to 6, an embodiment of an image decoding apparatus and an image encoding apparatus according to the present invention will be described. An image decoding apparatus and an image encoding apparatus according to the present invention are converted into an MPEG decoder and an MPEG for an MPEG-4 system. A case where the present invention is applied to an encoder will be described as an example.

(First Embodiment of Image Decoding Device of the Present Invention)
FIG. 1 is a configuration diagram of a main part of a first embodiment (MPEG decoder) of an image decoding apparatus according to the present invention. The first embodiment of the image decoding apparatus of the present invention performs parallel processing at the picture level in four parallels, that is, decodes four VOPs in parallel using VOP as a processing unit. A bit stream analysis unit, 18-0 to 18-3 are VOP decoders as picture decoding processing units, 19 is a frame memory, and 20 is a memory control unit.

  The bit stream analysis unit 17 receives the bit stream of the MPEG-4 digital image, detects the VOP start code (0x000001B6), and detects the VOP decoders 18-0 to 18-3 with respect to the VOP decoders 18-0 to 18-18. -3 distributes VOPs in charge of decoding so that four VOPs can be decoded in parallel.

  The bitstream analysis unit 17 analyzes the FCODE included in the header of the bitstream and acquires reference image area range information necessary for decoding the macroblock. From the reference image area range information, the VOP decoders 18-0 to 18-18 are obtained. The timing required for the VOP decoding process at -3 is calculated.

  Therefore, the bitstream analysis unit 17 sets the VOP so that the decoding start timing of each macroblock in the VOP decoders 18-0 to 18-3 is after completion of the decoding of the reference image area required by each macroblock. Decode processing start control of the decoders 18-0 to 18-3 is performed.

  The VOP decoders 18-0 to 18-3 perform VOP decoding processing, that is, variable length decoding, inverse quantization, inverse discrete cosine transform, and motion compensation, with VOP as a processing unit. 20-0 to 20-20 -3 is a variable length decoding unit, 21-0 to 21-3 are inverse quantization units, 22-0 to 22-3 are inverse discrete cosine transform units, and 23-0 to 23-3 are motion compensation units.

  Here, the bitstream analysis unit 17 gives a macroblock processing activation signal to the VOP decoders 18-0 to 18-3 so that the decoding processing in the VOP decoders 18-0 to 18-3 is synchronized in units of macroblocks. Control is performed so that the decoding processing in the decoders 18-0 to 18-3 proceeds one macroblock at a time. Therefore, in the VOP decoders 18-0 to 18-3, a plurality of VOPs are decoded in parallel by the pipeline processing method in units of macroblocks.

  The frame memory 19 stores decoded images output from the VOP decoders 18-0 to 18-3, and has a capacity for storing decoded images of a plurality of frames. The memory control unit 20 writes the decoded image output from the VOP decoders 18-0 to 18-3 to the frame memory 19 and moves the reference image stored in the frame memory 19 to the motion compensation units 23-0 to 23-3. This is to control the transfer and the like.

  FIG. 2 is a diagram showing an operation example of the first embodiment of the image decoding apparatus of the present invention. FIG. 2 (A) is a decoding process timing in the VOP decoders 18-0 to 18-3, and FIG. The decoding progress state at the time T shown in FIG. Note that the reference image area range of the macroblock = ± 32 (FCODE = 2), the VOP arrangement of the bitstream is composed of only I-VOP and P-VOP, and I0, P1, P2, and P3 are VOP decoders 18 respectively. The case where it distributes to -0, 18-1, 18-2, 18-3 is taken as an example.

  Since the reference image area range of the macroblock is ± 32, the VOP decoder 18-1 decodes the P1 when the VOP decoder 18-0 completes the decoding of the third macroblock at the top of the I0 frame. The VOP decoder 18-2 can start the decoding process of P2 when the VOP decoder 18-1 completes the decoding process of the third macroblock at the top of the frame of P1, The VOP decoder 18-3 can start the decoding process of P3 when the VOP decoder 18-2 completes the decoding process of the third macroblock at the top of the frame of P2.

  As described above, the decoding start control is performed by the bit stream analysis unit 17. At such timing, the IOP in the VOP decoders 18-0, 18-1, 18-2, and 18-3 is performed. , P1, P2, and P3 decoding processing, the decoding progress status of I0, P1, P2, and P3 in the VOP decoders 18-0 to 18-3 at time T shown in FIG. B).

  In FIG. 2B, 24 is a processing macroblock in the VOP decoder 18-0, 25 is a processing macroblock in the VOP decoder 18-1, 26 is a processing macroblock in the VOP decoder 18-2, 27 is A processing macroblock in the VOP decoder 18-3, 28 indicates a motion vector range of the processing macroblock 25, 29 indicates a motion vector range of the processing macroblock 26, and 30 indicates a motion vector range of the processing macroblock 27.

  As described above, according to the first embodiment of the image decoding apparatus of the present invention, the VOP decoders 18-0 to 18-3 have the decoding processing start timing of each macroblock completed decoding of the reference image area of each macroblock. Since the control is performed later, four VOPs can be decoded in parallel. Therefore, high processing performance can be realized without increasing the operating frequency. If the processing performance is the same as that when serially processing a VOP, the operating frequency of the VOP decoders 18-0 to 18-3 can be reduced to ¼, thereby reducing power consumption. it can.

(Second Embodiment of Image Decoding Device of the Present Invention)
FIG. 3 is a block diagram of the main part of the second embodiment (MPEG decoder) of the image decoding apparatus of the present invention. As in the first embodiment of the image decoding apparatus of the present invention, the second embodiment of the image decoding apparatus of the present invention performs parallel processing at the picture level in 4 parallel processes, that is, 4 VOPs as processing units. One VOP is decoded in parallel. 31-0 to 31-3 are VOP decoders as picture decoding processing units, 32 is a frame memory, 33 is a memory control unit, and 34 is a decoding control unit.

  The VOP decoders 31-0 to 31-3 detect a specific VOP from the bit stream of the input MPEG-4 digital image and decode the VOP, that is, variable length decoding, inverse quantization, inverse discrete cosine transform, 35-0 to 35-3 are VOP detection units, 36-0 to 36-3 are variable length decoding units, 37-0 to 37-3 are inverse quantization units, and 38-0 to 38-3 are motion compensation units. Reference numeral 38-3 denotes an inverse discrete cosine transform unit, and 39-0 to 39-3 denote motion compensation units.

  The VOP decoders 31-0 to 31-3 include reference image region position calculation units 40-0 to 40-3, and the reference image region position calculation units 40-0 to 40-3 are currently processing. Along with the position information in the VOP of the macroblock, the reference image area position information required by the currently processed macroblock is output to the decode control unit 34.

  The frame memory 32 stores decoded images output from the VOP decoders 31-0 to 31-3, and has a capacity to store decoded images of a plurality of frames. The memory control unit 33 writes the decoded image output from the VOP decoders 31-0 to 31-3 to the frame memory 32 and moves the reference image stored in the frame memory 32 to the motion compensation units 39-0 to 39-3. This is to control the transfer and the like.

  The decode control unit 34 assigns VOPs in the input bitstream to the VOP decoders 31-0 to 31-3. In response to this, the VOP detectors 31-0 to 31-3 detect the specific VOP assigned from the input bit stream.

  The decode control unit 34 also outputs the in-VOP position information of the currently processed macroblock output from the VOP decoders 31-0 to 31-3 and the reference image area position information required by the currently processed macroblock. The macro block processing start signal is given to the VOP decoders 31-0 to 31-3 so that the decoding process start timing of each macro block is after the decoding of the reference image area of each macro block is completed, and the VOP decoder 31-0 ~ 31-3 are instructed to start decoding process and wait for each macroblock. Therefore, in the VOP decoders 31-0 to 31-3, decoding processing of a plurality of VOPs is performed in parallel by the pipeline processing method in units of macroblocks.

  FIG. 4 is a diagram showing an operation example of the second embodiment of the image decoding apparatus of the present invention. 4A shows the decoding processing timing in the VOP decoders 31-0 to 31-3, and FIG. 4B shows the decoding progress status at time T shown in FIG. 4A. The VOP arrangement of the bitstream is composed only of I-VOP and P-VOP, and I0, P1, P2, and P3 are allocated to VOP decoders 31-0, 31-1, 31-2, and 31-3, respectively. Take the case as an example.

  In this case, the VOP detectors 35-0 to 35-3 of the VOP decoders 31-0 to 31-3 detect the start code (0x000001B6) of the VOP in the bitstream, and the information in the header (vop_coding_type, vop_time_increment, etc.) Based on the above, a specific VOP assigned from the decode control unit 34 is detected. Here, when the VOP detection unit 35-0 detects I0, since I0 does not require a reference picture, the VOP decoder 31-0 immediately starts decoding I0.

  Next, when the VOP detection unit 35-1 detects P1, it enters a standby state for starting VOP decoding. Then, the reference image region position calculation unit 40-1 calculates a reference image region position necessary for processing the first macroblock MB0 in the reference image I0 from the first macroblock header information of P1, and the macroblock MB0. The decoding control unit 34 is notified of the position information in the VOP and the position information of the reference image area. The decoding control unit 34 monitors the progress of the decoding process of the macroblock of I0, and after the decoding of the reference image area position where the MB0 of P1 is necessary, the MB0 decoding process of P1 is performed on the VOP decoder 31-1. Issue a start signal.

  Hereinafter, similarly, the reference image area position calculation units 40-0 to 40-3 decode the intra-picture position information and the reference image area position information of the macroblocks decoded by the VOP decoders 31-0 to 31-3. The decoding control unit 34 controls the start and standby of the decoding process in the VOP decoders 31-0 to 31-3 in units of macroblocks.

  In FIG. 4B, 41 is a processing macroblock in the VOP decoder 31-0, 42 is a processing macroblock in the VOP decoder 31-1, 43 is a processing macroblock in the VOP decoder 31-2, 44 is A processing macroblock in the VOP decoder 31-3, 45 indicates a reference image area of the processing macroblock 42, 46 indicates a reference image area of the processing macroblock 43, and 47 indicates a reference image area of the processing macroblock 44.

  Here, for example, when the motion vector of the processing macroblock 43 in the VOP decoder 31-2 points to the unprocessed area 46 in the VOP decoder 31-1, the processing macroblock in the VOP decoder 31-2. The decoding process of 43 is controlled by the decoding control unit 34 so as to wait until the decoding of the reference image area 46 in the VOP decoder 31-2 is completed.

  As described above, according to the second embodiment of the image decoding apparatus of the present invention, the VOP decoders 31-0 to 31-3 set the decoding process start timing of each macroblock to the completion of decoding of the reference image area of each macroblock. Since control is performed later, four VOPs can be processed in parallel. Therefore, high processing performance can be realized without increasing the operating frequency. If the processing performance is the same as when serially processing a VOP, the operating frequency of the VOP decoders 31-0 to 31-3 can be reduced to ¼, thereby reducing power consumption. it can.

  Patent Document 1 describes an MPEG decoder that performs variable-length decoding processing, inverse quantization processing, and inverse discrete cosine transform processing by decoding a plurality of blocks in parallel by a pipeline processing method using blocks as processing units. However, the first and second embodiments of the image decoding apparatus according to the present invention perform parallel processing at the picture level, and are not suggested by Patent Document 1.

(One Embodiment of MPEG Encoder of the Present Invention)
FIG. 5 is a configuration diagram of a main part of an embodiment (MPEG encoder) of the image encoding apparatus of the present invention. One embodiment of the image coding apparatus according to the present invention performs two parallel processings at the picture level, that is, encodes two VOPs in parallel using VOP as a processing unit. Memory, 48 is a memory control unit, 49-0 and 49-1 are VOP encoders which are picture encoding processing units, 50-0 and 50-1 are stream buffers, and 51 is a stream synthesis unit.

  The frame memory 47 is for storing an input image given from the outside and a local decoded image created by the VOP encoders 49-0 and 49-1. The memory control unit 48 writes the input image to the frame memory 47, distributes the VOP stored in the frame memory 47 to the VOP encoders 49-0 and 49-1, and is created by the VOP encoders 49-0 and 49-1. It controls the writing of the local decoded image into the frame memory 47 and the transfer of the reference image from the frame memory 47 to the VOP encoders 49-0 and 49-1.

  Based on the reference image area range required by the macroblock, the memory control unit 48 determines the reference timing required for each macroblock for the encoding process start timing of each macroblock in the VOP encoders 49-0 and 49-1. The VOP assigned to the encoder is distributed to the VOP encoders 49-0 and 49-1, and the start and standby of the encoding process are controlled so that the encoding is completed for the area. Encode two VOPs in parallel.

  The VOP encoders 49-0 and 49-1 encode VOPs in the input image distributed by the memory control unit 48. 52-0 and 52-1 are motion vector calculation units, 53-0, 53-1 is a subtractor for obtaining a difference between the processing target macroblock and the corresponding prediction macroblock, 54-0 and 54-1 are discrete cosine transform units, 55-0 and 55-1 are quantization units, 56- 0 and 56-1 are variable length coding units, 57-0 and 57-1 are inverse quantization units, 58-0 and 58-1 are inverse discrete cosine transform units, and 59-0 and 59-1 are restored differences. This is an adder that creates a local decoded image by adding a signal and a reference image.

  Here, the memory control unit 48 gives a macro block processing start signal to the VOP encoders 49-0 and 49-1, so that the encoding processing in the VOP encoders 49-0 and 49-1 is synchronized in units of macro blocks. Control is performed so that the encoding process in the encoders 49-0 and 49-1 proceeds by one macro block. Therefore, in the VOP encoders 49-0 and 49-1, encoding processing of a plurality of VOPs is performed in parallel by the pipeline processing method in units of macroblocks.

  The stream buffer 50-0 temporarily stores the bit stream output from the VOP encoder 49-0, the stream buffer 50-1 temporarily stores the bit stream output from the VOP 49-1, and the stream The combining unit 51 combines the bit streams temporarily stored in the stream buffers 50-0 and 50-1.

  In the present embodiment, the reference vector region range required by the macroblock encoded by the VOP encoders 49-0 and 49-1 is determined by the motion vector calculation units 52-0 and 52-1, but is not necessarily the same as the FCODE information. The reference image region range indicated by the FCODE information ≧ the reference image region range actually used by the VOP encoders 49-0 and 49-1 may be satisfied.

  FIG. 6 is a diagram showing an operation example of an embodiment of the image encoding device of the present invention. 6A shows the encoding process timing in the VOP encoders 49-0 and 49-1, and FIG. 6B shows the progress of encoding at time T shown in FIG. 6A. Note that the reference image area range = ± 32 (FCODE = 2), and the VOP arrangement of the created bitstream is composed of only I-VOP and P-VOP, and I0 and P1 are VOP encoders 49-0 and 49, respectively. As an example, it is created at -1.

  Since the reference image area range = ± 32, the VOP encoder 49-1 starts the encoding process of P1 when the VOP encoder 49-0 completes the encoding process of the third macroblock at the top of the I0 frame. be able to. This encoding start control is performed by the memory control unit 48 as described above. When the encoders of I0 and P1 in the VOP encoders 49-0 and 49-1 are started at such timing, FIG. The encoding progress status of I0 and P1 in the VOP encoders 49-0 and 49-1 at time T shown in A) is as shown in FIG.

  6B, reference numeral 60 denotes a processing macro block in the VOP encoder 49-0, 61 denotes a processing macro block in the VOP encoder 49-1, and 62 denotes a motion vector range of the processing macro block 61.

  As described above, according to an embodiment of the image encoding device of the present invention, the VOP encoders 49-0 and 49-1 each have a reference image area that requires each macroblock to start encoding processing of each macroblock. Therefore, the two VOPs can be encoded in parallel. Therefore, high processing performance can be realized without increasing the operating frequency. If the processing performance is the same as that when serially processing a picture, the operating frequency of the VOP encoders 49-0 and 49-1 can be halved to reduce power consumption. it can.

  Patent Document 2 describes an MPEG encoder that divides one picture into four images and processes the four divided images in parallel. One embodiment of the image encoding device of the present invention is a picture encoder. This is to perform parallel processing at the level, and is not suggested by Patent Document 2.

  In the above-described embodiment, the case where the image decoding apparatus and the image encoding apparatus of the present invention are applied to an MPEG decoder and an MPEG encoder for the MPEG-4 system has been described as an example, but the image decoding apparatus and the image code of the present invention are described. The encoding apparatus can also be applied to image decoding apparatuses and image encoding apparatuses such as MPEG decoders and MPEG encoders for the MPEG-2 system.

  Here, when arranging the image decoding apparatus and the image encoding apparatus of the present invention, the image decoding apparatus and the image encoding apparatus of the present invention include at least the following image decoding apparatus and image encoding apparatus.

  (Supplementary note 1) A plurality of picture decoding processing units for decoding a plurality of pictures in parallel are provided, and the decoding start timing of each macroblock of each picture decoding processing unit is set in the reference image area of each macroblock. An image decoding apparatus characterized by being after decoding is completed.

  (Supplementary note 2) The image decoding apparatus according to supplementary note 1, further comprising: a bitstream analysis unit that analyzes an input bitstream and distributes pictures to the plurality of picture decoding processing units.

  (Supplementary Note 3) The bitstream analysis unit extracts reference image region range information of a macroblock from the bitstream, and decodes each macroblock of the plurality of picture decoding processing units based on the reference image region range information The image decoding apparatus according to appendix 2, wherein the decoding processing activation control of the plurality of picture decoding processing units is performed so that the processing start timing is after completion of decoding of the reference image area of each macroblock.

  (Supplementary Note 4) The bitstream analysis unit provides a macroblock processing activation signal to each picture decoding processing unit so that the decoding processing in each picture decoding processing unit is synchronized in units of macroblocks, and decoding in each picture decoding processing unit 4. The image decoding apparatus according to appendix 3, wherein the control is performed so that the process proceeds one macroblock at a time.

  (Supplementary note 5) The image decoding apparatus according to supplementary note 1, wherein each of the plurality of picture decoding processing units includes a picture detection unit that extracts only a specific picture from an input bitstream.

  (Supplementary Note 6) Each of the plurality of picture decoding processing units has means for notifying the control unit of in-picture position information and reference image region position information of a macroblock to be decoded, and the control unit is in units of macroblocks. The image decoding apparatus according to appendix 5, wherein start and standby of decoding processing in the plurality of picture decoding processing units are controlled.

  (Supplementary note 7) A plurality of picture encoding processing units for encoding a plurality of pictures in parallel, and the encoding processing start timing of each macroblock of each picture encoding processing unit in the reference image area of each macroblock An image encoding apparatus characterized in that the encoding is performed after completion of encoding.

  (Additional remark 8) It has a control part which distributes a picture to the said several picture encoding process part, The said control part starts the encoding process of each macroblock of the said several picture encoding process part from the reference image area information of a macroblock The image encoding apparatus according to appendix 7, wherein the encoding process activation control of the plurality of picture encoding processing units is performed so that the timing is after completion of encoding of the reference image area required by each macroblock.

  (Supplementary note 9) The control unit performs encoding processing activation control of the plurality of picture encoding processing units in units of macro blocks so that encoding processing in the plurality of picture encoding processing units is synchronized in units of macro blocks. The image encoding apparatus according to appendix 8.

It is a block diagram of the principal part of 1st Embodiment (MPEG decoder) of the image decoding apparatus of this invention. It is a figure which shows the operation example of 1st Embodiment (MPEG decoder) of the image decoding apparatus of this invention. It is a block diagram of the principal part of 2nd Embodiment (MPEG decoder) of the image decoding apparatus of this invention. It is a figure which shows the operation example of 2nd Embodiment (MPEG decoder) of the image decoding apparatus of this invention. It is a block diagram of the principal part of one Embodiment (MPEG encoder) of the image coding apparatus of this invention. It is a figure which shows the operation example of one Embodiment (MPEG encoder) of the image coding apparatus of this invention. It is a figure which shows the structure of the frame image in MPEG-2. It is a block diagram of the principal part of an example of the conventional MPEG decoder. It is a block diagram of the principal part of the other example of the conventional MPEG decoder.

Explanation of symbols

DESCRIPTION OF SYMBOLS 17 ... Bit stream analysis part 18-0-18-3 ... VOP decoder 19 ... Frame memory 20 ... Memory control part 20-0-20-3 ... Variable length decoding part 21-0-21-3 ... Dequantization part 22 -0 to 22-3 ... inverse discrete cosine transform unit 23-0 to 23-3 ... motion compensation unit 31-0 to 31-3 ... VOP decoder 32 ... frame memory 33 ... memory control unit 34 ... decode control unit 35-0 ˜35-3, VOP detectors 36-0 to 36-3, variable length decoders 37-0 to 37-3, inverse quantization units 38-0 to 38-3, inverse discrete cosine transform units 39-0 to 39, -3 ... motion compensation unit 40-0 to 40-3 ... reference image region position calculation unit 47 ... frame memory 48 ... memory control unit 49-0, 49-1 ... VOP encoder 50-0, 50-1 ... stream buffer 51 ... strike Ream synthesis unit 52-0, 52-1 ... motion vector calculation unit 53-0, 53-1 ... subtraction unit 54-0, 54-1 ... discrete cosine transform unit 55-0, 55-1 ... quantization unit 56- 0, 56-1 ... variable length encoding unit 57-0, 57-1 ... inverse quantization unit 58-0, 58-1 ... inverse discrete cosine transform unit 59-0, 59-1 ... adder

Claims (5)

A plurality of picture decoding processing units for decoding a plurality of pictures in parallel;
An image decoding apparatus characterized in that the decoding processing start timing of each macroblock of each picture decoding processing unit is after completion of decoding of the reference image area of each macroblock.   The image decoding apparatus according to claim 1, further comprising: a bit stream analysis unit that analyzes an input bit stream and distributes pictures to the plurality of picture decoding processing units.   2. The image decoding apparatus according to claim 1, wherein each of the plurality of picture decoding processing units includes a picture detecting unit that extracts only a specific picture from an input bit stream. Each of the plurality of picture decoding processing units has means for notifying the control unit of in-picture position information and reference image area position information of a macroblock to be decoded,
The image decoding apparatus according to claim 3, wherein the control unit controls start and standby of decoding processing in the plurality of picture decoding processing units in units of macroblocks. Having a plurality of picture encoding processing units for encoding a plurality of pictures in parallel;
An image encoding apparatus characterized in that the encoding process start timing of each macroblock of each picture encoding processing unit is after completion of encoding of a reference image area of each macroblock.

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