JP2006013709A - Driving method of solid state image sensor, solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method of a solid state image sensor in which sufficient reading characteristics can be secured even when the pixel cell size of a solid state image sensor is reduced, and to provide a solid state imaging device. <P>SOLUTION: In a solid state image sensor having a sensor 1 and a charge transfer section 2 where 2n-phase driving is performed by 2n sheets of a transfer electrode 18, x (n<x<2n) sheets of transfer electrodes 18B1, 18B3 and 18A4 out of 2n sheets of the transfer electrode 18 are applied with read-out pulse voltages. The solid state imaging device comprises the solid state image sensor, and a means for applying a voltage to the transfer electrode 18 wherein the read-out pulse voltage is applied from the voltage applying means to the x sheets of the transfer electrode 18B1, 18B3 and 18A4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a driving method of a solid-state imaging device having a charge transfer unit for transferring signal charges, and a solid-state imaging device including the solid-state imaging device.

  In recent years, in CCD solid-state imaging devices used in digital still cameras (DSC) and digital video cameras (DVC), pixel cell sizes have been reduced along with the increase in the number of pixels and the reduction in optical size.

  In a conventional CCD solid-state imaging device, signal charges photoelectrically converted by each light receiving sensor unit are read out to a charge transfer unit such as a vertical transfer register provided on one side of the light receiving sensor unit of each column, and this charge transfer The signal charge is transferred in the unit (see, for example, Patent Document 1 and Patent Document 2).

JP-A-6-77450 (FIG. 7) JP 2002-270811 A (FIGS. 7 and 8)

  However, as the pixel cell size of the solid-state imaging device is reduced, deterioration of basic characteristics such as sensitivity and smear is a problem.

In addition, since the pixel cell size is reduced, the signal charge readout characteristic from the sensor unit to the vertical transfer register is deteriorated. Therefore, it is necessary to increase the readout pulse voltage.
This is because, by reducing the pixel cell size, the stage length of each transfer electrode of the vertical transfer register, that is, the length in the vertical direction (vertical transfer direction) is reduced, and signal charges are read from the sensor unit to the vertical transfer register. This is because the frontage is shortened.

  In order to solve the above-described problems, in the present invention, a solid-state imaging device driving method and a solid-state imaging device that can ensure sufficient readout characteristics even when the pixel cell size of the solid-state imaging device is reduced. It is to provide.

  In the solid-state imaging device driving method of the present invention, the charge transfer unit is 2n (n is a natural number) with respect to the solid-state imaging device having the sensor unit and the charge transfer unit to which the signal charge read from the sensor unit is transferred. 2n-phase driving is performed by the transfer electrodes), and the read pulse voltage is applied to x transfer electrodes satisfying n <x <2n among the 2n transfer electrodes.

  The solid-state imaging device of the present invention includes a sensor unit and a solid-state imaging device having a charge transfer unit for transferring signal charges read from the sensor unit, and a voltage applying unit that applies a voltage to the transfer electrode of the charge transfer unit. The charge transfer unit is configured to perform 2n-phase driving by 2n (n is a natural number) transfer electrodes, and x satisfying n <x <2n among the 2n transfer electrodes by the voltage applying unit. A read pulse voltage is applied to one transfer electrode.

According to the solid-state imaging device driving method of the present invention described above, by applying a read pulse voltage to x transfer electrodes that satisfy n <x <2n among 2n transfer electrodes that are driven in 2n phase. Compared with the normal configuration in which the read pulse voltage is applied to n transfer electrodes, the number of transfer electrodes to which the read voltage is applied can be increased to widen the opening for reading.
As a result, the signal charge can be easily read out, so that the readout voltage for reading out the signal charge from the sensor unit to the charge transfer unit can be reduced.

According to the configuration of the solid-state imaging device of the present invention described above, the read pulse voltage is applied to the x transfer electrodes satisfying n <x <2n among the 2n transfer electrodes that are driven by the 2n phase by the voltage application unit. The number of transfer electrodes to which the read voltage is applied is increased and the opening for reading is widened compared to the configuration of a normal device in which the read pulse voltage is applied to the n transfer electrodes. Can do.
As a result, the signal charge can be easily read out, so that the readout voltage for reading out the signal charge from the sensor unit to the charge transfer unit can be reduced.

In the solid-state imaging device driving method of the present invention and the solid-state imaging device of the present invention, the signal charges are read from at least the sensor unit between the sensor units adjacent to each other in the charge transfer direction of the charge transfer unit. The channel stop region may not be formed in a part of the structure.
In such a configuration, among the x transfer electrodes to which the read pulse voltage is applied, the charge transfer unit below the transfer electrode of the transfer electrode corresponding to the sensor transfer unit adjacent to the charge transfer direction of the charge transfer unit. In the path for reading signal charges from the sensor part, the channel stop region does not become a barrier because the channel stop region is not formed at least in a part on the reading side. As a result, the signal charge can be easily read out to the charge transfer unit below the transfer electrode of the transfer electrode corresponding to the sensor unit adjacent in the charge transfer direction of the charge transfer unit.
Therefore, the signal charge can be read more easily, and the read voltage can be further reduced.

According to the present invention described above, since the read voltage can be reduced, sufficient read characteristics can be ensured even if the size of the pixel cell is reduced.
Thereby, the size of the pixel cell can be reduced, so that the number of pixels of the solid-state imaging device can be increased and the size of the solid-state imaging device can be reduced.

In addition, since the readout voltage can be reduced, the power consumption of the solid-state imaging device can be reduced.
In addition, since the readout voltage can be reduced, the voltage application means for applying a voltage to the transfer electrode for signal charge readout can be shared with other voltage application means, thereby reducing the number of power supplies in the system. It is also possible to do.
Furthermore, since it is possible to reduce the occurrence of defective read defects caused by a high read voltage, it is possible to stably manufacture a solid-state image sensor having good read characteristics, and the manufacturing yield of the solid-state image sensor. Can also be improved.

  Furthermore, the readout voltage can be further lowered by adopting a configuration in which the solid-state imaging device has a part of the channel stop region between pixels.

First, FIG. 1 shows a schematic configuration diagram (plan view) of an embodiment of a solid-state imaging device to which the present invention is applied. FIG. 2 shows a cross-sectional view of the solid-state imaging device of FIG.
In this solid-state imaging device, the sensor units 1 composed of photoelectric conversion elements are arranged in a matrix as shown in FIG. 1, and signals accumulated by the sensor unit 1 on one side (left side in FIG. 1) of each sensor unit row. A vertical transfer register 2 is provided as a charge transfer unit for transferring charges, and an imaging region 3 is configured by the sensor unit 1 and the vertical transfer register 2.
A horizontal transfer register 4 is connected to one end of the vertical transfer register 2, and an output buffer 5 is connected to one end of the horizontal transfer register 4.

As shown in FIG. 2, a P-type semiconductor well region 12 is formed on a semiconductor substrate, for example, an N-type silicon substrate 11. An N-type charge accumulation region 13 and a P-type high concentration (P ⁺⁺ ) positive charge accumulation region constituting the sensor unit 1 and an N-type transfer channel of the vertical transfer register 2 are formed on the surface of the N-type silicon substrate 11. A region 16 and a second P-type semiconductor well region 15 therebelow and a P-type (P ⁺ ) channel stop region 7 are formed. A read gate unit 6 is provided between the sensor unit 1 and the left vertical transfer register 2, and a channel stop region 7 is formed between the sensor unit 1 and the right vertical transfer register 2.
A transfer electrode 18 made of, for example, a polycrystalline silicon layer is formed on the N-type silicon substrate 11 via a gate insulating film 17. The transfer electrode 18 is formed over the vertical transfer register 2, the read gate unit 6, and the channel stop region 7. A light shielding film 20 made of aluminum or tungsten is formed on the transfer electrode 18 via an interlayer insulating film 19. The light shielding film 20 has an opening on the sensor unit 1, and light enters the sensor unit 1 through the opening.
A passivation film 21 and a planarizing layer 22 are formed on the light shielding film 20, and an on-chip lens 23 is formed on the planarizing layer 22.
Further, a color filter (not shown) is provided between the planarization layer 22 and the on-chip lens 23 as necessary.

  In the vertical transfer register 2, the transfer channel region 16 in the silicon substrate 11, the gate insulating film 17, and the transfer electrode 18 constitute a charge transfer unit having a CCD structure.

Here, FIG. 3 shows a conceptual diagram of the potential in the reading direction (A′-A) and the depth direction (A′-A ″) from the sensor unit 1 in the solid-state imaging device shown in FIGS. 1 and 2.
The signal charge e accumulated in the sensor unit 1 is read out from the sensor unit 1 to the vertical transfer register 2 when a high-level read pulse voltage (φV1 = High) is applied to the transfer electrode 18.
Factors that control the read characteristics from the sensor unit 1 to the vertical transfer register 2 include the read pulse voltage, the potential distribution of the sensor unit 1, and the ROG (read gate) length.
Note that the signal charge e overflowed from the sensor unit 1 beyond the overflow barrier caused by the P-type semiconductor well region 12 is discharged to the substrate 11 side.

FIG. 8 shows a plan view when the configuration for reading signal charges from the sensor unit 1 to the vertical transfer register 2 is the same as that of a normal solid-state imaging device.
FIG. 8 shows a configuration in which the transfer electrode 18 of the vertical transfer register 2 is configured by two normal polycrystalline silicon layers and four-phase driving is performed.
The transfer electrodes 18A2 and 18A4 made of the lower polycrystalline silicon layer and the transfer electrodes 18B1 and 18B3 made of the upper second polycrystalline silicon layer partially overlap each other in the vertical transfer register 2. Are arranged alternately.
The first-phase vertical transfer pulse voltage φV1 is applied to the transfer electrode 18B1 made of the second polycrystalline silicon layer, and the second-phase vertical transfer pulse is applied to the transfer electrode 18A2 made of the first polycrystalline silicon layer. A voltage φV2 is applied, a third-phase vertical transfer pulse voltage φV3 is applied to the transfer electrode 18B3 made of the second polycrystalline silicon layer, and a transfer electrode 18A4 made of the first polycrystalline silicon layer is applied to the first transfer electrode 18A4. A four-phase vertical transfer pulse voltage φV4 is applied.
Then, as shown in the timing chart of FIG. 9, the readout pulse 30 is applied to the vertical transfer pulse voltages φV1 and φV3 applied to the transfer electrodes 18B1 and 18B3 made of the second polycrystalline silicon layer, respectively. Signal charges are read from the unit 1 to the vertical transfer register 2.
As a result, the transfer electrodes 18B1 and 18B3 made of the second polycrystalline silicon layer also serve as the readout electrodes, respectively, and the length L of the readout aperture matches the effective length of the transfer electrodes 18B1 and 18B3.

  As the pixel cell size is reduced, in the configuration shown in FIG. 8, the reading openings (length L) of the transfer electrodes 18B1 and 18B3 made of the second polycrystalline silicon layer become narrower. As the characteristics deteriorate, it is necessary to increase the read voltage.

  Further, since the pixel cell size is reduced, the size of each part is reduced and the blooming margin is reduced. Therefore, it is necessary to change the potential distribution configuration of the sensor unit 1 in order to secure the blooming margin. If an attempt is made to secure a blooming margin in this way, the read characteristics become more severe.

Therefore, the solid-state imaging device shown in FIGS. 1 and 2 is driven so as to increase the number of transfer electrodes 18 to which the read pulse voltage is applied, as compared with the configuration of FIG.
As an embodiment of the present invention, a case in which driving is performed in this way will be described.

  In the present embodiment, in particular, as shown in the plan view of FIG. 4, the transfer electrode 18B1 to which the first-phase vertical transfer pulse φV1 is applied and the transfer electrode 18B3 to which the third-phase vertical transfer pulse φV3 is applied are applied. In addition to applying the read pulse, the read pulse is also applied to the transfer electrode 18A4 between the transfer electrodes 18B1 and 18B3.

As a result, as indicated by an arrow in FIG. 4, the signal charge is also read out to the vertical transfer register 2 by the transfer electrode 18A4.
The signal charges accumulated in the sensor unit 1 in the upper row in FIG. 4 are transferred from the sensor unit 1 through the transfer electrode 18B3 and the transfer electrode 18A4 in the lower silicon substrate 11 (the portion becomes the read gate unit 6). , Read to the transfer channel region 16 of the vertical transfer register 2.
The signal charges accumulated in the sensor unit 1 in the lower row in FIG. 4 are transferred from the sensor unit 1 through the transfer electrode 18A4 and the transfer electrode 18B1 in the silicon substrate 11 therebelow (that portion becomes the read gate unit 6). , Read to the transfer channel region 16 of the vertical transfer register 2.

  In order to drive in this way, as shown in the timing chart of FIG. 5, the readout pulse 30 is also applied to the fourth-phase vertical transfer pulse φV4 applied to the transfer electrode 18A4.

By driving in this way, the reading window (length L) is made of the first polycrystalline silicon layer sandwiched between the transfer electrodes 18B1 and 18B3 made of the second polycrystalline silicon layer. As the transfer electrode 18A4 is added, it is wider than the conventional case (see FIG. 8), so that the signal charge can be easily read.
In this case, the length L of the reading front is substantially the length of the sensor unit 1.

In order to perform the above-described driving, voltage applying means (for example, a wiring, a voltage control circuit, a power supply unit, etc.) for applying a voltage to each transfer electrode 18B1, 18A2, 18B3, 18A4 of the vertical transfer register 2 is provided. What is necessary is just to comprise so that the read pulse 30 may be applied also to the transfer electrode 18A4.
And a solid-state image sensor and such a voltage application means are provided, and a solid-state imaging device is comprised.

According to the above-described embodiment, since the read pulse 30 is also applied to the fourth-phase vertical transfer pulse φV4 applied to the transfer electrode 18A4, the four transfer electrodes 18B1, four-phase drive are provided. A read pulse 30 is applied to three transfer electrodes 18B1, 18B3, and 18A4 of 18A2, 18B3, and 18A4. The charge is read out.
As a result, an opening for reading signal charges from the sensor unit 1 to the vertical transfer register 2 is widened, and signal charges can be easily read.
Thereby, the voltage of the read pulse 30, that is, the read voltage can be reduced as compared with the conventional configuration.
Accordingly, even if the size of the pixel cell is reduced, sufficient readout characteristics can be ensured.

Since the readout voltage can be reduced, the power consumption of the solid-state imaging device can be reduced.
In addition, since the readout voltage can be reduced, the voltage application means for applying a voltage to the transfer electrode for signal charge readout can be shared with other voltage application means, thereby reducing the number of power supplies in the system. It is also possible to do.

Further, since the read voltage can be reduced, it is possible to reduce read defect defects that occur due to a high read voltage.
Therefore, it is possible to stably manufacture a solid-state imaging device having good readout characteristics, and the manufacturing yield of the solid-state imaging device can be improved.

  Next, another embodiment of the present invention will be described.

In the configuration of a normal CCD solid-state imaging device, as shown in a schematic plan view in FIG. 10, a channel stop region 7 is provided in a hatched region in the silicon substrate.
That is, the channel stop region 7 includes a vertical transfer register 2 between the sensor units 1 of pixels adjacent to each other in the vertical transfer direction, and on the opposite side of the sensor unit 1 and the signal electrode readout side (the side with the readout gate unit). (Channel stop region 7 in the cross-sectional view of FIG. 2).
Further, by providing the channel stop region 7 between the sensor portions 1 of the pixels adjacent to each other in the vertical transfer direction, the generation of charges that cause smear between pixels and the color mixture of charges between pixels are suppressed. ing.

On the other hand, in the present embodiment, as shown in a schematic plan view in FIG. 6, the sensor of the adjacent pixel between the sensor unit 1 in the upper row and the sensor unit 1 in the lower row in the figure. A part of the channel stop region 7 (write channel stop; LCS) between the parts 1 is cut out and formed only on a part of the side opposite to the reading side (on the right vertical transfer register 2 side of the sensor part 1). ing.
Note that there is a channel stop region between the sensor unit 1 in the upper row in the figure and the sensor unit in the upper row (not shown), and between the sensor unit 1 in the lower row and the sensor unit in the lower row (not shown). 7 is formed as a whole.

  In the present embodiment, similarly to the previous embodiment, the transfer electrode 18A4 to which the fourth-phase vertical transfer pulse φV4 is applied is also driven to apply the read pulse 30.

In this way, the transfer electrode 18A4 is also driven to apply the readout pulse 30, and as described above, a part of the channel stop region 7 between the sensor portions 1 of the pixels adjacent in the vertical transfer direction is removed. As indicated by an arrow in FIG. 6, it becomes possible to read signal charges from the sensor unit 1 to the transfer channel region 16 below the transfer electrode 18A4, and the length L of the reading unit is widened. Can be almost the same.
At this time, since the channel stop region 7 does not become a barrier in the path for reading the signal charges from the sensor unit 1 to the transfer channel region 16 below the transfer electrode 18A4, the transfer electrode 18A4 is more easily formed than in the previous embodiment. The signal charge can be read out to the lower transfer channel region 16.

However, when the present embodiment is applied to a normal interline transfer (IT) type solid-state imaging device, the combination of pixels from which signal charges are read out for each field (odd field and even field) when performing field readout. Therefore, it is necessary to remove the channel stop region 7 between all the sensor sections.
Thus, if the channel stop region 7 is removed between all the sensor units in one row, it is disadvantageous for smear and color mixing.

Therefore, it is desirable to apply the configuration in which the channel stop region 7 between the sensor units 1 of the present embodiment is removed when the combination of pixels from which signal charges are read is fixed.
As a configuration in which the combination of pixels from which signal charges are read out is fixed, for example, there is a configuration in which all pixels can be read out (progressive scan) with a vertically double-dense structure.
For example, as described in Japanese Patent Application Laid-Open No. 2000-184286, the vertical double-dense structure always has two vertical sensor units (photoelectric conversion elements), which is twice the normal number. By adding signal charges between two specific sensor units, all pixel readout is possible.

When the configuration of the present embodiment is applied to a vertically double dense structure, in FIG. 6, the upper row sensor units 1 and the lower row sensor units 1 are combined one by one up and down, Each of the two sensor units 1 is configured to add signal charges.
Thereby, in the combination of the sensor units 1 that always add signal charges, the channel stop region 7 between the sensor units 1 can be removed to widen the reading window.

Here, in the configuration of the conventional CCD solid-state imaging device and the configuration in which the channel stop region 7 between the three-electrode readout and the sensor unit 1 of the present embodiment is omitted, the potential distribution was obtained by simulation. The obtained potential contour lines are shown in FIG. 7A shows the case of the conventional configuration shown in FIG. 8, and FIG. 7B shows the case of the configuration of the present embodiment.
Comparing FIG. 7A and FIG. 7B, it can be seen that, by using the configuration of the present embodiment, the signal charge reading window for the vertical transfer register 2 of the sensor unit 1 is widened and the reading is facilitated.

  According to the above-described embodiment, the read voltage pulse is applied to the three transfer electrodes 18B1, 18B3, and 18A4 out of the four-phase drive transfer electrodes 18 (18B1, 18A2, 18B3, and 18A4) as in the previous embodiment. By driving so as to add, the reading window can be wider than the conventional structure, so that the reading characteristics can be improved and the reading voltage can be reduced.

  Further, according to the present embodiment, the channel stop region 7 between the adjacent sensor units 1 is removed, so that in the path for reading signal charges from the sensor unit 1 to the transfer channel 16 below the transfer electrode 18A4, the channel stop Since the region 7 does not become a barrier, the signal charge can be easily read out, so that the read voltage can be further reduced.

Accordingly, even if the size of the pixel cell is reduced, sufficient readout characteristics can be ensured.
Thereby, the size of the pixel cell can be reduced, so that the number of pixels of the solid-state imaging device can be increased and the size of the solid-state imaging device can be reduced.

  Since the readout voltage can be reduced, the power consumption of the solid-state imaging device can be reduced, and the voltage application unit that applies the voltage to the transfer electrode for signal charge readout is replaced with another voltage application unit. It is also possible to reduce the number of power supplies in the system.

Further, since the read voltage can be reduced, it is possible to reduce read defect defects that occur due to a high read voltage.
Therefore, it is possible to stably manufacture a solid-state imaging device having good readout characteristics, and the manufacturing yield of the solid-state imaging device can be improved.

  In the present embodiment, most of the channel stop region 7 between the sensor units 1 is removed. However, for example, only half or only a part of the channel stop region 7 between the sensor units 1 is extracted on the readout side. Even if it does in this way, compared with the structure which formed all without pulling out the channel stop area | region 7, the effect which makes the read of a signal charge easy is acquired.

  In each of the above-described embodiments, the transfer electrode 18 of the vertical transfer register 2 is configured by two electrode layers, and four-phase driving is performed in the vertical transfer register 2. However, the present invention has other electrode layer numbers. It is also possible to apply to a driving configuration.

In the present invention, a read pulse is applied to x transfer electrodes satisfying n <x <2n out of 2n in a solid-state imaging device that drives 2n phases by 2n (n is a natural number) transfer electrodes. Constitute. That is, x is in the range of (n + 1) to (2n-1). As a result, it is possible to widen the reading window and reduce the read voltage, compared to the normal configuration in which the read pulse is applied to the n transfer electrodes of the 2n transfer electrodes.
In the present invention, it is desirable that 2n transfer electrodes are composed of n electrode layers.

In each of the above-described embodiments, the case where the present invention is applied to a CCD solid-state imaging device in which the sensor units 1 are arranged in a matrix has been described. However, in the present invention, for example, the sensor units are arranged in a line. The present invention can also be applied to a CCD solid-state imaging device.
Furthermore, the present invention is not limited to a CCD solid-state imaging device in which a vertical transfer register having a CCD structure is formed as a charge transfer unit, but may be applied to any solid-state imaging device having a charge transfer unit capable of performing similar charge transfer driving. Is possible.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

It is a schematic block diagram (plan view) of one form of a solid-state image sensor to which the present invention is applied. It is sectional drawing of the solid-state image sensor of FIG. FIG. 2 is a conceptual diagram of potentials in a reading direction and a depth direction from the sensor unit of the solid-state imaging device in FIG. 1. It is a top view which shows the electrode structure in one embodiment of this invention. It is a drive timing chart in one embodiment of the present invention. It is a schematic plan view which shows the position of the channel stop area | region in other embodiment of this invention. A is a potential contour line in the case of the electrode structure of FIG. B is a potential contour line in the case of the electrode structure of FIG. It is a top view which shows the conventional electrode structure. It is a timing chart of the conventional drive. It is a typical top view which shows the position of the channel stop area | region of the conventional structure.

Explanation of symbols

1 sensor unit, 2 vertical transfer register, 4 horizontal transfer register, 6 readout gate unit, 7 channel stop region, 13 charge storage region, 14 positive charge storage region, 16 transfer channel region, 18, 18B1, 18A2, 18B3, 18A4 transfer Electrode, 20 light shielding film, 23 on-chip lens

Claims (4)

For a solid-state imaging device having a sensor unit and a charge transfer unit for transferring signal charges read from the sensor unit,
The charge transfer unit is configured to perform 2n-phase driving by 2n (n is a natural number) transfer electrodes,
A reading pulse voltage is applied to x transfer electrodes satisfying n <x <2n among the 2n transfer electrodes.   The solid-state imaging device has a configuration in which a channel stop region is not formed at least in a part on the side where signal charges are read from the sensor unit between the sensor units adjacent to each other in the charge transfer direction of the charge transfer unit. The method for driving a solid-state imaging device according to claim 1, wherein A solid-state imaging device having a sensor unit and a charge transfer unit for transferring signal charges read from the sensor unit;
Voltage application means for applying a voltage to the transfer electrode of the charge transfer unit,
The charge transfer unit is configured to perform 2n-phase driving by 2n (n is a natural number) transfer electrodes,
A readout pulse voltage is applied to the x transfer electrodes satisfying n <x <2n among the 2n transfer electrodes by the voltage applying unit.   The solid-state imaging device has a configuration in which a channel stop region is not formed at least in a part on the side where signal charges are read from the sensor unit between the sensor units adjacent to each other in the charge transfer direction of the charge transfer unit. The solid-state imaging device according to claim 3.

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