JP2006012009A - Monitoring circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress costs for measures against noise and stabilization of power source voltage in a monitoring circuit which is effective technology for use in a fail-safe system for detecting an abnormal operation of a computer and automatically making it take an avoiding actions, etc. <P>SOLUTION: The monitoring circuit is provided with a means (1) for charging electric charge to a capacitor, a power source voltage determination means (5) for monitoring the power source voltage of a monitoring object, a first discharging means (2a) for performing discharge when an amount of the electric charge of the capacitor exceeds a first amount of electric charge, a second discharging means (2b) for performing discharge of the capacitor when the power supply voltage becomes less than first reference voltage and an amount of electric charge judgment means (4) for generating a signal to reset the monitoring object when the amount of electric charge of the capacitor becomes less than second amount of electric charge set as lower than the first amount of electric charge by discharge of the electric charge of the capacitor after the amount of electric charge of the capacitor exceeds the first electric charge. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a monitoring circuit which is an effective technique for use in a fail-safe system or the like that detects an abnormal operation of a computer and automatically takes avoidance measures.

FIG. 5 shows a circuit diagram of a conventional monitoring circuit. The conventional monitoring circuit shown in FIG. 3 safely protects the microcomputer 107 when the power supply voltage 108 (VDD) of the microcomputer 107, which is an example of the monitoring target, is lower than the power supply voltage for the microcomputer 107 to operate safely. Monitoring the power supply voltage 108 of the microcomputer 107 for ending the process, and resetting the microcomputer 107 when the time when the microcomputer 107 is not operating normally exceeds a predetermined time. Sometimes the arrival interval of the normal operation clock output from the microcomputer 107 is measured. The power supply voltage 108 of the microcomputer 107 is monitored by using the comparator 105 which is power supply voltage determination means, and the normal operation clock interval is monitored by the constant current source 101 which is charging means and the constant current source which is discharging means. By controlling the current source 102a and the NMOS transistor 102b serving as the discharging means, the amount of charge accumulated in the capacitor 103 is measured by the window comparator 104 serving as the charge amount judging means to create a certain time, and the normal operation clock is reached. Observe and do. Therefore, when the power supply voltage 108 is normal, not during power reduction, and the normal operation clock is input to the monitoring circuit, the microcomputer 107 continues to operate without being reset. The same power supply voltage is used for the power supply voltage of the microcomputer 107 and the power supply of the monitoring circuit.

The operation of the conventional monitoring circuit shown in FIG. 5 will be described with reference to the voltage fluctuation diagram of the conventional monitoring circuit shown in FIG. In FIG. 6, the vertical axis represents voltage, and the horizontal axis represents time. The graphs shown in FIG. 6 are (a) the power supply voltage 108 of the microcomputer 107, (b) the normal operation clock from the microcomputer 107, and (c) the window. The charge amount of the capacitor 103 measured by the comparator 104, (d) a reset signal (low and reset state) from the comparator 105 and the window comparator 104 to the microcomputer 107, and (e) the output of the window comparator 104 are shown.

A vertical line (0) in FIG. 6 indicates the timing when the power is supplied to the conventional monitoring circuit and the microcomputer 107 shown in FIG. At this time, the constant current source 101 that is a charging circuit is started, but the constant current source 102a that discharges faster than the charging speed of the constant current source 101 and the NMOS transistor 102b that discharges the capacitor 103 by a switching operation are also started. Therefore, the electric charge of the capacitor 103 is not accumulated. Since the constant current source 101 that is a charging circuit is always activated unless the power of the monitoring circuit is turned off, the charge of the capacitor 103 is generated when the constant current source 102a and the NMOS transistor 102b that are discharging means are not activated. The capacitor 103 continues to accumulate charges, and the capacitor 103 is discharged by activating the constant current source 102a and the NMOS transistor 102b. When the NMOS transistor 102b is activated, the charge of the capacitor 103 is instantaneously discharged as compared with the case where only the constant current source 102a is activated.

A vertical line (6) and a vertical line (10) in FIG. 6 indicate that the normal operation clock from the microcomputer 107 shown in the conventional monitoring circuit in FIG. 5 is not input to the monitoring circuit. The timing at which the charge of 103 is accumulated and the charge amount of the capacitor 103 measured by the window comparator 104 as charge amount determination means exceeds the threshold voltage (VCthh) on the high side of the window comparator 104 is shown. At this time, the output of the window comparator 104 becomes high, and the microcomputer 107 is reset by the output high of the window comparator 104.

The vertical lines (3) and (8) in FIG. 6 indicate the timing when the power supply voltage 108 monitored by the conventional monitoring circuit in FIG. 5 decreases and falls below the low-side threshold voltage (VDDthl) of the comparator 105. ing. At this time, the microcomputer 107 is reset by the output of the comparator 105.

The vertical line (2) and vertical line (5) in FIG. 6 indicate that the normal operation clock from the microcomputer 107 is input to the conventional monitoring circuit in FIG. The timing at which discharge of the electric charge 103 starts is shown.

The vertical line (1), vertical line (4), and vertical line (9) in FIG. 6 indicate that the power supply voltage 108 of the microcomputer 107 of the conventional monitoring circuit in FIG. The timing when it exceeds (VDDthh) is shown. At this time, the constant current source 102a and the NMOS transistor 102b which are discharging means are stopped.

The output of the window comparator 104 in FIG. 5 has the waveform shown in the graph (e) in FIG. The logic circuit 106 operates so as to transmit or not transmit the output of the window comparator 104 to the microcomputer 107 and the constant current source 102a. The logic circuit 109 also operates so as to transmit the output of the comparator 105, the logic circuit 106, and the microcomputer 107 to the constant current source 101 or not. Reference numeral 108 shown in FIG. 5 is also a power supply voltage of the monitoring circuit, and the resistor groups 110a, 110b, and 110c are used to set a high-side threshold voltage and a low-side threshold value voltage (VCthl) of the window comparator 104. .

The conventional monitoring circuit shown in FIG. 5 has been described above. In summary, when the electric charge of the capacitor 103 is accumulated and the voltage measured by the window comparator 104 exceeds the high-side threshold voltage of the window comparator 104, the The microcomputer 107 is reset by the output, and when the power supply voltage 108 decreases and falls below the low-side threshold voltage of the comparator 105, the microcomputer 107 operates to reset the microcomputer 107 by the output of the comparator 105. The microcomputer 107 is reset by one path. When the power supply voltage 108 drops and falls below the low threshold voltage of the comparator 105, the microcomputer 107 is reset, and at the same time, the capacitor 103 is instantly discharged to measure a certain period. Similarly, in Japanese Utility Model Laid-Open No. 5-40942, the electric charge of the capacitor is instantaneously discharged.
Japanese Utility Model Publication 5-40942

However, in the conventional monitoring circuit shown in FIG. 5, the normal operation clock (A) from the microcomputer 107 when the microcomputer 107 is operating normally at the timing of the vertical line (4) shown in FIG. 6 is input to the monitoring circuit. Nevertheless, the microcomputer 107 is reset even when the power supply voltage 108 returns to normal due to the instantaneous interruption of the power supply voltage 108 caused by noise or the like indicated by the vertical line (3) in FIG. B) shown. That is, the microcomputer 107 is reset although the microcomputer 107 is operating normally. In this way, the microcomputer is reset when the power supply voltage is momentarily interrupted by noise, etc., even during normal operation of the microcomputer, which means that the cost for noise countermeasures and stabilization of the power supply voltage will be spent. Since the microcomputer is reset, the processing of the controlled object controlled by the microcomputer is interrupted, resulting in a problem that the processing speed of the microcomputer and the electronic device including the controlled object is reduced.

The present invention has been made in order to solve the above-described problems inherent in the prior art in view of the above-described actual situation, and an object of the present invention is to provide a monitoring circuit that easily realizes noise countermeasures. Furthermore, it is providing the semiconductor device provided with the above-mentioned monitoring circuit.

In order to achieve the above object, the monitoring circuit according to claim 1 comprises:
Means for charging the capacitor with charge;
Power supply voltage determination means for monitoring the power supply voltage to be monitored;
First discharge means for discharging when the charge amount of the capacitor exceeds the first charge amount;
Second discharge means for discharging the capacitor when the power supply voltage falls below a first reference voltage;
After the charge amount of the capacitor exceeds the first charge amount, the charge of the capacitor is discharged to fall below a second charge amount set lower than the first charge amount. Charge amount determination means for issuing a signal for resetting the audit target;
It is characterized by providing.

The monitoring circuit according to claim 2 comprises:
When the power supply voltage to be monitored falls below the first reference voltage, the charge of the capacitor is discharged, so that the power supply voltage to be monitored is reduced until the charge amount falls below the second charge amount. 2. The monitoring circuit according to claim 1, wherein the second discharge unit is stopped when the second reference voltage set higher than the first reference voltage is exceeded after returning.

The monitoring circuit according to claim 3 comprises:
When the power supply voltage to be monitored falls below the first reference voltage, the charge of the capacitor is discharged, so that the power supply voltage to be monitored is reduced until the charge amount falls below the second charge amount. 2. The monitoring according to claim 1, wherein the first and the second discharging means are stopped when returning and exceeding the second reference voltage set higher than the first reference voltage. Circuit.

The monitoring circuit according to claim 4, wherein the first discharging means is a constant current source, the second discharging means is an NMOS transistor, and an on-resistance of the NMOS transistor is determined based on the first charge amount. 4. The monitoring circuit according to claim 1, wherein the monitoring circuit is set so as to discharge a charge corresponding to the second charge amount in 5 to 400 μs.

The monitoring circuit according to claim 5, wherein the first and second discharging means are constant current sources, and the power supply voltage determining means is a comparator. The monitoring circuit according to any one of the above.

A semiconductor device according to a sixth aspect is a semiconductor device comprising the monitoring circuit according to any one of the first to fifth aspects.

It is possible to provide a monitoring circuit that easily implements noise countermeasures and eliminates unnecessary interruption of processing of a microcomputer that is operating normally. Disappear.

Compared with the conventional monitoring circuit shown in FIG. 5, the monitoring circuit according to the present invention shown in FIG. 1 does not have a path for resetting the microcomputer by the output of the power supply voltage determination means, and discharges by the switching operation. The on-resistance of the NMOS transistor to be performed is increased (in this embodiment, the amount of on-resistance required for about 40 μs for discharging the charge of the capacitor 3 to almost zero is intentionally set) to suppress the discharge capability. It is. Also, after the power supply voltage falls below the low threshold voltage of the comparator, which is the power supply voltage determination means, the NMOS transistor (second discharge means), which is the discharge means, is restored when the comparator returns to the high threshold voltage of the comparator. It works to stop.

The operation of the first embodiment of the monitoring circuit according to the present invention shown in FIG. 1 will be described below using the voltage fluctuation diagram of the monitoring circuit according to the first embodiment according to the present invention shown in FIG.
In FIG. 2, the vertical axis represents voltage and the horizontal axis represents time, and the graphs shown in FIG. 2 are (a) the power supply voltage 8 of the microcomputer 7, (b) the normal operation clock from the microcomputer 7, and (c The figure shows the charge amount of the capacitor 3 measured by the window comparator 104, (d) the reset signal from the comparator 5 to the microcomputer 7 (low and reset state), and (e) the output of the window comparator 4.

A vertical line (0) shown in FIG. 2 indicates a timing when the monitoring circuit according to the present invention in FIG. 1 and the microcomputer 7 to be monitored are turned on. At this time, the constant current source 1 which is a charging circuit is activated, but the constant current source 2a (first discharging means) and the NMOS transistor 2b (second discharging means) each discharge faster than the charging speed of the constant current source 1. The capacitor 3 is not charged. It should be noted that the constant current source 1 is always activated unless the monitoring circuit is powered off.

The vertical line (1) shown in FIG. 2 indicates the timing when the power supply voltage 8 of the microcomputer 7 exceeds the high-side threshold voltage (VDDthh which is the second reference voltage) of the comparator 5 which is the power supply voltage determination means. At this time, the constant current source 2a, which is a discharging means, and the NMOS transistor 2b having a high on-resistance are stopped by the output of the comparator 5, so that the charge of the capacitor 3 starts to accumulate. Note that the high-side threshold voltage of the comparator 5 and the low-side threshold voltage (VDDthl, which is a first reference voltage), which will be described later, are given hysteresis by feeding back the output of the comparator 5 and performing resistance division. It is set.

A section between the vertical line (1) and the vertical line (2) shown in FIG. 2 shows a state in which charges are accumulated in the capacitor 3 by the constant current source 1.

A vertical line (2) shown in FIG. 2 indicates that charge is accumulated in the capacitor 3, and the charge amount of the capacitor 3 is the threshold voltage on the low side of the window comparator 4 serving as charge amount determination means (voltage VCthl corresponding to the second charge amount). This indicates the timing when the output of the window comparator 4 becomes low. At this time, the logic circuit 6 operates so as not to transmit the low output of the window comparator 4. The logic circuit 9 also transmits or does not transmit the output of the window comparator 4, the comparator 5, and the microcomputer 7 to the constant current source 1 that is the charging means, the constant current source 2 a that is the discharging means, and the NMOS transistor 2 b with high on-resistance. To work. Note that a low-side threshold voltage and a later-described high-side threshold voltage (voltage VCthh corresponding to the first charge amount) of the window comparator 4 respectively divide the power supply voltage 8 of the window comparator 4 by resistors 10a, 10b, and 10c. Is set by.

A section between the vertical line (2) and the vertical line (3) shown in FIG. 2 shows a state in which charges are accumulated in the capacitor 3 by the constant current source 1.

A vertical line (3) shown in FIG. 2 indicates a timing at which charges are accumulated in the capacitor 3 and the amount of charge of the capacitor 3 measured by the window comparator 4 exceeds the high-side threshold voltage of the window comparator 4. At this time, the output of the window comparator 4 becomes high, and the output of the window comparator 4 brings the microcomputer 7 into a reset release state. Further, the constant current source 2a, which is a discharging means, is activated by the output of the window comparator 4.

The section between the vertical line (3) and the vertical line (4) shown in FIG. 2 shows a state in which the electric charge of the capacitor 3 is released because the constant current source 2a which is a discharge circuit is activated.

A vertical line (4) shown in FIG. 2 indicates the timing when the charge of the capacitor 3 is released and the amount of charge of the capacitor 3 measured by the window comparator 4 falls below the high-side threshold voltage of the window comparator 4. At this time, the output of the window comparator 4 becomes low, but the logic circuit 6 operates so as not to transmit the output low of the window comparator 4.

A section between the vertical line (4) and the vertical line (5) shown in FIG. 2 shows a state in which the capacitor 3 is discharged because the constant current source 2a is activated.

A vertical line (5) shown in FIG. 2 indicates the timing at which the normal operation clock from the microcomputer 7 is input to the monitoring circuit according to the present invention. The normal operation clock arrives from the microcomputer 7 by controlling the constant current source 2a which is a discharging means of the monitoring circuit. When the normal operation clock from the microcomputer 7 is input to the monitoring circuit according to the present invention, the constant current source 2a serving as the discharging means stops and the charge of the capacitor 3 starts to be accumulated.

A section between the vertical line (5) and the vertical line (6) shown in FIG. 2 shows a state in which the electric charge is accumulated in the capacitor 3 because the constant current source 2a serving as the discharging means is stopped.

The monitoring circuit according to the present invention shown in FIG. 1 has a vertical line (6) in the timing shown in FIG. 2 and a section (between the vertical line (6) and the vertical line (7)). Since the operation is the same as the timing of 3) and the section shown between the vertical line (3) and the vertical line (4), the description is omitted.

The vertical line (8) shown in FIG. 2 indicates that the charge of the capacitor 3 is discharged by the constant current source 2 a serving as a discharging means, and the charge amount of the capacitor 3 measured by the window comparator 4 is lower than the low-side threshold voltage of the window comparator 4. Shows the timing. At this time, the output of the window comparator 4 becomes high, the microcomputer 4 is reset by the output of the window comparator 4, and the constant current source 2a as a discharging means is stopped.

The section shown between the vertical line (8) and the vertical line (9) shown in FIG. 2 shows a state in which the electric charge of the capacitor 3 starts to be accumulated because the constant current source 2a serving as the discharging means has stopped. .

The monitoring circuit according to the present invention shown in FIG. 1 has the vertical line (2) shown in FIG. 2 in the timing of the vertical line (9) shown in FIG. 2 and the section between the vertical lines (9) and (11). ) And the same operation as the section shown between the vertical line (2) and the vertical line (4), the description of the operation is omitted.

A vertical line (12) shown in FIG. 2 indicates a timing at which the power supply voltage 8 of the microcomputer 7 decreases due to noise or the like and falls below the low-side threshold voltage of the comparator 5. At this time, the output of the comparator 5 activates the NMOS transistor 2b having a higher discharge resistance than the constant current source 2a which is a discharging means, so that the potential of the capacitor 3 is activated only by the constant current source 2a. Compared to when it begins to fall sharply.

In the section between the vertical line (12) and the vertical line (13) shown in FIG. 2, the charge of the capacitor 3 is discharged by the constant current source 2a as the discharging means and the NMOS transistor 2b with high on-resistance as the discharging means. It shows the state. Note that the on-resistance of the NMOS transistor 2b having a high on-resistance is set such that the constant current source 2a and the NMOS transistor 2b having a high on-resistance cause the charge of the capacitor 3 corresponding to the threshold voltage on the high side of the window comparator 4 serving as the charge amount judging means. It is set so that it takes about 40 μs to release the electric charge corresponding to the low-side threshold voltage of the window comparator 4.

The vertical line (13) shown in FIG. 2 indicates the timing when the power supply voltage 8 returns from the instantaneous stage and exceeds the threshold voltage on the high side of the comparator 5. At this time, the output of the comparator 5 stops the NMOS transistor 2b having a high on-resistance, which is a discharging means.

A section between the vertical line (13) and the vertical line (13b) indicates a state in which the electric charge of the capacitor 3 is discharged by the constant current source 2a which is a discharging means.

A vertical line (13 b) indicates the timing at which the normal operation clock from the microcomputer 7 is input to the logic circuit 109. The constant current source 2a, which is a discharging means, is stopped by the normal operation clock from the microcomputer 7.

In the section between the vertical line (13b) and the vertical line (14) shown in FIG. 2, the constant current source 2a as the discharging means and the NMOS transistor 2b with high on-resistance as the discharging means are stopped. A state is shown in which the electric charge starts to be accumulated in the capacitor 3 by the constant current source 1 as means.

The monitoring circuit according to the present invention shown in FIG. 1 has a vertical line (10) in the timing of the vertical line (14) shown in FIG. 2 and the section between the vertical line (14) and the vertical line (15). ) And the same operation as the section between the vertical line (10) and the vertical line (11), the description of the operation is omitted.

A vertical line (16) shown in FIG. 2 indicates the timing when the power supply voltage 8 falls below the low-side threshold voltage of the comparator 5 due to noise or the like. At this time, the NMOS transistor 2b having a high on-resistance, which is a discharging means, is activated by the output of the comparator 5.

In the section between the vertical line (16) and the vertical line (17) shown in FIG. 2, the charge of the capacitor 3 is instantaneously generated by the constant current source 2a as the discharge means and the NMOS transistor 2b with high on-resistance as the discharge means. The released state is shown.

A vertical line (17) shown in FIG. 2 indicates the timing when the electric charge of the capacitor 3 is released and the potential of the capacitor 3 measured by the window comparator 4 falls below the threshold voltage on the low side of the window comparator 4. At this time, the output of the window comparator 4 becomes high, and the microcomputer 7 is reset by the output of the window comparator 4.

Although the section between the vertical line (17) and the vertical line (18) shown in FIG. 2 is moving from the instantaneous interruption of the power supply voltage 8 to the recovery, the electric charge of the capacitor 3 is discharged from the constant current source 2a as a discharging means. The state is shown as being emitted by the MOS transistor 2b having a high N-on resistance, which is a means.

A vertical line (18) shown in FIG. 2 indicates a timing when the microcomputer 7 recovers from an instantaneous interruption of the power supply voltage 8 and exceeds the threshold voltage on the high side of the comparator 5. At this time, the constant current source 2a as the discharging means and the NMOS transistor 2b with high on-resistance as the discharging means are stopped by the output of the comparator 5.

The section shown between the vertical line (18) and the vertical line (19) shown in FIG. 2 is a constant charging source because the constant current source 2a serving as a discharging unit and the NMOS transistor 2b having a high on-resistance serving as a discharging unit are stopped. A state in which electric charges are accumulated in the capacitor 3 by the current source 1 is shown.

The monitoring circuit according to the present invention shown in FIG. 1 has a vertical line (9) in the timing between the vertical line (19) shown in FIG. 2 and the section between the vertical line (19) and the vertical line (21). ) And the same operation as the section between the vertical line (9) and the vertical line (11), the description of the operation is omitted.

As described above, in the monitoring circuit according to the present invention shown in FIG. 1, the capacitor 3 is discharged, the potential of the capacitor 3 measured by the window comparator 4 is lowered, and the threshold voltage on the low side of the window comparator 4 is reduced. If it falls below, the microcomputer 7 is reset by the output of the window comparator 4, and when the power supply voltage 8 falls below the low-side threshold voltage of the comparator 5, the microcomputer 7 is not reset by the output of the comparator 5. The output of the comparator 5 activates the NMOS transistor 2b having a high on-resistance, which is a discharging means, and discharges the charge of the capacitor 3, whereby the voltage measured by the window comparator 4 becomes the threshold voltage on the low side of the window comparator 4. If it falls below, the microcomputer 7 is reset by the output of the window comparator 4 It is intended to operate. That is, the monitoring circuit according to the present invention monitors the normal operation clock interval of the microcomputer 7 and the power supply voltage 8 of the microcomputer 7, but there is only one path for resetting the microcomputer 7.

When the voltage falls below the level at which the microcomputer can operate safely, it is necessary to reset the microcomputer in order to safely stop the microcomputer. The conventional monitoring circuit of FIG. 5 resets when there is no need to reset the circuit, but the monitoring circuit according to the present invention shown in FIG. 1 has only one path for resetting the microcomputer, and the capacitor. It is possible to secure a certain amount of time by releasing the electric charge of the microcomputer, and when the power supply voltage of the microcomputer decreases instantaneously due to noise, etc., and immediately recovers, the microcomputer does not reset. It is.

From the above, the voltage fluctuation of the monitoring circuit according to the present invention does not generate the unnecessary reset signal (B) shown in FIG. 6 of the voltage fluctuation of the conventional monitoring circuit. The circuit can easily implement noise countermeasures.

The operation of the second embodiment of the monitoring circuit according to the present invention shown in FIG. 3 will be described below with reference to the voltage fluctuation diagram of the second embodiment of the monitoring circuit according to the present invention shown in FIG. In the second embodiment, the operation of the logic circuit 9 is changed as compared with the first embodiment, and a path from the comparator 5 serving as the power supply voltage determination means to the logic circuit 109 is provided, so that the power supply voltage is on the low side of the comparator 5. When the voltage falls below the threshold voltage, both the constant current source 2a (first discharge means), which is a discharge circuit, and the NMOS transistor 2b (second discharge means) having a high on-resistance are stopped. In FIG. 4, the vertical axis represents voltage and the horizontal axis represents time. The graphs shown in FIG. 4 are (a) the power supply voltage 8 of the microcomputer 7, (b) the normal operation clock from the microcomputer 7, and (c The figure shows the charge amount of the capacitor 3 measured by the window comparator 104, (d) the reset signal from the comparator 5 to the microcomputer 7 (low and reset state), and (e) the output of the window comparator 4.

The voltage fluctuation diagram of the monitoring circuit according to the present invention shown in FIG. 4 shows that the charge of the capacitor 3 is charged at the timing indicated by the vertical line (13) as compared with the voltage fluctuation diagram of the monitoring circuit according to the present invention shown in FIG. The state has changed. When the power supply voltage 8 of the microcomputer 7 falls below the low-side threshold voltage of the comparator 5 and then returns to the high-side threshold voltage, the output of the comparator 5 turns on the constant current source 2a, which is a discharging means, and turns on. This is because the logic circuit 9 operates so as to stop both the NMOS transistors 2b having high resistance.

As described above, even when the monitoring circuit according to the second embodiment of the present invention shown in FIG. 3 is used, the problem of the conventional monitoring circuit can be solved as in the first embodiment of the monitoring circuit according to the present invention. .

The present invention is not limited to the above-described embodiment, and all design changes within the scope of the matters described in the claims are included in the scope of the present invention. For example, the on-resistance of the NMOS transistor 2b having a high on-resistance described in the first embodiment of the present invention is merely an example, and the value of the on-resistance can be set according to the magnitude of noise to be removed. The on-resistance is a time of 5 μm to 400 μs for discharging the electric charge of the capacitor 3 corresponding to the threshold voltage on the high side of the window comparator 4 serving as the charge amount judging means until the threshold voltage on the low side of the window comparator 4 is reached. It may be set to take. Further, although the NMOS switch 2b is used in the discharging means of the present invention, substantially the same effect can be obtained even if the charge of the capacitor is discharged by replacing the NMOS transistor 2b having a high on-resistance with a constant current source. Even if an analog switch is used as the discharging means, it is possible to achieve substantially the same purpose.

1 is a block diagram of a monitoring circuit according to a first embodiment of the present invention. Voltage fluctuation diagram of Embodiment 1 (FIG. 1) of the monitoring circuit according to the present invention. FIG. 2 is a block diagram of a monitoring circuit according to a second embodiment of the present invention. Voltage fluctuation diagram of Embodiment 2 (FIG. 3) of the monitoring circuit according to the present invention Block diagram of a conventional monitoring circuit Voltage fluctuation diagram of conventional monitoring circuit (Fig. 5)

Explanation of symbols

1, 2a Constant current source 2b NMOS transistor 3 Capacitor 4 Window comparator 5 Comparator 6, 9 Logic circuit 7 Microcomputer 8 Power supply voltage 10a, 10b, 10c for microcomputer and monitoring circuit Resistance

Claims (6)

Means for charging the capacitor with charge;
Power supply voltage determination means for monitoring the power supply voltage to be monitored;
First discharge means for discharging when the charge amount of the capacitor exceeds the first charge amount;
Second discharge means for discharging the capacitor when the power supply voltage falls below a first reference voltage;
After the charge amount of the capacitor exceeds the first charge amount, the charge of the capacitor is discharged to fall below a second charge amount set lower than the first charge amount. Charge amount determination means for issuing a signal for resetting the audit target;
A monitoring circuit comprising: When the power supply voltage to be monitored falls below the first reference voltage, the charge of the capacitor is discharged, so that the power supply voltage to be monitored is reduced until the charge amount falls below the second charge amount. 2. The monitoring circuit according to claim 1, wherein the second discharging means is stopped when the second reference voltage set higher than the first reference voltage is exceeded after returning. When the power supply voltage to be monitored falls below the first reference voltage, the charge of the capacitor is discharged, so that the power supply voltage to be monitored is reduced until the charge amount falls below the second charge amount. 2. The monitoring according to claim 1, wherein the first and the second discharging means are stopped when returning and exceeding the second reference voltage set higher than the first reference voltage. circuit. The first discharge means is a constant current source, and the second discharge means is an NMOS transistor, and the on-resistance of the NMOS transistor corresponds to the second charge amount from the first charge amount. The monitoring circuit according to any one of claims 1 to 3, wherein the monitoring circuit is set so as to release the electric charge to be emitted in 5 to 400 µsec. 4. The monitoring circuit according to claim 1, wherein the first and second discharging means are constant current sources, and the power supply voltage determining means is a comparator. 6. A semiconductor device comprising the monitoring circuit according to claim 1.

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