JP2006004133A - Error correction and detection device in information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem in that the size of the LSI (large-Scale Integration) of an ASIC (Application-Specific Integrated Circuit) is inflated, causing the rise in the cost for the LSI since the more the number of DIMMs (Dual Inline Memory Modules) connected to the ASIC increases, the more the number of pins increases. <P>SOLUTION: In an error correction and detection device in an information processor, each ASIC 5, 6 of a first ASIC group prepares a group of ECCs (Error Correction Code) in the first ASIC group and has a function generating an ECC code for write data and adding the ECC code to the write data; a function dividing the write data with the ECC code into each ASIC 7, 8 of a second ASIC group; and an ECC check and ECC correction function for read data delivered from the DIMM. Each ASIC 7, 8 of the second ASIC group has: a function controlling the DIMM; a function sorting the write data so that the group of the ECCs generated in the first ASIC group may not access the same element in the DIMM; and a function returning the data sorted in writing to the original order for the read data delivered from the DIMM. Each function allows a one-byte error correction or two-byte error detection. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention is used in various information processing apparatuses such as a server that uses a general-purpose memory module (DIMM: Dual Inline Memory Module), and corrects errors in both hardware failure and software error in the information processing apparatus. The present invention relates to an error correction and detection apparatus in an information processing apparatus capable of detection.

(1): Conventional example 1
Conventional example 1 is an example using a single byte error detection code. Conventionally, as an example of using a single-byte error detection code, an example in which an ECC block is configured with 16 bytes + 16 ECC bits and a total of 144-bit data has been known. Since this ECC can correct a 4-bit block and detect a failure at two locations in a 4-bit block, it can be corrected and detected by accessing two DIMMs.

(2): Conventional example 2
Hereinafter, Patent Document 1 will be described as Conventional Example 2. Conventional example 2 (patent document 1) will be described with reference to patent document 2. Conventional example 2 (Patent Document 1) is to provide an efficient double-length single error correction double error detection Reed-Solomon code decoder that operates at a high speed with a small amount of hardware.

When 1 byte is b bits, a check matrix having a length of (2 ^b +2) × 2 bytes is used, and this is particularly effective for codes having an information bit length of 128 and a check bit length of 16. It has means for determining whether it is a single error or a double error. The decoder includes syndrome generation means, single error correction means, double error determination means, error detection means, and the like. Hereinafter, related technologies will be described in detail.

  (a): In a large-capacity storage device, an error correction / detection code is necessary to improve the reliability of operation. For this reason, 1-bit error correction / 2-bit error detection codes have been used. Furthermore, due to advances in semiconductor technology, several bits of information are stored as one byte in a single memory device. In this case, several bits are collectively errored due to a failure of one memory element.

For a storage device using this type of element, a code capable of detecting or correcting a byte error is effective. In the computer, 32, 64, and 128 are used as information bits. The present invention relates to a single byte error correction double byte error detection code that performs error processing in units of bytes, and is particularly effective in the case of information bits 128. This type of conventional example will be described. In this specification,
｜ ｜ ｜ ｜
｜ ｜
Is the sign of the matrix.

First, the basic form of a Reed-Solomon code that performs single-byte error double-byte error detection is shown. When α is the primitive element of GF (2 ^b ), the inspection matrix is as follows.

ただし、ｑ＝２^b 。この符号の符号長ｎ＝ｂ×（２^b ＋２）であり、ｂ＝４のとき、ｎ＝７２、情報ビットｋ＝６０となり、情報ビット６４、１２８の符号が構成できない。

Where q = 2 ^b . The code length of this code is n = b × (2 ^b +2). When b = 4, n = 72 and information bit k = 60, and the codes of information bits 64 and 128 cannot be configured.

Next, the code of Kanada and Fujiwara (“Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems”, IEEE Trans.on Computer, C-31, NO. 7, july 1982) uses the following check matrix. First, let T be the adjoint matrix of g (x) = X ⁴ + x + 1 that constitutes GF (2 ⁴ ). T and α are essentially the same.

として、さらに、Ｈ₀ の行を巡回させて、４倍の長さの検査マトリクスＨを作る。ｂ＝４であり、符号長ｎ＝９×４×４＝１４４、検査ビット長＝１６、情報ビット＝１２８である。モジュラ構成のため復号が複雑になる。

Further, the inspection matrix H having a length four times as long as the H ₀ row is circulated. b = 4, code length n = 9 × 4 × 4 = 144, check bit length = 16, and information bits = 128. Decoding is complicated due to the modular structure.

  Kanada and Fujiwara “Main Memory Error Detection / Correction Code” (Nippon Telegraph and Telephone Public Corporation, Research Practical Report Vol. 30, No. 4, 1981), a general method using byte error detection means at each byte position. A method is described.

Next, the inspection matrix of Patent Document 2 is valid for 64 bits of information and is described. when the q = 2 ^b, test matrix becomes the following equation.

これは、左半分のｑ−１列の基本行列を行巡回して、右半分におき、４列の単位検査マトリクスを加えている。ｂ＝４のとき、ｎ＝１５×２×４＋４×４＝１３６、情報ビットは１２０となる。情報ビットを１２８にするためには、３プロック構造となり復号は複雑になる。

In this method, a basic matrix of q-1 columns in the left half is cycled and placed in the right half, and a unit check matrix of 4 columns is added. When b = 4, n = 15 × 2 × 4 + 4 × 4 = 136, and information bits are 120. In order to set the information bits to 128, a three-block structure is used and decoding is complicated.

  The conventional (above) codes constituting the effective single-byte error correction / double-byte error detection code for the information bits 128 have complicated decoding methods. Therefore, it is necessary to find a check matrix of a single byte error correction / double byte error detection code effective for information bits 128, and to configure a decoder with a high decoding speed and a small amount of hardware.

  The present invention has been made to solve such problems, and is effective for information bits 128. In general, single-byte error correction / double-byte error detection in which b bits are one byte. An object of the present invention is to provide a decoder for double-length single error correction double error detection Reed-Solomon codes with a small amount of hardware by finding a code check matrix.

The error correction processing apparatus according to claim 1, wherein b bit is one byte, single byte error correction / double byte error detection code is adopted, q = 2 ^b is set,

の検査行列を用いると共に、下記の(1) 乃至(6) の手段を含むことを特徴とする。

And the following means (1) to (6) are included.

  (1) Syndrome generating means for generating syndromes C1, C2, C3, and C4 from the received sequence using the parity check matrix. However, C corresponds to the first row of the check matrix, C2 corresponds to the second row of the check matrix, C3 corresponds to the third row of the check matrix, and C4 corresponds to the fourth row of the check matrix.

  (2) Means for determining that there is no error when all the syndromes C1, C2, C3, and C4 are zero.

  (3) Means for determining the byte position in error.

  (4) Means for determining the magnitude of error.

  (5) Means to correct the error byte position information using the error size when there is a single error.

  (6) Means for detecting double errors.

  The error correction processing apparatus according to claim 2 is characterized in that an error checking means is provided at each byte position as means for obtaining a byte position having an error. According to this method, the amount of hardware increases, but high-speed decoding is performed.

The error correction processing apparatus according to claim 3 includes, as a part of means for detecting a double error, a double in each block of a block of q−1 columns and a block of q−1 columns from the left of the parity check matrix. In order to detect an error, S ₀ = C 1 + C 2, S ₁ = C 3, S ₂ = C 4, and if Z = S ₁ ² + S ₀ · S ² = 0 is true, one unit error is assumed, and if false, 2 is assumed. It includes a double error judging means for judging a serious error.

  The double-length single error correction double error detection Reed-Solomon code decoder according to the present invention uses an efficient check matrix to constitute a decoder with a small amount of hardware, and receives a received word. Syndrome is generated, single byte errors are corrected, and double byte errors are corrected at high speed.

(3): Conventional example 3
FIG. 6 is a conventional chip configuration diagram, and FIG. 7 is a chip configuration diagram when an ASIC having an interface with a conventional DIMM is divided. Hereinafter, Conventional Example 3 will be described with reference to FIGS.

(a): Explanation of chip configuration The example shown in FIG. 6A is a basic chip configuration, in which one ASIC0 is connected to the CPU, and one ASIC2 is connected to the one ASIC0. In this configuration, two (or two) DIMMs (DIMM: Dual Inline Memory Module) are connected to the one ASIC 2.

  In addition, the example shown in FIG. 6B is an example in which the one ASIC0 is divided into two, and two ASIC1 (the one obtained by dividing the ASIC0) is connected to the CPU, and the two ASIC0s are connected. In this configuration, one ASIC 2 is connected to the ASIC 1, and two DIMMs are connected to the one ASIC 2.

(b): Explanation of a chip configuration when an ASIC having an interface with a DIMM is divided. In the example shown in FIG. 7 (a), one ASIC 2 shown in FIG. 6 (a) is divided into two. In this example, one ASIC 0 is connected to the CPU, two ASICs 4 (the one ASIC 2 divided into two parts) are connected to the one ASIC 0, and one is connected to each of the two ASICs 4 This is a configuration in which the DIMMs are connected.

  Further, the example shown in FIG. 7B is an example in which one ASIC 0 shown in FIG. 7A is divided into two, and the CPU is divided into two ASICs 1 (one ASIC 0 is divided into two. In other words, one ASIC 4 is connected to each of the two ASICs 4, and one DIMM is connected to each of the two ASICs 4.

(4): Conventional example 4
Hereinafter, Patent Document 3 will be described as Conventional Example 4. Conventional Example 4 relates to a self-healing memory configuration, does not require a complicated data recovery method, performs error detection and correction for a plurality of errors on a plurality of channels, and supports hot swapping of a failed memory. A memory system configuration is provided.

  The memory configuration includes a CPU bus electrically coupled to the memory controller, a memory controller connected to the switching means, and a switch electrically connected to the plurality of memory modules.

  The plurality of memory modules include at least one data memory module, at least one data correction memory module, and at least a hot spare module. The data memory module, the error correction memory module, and the hot spare memory module are connected in parallel.

  Further, Conventional Example 4 also describes the following contents. That is, the size of available server memory systems continues to increase over time, and current server memory systems are often 64 gigabytes or more. As the size of the memory system increases, the possibility of failure of the memory bits, that is, the failure of the memory system, also increases.

  Memory system failures can occur with both temporary or permanent errors. Transient errors are generally caused by alpha particles. Permanent errors generally include memory cell wall failure, row or column decoder failure, state machine failure, or mechanical between the printed circuit board of a dual in-line memory module (hereinafter “DIMM”) and the system printed circuit board. There are other catastrophic failures such as interface failures.

(4): Conventional example 5
Hereinafter, Patent Document 4 will be described as Conventional Example 5. Conventional Example 5 relates to a redundant memory module and a memory controller, and enables abnormal DIMMs to be dynamically replaced during system operation.

  In the present invention, the ECC / ChipKill circuits 4-0 to 4-4 are used to generate / check / reconfigure the ECC and the parity generation / check / reconfiguration circuit 5 that performs ChipKill. When data is read, parity data is checked, and if an abnormal DIMM exists, the data is reconfigured from the normal DIMM.

As a result, by preparing one parity DIMM1-4 for four DIMMs 1-0 to 103, it is possible to hot-plug an abnormal DIMM in the event of a DIMM failure, and the memory degeneration function of the OS Allows dynamic exchange of DIMMs regardless.
JP-A-6-29865 JP 52-123147 A JP 2001-167001 A JP 2003-303139 A

(1): Issues of conventional examples 1 to 3
(a): In the case of the conventional example, as the number of DIMMs connected to the ASIC 2 increases, the number of PINs increases, so the LSI size of the ASIC 2 increases and the cost of the LSI increases.

  (b): As shown in FIG. 7, by dividing the ASIC into two ASICs 4, the number of pins per ASIC 4 can be reduced and the cost can be reduced. That is, in the normal case, the cost of the ASIC 2 shown in FIG. 6 and the two ASICs 4 obtained by dividing the ASIC 2 is two.

  (c): The figure in (a) of Fig. 7 uses ASIC0 to generate check bits and syndromes using single byte (1 byte) error and double byte (2 byte) error detection codes. It is possible to perform error correction / detection. However, as shown in FIG. 7B, in the example in which ASIC0 is also divided into two ASIC1, error correction and detection can be performed by using a single byte error / double byte error detection code in the CPU. In systems equipped with multiple CPUs, such as large machines, there are very many data exchanges between CPUs, so 16 byte single byte (1 byte) error, double byte (2 byte) error The detection code is not effective because the bit width is large.

(2): Problems of Conventional Examples 4 and 5 Conventional Examples 4 and 5 describe the above contents, but do not describe the specific configuration described in the claims of the present invention. The content is for reference only.

  The present invention solves the problem of the conventional example, creates an ECC block by a plurality of ASICs, and prevents the ECC block from being assigned to the same DIMM (general-purpose memory module, for example, DRAM) element. By allocating data to each other, it is possible to detect a single byte (1 byte) error and a double byte (2 byte) error, and to reduce the number of pins for one LSI.

(1): Error correction and detection in an information processing apparatus having a CPU, an ASIC, and two DIMMs (dual in-line memory module), and transferring write / read data between the CPU and the DIMM via the ASIC A first ASIC group divided into 2 or 4 (2 or 4) ASICs having an interface with the CPU and having the same function; and the first ASIC. And a second ASIC group comprising two ASICs having an interface with the two DIMMs and having the same function, and each ASIC of the first ASIC group has the first ASIC group An ECC block is created in the ASIC group, and the ECC block generates an ECC code for the write data and converts the generated ECC code to the write data. Additional function, a function of distributing write data with an ECC code to each ASIC of the second ASIC group, an ECC check and ECC correction function for read data from the DIMM, and each ASIC of the second ASIC group Includes a function for controlling the DIMM, a function for rearranging write data so that the ECC block generated in the first ASIC group does not access the same element in the DIMM, and a read data from the DIMM. On the other hand, it has a function of returning data rearranged at the time of writing, and each of the functions enables 1-byte error correction or 2-byte error detection.

  (2): An error correction / detection device in an information processing apparatus having a CPU, an ASIC, and two DIMMs, and transferring write / read data between the CPU and the DIMM via the ASIC, A first ASIC group composed of two or four ASICs each having an interface to the CPU and having the same function; an interface between the first ASIC group and the two DIMMs; And a second ASIC group composed of two ASICs having the same function, and each ASIC in the first ASIC group generates an ECC code for write data from the CPU to the DIMM, respectively. ECC code generation circuit to be assigned to write data, and transfer to distribute the write data with ECC code to each ASIC of the second ASIC group Data distribution circuit, ECC check circuit that performs ECC check on read data from DIMM to CPU, and error correction if the check result of the ECC check circuit is 1 byte error, error if it is 2 byte error An ECC correction circuit that performs only detection is provided, and each ASIC of the second ASIC group includes a memory controller that controls the DIMM, and an ECC block generated by the first ASIC group is the same in the DIMM. A write data rearrangement circuit that rearranges data so as not to access the elements, and a read data rearrangement circuit that restores the data rearranged at the time of writing to the read data from the DIMM. To do.

(Function)
Hereinafter, the operation based on the above configuration will be described with reference to FIG.

  (a): In the above (1), when data is written from the CPU to the two DIMMs, the write data is distributed and transmitted from the CPU to each ASIC (5, 6, etc.) of the first ASIC group. At this time, each ASIC in the first ASIC group creates an ECC block in the first ASIC group, and generates an ECC code for the write data using the ECC block, and converts the ECC code to the write data. Append. Then, the write data with the ECC code is distributed and transmitted to each ASIC (7, 8) in the second ASIC group.

  In addition, each ASIC in the second ASIC group performs DIMM control to rearrange the write data so that the ECC block generated in the first ASIC group does not access the same element in the DIMM. And write to DIMM.

  Further, each ASIC in the second ASIC group restores the data rearranged at the time of writing to the read data from the DIMM, and transmits the data to each ASIC in the first ASIC group. Each ASIC in the first ASIC group performs an ECC check on the received read data from the DIMM, corrects the read data if it is a 1-byte error, and only detects an error if it is a 2-byte error. To the CPU.

  (b): In (2), when data is written from the CPU to the two DIMMs, the write data is distributed and transmitted from the CPU to each ASIC (5, 6, etc.) of the first ASIC group. At this time, in each ASIC of the first ASIC group, the ECC code generation circuit 15 generates an ECC code for the write data from the CPU to the DIMM and assigns it to the write data. The transfer data distribution circuit 16 distributes the write data with the ECC code to each ASIC of the second ASIC group and transmits it.

  In each ASIC of the second ASIC group, when the write data rearrangement circuit 27 receives the write data with the ECC code, the write data rearrangement circuit 27 rearranges the data so that the ECC chunk is not assigned to the same DIMM, and the memory controller Write to the DIMM under the control of 26.

  Read data from the DIMM is read from the DIMM under the control of the memory controller 26, and the read data rearrangement circuit 28 restores the read data rearranged at the time of writing to the read data from the DIMM. . Thereafter, the restored read data is transmitted to each ASIC in the first ASIC group.

  In each ASIC of the first ASIC group, the ECC check circuit 19 performs an ECC check on the received read data, and the ECC correction circuit 20 performs error correction if the check result of the ECC check circuit 19 is a 1-byte error. If there is a 2-byte error, only error detection is performed. Thereafter, the data is transmitted to the CPU.

  (c): As described above, an ECC chunk is created by a plurality of ASICs, and data is allocated so that the ECC chunk is not assigned to the same DIMM (DRAM) element. It is possible to detect (1 byte) error and double byte (2 byte) error, and to reduce the number of pins for one LSI.

(1): Even in a configuration in which the number of ASIC pins per unit is reduced, it is possible to perform ECC correction and detection of DIMMs, so that the cost can be expected to be reduced with the same reliability.

  (2): A single byte (1 byte) is created by creating ECC chunks with multiple ASICs and allocating data so that the ECC chunks are not assigned to the same DIMM (Dual Inline Memory Module) element. ) Error and double byte (2 byte) error detection can be performed, and the number of pins for one LSI can be reduced.

§1: Explanation of simple chip configuration and connection FIG. 2 is an explanatory diagram of the chip configuration and connection. Hereinafter, an error correction / detection device in an information processing apparatus, and its simple chip configuration and connection will be described with reference to FIG.

(a): Description of error correction / detection device and its simple chip configuration and connection The device described below has a CPU, a plurality of ASICs, and two DIMMs (Dual Inline Memory Modules). An error correction / detection device in an information processing device that transfers write / read data to and from the device via an ASIC.

  In this apparatus, the ASIC has an interface with the CPU and a first ASIC group divided into two ASICs 5 and 6 having the same function, and an interface with the first ASIC group and the DIMM. And a second ASIC group composed of two ASICs 7 and 8 having the same function.

  Each ASIC of the first ASIC group creates an ECC block in the first ASIC group, and the ECC block generates an ECC code for write data and writes the generated ECC code. A function for adding data, a function for distributing write data with an ECC code to each ASIC of the second ASIC group, and an ECC check and ECC correction function for read data from the DIMM.

  In addition, each ASIC of the second ASIC group has a function to control the DIMM and rearranges the write data so that the ECC block generated in the first ASIC group does not access the same element in the DIMM. And a function to restore the data rearranged at the time of writing to the read data from the DIMM.

  In this way, ECC chunks are created by ASIC5 and ASIC6, data is rearranged and written so that the ECC chunks are not assigned to the same DIMM element, and the read data read out is based on the data rearranged at the time of writing. By transferring back to, single byte (1 byte) error and double byte (2 byte) error detection becomes possible.

(b): Description of Specific Example of Transfer Data For example, an example will be described in which 64-byte data is sliced from the CPU and 32-byte data is transferred to the ASICs 5 and 6.

  The ASICs 5 and 6 generate 16-byte data and 16-bit check bits using a single-byte error (1-byte error) and double-byte error (2-byte error) detection code in units of 16 bytes, respectively. The data is divided into byte data and 8-bit check bits and transferred to the ASICs 7 and 8.

  At this time, in a system that requires the accuracy of indicating the error location, a new ECC is generated so that error correction / detection is performed between ASICs 5-7, between ASICs 5-8, between ASICs 6-7, and between ASICs 6-8, It is also possible to point out errors.

  Further, in ASICs 7 and 8, 16 bytes total of 32 bytes of data are transferred from ASIC 5 and ASIC 6 respectively, so 8 bytes and 8 bits of check bits, a total of 72 bits of data width (burst length = 4) Access. At this time, data assignment is performed so that ECC blocks created by the ASICs 5 and 6 are written into the same element of the same DIMM (DRAM) and are not read out.

§2: Description of apparatus configuration and processing FIG. 3 is an explanatory diagram of processing. Hereinafter, the configuration and processing of the apparatus will be described with reference to FIG. FIG. 3 shows the processing with the chip configuration shown in FIG.

  (1): The configuration of this device is as follows.

  An error correction / detection device in an information processing apparatus having a CPU, a plurality of ASICs, and two DIMMs, and transferring write / read data between the CPU and the DIMMs via the ASIC, each for the CPU A first ASIC group composed of two ASICs 5 and 6 having an interface and the same function, and two ASICs 7 each having an interface with the first ASIC group and the DIMM and having the same function , 8 and the second ASIC group.

  The CPU includes a program 11 for reading and writing data between the CPU and the two DIMMs, various processes for the data, a request transmission / reception circuit 12 for transmitting / receiving requests, and a plurality of ASICs ( A transfer data distribution circuit 13 for distributing data to the ASICs 5 and 6) is provided.

  Each of the ASICs 5 and 6 in the first ASIC group generates an ECC code for the write data from the CPU to the DIMM and applies the write data to the write data, and the write with the ECC code. Transfer data distribution circuit 16 that distributes data to each ASIC of the second ASIC group, ECC check circuit 19 that performs ECC check on read data from the DIMM to the CPU, and the check result of the ECC check circuit is a 1-byte error. If so, the error correction is performed, and if it is a 2-byte error, the ECC correction circuit 20 that only detects the error, the reception circuit 14 that receives data from the CPU, and the data from each ASIC of the second ASIC group are received. Receiving circuit 18, transmitting circuit 21 for transmitting data to the CPU, and second AS Group C each ASIC7,8 and a transmission circuit 17 for transmitting data.

  The ASICs 7 and 8 of the second ASIC group are respectively the same elements in the DIMM in which the ECC blocks generated by the memory controller 26 for controlling the DIMM and the ASICs 5 and 6 of the first ASIC group are included in the DIMM. A write data rearrangement circuit 27 for rearranging data so as not to access the data, a read data rearrangement circuit 28 for restoring the data rearranged at the time of writing to the read data from the DIMM, and a first ASIC group A receiving circuit 25 for receiving data from each of the ASICs 5 and 6 and a transmitting circuit 29 for transmitting data to each of the ASICs 5 and 6 of the first ASIC group.

  (2): Processing in this device is as follows.

  (a): In the CPU, the request transmission / reception circuit 12 transmits / receives a write / read request to the memory (DIMM) generated by the program 11 in the CPU to the ASICs 5, 6. In this case, the write data is transferred to the distribution ASICs 5 and 6 by the transfer data distribution circuit 13, and the read data is received from the ASICs 5 and 6 and sent to the program 11.

  (b): The ASICs 5 and 6 receive the write / read request from the CPU by the reception circuit 14 and transfer them from the transmission circuit 17 to the ASICs 7 and 8. The write data is also received by the receiving circuit 14, an ECC code is generated by the ECC code generating circuit 15, and added to the write data. Then, after the transfer data distribution circuit 16 distributes the data, the transmission circuit 17 transmits the data to the ASICs 7 and 8. Read data from the DIMM is received by the receiving circuit 18 from the ASICs 7 and 8, and an error check of the data is performed by the ECC check circuit 19.

  The ECC correction circuit 20 corrects if one block (1 byte) is an error out of 36 blocks with 4 bits as one block, and detects if there is an error in 2 blocks (2 bytes). The transmission circuit 21 transmits this fact to the CPU.

  (c): In the ASICs 7 and 8, the write circuit / read data request is received by the receiving circuit 25, converted into a DIMM control signal by the memory controller 26, and sent to the DIMM. The write data is also received by the receiving circuit 25, and the write data rearrangement circuit 27 rearranges the data so that the ECC block generated by the ASICs 5 and 6 does not access the same element in the DIMM. As for the read data, the data rearranged at the time of writing by the read data rearrangement circuit 28 is restored and transmitted to the ASICs 5 and 6 by the transmission circuit 29.

  (d): As described above, even when the LSI is divided, it is possible to perform 1 block correction (1 byte correction) and 2 block detection (2 byte detection) of the DIMM as usual. Further, even when the wiring on the system board fails between the ASICs 5 and 6 and the ASICs 7 and 8 and between the ASICs 7 and 8 and the DIMM, the error can be corrected or detected by the ECC check.

§3: Explanation of data examples and processing
(1): Explanation of data FIG. 4 is an explanatory diagram of a data example. Hereinafter, an example of data will be described with reference to FIG.

  (a): Assume that the illustrated data is stored in the CPU of FIG. In this case, as illustrated, 1ST (first: first) data is 8B (B: byte) data “A0-3” (first 4 bytes) + “A4-7” (second 4 bytes). It is. The 2ND (second: second) data is 8B (B: byte) data “B0-3” (first 4 bytes) + “B4-7” (second 4 bytes).

  The 3RD (third: third) data is 8B (byte) data “C0-3” (first 4 bytes) + “C4-7” (second 4 bytes). The 4TH (fourth) data is 8B (byte) data “D0-3” (first 4 bytes) + “D4-7” (second 4 bytes).

  The 5TH (fifth) data is 8B (byte) data “E0-3” (first 4 bytes) + “E4-7” (second 4 bytes). The 6TH (sixth) data is 8B (byte) data “F0-3” (first 4 bytes) + “F4-7” (second 4 bytes). The 7TH (seventh) data is 8B (byte) data “G0-3” (first 4 bytes) + “G4-7” (second 4 bytes). The 8TH (8th) data is 8B (byte) data “H0-3” (first 4 bytes) + “H4-7” (second 4 bytes).

  It is assumed that a total of 8 bytes of data of the first half 4 bytes and the last 4 bytes are present in the CPU. This data is data written from the CPU to the DIMM or data read from the DIMM.

  (b): When the CPU has the above-mentioned 4-byte data of the first half and 4-byte data of the latter half in the CPU, and writing this data to the DIMM, the 8-byte data from the CPU to the ASICs 5 and 6 Is divided into 4 bytes and transferred.

  At this time, the ASIC 5 has 4 bytes A0-3, 4 bytes B0-3, 4 bytes C0-3, 4 bytes D0-3, 4 bytes E0-3, 4 bytes F0-3, and G0. 4 bytes of -3 and 4 bytes of H0-3 are stored.

  The ASIC 6 includes 4 bytes A4-7, 4 bytes B4-7, 4 bytes C4-7, 4 bytes D4-7, 4 bytes E4-7, 4 bytes F4-7, G4- 7 4 bytes and H4-7 4 bytes are stored.

  When data is written, ECC bits are generated using these data as an ECC block and added to the data. Further, when data is read, data in which an ECC bit is added to these data (transferred data) is checked. Specifically, it is as follows.

  ECC bits j0-F are generated (during data write) / check (during data read) with 16 bytes of A0-3 / B0-3 / C0-3 / D0-3. ECC bits k0-F are generated (during data writing) / checked (during data reading) with 16 bytes of E0-3 / F0-3 / G0-3 / H0-3.

  ECC bits m0-F are generated (during data writing) / checked (during data reading) with 16 bytes of A4-7 / B4-7 / C4-7 / D4-7. ECC bits n0-F are generated (during data write) / check (during data read) with 16 bytes of E4-7 / F4-7 / G4-7 / H4-7.

  In this way, the following data is stored in the ASICs 5 and 6. That is, (A0-3, B0-3, C0-3, D0-3) + (j0-F) and (E0-3, F0-3, G0-3, H0-3) + (k0-F) Data is stored. The ASIC 6 includes (A4-7, B4-7, C4-7, D4-7) + (m0-F) and (E4-7, F4-7, G4-7, H4-7) + (n0 -F) data is stored.

  (c): Next, data transfer is performed between the ASICs 5 and 6 and the ASICs 7 and 8. In this case, the ASIC 7 includes data (A0-3 + j0-3), (C0-3 + j8-B), (E0-3 + k0-3), (G0-3 + k8-B), and (A4-7 + m0-3), ( C4-7 + m8-B), (E4-7 + n0-3), and (G4-7 + n8-B) data are stored.

  The ASIC 8 includes data (B0-3 + j4-7), (D0-3 + jC-F), (F0-3 + k4-7), (H0-3 + kC-F), and (B4-7 + m4-7), (D4). −7 + mC−F), (F0−3 + n4−7), and (H0−3 + nC−F) data are stored.

  When correcting and detecting a failure during data transfer between the ASICs 5-7 and ASIC6 and between the ASICs 6-7 and 8 (correcting if it is 1 bit and only detecting if it is a 2-bit error) Guard with another ECC.

  (d): Next, the ASICs 7 and 8 perform data transfer with the DIMM (read / write data).

  In this case, in the DIMM that performs data transfer with one ASIC 7, the 1st (first) data is A0-3, A4-7, j0-3, m0-3. 2ND (second) data is C4-7, C0-3, m8-B, and j8-B. The 3RD (third) data is data of E0-3, E4-7, k0-3, and n0-3. The 4TH (fourth) data is G4-7, G0-3, n8-B data.

  In the DIMM that performs data transfer with the other ASIC 8, the 1st (first) data is B0-3, B4-7, j4-7, and m4-7. The 2ND (second) data is D4-7, D0-3, mC-F, and jC-F. The 3RD (third) data is data of F0-3, F4-7, k4-7, and n4-7. 4TH (fourth) data is H4-7, H0-3, nC-F, and KC-F data.

  In this way, ECC blocks created by the ASICs 5 and 6 do not access the same DIMM (DRAM).

§4: Explanation when data is sliced into four between CPU and ASIC FIG. 5 is an explanatory diagram when data is sliced into four between CPU and ASIC. Hereinafter, with reference to FIG. 5, a modification example in which data is sliced into four between the CPU and the ASIC will be described.

(a): Description of Other Embodiments (Modifications) As shown in FIG. 5, in this example, the CPU is connected to a ASIC (first ASIC group) divided into four parts composed of ASICs 9, 10, 11, and 12. Then, two ASICs 13 and 14 (second ASIC group) are connected to the four divided ASICs 9, 10, 11, and 12, respectively. Also, one DIMM is connected to each of the two ASICs 13 and 14. With this configuration, the data can be sliced into four.

  In this case, since 16-byte data is transferred to the ASICs 9, 10, 11, and 12 (first ASIC group), an ECC block is generated in units of 16 bytes, and the above-described FIGS. As in the example, data assignment is performed so that the chunk is not read from or written to the same element of the same DIMM.

(b): Description of Specific Data Example In the apparatus shown in FIG. 5, an example in which data is sliced into four parts between the CPU and the ASIC is shown. In this apparatus, since 16 bytes of data are transferred to the ASICs 9, 10, 11, and 12, ECC chunks are generated in units of the 16 bytes, and the ECC chunks are the same in the same DIMM as described above. Data assignment is performed so that writing to or reading from the element is not performed.

  This makes it possible to correct and detect an error even when an address failure, data failure, or one DIMM failure occurs. Therefore, the number of ASIC pins per one can be reduced, and cost reduction can be expected. In addition, a large number of DIMMs and CPUs can be installed.

It is a principle explanatory view of the present invention. It is explanatory drawing of the chip | tip structure and connection in embodiment. It is process explanatory drawing in embodiment. It is explanatory drawing of the example of data in embodiment. It is explanatory drawing when data is sliced into four between CPU-ASIC in embodiment. It is a conventional chip configuration diagram. It is a chip configuration diagram when an ASIC having an interface with a conventional DIMM is divided.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Program 12 Request transmission / reception circuit 13 Transfer data distribution circuit 14 Reception circuit 15 ECC code generation circuit 16 Transfer data distribution circuit 17 Transmission circuit 18 Reception circuit 19 ECC check circuit 20 ECC correction circuit 21 Transmission circuit 25 Reception circuit 26 Memory controller 27 Write data Rearrangement circuit 28 Read data rearrangement circuit 29 Transmission circuit

Claims (2)

An error correction / detection device in an information processing apparatus having a CPU, an ASIC, and two DIMMs, and transferring write / read data between the CPU and the DIMM via the ASIC,
The ASIC has an interface with the CPU and a first ASIC group divided into two or four ASICs having the same function, and an interface with the first ASIC group and the two DIMMs. And a second ASIC group consisting of two ASICs having the same function.
Each ASIC of the first ASIC group creates an ECC block within the first ASIC group, and the ECC block generates an ECC code for write data and converts the generated ECC code to write data. Additional function, a function of distributing write data with ECC code to each ASIC of the second ASIC group, an ECC check and ECC correction function for read data from DIMM,
Each ASIC in the second ASIC group performs a DIMM control function and rearranges write data so that the ECC block generated in the first ASIC group does not access the same element in the DIMM. And a function to restore the data rearranged at the time of writing to the read data from the DIMM,
An error correction / detection device in an information processing apparatus, wherein each function enables one-byte error correction or two-byte error detection. An error correction / detection device in an information processing apparatus having a CPU, an ASIC, and two DIMMs, and transferring write / read data between the CPU and the DIMM via the ASIC,
Each of the CPUs has an interface, and has an interface between the first ASIC group composed of two or four ASICs having the same function, and the first ASIC group and the two DIMMs. And a second ASIC group consisting of two ASICs having the same function,
Each ASIC of the first ASIC group generates an ECC code for generating write data from the CPU to the DIMM and assigning the write data to the write data, and the write data with the ECC code is sent to the second data. Transfer data distribution circuit that distributes to each ASIC of the ASIC group, ECC check circuit that performs ECC check on read data from DIMM to CPU, and error correction if the check result of the ECC check circuit is a 1-byte error If it is a 2-byte error, it has an ECC correction circuit that only detects errors,
Each ASIC of the second ASIC group is arranged to rearrange the data so that the memory controller that controls the DIMM and the ECC block generated by the first ASIC group do not access the same element in the DIMM. And a read data rearrangement circuit that restores the data rearranged at the time of writing with respect to the read data from the DIMM. .

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