JP2006003759A - Microcontroller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcontroller in which external components which are randomly arrayed and vary in terminal arrays can be easily connected without providing vacant terminals unrelated to an electric operation. <P>SOLUTION: By setting of an array changing transistor 22 by software, it is made possible to freely allocate from which of high voltage terminals 2, 3 and 4, the display data 17, 18, and 19 to be output from the high voltage terminals 2, 3 and 4 can be output. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a microcontroller having a plurality of high voltage terminals connected to signal line terminals in order to drive, for example, a fluorescent display tube as an external component having a plurality of signal line terminals.

  Conventionally, as an external component having a plurality of signal line terminals, for example, in a microcontroller having a plurality of high voltage terminals connected to the signal line terminals in order to drive a fluorescent display tube, etc., these high voltage terminals, As a technique for easily connecting the fluorescent display tubes whose connection terminals are not arranged in order corresponding to the microcontroller on the printed circuit board, there is a technique that uses an unused terminal of the microcontroller.

In such a conventional microcontroller (see, for example, Patent Document 1), an input / output terminal or a fixed potential output terminal irrelevant to the electrical operation of the microcontroller is used for relaying a wiring pattern. It was easy to connect different parts.
Japanese Patent Laid-Open No. 4-137771 (FIG. 1)

  However, in the conventional microcontroller as described above, it is necessary to provide an empty terminal unrelated to the electrical operation as the external connection terminal, and in addition, between external parts having different terminal arrangements arranged at random. The problem was that it could not be connected easily.

  The present invention solves the above-mentioned conventional problems, and can be easily connected between external parts having different terminal arrangements arranged at random without providing empty terminals unrelated to electrical operation. Provide a controller.

  In order to solve the above-described problems, a microcontroller according to claim 1 of the present invention includes a plurality of high voltage terminals for driving a fluorescent display tube, a memory for storing display data, and a memory stored in the memory. A display output control circuit for controlling the readout output of the display data, a selection circuit for selecting display data output from the display output control circuit, and a register for setting the selection contents of the selection circuit. The output destination of the display data from the display output control circuit selected by the selection circuit based on the setting of the register is arbitrarily assigned from the plurality of high voltage terminals.

  According to a second aspect of the present invention, there is provided a microcontroller according to the first aspect, wherein the high breakdown voltage terminal includes a high breakdown voltage P-channel transistor and a high breakdown voltage N-channel transistor. It is configured to control connection of a negative power source that drives a tube, and the register is configured to set whether or not a negative power source is connected to a part of the register, thereby controlling connection of the negative power source of the high withstand voltage terminal It is characterized by having comprised as follows.

  According to a third aspect of the present invention, a microcontroller includes a plurality of high voltage terminals for driving the fluorescent display tube, a memory for storing display data, and a display data for reading the display data stored in the memory. A display output control circuit for outputting a memory address, an addressing conversion circuit for calculating a memory address output from the display output control circuit, and a register for setting the addressing conversion circuit, Based on the setting of the register, the memory address output from the display output control circuit is calculated by the addressing conversion circuit, and the output destination of the display data from the memory is determined according to the specified memory address. The high withstand voltage terminal is arbitrarily changed.

  According to a fourth aspect of the present invention, there is provided a microcontroller comprising a plurality of high voltage terminals for driving the fluorescent display tube, a memory for storing display data, and a display data for reading the display data stored in the memory. A display output control circuit for outputting a memory address; a register for storing information for selectively outputting the display data in the memory to any one of the plurality of high withstand voltage terminals; and the display data stored in the register The display data input from the memory to the display output control circuit by the data conversion circuit based on the setting of the register. It is characterized in that it is configured to selectively output to the terminal.

  As described above, the arrangement of the corresponding signals for the external connection terminals can be freely set using software.

  As described above, according to the present invention, it is possible to freely assign which terminal the display data output from the high withstand voltage terminal is output by setting the register by software.

Therefore, it is possible to easily connect the microcontroller and a fluorescent display tube having a terminal arrangement different from the terminal arrangement on the printed board.
Further, when the display data is not output, the port function can be selected, so that not only connection on the printed board can be realized more easily, but also the degree of freedom in designing the set system can be increased.

Hereinafter, a microcontroller showing an embodiment of the present invention will be specifically described with reference to the drawings.
(Embodiment 1)
A microcontroller according to a first embodiment of the present invention will be described.

  FIG. 1 is a block diagram showing a schematic internal configuration of the microcontroller according to the first embodiment. In FIG. 1, 1 is a microcontroller, and 2 to 4 are display output terminals. Since the number of display output terminals does not change, the final terminal is the terminal n. Reference numeral 5 denotes a RAM which can arbitrarily set data by a program, and stores display data. The display data is arranged in order from SEG0 to SEGn. Reference numeral 6 is a ROM for storing program data, 7 is a display output control circuit for controlling the display data taken out from the RAM 5 and outputting it to the terminals 2 to 4, 8 is a data bus, 9 is an address bus, and 10 is a display output control circuit 7 Display data lines that transmit display data output from the display number. 22 is an array conversion register for setting to which terminal the data of SEG1 to SEGn arranged regularly is to be output, and 11 to 13 select which data on the display data line 10 based on the information from the array conversion register 22 14 to 16 are control signals to the conversion circuits 11 to 13 generated from the array conversion register 22, and exist as many as the number of conversion circuits 11 to 13, that is, the number of terminals 2 to 4. To do. Reference numerals 17 to 19 denote output data from the conversion circuits 11 to 13, reference numeral 21 denotes a CPU, and reference numeral 20 denotes a bus opening request signal output from the display output control circuit 7 to the CPU 21.

Next, the operation will be described with reference to FIGS.
FIG. 2 is a timing chart showing the operation of each part in FIG. Here, SEG1 to SEGn are individual signals in the display data line 10.

  In the display data transfer state, the display output control circuit 7 issues a bus opening request signal 20 to the CPU 21. When the CPU 21 detects the signal, it opens the data bus 8 and the address bus 9. The display output control circuit 7 outputs an address to the address bus 9, and the RAM 5 outputs data at the address to the data bus 8. The data is display data, and is arranged in order of SEG2 and SEG3 from SEG1. The display output control circuit 7 receives an output signal from the data bus 8 and outputs it to the display data line 10.

  The conversion circuits 11 to 13 determine which data among the data from the display data line 10 is to be output to which terminal based on each data in the array conversion register 22. For example, the conversion circuit 11 is a circuit for selecting display data to be output to the terminal 1, and data suitable for the terminal 1 is input and selected in the array conversion register 22.

In FIG. 2, terminal 1 has SEG3 selected in the display data, and terminal 2 has SEG1 selected. In this way, display data can be output to any terminal.
(Embodiment 2)
A microcontroller according to a second embodiment of the present invention will be described.

  FIG. 3 is a block diagram showing a schematic internal configuration of the microcontroller according to the second embodiment. In FIG. 3, a different part from FIG. 1 is provided with new selection circuits 25, 26, 27 for switching display data output from the selection circuits 11, 12, 13 and port data, and the selection circuits 25, 26, The output data from 27 is output to the output latch. The selection circuits 25, 26, and 27 can set the selection of the port data 28, 29, and 30 or the display data from the selection circuits 11, 12, and 13 by the register group 801 added to the array conversion register 22. Further, a negative power source (hereinafter referred to as VPP) for driving the fluorescent display tube is input to the terminals 2, 3, 4 from the VPP power line 23, and further, VPP connection control signals 31, 32, 33 from the register group 801. Is input to terminals 2, 3, and 4. Other than this, the same operation as in FIG. 1 is performed.

  FIG. 4 is a diagram illustrating the inside of the terminals (1 to n) 2, 3, and 4 in detail. Terminals (1 to n) 2, 3, and 4 are configured by high breakdown voltage Pch transistors 80 and 81, high breakdown voltage Nch transistor 82, resistor 83, and functional elements 84 and 85.

Hereinafter, the operation of this circuit will be described with reference to FIGS.
First, when it is desired to output display data from the terminals 2, 3, 4, the selection circuits 25, 26, 27 select the output from the selection circuits 11, 12, 13 according to the setting of the register group 801. Furthermore, an “L” signal is output from the VPP connection control signals 31, 32, 33 according to the setting of the register group 801.

  Here, display data 17, 18, and 19 are input to terminals 2, 3, and 4, respectively. When the display data is “H”, the output of the functional element 84 is “H”, and the high breakdown voltage Pch transistor 81 is turned off. Then, the gate signal of the high breakdown voltage Nch transistor 82 becomes the VPP potential through the resistor 83 connected to the VPP power supply line 23 and is turned OFF. Further, since the output of the functional element 85 becomes “L”, the high breakdown voltage Pch transistor 80 is turned ON. Accordingly, an “H” potential is output from the terminal PAD.

  Next, when the display data is “L”, the output of the functional element 84 becomes “L”, and the high breakdown voltage Pch transistor 81 is turned ON. Then, the gate of the high breakdown voltage Nch transistor 82 becomes “H” potential, and the high breakdown voltage Nch transistor 82 is turned ON. Since the “H” potential is output from the functional element 85, the high breakdown voltage Pch transistor 80 is turned off. Therefore, the VPP potential can be output from the terminal PAD. Display data can be output by repeating these series of operations.

Next, the case where a terminal is used as a port will be described.
When the terminal is used as a port, the register group 801 is set to the port setting, and the selection circuits 25, 26, and 27 select and output the port data 28, 29, and 30. Furthermore, the VPP connection control signal always outputs “H” by setting the register group 801. When the “H” potential is constantly input to the VPP connection control signals 31, 32, and 33 at the terminals 2, 3, and 4, the functional element 84 always outputs “H”. Therefore, the high breakdown voltage Pch transistor 81 is always turned off. As a result, the gate of the high breakdown voltage Nch transistor 82 becomes the VPP potential, and the high breakdown voltage Nch transistor 82 can be always turned off.

Therefore, the port data 28, 29, and 30 can drive only the high breakdown voltage Pch transistor 80 via the functional element 85, and the VPP potential is not output outside the terminal. It can be used as a Pch open drain port output terminal.
(Embodiment 3)
A microcontroller according to a third embodiment of the present invention will be described.

  FIG. 5 is a block diagram showing a schematic internal configuration of the microcontroller according to the third embodiment. In FIG. 5, the microcontroller 1, terminals 2 to 4, RAM 5, ROM 6, display output control circuit 7, data bus 8, address bus 9, display output data 17 to 19, bus release request signal 20, CPU 21, array conversion register 22 Operates in the same manner as in FIG.

  In FIG. 5, reference numeral 37 denotes an addressing conversion circuit that receives address data from the display output control circuit 7 and performs address conversion based on the array conversion register 22. The difference from the first embodiment is that when the display data is selectively output to any terminal by the array conversion register, it is not performed by the conversion circuit provided at each terminal, but by converting the address read from the ROM 6, It is a point to do.

  FIG. 6 is a detailed circuit of the addressing conversion circuit 37. Reference numeral 41 denotes a shift amount control circuit that receives an output from the array conversion register 22 and calculates an address shift amount. Reference numeral 40 denotes a shift operation circuit that outputs an operation result to the address bus based on data from the shift amount control circuit 41. .

Hereinafter, the operation will be described with reference to FIG.
In the display data transfer state, the display output control circuit 7 outputs a memory address output 38. The addressing conversion circuit 37 receives an array conversion register output 39 that is a conversion setting output from the array conversion register 22 along with the memory address output 38. The shift amount control circuit 41 determines how much the address should be shifted with respect to the address that should be output. The shift calculation circuit 40 receives the shift amount from the shift amount control circuit 41 and receives the memory address output 38 that is an output from the display output control circuit 7 to perform calculation. The calculation result is output to the address bus 9, and the output of the display data can be changed to an arbitrary terminal set by the array conversion register 22 by converting the address output from the display output control circuit 7 by the addressing conversion circuit 37. .
(Embodiment 4)
A microcontroller according to a fourth embodiment of the present invention will be described.

  FIG. 7 is a block diagram showing a schematic internal configuration of the microcontroller according to the fourth embodiment. In FIG. 7, the operations from 1 to 21 are the same as those in FIG. A data array conversion circuit 42 has a two-stage buffer and converts the data array based on the array conversion register 22.

  FIG. 8 is a detailed circuit of the data array conversion circuit 42 of FIG. In this example, there are four output terminals. 50 to 53 are first-stage flip-flops for storing display data from the data bus 8, and there are as many as the number of output terminals. 46 is SEG0, 47 is SEG1, 48 is SEG2, 49 is SEG3 data, and these SEG data are stored in the first stage flip-flops 50 to 53, respectively. 54 to 57 are tri-state buffers, and there are similarly the number of output terminals. 44 is a read signal generating circuit for generating a signal for sequentially enabling the tristate buffers 54 to 57 one by one, and 58 to 61 are data read signals output from the read signal generating circuit 44. , That is, the number of output terminals independently exists. 67 to 70 are second-stage flip-flops for storing display data, and there are also the same number as the number of output terminals. 45 is an acquisition signal generation circuit for generating a signal for enabling only one of the second-stage flip-flops 67 to 70 based on information from the array conversion register 22, and 63 to 66 are output from the acquisition signal generation circuit 45. The number of output terminals is the same as the number of output terminals. 62 is a common bus for transferring data of the tristate buffers 54 to 57 and the second stage buffers 67 to 70, and 71 is a synchronous clock for operating the read signal generation circuit 44 and the capture signal generation circuit 45 in synchronization.

Next, the operation will be described with reference to FIGS.
FIG. 9 is a timing chart showing the operation of each part in FIG. Here, the display data has four segments, but even if the number of segments increases without limit, the operation and action are the same.

  In the display data transfer state, the display data 46 updated with SEG0 is transferred to the first stage flip-flop 50 via the data bus 8 at the timing of T4. At this time, all the data read signals 58 to 61 generated by the read signal generating circuit 44 output signals in a disabled state, all the tristate buffers 54 to 57 are turned OFF, and the display output control circuit 7 displays display data. Has not been updated.

  Next, the data 47 of SEG1 is taken into the first stage flip-flop 51 at the timing of T5. This operation is repeated for the number of segments. When a plurality of data buses 8 are used, the number of repetitions decreases in proportion to the data bus width.

  Next, after the display data corresponding to all the SEGs are stored in the first stage flip-flops 50 to 53, in synchronization with the synchronous clock 71, the read signal generating circuit 44 outputs the data read signal 58 at the timing T9. To do. The data read signal 58 is a signal that enables the tristate buffer 54, that is, only one segment data, and after one tristate buffer is enabled for a certain period, it is disabled at the timing of T10. In the enable period, the display data of the segment selected by the read signal generation circuit 44 is transmitted to the common bus 62. In this case, the data 46 of SEG0 is transmitted.

  The capture signal generation circuit 45 operates in synchronization with the synchronous clock 71, selects a segment to be displayed at the terminal 1 from the array conversion register 22, and captures data into the selected second-stage flip-flop. Is generated. In FIG. 9, a data capture signal is generated so that the data of SEG 2 is output to terminal 2.

  In this way, one segment data is converted and transferred to the display output control circuit 7. Thereafter, the next segment data is converted in the same manner.

  The microcontroller of the present invention can easily connect a fluorescent display tube having a terminal arrangement different from the terminal arrangement on the printed circuit board using the external connection terminal, and is a semiconductor for driving the fluorescent display tube. Applicable as a device.

The block diagram which shows the structure of the microcontroller of Embodiment 1 of this invention. Timing chart showing the operation of the microcontroller of the first embodiment The block diagram which shows the structure of the microcontroller of Embodiment 2 of this invention. The block diagram which shows the internal structure of the external connection terminal in the microcontroller of Embodiment 2 The block diagram which shows the structure of the microcontroller of Embodiment 3 of this invention. The block diagram which shows the internal structure of the address specification conversion circuit in the microcontroller of Embodiment 3 The block diagram which shows the structure of the microcontroller of Embodiment 4 of this invention. The block diagram which shows the internal structure of the data array conversion circuit in the microcontroller of Embodiment 4 Timing chart showing the operation of the microcontroller of the fourth embodiment

Explanation of symbols

1 Microcontroller 2 to 4 External connection terminal 5 RAM
6 ROM
7 Display Output Control Circuit 8 Data Bus 9 Address Bus 10 Display Data Line 11, 12, 13 Conversion Circuit (Selection Circuit)
20 Bus release request signal 21 CPU
22 Array conversion register 23 VPP power supply line 25, 26, 27 Conversion circuit (selection circuit)
28, 29, 30 Port data 37 Addressing conversion circuit 40 Shift operation circuit 41 Shift amount control unit 42 Data array conversion circuit 44 Read signal generation circuit 45 Capture signal generation circuit 80, 81 High breakdown voltage Pch transistor 82 High breakdown voltage Nch transistor 801 Array conversion register

Claims (4)

  A plurality of high voltage terminals for driving the fluorescent display tube, a memory for storing display data, a display output control circuit for controlling a read output of the display data stored in the memory, and an output from the display output control circuit A selection circuit for selecting the displayed display data, and a register for setting the selection contents of the selection circuit, based on the setting of the register, from the display output control circuit selected by the selection circuit An output destination of the display data is arbitrarily assigned from the plurality of high withstand voltage terminals.   The high withstand voltage terminal has a high withstand voltage P channel transistor and a high withstand voltage N channel transistor, and is configured to control connection of a negative power source for driving the fluorescent display tube. 2. The microcontroller according to claim 1, wherein the microcontroller is configured to set the presence or absence of connection of a power source, and controls connection of a negative power source of the high withstand voltage terminal.   A plurality of high voltage terminals for driving the fluorescent display tube, a memory for storing display data, a display output control circuit for outputting a memory address for reading display data stored in the memory, and the display output control An addressing conversion circuit for calculating a memory address output from the circuit, and a register for setting the addressing conversion circuit, and the display by the addressing conversion circuit based on the setting of the register A memory address output from an output control circuit is calculated, and an output destination of display data from the memory is arbitrarily changed from the plurality of high withstand voltage terminals in accordance with designation of the calculated memory address. controller.   A plurality of high voltage terminals for driving the fluorescent display tube, a memory for storing display data, a display output control circuit for outputting a memory address for reading display data stored in the memory, and a memory in the memory A register for storing information for selectively outputting display data to an arbitrary terminal among the plurality of high withstand voltage terminals, and a data conversion circuit controlled by the display data stored in the register, and setting of the register Based on the above, the data conversion circuit selectively outputs the display data input from the memory to the display output control circuit to an arbitrary terminal among the plurality of high withstand voltage terminals.

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