JP2006003331A - Testing device and testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily pursue a cause when a header pattern indicating the start of a test is not detected. <P>SOLUTION: This testing device for determining the quality of a tested device, based on a comparison result of an output pattern sequence output sequentially from a terminal of the testing device with an expected valued pattern sequence to be compared with the output pattern sequence, is provided with a header pattern detecting part for detecting whether the output pattern sequence consistent with a header pattern sequence is output from the tested device or not, an expected value comparing part for comparing the output pattern sequence output from the tested device following to the header pattern sequence with the expected valued pattern sequence, when the header pattern sequence is detected, and a selection-writing part for storing the comparison result by the expected value comparing part in a failure memory, when the output pattern sequence consistent with the header pattern sequence is detected, and for storing the output pattern sequence output from the tested device in the failure memory, when the output pattern sequence consistent with the header pattern sequence is not detected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a test apparatus and a test method. In particular, the present invention relates to a test apparatus and a test method for starting pass / fail judgment for an output pattern output after a header pattern indicating the start of a test is output from a device under test.

The test apparatus performs a test of a device under test (DUT) to be tested based on a test program. Specifically, the test apparatus sequentially reads out and executes test program instructions from the memory. Then, the test apparatus reads a test pattern associated with each command from the memory and outputs it to each terminal of the device under test. The output pattern output as a result is compared with a predetermined expected value pattern to be output by the device under test.
Since the existence of the prior art known in the literature is not grasped at present, the description is omitted.

  Depending on the device under test, the timing at which the output of the output pattern sequence is started may not be determined. For this reason, a method of causing the device under test to output a predetermined header pattern string indicating the head of the output pattern string is conceivable. That is, according to this method, when a header pattern sequence is detected, the test apparatus compares an output pattern sequence output subsequent to the header pattern with an expected value pattern sequence. However, detection of an output pattern sequence that matches the header pattern sequence may fail due to a failure of the device under test. In this case, conventionally, it has been difficult to analyze the cause of failure in detecting the header pattern sequence.

  Accordingly, an object of the present invention is to provide a test apparatus and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above problem, in the first embodiment of the present invention, the comparison result between the output pattern sequence sequentially output from the terminal of the device under test and the expected value pattern sequence to be compared with the output pattern sequence is used. Based on a test apparatus that determines whether the device under test is good or bad, and a header pattern detection unit that detects whether an output pattern sequence that matches a predetermined header pattern sequence is output from the device under test; When an output pattern string that matches the header pattern string is detected, an expected value that compares the output pattern string output from the device under test following the output pattern string that matches the header pattern string with the expected value pattern string When the comparison unit and an output pattern sequence that matches the header pattern sequence are detected, the comparison result by the expected value comparison unit is stored in the fail memory, When the output pattern sequence matching the Ddapatan column is not detected, to provide a test apparatus and a selective writing unit for storing the output pattern sequence of the device under test to the fail memory.

In addition, it further includes an instruction execution unit that sequentially executes a plurality of instructions including a detection start instruction instructing the start of detection of the header pattern sequence for each instruction cycle, and the selective writing unit is configured to execute the detection start instruction Start the output pattern writing process that sequentially writes the output pattern output from the device under test to the fail memory. If an output pattern string that matches the header pattern string is detected, stop the output pattern writing process. Processing for sequentially storing the comparison results by the expected value comparison unit in the fail memory may be started.
In addition, the selective writing unit outputs from the device under test until a predetermined number of instruction cycles elapses after the detection start instruction is executed when an output pattern string that matches the header pattern string is not detected. The output pattern sequence may be stored in the fail memory, or the output pattern sequence output after the elapse of a predetermined number of instruction cycles may not be stored in the fail memory.

  In the second embodiment of the present invention, the quality of the device under test is determined based on the comparison result between the output pattern sequence sequentially output from the terminal of the device under test and the expected value pattern sequence to be compared with the output pattern sequence. A header pattern detection stage for detecting whether an output pattern string that matches a predetermined header pattern string is output from the device under test, and an output pattern that matches the header pattern string An expected value comparison stage for comparing the output pattern sequence output from the device under test with the expected value pattern sequence following the output pattern sequence that matches the header pattern sequence when the sequence is detected; When a matching output pattern sequence is detected, the comparison result in the expected value comparison stage is stored in the fail memory, and the header pattern sequence When the match output pattern sequence is not detected, to provide a test method and a selective writing step of storing the output pattern sequence of the device under test to the fail memory.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  According to the present invention, when the header pattern indicating the start of the test is not detected, it is possible to easily investigate the cause.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 shows the configuration of the test apparatus 10. The test apparatus 10 is a test apparatus that tests the DUT 100 including one or a plurality of terminals, and includes a main memory 102, a central pattern control unit 112, and a plurality of channel blocks 130.

  The main memory 102 stores the test program of the DUT 100 and records an output pattern output from the DUT 100 as a result of executing the test program. The main memory 102 includes an instruction memory 104, a plurality of test pattern memories 106, a plurality of expected value pattern memories 108, and a digital capture memory 110.

  The instruction memory 104 stores each instruction included in the test program. Each of the plurality of test pattern memories 106 is provided corresponding to each terminal of the DUT 100, and stores a test pattern string used during an instruction cycle period for executing the instruction in association with each instruction for each terminal.

  Here, the test pattern sequence includes a plurality of test patterns to be sequentially output to the terminals of the DUT 100 during the instruction cycle. For example, when the test apparatus 10 outputs a 32-bit signal per instruction cycle to the DUT 100, the test pattern memory 106 corresponds to each instruction and corresponds to a 32-bit signal output during one instruction cycle. A test pattern sequence consisting of 32 test patterns is stored.

  Each of the plurality of expected value pattern memories 108 is provided corresponding to each terminal of the DUT 100, and stores an expected value pattern sequence used during an instruction cycle period for executing the instruction in association with each instruction. Here, the expected value pattern sequence includes a plurality of expected value patterns to be sequentially compared with a plurality of output patterns sequentially output from the terminals of the DUT 100 during the instruction cycle. The digital capture memory 110 records an output pattern output from the DUT 100 as a result of executing the test program.

  In the above, the instruction memory 104, the plurality of test pattern memories 106, the plurality of expected value pattern memories 108, and / or the digital capture memory 110 may be provided by being divided into separate memory modules that constitute the main memory 102. These may be provided as different storage areas in the same memory module.

  The central pattern control unit 112 is connected to the main memory 102 and the plurality of channel blocks 130 and performs processing common to each terminal of the DUT 100. The central pattern control unit 112 includes a pattern list memory 114, a vector generation control unit 116, a central capture control unit 120, and a pattern result memory 122.

  The pattern list memory 114 stores the start / end address of the routine in the instruction memory 104, the start address of the test pattern in the test pattern memory 106, and the expected value pattern in the expected value pattern memory 108 for each of the main routine and each subroutine of the test program. Stores the start address, etc. The vector generation control unit 116 is an example of an instruction execution unit according to the present invention, and sequentially executes instructions included in the test program of the DUT 100 for each instruction cycle. More specifically, the vector generation control unit 116 sequentially reads out each instruction from the start address to the end address from the pattern list memory 114 and executes them sequentially for each routine.

  The central capture control unit 120 receives the pass / fail judgment results for each terminal of the DUT 100 from each channel block 130 and totals the pass / fail judgment results of the DUT 100 for each routine. The pattern result memory 122 stores the quality determination result of the DUT 100 for each routine.

  Each of the plurality of channel blocks 130 is provided corresponding to each terminal of the DUT 100. Each channel block 130 includes a channel pattern generation unit 140, a timing generation unit 160, a driver 170, and a comparator 180.

  The channel pattern generation unit 140 generates a test pattern sequence or an expected value pattern sequence used for testing the terminal, and compares the output pattern sequence and the expected value pattern sequence of the DUT 100. The channel pattern generation unit 140 includes a sequential pattern generation unit 142, a format control unit 144, a sequential pattern generation unit 146, a hunt / compare unit 148, a fail capture control unit 150, and a fail capture memory 152.

  The sequential pattern generation unit 142 receives from the vector generation control unit 116 the start address of the test pattern sequence to be output corresponding to the routine to be executed. Then, the sequential pattern generation unit 142 reads the test pattern sequence from the test pattern memory 106 in order from the start address corresponding to each instruction cycle, and sequentially outputs it to the format control unit 144. The format control unit 144 converts the test pattern sequence into a format for controlling the driver 170.

  The sequential pattern generation unit 146 receives the start address of the expected value pattern sequence from the vector generation control unit 116 corresponding to the routine to be executed. Then, the sequential pattern generation unit 146 reads the expected value pattern from the expected value pattern memory 108 in order from the start address corresponding to each instruction cycle, and sequentially outputs the expected value pattern to the hunt / compare unit 148 and the fail capture control unit 150. The hunt compare unit 148 inputs the output pattern sequence output from the DUT 100 via the comparator 180 and compares it with the expected value pattern sequence. Here, the hunt compare unit 148 starts the comparison with the expected value pattern string on the condition that a specific header pattern string is output from the DUT 100 for the output pattern string output from the DUT 100 at an indefinite timing. It may have a function. In this case, the hunt / compare unit 148 may start detection of the header pattern sequence on condition that a detection start instruction for starting detection of an output pattern sequence that matches the header pattern sequence is executed.

  The fail capture control unit 150 receives information on match / mismatch between the output pattern sequence of the DUT 100 and the expected value pattern sequence from the hunt compare unit 148, and generates a pass / fail judgment result of the DUT 100 for the terminal. The fail capture memory 152 stores fail information including the result of hunt processing by the hunt / compare unit 148, the value of the output pattern that does not match the expected value, and the like.

  The timing generation unit 160 generates a timing at which the driver 170 outputs each test pattern in the test pattern sequence, and a timing at which the comparator 180 takes in the output pattern of the DUT 100. The driver 170 outputs each test pattern output from the format control unit 144 in the channel pattern generation unit 140 to the DUT 100 at the timing specified by the timing generation unit 160. The comparator 180 acquires the output pattern output from the terminal of the DUT 100 at the timing specified by the timing generation unit 160 and supplies the output pattern to the hunt / compare unit 148 and the digital capture memory 110 in the channel block 130.

  Note that the channel pattern generation unit 140 has a function of the sequential pattern generation unit 142 and the sequential pattern generation unit 146 instead of the configuration in which the sequential pattern generation unit 142 and the sequential pattern generation unit 146 described above are separately provided. A configuration including a sequential pattern generation unit may be employed.

  FIG. 2 shows the configuration of the hunt / compare unit 148. The hunt / compare unit 148 has a header pattern detection unit 200, an alignment unit 210, an expected value comparison unit 220, and a selective writing unit 230. The header pattern detection unit 200 inputs the output pattern sequence output from the device under test 100 from the comparator 180. Then, based on the signal received from the vector generation control unit 116, the header pattern detection unit 200 determines whether or not a detection start instruction for instructing the start of detection of the output pattern sequence that matches the header pattern sequence has been executed. When the detection start instruction is executed, the header pattern detection unit 200 detects whether or not an output pattern sequence that matches a predetermined header pattern sequence is output from the device under test 100.

  When the header pattern sequence is detected, the header pattern detection unit 200 adjusts the output timing of the output pattern sequence based on the time elapsed from the start of detection of the header pattern sequence until the header pattern sequence is detected. The parameter to be set is set in the alignment unit 210. For example, the header pattern detection unit 200 may set a delay amount for delaying the output pattern sequence in the alignment unit 210. By appropriately setting the delay amount, the output pattern sequence and the expected value pattern sequence can be synchronized.

  The alignment unit 210 inputs the output pattern sequence output from the device under test 100 from the comparator 180. Then, the alignment unit 210 delays the input output pattern sequence by the delay amount set by the header pattern detection unit 200 and sends it to the expected value comparison unit 220 and the selective writing unit 230. When an output pattern sequence that matches the header pattern sequence is detected, the expected value comparison unit 220 expects an output pattern sequence that is output from the device under test 100 following the output pattern sequence that matches the header pattern sequence. Compare with value pattern sequence. Here, the output pattern sequence that follows the output pattern sequence that matches the header pattern sequence is not only the output pattern that is output continuously from the output pattern sequence that matches the header pattern sequence, but also that that matches the header pattern sequence. It includes an output pattern that is output after another pattern is output after the output pattern string is output.

  The selective writing unit 230 sends the comparison result input from the expected value comparison unit 220 to the fail capture control unit 150 when an output pattern sequence that matches the header pattern sequence is detected. Thereby, the selective writing unit 230 can store the comparison result by the expected value comparison unit 220 in the fail capture memory 152 when an output pattern sequence that matches the header pattern sequence is detected.

  On the other hand, the selective writing unit 230 sends the output pattern input from the alignment unit 210 to the fail capture control unit 150 when an output pattern that matches the header pattern sequence is not detected. Thus, the selective writing unit 230 can store the output pattern sequence of the device under test 100 in the fail capture memory 152 when an output pattern sequence that matches the header pattern sequence is not detected.

  FIG. 3 shows the timing of processing in which the hunt / compare unit 148 detects the header pattern sequence. The vector generation control unit 116 executes each of the plurality of instructions through a pipeline of a plurality of stages including an instruction execution stage and a comparison stage. More specifically, in the instruction execution stage, the vector generation control unit 116 sequentially executes a plurality of instructions including a detection start instruction instructing the start of detection of the header pattern sequence for each instruction cycle. For example, the vector generation control unit 116 sequentially executes the detection start instruction, the instruction 2 and the instruction 3 in this order, and finally executes the detection end instruction.

  Then, the sequential pattern generation unit 146 sequentially reads the expected value pattern corresponding to the instruction for each of the plurality of instructions from the expected value pattern memory 108. For example, the sequential pattern generation unit 146 sequentially reads the expected value pattern 1 corresponding to the detection start command, the expected value pattern 2 corresponding to the command 2, and the expected value pattern 3 corresponding to the command 3. Here, since the comparison stage is executed after the instruction execution stage, the timing at which the expected value pattern sequence is referred to in the comparison stage is delayed from the timing at which the corresponding instruction is executed in the instruction execution stage.

  In the comparison stage, the comparator 180 acquires the output pattern output from the terminal of the DUT 100 and supplies it to the hunt compare unit 148. For example, the hunt / compare unit 148 acquires the output pattern 1, omits a part of the middle, and sequentially acquires the header pattern string, the output pattern N, and the output pattern N + 1.

  Since the alignment unit 210 has not received a delay amount setting for delaying the output pattern sequence from when the detection start instruction is executed until the header pattern sequence is detected, the acquired output pattern sequence is delayed. The data is output to the selective writing unit 230 without being performed. In response to this, the selective writing unit 230 instructs the fail capture control unit 150 to write the output pattern sequence to the fail capture memory 152. Thus, the selective writing unit 230 starts the output pattern writing process for sequentially writing the output patterns output from the device under test 100 to the fail capture memory 152 when the detection start command is executed.

  Here, preferably, the selective writing unit 230, when an output pattern sequence that matches the header pattern sequence is not detected, until the predetermined number of instruction cycles elapses after the detection start command is executed. Only the output pattern sequence output from the device 100 is stored in the fail capture memory 152. That is, the selective writing unit 230 does not store the output pattern string output after the instruction cycle number has elapsed in the fail capture memory 152. As a result, it is possible to efficiently save only the patterns that are useful for investigating the cause where the header pattern sequence is not detected. Instead, the selective writing unit 230 is output during a period from when the detection start instruction is executed until when the detection end instruction is executed when an output pattern string that matches the header pattern string is not detected. All output pattern sequences may continue to be stored in the fail capture memory 152.

  On the other hand, when the header pattern detection unit 200 detects an output pattern sequence that matches the header pattern sequence, the header pattern detection unit 200 sets a predetermined delay amount in the alignment unit 210 in order to match the read timing of the expected value pattern and the output pattern. . As a result, the alignment unit 210 delays the output pattern sequence output from the device under test 100 following the header pattern sequence, and matches the output timing of the expected value pattern sequence.

In response to this, the expected value comparison unit 220 compares the output pattern sequence output from the device under test with the output pattern sequence that matches the header pattern sequence with the expected value pattern sequence. In this case, the selective writing unit 230 instructs the fail capture control unit 150 to store the comparison result by the expected value comparison unit 220 in the fail capture memory 152. As described above, when an output pattern sequence that matches the header pattern sequence is detected, the selective writing unit 230 stops the output pattern writing process and sends the comparison result by the expected value comparison unit 220 to the fail capture memory 152. The process of sequentially storing is started.
Note that the fail capture memory 152 may continue to hold the output pattern sequence output before the detection without erasing even when the header pattern sequence is detected, or the output output before the detection. The pattern string may be overwritten with the comparison result.

  As described above, according to FIG. 3, the test apparatus 10 writes the output pattern sequence to the fail capture memory 152 until the header pattern sequence is detected, and outputs the output pattern sequence when the header pattern sequence is detected. The comparison result between the pattern sequence and the expected value pattern sequence is written into the fail capture memory 152. Thereby, when the header pattern is not detected, the cause can be easily analyzed. Further, when a header pattern sequence is detected, the storage capacity of the fail capture memory 152 can be effectively utilized.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

FIG. 1 shows the configuration of the test apparatus 10. FIG. 2 shows the configuration of the hunt / compare unit 148. FIG. 3 shows the timing of processing in which the hunt / compare unit 148 detects the header pattern sequence.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Test apparatus 100 Device under test 102 Main memory 104 Instruction memory 106 Test pattern memory 108 Expected value pattern memory 110 Digital capture memory 112 Central pattern control unit 114 Pattern list memory 116 Vector generation control unit 120 Central capture control unit 122 Pattern result memory 130 Channel block 140 Channel pattern generation unit 142 Sequential pattern generation unit 144 Format control unit 146 Sequential pattern generation unit 148 Hunt / compare unit 150 Fail capture control unit 152 Fail capture memory 160 Timing generation unit 170 Driver 180 Comparator 200 Header pattern detection unit 210 Alignment Unit 220 expected value comparison unit 230 selective writing unit

Claims (4)

A test apparatus for determining pass / fail of the device under test based on a comparison result between an output pattern sequence sequentially output from a terminal of the device under test and an expected value pattern sequence to be compared with the output pattern sequence. ,
A header pattern detector that detects whether or not an output pattern sequence that matches a predetermined header pattern sequence is output from the device under test;
When an output pattern sequence that matches the header pattern sequence is detected, an output pattern sequence that is output from the device under test following the output pattern sequence that matches the header pattern sequence is the expected value pattern sequence. An expected value comparison unit to be compared;
When an output pattern sequence that matches the header pattern sequence is detected, the comparison result by the expected value comparison unit is stored in a fail memory, and when an output pattern sequence that matches the header pattern sequence is not detected, A test apparatus comprising: a selective writing unit that stores an output pattern sequence of the device under test in the fail memory. A plurality of instructions including a detection start instruction for instructing the start of detection of the header pattern sequence, further comprising an instruction execution unit that sequentially executes every instruction cycle;
The selective writing unit starts an output pattern writing process for sequentially writing output patterns output from the device under test to the fail memory when the detection start instruction is executed, and matches the header pattern sequence 2. The test apparatus according to claim 1, wherein when the output pattern sequence to be detected is detected, the output pattern writing process is stopped, and the process of sequentially storing the comparison result by the expected value comparison unit in the fail memory is started. The selective writing unit outputs from the device under test when a predetermined number of instruction cycles elapses after the detection start instruction is executed when an output pattern string that matches the header pattern string is not detected. The test apparatus according to claim 2, wherein the output pattern string that has been output is stored in the fail memory, and the output pattern string that is output after the predetermined number of instruction cycles has elapsed is not stored in the fail memory. A test method for determining pass / fail of the device under test based on a comparison result between an output pattern sequence sequentially output from a terminal of the device under test and an expected value pattern sequence to be compared with the output pattern sequence. ,
A header pattern detection stage for detecting whether or not an output pattern sequence matching a predetermined header pattern sequence is output from the device under test;
When an output pattern sequence that matches the header pattern sequence is detected, an output pattern sequence that is output from the device under test following the output pattern sequence that matches the header pattern sequence is the expected value pattern sequence. An expected value comparison stage to compare;
When an output pattern sequence that matches the header pattern sequence is detected, the comparison result in the expected value comparison stage is stored in a fail memory, and when an output pattern sequence that matches the header pattern sequence is not detected, And a selective writing step of storing an output pattern string of the device under test in the fail memory.

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