JP2005353938A - Semiconductor apparatus - Google Patents

Semiconductor apparatus Download PDF

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Publication number
JP2005353938A
JP2005353938A JP2004175002A JP2004175002A JP2005353938A JP 2005353938 A JP2005353938 A JP 2005353938A JP 2004175002 A JP2004175002 A JP 2004175002A JP 2004175002 A JP2004175002 A JP 2004175002A JP 2005353938 A JP2005353938 A JP 2005353938A
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semiconductor chip
recess
predetermined
wire
semiconductor device
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Japanese (ja)
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Jun Sakazume
順 坂爪
Toshihiro Miura
俊広 三浦
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Renesas Technology Corp
Hitachi Information Technology Co Ltd
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Renesas Technology Corp
Hitachi Hybrid Network Co Ltd
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Priority to JP2004175002A priority Critical patent/JP2005353938A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

<P>PROBLEM TO BE SOLVED: To enable accurate positioning of a semiconductor chip and constant wire length. <P>SOLUTION: A rectangular semiconductor chip has a wiring substrate having a rectangular recess in its upper surface, a plurality of wiring lines formed on the upper surface of the wiring substrate, predetermined parts of which are used as bonding pads for wire connection, a rectangular semiconductor chip fixed to the recess in the upper surface of the wiring substrate and having a plurality of electrodes on its upper surface, and conductive wires for electrically connecting the electrodes and the bonding pads. Adjacent two of four inner peripheral surface sides of the recess form inclined surfaces. When the semiconductor chip is accommodated within the recess, the semiconductor chip to be fixed within the recess is slid along the inclined surfaces and abuts at their sides against the sides corresponding to the inclined surfaces for its positioning. As a result, distances between the predetermined electrodes and the predetermined bonding pads connected to the predetermined electrodes by the wires are set to be within a predetermined dimensional error range. A transistor forming the final amplification stage of an amplification circuit is formed in the semiconductor chip, and a wire length thereof to be connected at its output electrode has a length within the predetermined error range. Consequently, the high frequency characteristic of the chip can be stabilized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置に係わり、特に高周波増幅回路を形成した半導体チップを封止体に封止した半導体装置に適用して有効な技術に関する。   The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a semiconductor chip on which a high-frequency amplifier circuit is formed is sealed in a sealing body.

携帯電話機に組み込まれる高周波電力増幅装置（高周波電力増幅モジュール）は、セラミック基板（配線基板）の上面に表面実装型部品や半導体チップを搭載している。表面実装型部品は、チップ抵抗，チップコンデンサ，チップインダクタ等の受動部品である。また、半導体チップにはＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor ）等のトランジスタが形成されている。高周波電力増幅装置においては、複数のトランジスタが縦列接続されて多段構成の増幅回路が形成されている。半導体チップの上面の電極とセラミック基板の上面の配線のボンディングパッドは導電性のワイヤで接続されている。また、四角形の半導体チップはセラミック基板の上面に設けた四角形の窪み内に固定されている（例えば、特許文献１）。   2. Description of the Related Art A high frequency power amplifier (high frequency power amplifier module) incorporated in a mobile phone has a surface-mounted component or a semiconductor chip mounted on the upper surface of a ceramic substrate (wiring substrate). Surface-mount components are passive components such as chip resistors, chip capacitors, and chip inductors. A transistor such as a MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor) is formed on the semiconductor chip. In a high frequency power amplifier, a plurality of transistors are connected in cascade to form an amplifier circuit having a multistage configuration. The electrode on the upper surface of the semiconductor chip and the bonding pad of the wiring on the upper surface of the ceramic substrate are connected by a conductive wire. In addition, the rectangular semiconductor chip is fixed in a rectangular recess provided on the upper surface of the ceramic substrate (for example, Patent Document 1).

特開平９−１１６０９１号公報JP-A-9-116091

半導体チップを窪み内に固定する構造の高周波電力増幅装置では、窪みの大きさは基板製造ばらつき、半導体チップ搭載ばらつき等を考慮することから、半導体チップの大きさに対しある一定のクリアランス（隙間）を有する構造になっている。   In a high-frequency power amplifier having a structure in which a semiconductor chip is fixed in a recess, the size of the recess takes into account substrate manufacturing variations, semiconductor chip mounting variations, etc., and therefore a certain clearance (gap) with respect to the size of the semiconductor chip. It has the structure which has.

しかし、このクリアランスの存在によって、窪み内に固定された半導体チップの搭載位置がばらつく。このばらつきは半導体チップの出力用の電極に接続されるワイヤの長さのばらつきを引き起し、インダクタンスのばらつきとなって高周波特性が変動する。   However, the presence of this clearance varies the mounting position of the semiconductor chip fixed in the recess. This variation causes variations in the length of the wires connected to the output electrodes of the semiconductor chip, resulting in variations in inductance and high-frequency characteristics.

本発明の一つの目的は、半導体チップを高精度に位置決めできる半導体装置を提供することにある。
本発明の一つの目的は、半導体チップの電極に接続するワイヤの長さを高精度に決定できる半導体装置を提供することにある。
本発明の一つの目的は、高周波特性を向上できる高周波電力増幅装置を提供することにある。
本発明の前記ならびにそのほかの目的と新規な特徴は、本明細書の記述および添付図面からあきらかになるであろう。 One object of the present invention is to provide a semiconductor device capable of positioning a semiconductor chip with high accuracy.
One object of the present invention is to provide a semiconductor device capable of determining the length of a wire connected to an electrode of a semiconductor chip with high accuracy.
One object of the present invention is to provide a high-frequency power amplifier that can improve high-frequency characteristics.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば、下記のとおりである。   The following is a brief description of an outline of typical inventions disclosed in the present application.

（１）上面に四角形の窪みを有する配線基板と、前記配線基板の上面に形成され所定部がワイヤ接続用のボンディングパッドとなる複数の配線と、前記配線基板の上面の前記窪み内に固定され上面に電極を複数有する四角形の半導体チップと、前記電極と前記ボンディングパッドを電気的に接続する導電性のワイヤとを有する半導体装置であって、前記窪みの内周面の４辺のうち隣り合う２辺は斜面となっていることを特徴とする。   (1) A wiring board having a quadrangular depression on the upper surface, a plurality of wirings formed on the upper surface of the wiring board and having predetermined portions as bonding pads for wire connection, and fixed in the depression on the upper surface of the wiring board. A semiconductor device having a rectangular semiconductor chip having a plurality of electrodes on an upper surface and a conductive wire that electrically connects the electrodes and the bonding pads, and is adjacent to four sides of the inner peripheral surface of the recess Two sides are sloped.

また、前記斜面に対面する辺が略垂直状に延在する壁面になっている。また、前記窪み内に固定される前記半導体チップは前記窪み内に収容される際前記斜面を滑落して前記斜面に対面する辺に当接して位置決めされ、所定の前記電極とこの所定の電極と前記ワイヤを介して接続される所定の前記ボンディングパッドとの距離が所定の寸法誤差内になるように構成されている。前記半導体チップには増幅回路の最終増幅段を構成するトランジスタが形成され、前記トランジスタの出力用の電極とこの出力用の電極に前記ワイヤを介して接続される前記ボンディングパッドとの距離が前記所定の寸法誤差内になるように構成されている。   Further, the side facing the slope is a wall surface extending in a substantially vertical shape. Further, when the semiconductor chip fixed in the recess is housed in the recess, the semiconductor chip slides down the slope and is positioned in contact with the side facing the slope, and the predetermined electrode and the predetermined electrode The distance from the predetermined bonding pad connected via the wire is set within a predetermined dimensional error. The semiconductor chip is formed with a transistor constituting a final amplification stage of an amplifier circuit, and the distance between the output electrode of the transistor and the bonding pad connected to the output electrode via the wire is the predetermined value. It is configured to be within the dimensional error.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
前記（１）の手段によれば、（ａ）四角形の窪み内に四角形の半導体チップが入れられて固定されるが、窪みの内周面の４辺のうち隣り合う２辺は斜面となり、また、前記斜面に対面する辺が略垂直状に延在する壁面になっている。従って、前記半導体チップは前記窪み内に収容される際前記斜面を滑落して前記斜面に対面する辺に当接して位置決めされる。実施例の場合、窪みの内周面の４辺のうち隣り合う２辺は斜面となっていることから、半導体チップはこの隣り合う２辺を滑落することになり、残りの隣り合う２辺のなす角部に向かって移動し、残りの２辺に当たって停止し、位置決めされることになる。この結果、半導体チップは高精度に位置決めされ、半導体チップの所定の電極とこの所定の電極とワイヤを介して接続される所定のボンディングパッドとの距離が所定の寸法誤差内になり、ワイヤ長さが一定長さ域に納まるため、ワイヤのインダクタンスが所定の寸法誤差内になり、半導体装置の特性が安定する。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the means of (1), (a) a rectangular semiconductor chip is placed and fixed in a rectangular recess, but two adjacent sides of the four inner peripheral surfaces of the recess are inclined, The side facing the slope is a wall surface extending substantially vertically. Therefore, when the semiconductor chip is accommodated in the recess, the semiconductor chip slides down the slope and is positioned in contact with the side facing the slope. In the case of the embodiment, since the two adjacent sides of the four inner peripheral surfaces of the recess are inclined, the semiconductor chip slides down the two adjacent sides, and the remaining two adjacent sides. It moves toward the corner that it makes, stops by hitting the remaining two sides, and is positioned. As a result, the semiconductor chip is positioned with high accuracy, and the distance between a predetermined electrode of the semiconductor chip and a predetermined bonding pad connected to the predetermined electrode via a wire falls within a predetermined dimensional error, and the wire length Therefore, the inductance of the wire falls within a predetermined dimensional error, and the characteristics of the semiconductor device are stabilized.

（ｂ）上記（ａ）において、前記半導体チップに増幅回路の最終増幅段を構成するトランジスタが形成されている場合、前記トランジスタの出力用の電極とこの出力用の電極に前記ワイヤを介して接続される前記ボンディングパッドとの距離が前記所定の寸法誤差内になるように構成される。従って、最終増幅段を構成するトランジスタの出力用の電極に接続されるワイヤの長さは所定誤差内の長さとなり、ワイヤのインダクタンスが所定の寸法誤差内となり、高周波特性が安定する。   (B) In the above (a), when the transistor constituting the final amplification stage of the amplifier circuit is formed on the semiconductor chip, the output electrode of the transistor is connected to the output electrode via the wire. The distance from the bonding pad is set to be within the predetermined dimensional error. Therefore, the length of the wire connected to the output electrode of the transistor constituting the final amplification stage is within a predetermined error, the inductance of the wire is within a predetermined dimensional error, and the high frequency characteristics are stabilized.

以下、図面を参照して本発明の実施の形態を詳細に説明する。なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

図１乃至図６は本発明の実施例１である半導体装置に係わる図である。本実施例１では、搬送周波数が１．９ＧＨｚとなるＧＳＭ（Global System for Mobile Communication）方式の携帯電話機の送信用高周波電力増幅装置の製造に本発明を適用した例について説明する。   1 to 6 are diagrams relating to a semiconductor device which is Embodiment 1 of the present invention. In the first embodiment, an example will be described in which the present invention is applied to the manufacture of a high frequency power amplifying device for transmission of a GSM (Global System for Mobile Communication) mobile phone having a carrier frequency of 1.9 GHz.

半導体装置１は高周波電力増幅装置１であり、図２に示すように、配線基板（モジュール基板）２と、この配線基板２の上面を覆う絶縁性樹脂で形成される封止体３とからなり、外観的には偏平な矩形体（立方体）構造になっている。配線基板２と封止体３によってパッケージ４が形成されている。   The semiconductor device 1 is a high-frequency power amplifying device 1 and includes a wiring board (module board) 2 and a sealing body 3 formed of an insulating resin that covers the upper surface of the wiring board 2 as shown in FIG. In appearance, it has a flat rectangular (cubic) structure. A package 4 is formed by the wiring substrate 2 and the sealing body 3.

また、高周波電力増幅装置（高周波電力増幅モジュール）１の下面（底面）には、図３に示すように外部電極端子５が複数設けられている。外部電極端子５は、入力端子Ｐin、出力端子Ｐout 、電源電位端子Ｖdd、制御端子Ｖapc 、基準電位（ＧＮＤ）端子等を構成する。濃い黒い部分で囲まれる５個の外部電極端子５はＧＮＤ端子である。   A plurality of external electrode terminals 5 are provided on the lower surface (bottom surface) of the high-frequency power amplifier (high-frequency power amplifier module) 1 as shown in FIG. The external electrode terminal 5 includes an input terminal Pin, an output terminal Pout, a power supply potential terminal Vdd, a control terminal Vapc, a reference potential (GND) terminal, and the like. Five external electrode terminals 5 surrounded by a dark black part are GND terminals.

このような高周波電力増幅装置１の等価回路は、図４のようになっている。この等価回路で示される増幅回路は、複数のトランジスタを順次縦列接続した３段構成になっている。各トランジスタは増幅段を構成する。トランジスタＱ１は第１増幅段（初段増幅器）となり、トランジスタＱ２は第２増幅段（次段増幅器）となり、トランジスタＱ３，Ｑ４は第３増幅段（最終増幅器：最終増幅段）となっている。最終増幅段（出力段）では出力を増大させるため並列に二つのトランジスタＱ３，Ｑ４を接続する電力合成構成になっている。トランジスタは、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor ）が使用されている。   An equivalent circuit of such a high-frequency power amplifying apparatus 1 is as shown in FIG. The amplifier circuit shown by this equivalent circuit has a three-stage configuration in which a plurality of transistors are connected in series. Each transistor constitutes an amplification stage. The transistor Q1 is a first amplification stage (first stage amplifier), the transistor Q2 is a second amplification stage (next stage amplifier), and the transistors Q3 and Q4 are third amplification stages (final amplifier: final amplification stage). The final amplification stage (output stage) has a power combining configuration in which two transistors Q3 and Q4 are connected in parallel to increase the output. A MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor) is used as the transistor.

この増幅回路においては、各トランジスタの入出力信号を制御するために各部に入力整合回路、出力整合回路、段間整合回路、バイアス回路が設けられ、さらにはノイズフイルター等の回路が設けられている。これらの回路はコンデンサ（Ｃ１〜Ｃ１３），バイパスコンデンサ（ＣＢ１，ＣＢ２），抵抗（Ｒ１〜Ｒ５），インダクタＬによって形成されている。なお、回路図で示す細い長方形部分はマイクロストリップラインを示す。   In this amplifier circuit, an input matching circuit, an output matching circuit, an interstage matching circuit, and a bias circuit are provided in each part to control input / output signals of each transistor, and further, a circuit such as a noise filter is provided. . These circuits are formed by capacitors (C1 to C13), bypass capacitors (CB1 and CB2), resistors (R1 to R5), and an inductor L. A thin rectangular portion shown in the circuit diagram indicates a microstrip line.

本実施例では２個の半導体チップが使用される。一つの半導体チップ（チップ１）には、トランジスタＱ１，Ｑ２及び抵抗Ｒ１〜Ｒ４がモノリシックに形成されている（図４参照）。チップ１においては、少なくともａ〜ｆで示す電極（パッド電極）を有し、これらパッド電極に接続されるワイヤを介して配線基板２の上面に設けられた配線のボンディングパッドに電気的に接続されるようになる。   In this embodiment, two semiconductor chips are used. In one semiconductor chip (chip 1), transistors Q1 and Q2 and resistors R1 to R4 are formed monolithically (see FIG. 4). The chip 1 has at least electrodes (pad electrodes) indicated by a to f, and is electrically connected to a bonding pad of wiring provided on the upper surface of the wiring board 2 through wires connected to the pad electrodes. Become so.

他の半導体チップ（チップ２）には、最終増幅段を構成するトランジスタＱ３，Ｑ４及び抵抗Ｒ５がモノリシックに形成されている（図４参照）。チップ２においては、少なくともｈ〜ｊで示す電極（パッド電極）を有し、これらパッド電極に接続されるワイヤを介して配線基板２の上面に設けられた配線のボンディングパッドに電気的に接続されるようになる。図４で示すｉ，ｊで示す端子（パッド電極）が最終増幅段を構成するトランジスタＱ３，Ｑ４の出力用の電極となり、この出力用の電極に接続されるワイヤの長さを所定誤差内にすることが高周波電力増幅装置１の高周波特性を良好に維持することになる。従って、チップ２の半導体チップを高精度に位置決めして固定することが重要になる。   In the other semiconductor chip (chip 2), transistors Q3 and Q4 and a resistor R5 constituting the final amplification stage are monolithically formed (see FIG. 4). The chip 2 has at least electrodes (pad electrodes) indicated by h to j, and is electrically connected to a bonding pad of wiring provided on the upper surface of the wiring substrate 2 through wires connected to the pad electrodes. Become so. The terminals (pad electrodes) indicated by i and j shown in FIG. 4 serve as output electrodes of the transistors Q3 and Q4 constituting the final amplification stage, and the length of the wire connected to the output electrode is within a predetermined error. This maintains the high frequency characteristics of the high frequency power amplifying apparatus 1 well. Therefore, it is important to position and fix the semiconductor chip of the chip 2 with high accuracy.

図５はチップ２を構成する半導体チップ１０が搭載された配線基板２の一部を示す模式図である。半導体チップ１０の上面にはワイヤを接続するための電極（パッド電極）１１が複数設けられている。図５において、特に限定はされないが、電極１１は左右に８個づつ配置されている。右上側の４個の電極１１がトランジスタＱ３の出力用の電極１１ａであり、右下側の４個の電極１１がトランジスタＱ４の出力用の電極１１ａである。四角形（長方形）の半導体チップ１０は、半導体チップ１０に相似形となる窪み１５内に固定される。窪み１５は半導体チップ１０よりも大きくなり、四角形の隣り合う２辺の内周面は斜面１６になっている。即ち、窪み１５の開口側の寸法に比較して窪み１５の底の寸法が狭くなるような傾斜面になっている。図６は図５のＸ−Ｘ線に沿う断面図であり、左側に斜面１６が示されている。図５において点々を施した領域が斜面１６である。図５に示すように、上辺と左辺の内周面が斜面１６を構成し、これら斜面１６に対面する下辺及び右辺の内周面は、図６に示すように、略垂直状に延在する壁面（垂直面）になっている。そして、この下辺及び右辺の内周面が半導体チップの固定位置を決める基準面となる。   FIG. 5 is a schematic diagram showing a part of the wiring board 2 on which the semiconductor chip 10 constituting the chip 2 is mounted. A plurality of electrodes (pad electrodes) 11 for connecting wires are provided on the upper surface of the semiconductor chip 10. In FIG. 5, although not particularly limited, eight electrodes 11 are arranged on the left and right. The four electrodes 11 on the upper right side are the output electrodes 11a of the transistor Q3, and the four electrodes 11 on the lower right side are the output electrodes 11a of the transistor Q4. A rectangular (rectangular) semiconductor chip 10 is fixed in a recess 15 that is similar to the semiconductor chip 10. The recess 15 is larger than the semiconductor chip 10, and the inner peripheral surface of two adjacent sides of the quadrangle is a slope 16. That is, the inclined surface is such that the dimension of the bottom of the depression 15 becomes narrower than the dimension of the opening of the depression 15. FIG. 6 is a cross-sectional view taken along the line XX of FIG. 5, and a slope 16 is shown on the left side. In FIG. 5, the dotted area is the slope 16. As shown in FIG. 5, the inner peripheral surfaces of the upper side and the left side constitute a slope 16, and the inner peripheral surfaces of the lower side and the right side facing the slope 16 extend substantially vertically as shown in FIG. 6. It is a wall surface (vertical surface). The inner peripheral surfaces of the lower side and the right side serve as a reference plane that determines the fixing position of the semiconductor chip.

従って、窪み１５内に半導体チップ１０を落下供給すると、図１に示すように、落下する半導体チップ１０はその一部を斜面１６上を滑動落下することになる。窪み１５の隣り合う２辺の内周面が斜面１６となることから、半導体チップ１０は平面の２方向が制御されることになり、半導体チップ１０は図５の矢印に示すように窪み１５の下辺と右辺との角部ｐに向かって進み、半導体チップ１０の２辺を位置決めの基準面となる下辺と右辺の内周面に当接して停止することになる。これにより、半導体チップ１０は高精度の位置決めが可能になる。その後、予め窪み１５の底あるいは半導体チップ１０の下面に付着させておいた接着剤（省略）によって半導体チップ１０を窪み１５の底面に固定する。   Accordingly, when the semiconductor chip 10 is dropped and supplied into the recess 15, a part of the falling semiconductor chip 10 slides and falls on the slope 16 as shown in FIG. 1. Since the inner peripheral surfaces of the two adjacent sides of the recess 15 become the slope 16, the semiconductor chip 10 is controlled in two plane directions, and the semiconductor chip 10 has the recess 15 as shown by the arrow in FIG. Proceeding toward the corner part p between the lower side and the right side, the two sides of the semiconductor chip 10 are brought into contact with the inner peripheral surface of the lower side and the right side as positioning reference surfaces and stopped. Thereby, the semiconductor chip 10 can be positioned with high accuracy. Thereafter, the semiconductor chip 10 is fixed to the bottom surface of the recess 15 with an adhesive (omitted) previously attached to the bottom of the recess 15 or the lower surface of the semiconductor chip 10.

その後、図５に示すように、配線基板２の上面に設けた配線２０のボンディングパッド２１と、半導体チップ１０の電極１１を導電性のワイヤ２２で接続する。このワイヤボンディングにおいて、出力用の電極１１ａとボンディングパッド２１とを接続するワイヤ２２の長さは所定誤差内の寸法になる。例えば、出力用の電極１１ａとボンディングパッド２１とを接続するワイヤ２２の長さをＬとすれば、接続されたワイヤの長さはＬ±20μｍとなる。   Thereafter, as shown in FIG. 5, the bonding pad 21 of the wiring 20 provided on the upper surface of the wiring substrate 2 and the electrode 11 of the semiconductor chip 10 are connected by a conductive wire 22. In this wire bonding, the length of the wire 22 connecting the output electrode 11a and the bonding pad 21 is a dimension within a predetermined error. For example, if the length of the wire 22 connecting the output electrode 11a and the bonding pad 21 is L, the length of the connected wire is L ± 20 μm.

なお、図６に示すように、半導体チップ１０のばらつきを見込んで窪み１５の底の寸法は半導体チップ１０の寸法に比較してα程大きく形成されている。βが従来の余裕寸法であり、本実施例のαに比較して充分大きい。一例を上げるならば、αは20μｍ、βは100μｍ程度である。
これにより、出力用の電極１１ａに接続されるワイヤ２２のインダクタンスは所定誤差内になり、高周波電力増幅装置１の高周波特性が安定する。 As shown in FIG. 6, the bottom dimension of the recess 15 is formed so as to be larger than the dimension of the semiconductor chip 10 in consideration of the variation of the semiconductor chip 10. β is a conventional margin, which is sufficiently larger than α in the present embodiment. For example, α is about 20 μm and β is about 100 μm.
As a result, the inductance of the wire 22 connected to the output electrode 11a falls within a predetermined error, and the high-frequency characteristics of the high-frequency power amplifier 1 are stabilized.

本実施例１によれば以下の効果を有する。
（１）四角形の窪み１５内に四角形の半導体チップ１０が入れられて固定されるが、窪み１５の内周面の４辺のうち隣り合う２辺は斜面１６となり、また、斜面１６に対面する辺が略垂直状に延在する壁面になっている。従って、半導体チップ１０は窪み１５内に収容される際斜面１６を滑落して斜面１６に対面する辺に当接して位置決めされる。実施例１の場合、窪み１５の内周面の４辺のうち隣り合う２辺は斜面１６となっていることから、半導体チップ１０はこの隣り合う２辺の斜面１６を滑落することになり、残りの隣り合う２辺のなす角部に向かって移動し、残りの２辺に当たって停止し、位置決めされることになる。この結果、半導体チップ１０は高精度に位置決めされ、半導体チップ１０の所定の電極１１とこの所定の電極１１とワイヤ２２を介して接続される所定のボンディングパッド２１との距離が所定の寸法誤差内になり、ワイヤ長さが一定長さ域に納まるため、ワイヤのインダクタンスが所定の寸法誤差内になり、半導体装置１０の特性が向上しかつ安定する。 The first embodiment has the following effects.
(1) Although the rectangular semiconductor chip 10 is placed and fixed in the rectangular recess 15, two adjacent sides of the four inner peripheral surfaces of the recess 15 become the inclined surfaces 16 and face the inclined surfaces 16. The side is a wall surface extending substantially vertically. Therefore, when the semiconductor chip 10 is accommodated in the recess 15, the semiconductor chip 10 slides down the slope 16 and is positioned in contact with the side facing the slope 16. In the case of Example 1, since two adjacent sides of the four sides of the inner peripheral surface of the recess 15 are slopes 16, the semiconductor chip 10 slides down the slopes 16 of the two adjacent sides. It moves toward the corner formed by the remaining two adjacent sides, hits the remaining two sides, stops, and is positioned. As a result, the semiconductor chip 10 is positioned with high accuracy, and the distance between the predetermined electrode 11 of the semiconductor chip 10 and the predetermined bonding pad 21 connected to the predetermined electrode 11 via the wire 22 is within a predetermined dimensional error. Thus, since the wire length falls within a certain length range, the inductance of the wire falls within a predetermined dimensional error, and the characteristics of the semiconductor device 10 are improved and stabilized.

（２）上記（１）において、半導体チップ１０に増幅回路の最終増幅段を構成するトランジスタが形成されていることから、前記トランジスタの出力用の電極１１ａとこの出力用の電極１１ａにワイヤ２２を介して接続されるボンディングパッド２１との距離が所定の寸法誤差内になるように構成される。従って、最終増幅段を構成するトランジスタの出力用の電極１１ａに接続されるワイヤ２２の長さは所定誤差内の長さとなり、ワイヤのインダクタンスが所定の寸法誤差内となり、高周波特性が向上しかつ安定する。   (2) In the above (1), since the transistor constituting the final amplification stage of the amplifier circuit is formed in the semiconductor chip 10, the wire 22 is connected to the output electrode 11a of the transistor and the output electrode 11a. The distance between the bonding pad 21 and the bonding pad 21 is set within a predetermined dimensional error. Therefore, the length of the wire 22 connected to the output electrode 11a of the transistor constituting the final amplification stage is within a predetermined error, the inductance of the wire is within a predetermined dimensional error, and the high frequency characteristics are improved. Stabilize.

図７は本発明の実施例２である高周波電力増幅装置の最終増幅段を構成するトランジスタを有する半導体チップを含むモジュール基板の一部の平面図である。本実施例２は実施例１の高周波電力増幅装置１において、最終増幅段を構成するトランジスタＱ３，Ｑ４を形成した半導体チップ１０を窪み１５内に固定する場合、実施例１の場合は隣り合う２辺の内周面を斜面１６としてあるが、１辺の内周面のみを斜面１６としたものである。そして、出力用の電極１１ａが位置する側の半導体チップ１０の１辺が、前記斜面１６に対面する垂直壁に当接して位置決めするようにしたものである。図７では、窪み１５の底において、半導体チップ１０の左右に隙間（クリアランス）が存在する図面としてあるが、この合計のクリアランス長さは、実施例１の場合と同様にαである。   FIG. 7 is a plan view of a part of a module substrate including a semiconductor chip having a transistor constituting the final amplification stage of the high-frequency power amplification device according to the second embodiment of the present invention. In the second embodiment, in the high-frequency power amplifying apparatus 1 of the first embodiment, when the semiconductor chip 10 on which the transistors Q3 and Q4 constituting the final amplification stage are formed is fixed in the depression 15, the two adjacent in the case of the first embodiment. Although the inner peripheral surface of the side is the slope 16, only the inner peripheral surface of one side is the slope 16. Then, one side of the semiconductor chip 10 on the side where the output electrode 11a is located is positioned in contact with a vertical wall facing the slope 16. In FIG. 7, a gap (clearance) is present on the left and right sides of the semiconductor chip 10 at the bottom of the recess 15. The total clearance length is α as in the first embodiment.

本実施例２の高周波電力増幅装置１においても、出力用の電極１１ａに接続されるワイヤ２２の長さも所定誤差内の寸法（最も長いワイヤの長さはＬ＋αとなる）となり、ワイヤのインダクタンスを所定誤差内とすることができ、高周波特性が向上し、かつ安定する。   Also in the high frequency power amplifying apparatus 1 of the second embodiment, the length of the wire 22 connected to the output electrode 11a is also within a predetermined error (the length of the longest wire is L + α), and the inductance of the wire is reduced. It can be within a predetermined error, and high frequency characteristics are improved and stabilized.

図８及び図９は本発明の実施例３である高周波電力増幅装置に係わる図である。図８は高周波電力増幅装置の最終増幅段を構成するトランジスタを有する半導体チップを含むモジュール基板の一部の平面図、図９は図８のＸ−Ｘ線に沿う断面図である。   8 and 9 are diagrams related to a high-frequency power amplifying apparatus that is Embodiment 3 of the present invention. FIG. 8 is a plan view of a part of a module substrate including a semiconductor chip having a transistor constituting the final amplification stage of the high-frequency power amplifier, and FIG. 9 is a cross-sectional view taken along line XX of FIG.

本実施例３は実施例１の高周波電力増幅装置１において、最終増幅段を構成するトランジスタＱ３，Ｑ４を形成した半導体チップ１０を窪み１５内に固定する場合、実施例１の場合は隣り合う２辺の内周面を斜面１６としてあるが、対面する２辺の内周面を斜面１６としたものである。斜面１６を設ける辺はワイヤを引き出す側であり、半導体チップ１０の出力用の電極１１ａに接続されるワイヤ２２はこの一方の斜面１６を交差するように延在する。   In the third embodiment, in the high-frequency power amplifying apparatus 1 of the first embodiment, when the semiconductor chip 10 on which the transistors Q3 and Q4 constituting the final amplification stage are formed is fixed in the recess 15, the two adjacent in the case of the first embodiment. The inner peripheral surface of the side is the slope 16, but the inner peripheral surface of the two sides facing each other is the slope 16. The side on which the inclined surface 16 is provided is the side from which the wire is drawn, and the wire 22 connected to the output electrode 11a of the semiconductor chip 10 extends so as to intersect this one inclined surface 16.

半導体チップ１０は対面する一対の斜面１６に案内される結果、図８及び図９に示すように、窪み１５の中心に半導体チップ１０の中心が位置するような位置決めが行われる。図８及び図９では、窪み１５の底において、半導体チップ１０の左右に隙間（クリアランス）が存在する図面としてあるが、この合計のクリアランス長さは、実施例１の場合と同様にαである。図９では、窪み１５の中心に半導体チップ１０の中心が位置した状態としてあることから、半導体チップ１０の両側のクリアランスはそれぞれα／２となる。   As a result of being guided by the pair of inclined surfaces 16 facing each other, the semiconductor chip 10 is positioned such that the center of the semiconductor chip 10 is positioned at the center of the recess 15 as shown in FIGS. In FIGS. 8 and 9, there are gaps (clearances) on the left and right of the semiconductor chip 10 at the bottom of the recess 15. The total clearance length is α as in the first embodiment. . In FIG. 9, since the center of the semiconductor chip 10 is located at the center of the recess 15, the clearances on both sides of the semiconductor chip 10 are each α / 2.

本実施例３の高周波電力増幅装置１においても、出力用の電極１１ａに接続されるワイヤ２２の長さも所定誤差内の寸法（最も長いワイヤの長さはＬ＋αとなる）となり、ワイヤのインダクタンスを所定誤差内とすることができ、高周波特性が向上し、かつ安定する。   Also in the high frequency power amplifying apparatus 1 of the third embodiment, the length of the wire 22 connected to the output electrode 11a is also within a predetermined error (the length of the longest wire is L + α), and the inductance of the wire is reduced. It can be within a predetermined error, and high frequency characteristics are improved and stabilized.

図１０は本発明の実施例４である高周波電力増幅装置に係わる図である。図１０は高周波電力増幅装置の最終増幅段を構成するトランジスタを有する半導体チップを含むモジュール基板の一部の平面図である。   FIG. 10 is a diagram related to a high-frequency power amplifying apparatus that is Embodiment 4 of the present invention. FIG. 10 is a plan view of a part of a module substrate including a semiconductor chip having a transistor constituting the final amplification stage of the high-frequency power amplifier.

本実施例４は実施例１の高周波電力増幅装置１において、最終増幅段を構成するトランジスタＱ３，Ｑ４を形成した半導体チップ１０を窪み１５内に固定する場合、実施例１の場合は隣り合う２辺の内周面を斜面１６としてあるが、窪み１５の全ての辺、即ち４辺の内周面を斜面１６としたものである。半導体チップ１０の出力用の電極１１ａに接続されるワイヤ２２は斜面１６を交差するように延在する。   In the fourth embodiment, in the high-frequency power amplifying apparatus 1 of the first embodiment, when the semiconductor chip 10 on which the transistors Q3 and Q4 constituting the final amplification stage are formed is fixed in the depression 15, the two adjacent in the case of the first embodiment. Although the inner peripheral surface of the side is the inclined surface 16, all the sides of the recess 15, that is, the inner peripheral surface of four sides are the inclined surfaces 16. The wire 22 connected to the output electrode 11 a of the semiconductor chip 10 extends so as to cross the inclined surface 16.

図１０に示すように、四角形の窪み１５の４辺が斜面１６となり、これら斜面１６が半導体チップ１０を窪み１５の中心に案内する傾斜面になっていることから、窪み１５内に入れられた半導体チップ１０は窪み１５の中心に半導体チップ１０の中心が向かうような動きをして窪み１５上に位置決めされる。   As shown in FIG. 10, four sides of the quadrangular depression 15 are inclined surfaces 16, and these inclined surfaces 16 are inclined surfaces that guide the semiconductor chip 10 to the center of the depression 15, so that they are placed in the depression 15. The semiconductor chip 10 is positioned on the depression 15 by moving so that the center of the semiconductor chip 10 is directed to the center of the depression 15.

図１０では、窪み１５の底において、半導体チップ１０の各辺の外側に隙間（クリアランス）が存在する図面としてあるが、出力用の電極１１ａに接続されるワイヤ２２の延在方向の合計のクリアランス長さは、実施例１の場合と同様にαである。   In FIG. 10, a clearance (clearance) is present outside each side of the semiconductor chip 10 at the bottom of the recess 15, but the total clearance in the extending direction of the wire 22 connected to the output electrode 11a. The length is α as in the case of the first embodiment.

本実施例４の高周波電力増幅装置１においても、出力用の電極１１ａに接続されるワイヤ２２の長さも所定誤差内の寸法（最も長いワイヤの長さはＬ＋αとなる）となり、ワイヤのインダクタンスを所定誤差内とすることができ、高周波特性が向上し、かつ安定する。   Also in the high frequency power amplifying apparatus 1 of the fourth embodiment, the length of the wire 22 connected to the output electrode 11a is also within a predetermined error (the length of the longest wire is L + α), and the inductance of the wire is reduced. It can be within a predetermined error, and high frequency characteristics are improved and stabilized.

以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   The invention made by the present inventor has been specifically described on the basis of the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

本発明の実施例１である半導体装置の製造におけるチップボンディング状態を示す模式的断面図である。It is typical sectional drawing which shows the chip bonding state in manufacture of the semiconductor device which is Example 1 of this invention. 本実施例１の半導体装置（高周波電力増幅装置）の外観を示す斜視図である。1 is a perspective view illustrating an appearance of a semiconductor device (high frequency power amplifier) according to a first embodiment. 前記高周波電力増幅装置の底面図である。It is a bottom view of the high frequency power amplifier. 前記高周波電力増幅装置の等価回路図である。It is an equivalent circuit diagram of the high-frequency power amplifier. 前記高周波電力増幅装置において、最終増幅段を構成するトランジスタを有する半導体チップを含むモジュール基板の一部の平面図である。FIG. 3 is a plan view of a part of a module substrate including a semiconductor chip having a transistor constituting a final amplification stage in the high-frequency power amplifier device. 図５のＸ−Ｘ線に沿う一部の断面図である。FIG. 6 is a partial cross-sectional view taken along line XX in FIG. 5. 本発明の実施例２である高周波電力増幅装置の最終増幅段を構成するトランジスタを有する半導体チップを含むモジュール基板の一部の平面図である。It is a top view of a part of module board containing the semiconductor chip which has the transistor which comprises the final amplification stage of the high frequency power amplifier which is Example 2 of this invention. 本発明の実施例３である高周波電力増幅装置の最終増幅段を構成するトランジスタを有する半導体チップを含むモジュール基板の一部の平面図である。It is a top view of a part of module board containing the semiconductor chip which has the transistor which comprises the final amplification stage of the high frequency power amplifier which is Example 3 of this invention. 図８のＸ−Ｘ線に沿う一部の断面図である。FIG. 9 is a partial cross-sectional view taken along line XX in FIG. 8. 本発明の実施例４である高周波電力増幅装置の最終増幅段を構成するトランジスタを有する半導体チップを含むモジュール基板の一部の平面図である。It is a top view of a part of module board containing the semiconductor chip which has the transistor which comprises the final amplification stage of the high frequency power amplifier which is Example 4 of this invention.

符号の説明Explanation of symbols

１…半導体装置（高周波電力増幅装置）、２…配線基板、３…封止体、４…パッケージ、５…外部電極端子、１０…半導体チップ、１１…電極、１１ａ…出力用の電極、１５…窪み、１６…斜面、２０…配線、２１…ボンディングパッド、２２…ワイヤ。


DESCRIPTION OF SYMBOLS 1 ... Semiconductor device (high frequency power amplifier), 2 ... Wiring board, 3 ... Sealing body, 4 ... Package, 5 ... External electrode terminal, 10 ... Semiconductor chip, 11 ... Electrode, 11a ... Electrode for output, 15 ... Indentation, 16 ... slope, 20 ... wiring, 21 ... bonding pad, 22 ... wire.


Claims (5)

上面に四角形の窪みを有する配線基板と、
前記配線基板の上面に形成され所定部がワイヤ接続用のボンディングパッドとなる複数の配線と、
前記配線基板の上面の前記窪み内に固定され上面に電極を複数有する四角形の半導体チップと、
前記電極と前記ボンディングパッドを電気的に接続する導電性のワイヤとを有する半導体装置であって、
前記窪みの内周面の４辺のうち少なくとも１辺は斜面となっていることを特徴とする半導体装置。 A wiring board having a rectangular depression on the upper surface;
A plurality of wirings that are formed on the upper surface of the wiring board and whose predetermined portions serve as bonding pads for wire connection;
A rectangular semiconductor chip fixed in the depression on the upper surface of the wiring board and having a plurality of electrodes on the upper surface;
A semiconductor device having a conductive wire that electrically connects the electrode and the bonding pad,
2. A semiconductor device according to claim 1, wherein at least one of the four sides of the inner peripheral surface of the recess is a slope. 前記窪みの内周面の４辺のうち隣り合う２辺は斜面となっていることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein two adjacent sides among the four sides of the inner peripheral surface of the recess are slopes. 前記窪みの内周面の４辺のうちの１辺または隣り合う２辺が前記斜面となり、この斜面に対面する辺が略垂直状に延在する壁面になっていることを特徴とする請求項１に記載の半導体装置。 The one side or two adjacent sides of the four sides of the inner peripheral surface of the recess are the inclined surfaces, and the side facing the inclined surface is a wall surface extending substantially vertically. 2. The semiconductor device according to 1. 前記窪み内に固定される前記半導体チップは前記窪み内に収容される際前記斜面を滑落して前記斜面に対面する辺に当接して位置決めされ、所定の前記電極とこの所定の電極と前記ワイヤを介して接続される所定の前記ボンディングパッドとの距離が所定の寸法誤差内になるように構成されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor chip fixed in the recess is positioned by sliding down the inclined surface and contacting the side facing the inclined surface when housed in the recess, and the predetermined electrode, the predetermined electrode, and the wire The semiconductor device according to claim 1, wherein a distance from the predetermined bonding pad connected via a pin is within a predetermined dimensional error. 前記半導体チップには増幅回路の最終増幅段を構成するトランジスタが形成され、前記トランジスタの出力用の電極とこの出力用の電極に前記ワイヤを介して接続される前記ボンディングパッドとの距離が前記所定の寸法誤差内になるように構成されていることを特徴とする請求項４に記載の半導体装置。
The semiconductor chip is formed with a transistor constituting a final amplification stage of an amplifier circuit, and a distance between the output electrode of the transistor and the bonding pad connected to the output electrode via the wire is the predetermined value. The semiconductor device according to claim 4, wherein the semiconductor device is configured so as to be within a dimensional error.
JP2004175002A 2004-06-14 2004-06-14 Semiconductor apparatus Pending JP2005353938A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134956A (en) * 2009-12-25 2011-07-07 Shinko Electric Ind Co Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134956A (en) * 2009-12-25 2011-07-07 Shinko Electric Ind Co Ltd Semiconductor device
US8729680B2 (en) 2009-12-25 2014-05-20 Shinko Electric Industries Co., Ltd. Semiconductor device

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