JP2005353661A - Semiconductor photodetector - Google Patents

Semiconductor photodetector Download PDF

Info

Publication number
JP2005353661A
JP2005353661A JP2004169871A JP2004169871A JP2005353661A JP 2005353661 A JP2005353661 A JP 2005353661A JP 2004169871 A JP2004169871 A JP 2004169871A JP 2004169871 A JP2004169871 A JP 2004169871A JP 2005353661 A JP2005353661 A JP 2005353661A
Authority
JP
Japan
Prior art keywords
light receiving
semiconductor
photoelectric conversion
receiving surface
receiving element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004169871A
Other languages
Japanese (ja)
Other versions
JP4027917B2 (en
Inventor
Eiji Kawamo
英司 川面
Atsushi Hiraoka
淳 平岡
Satoshi Matsumoto
松本  聡
Kenji Kono
健治 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP2004169871A priority Critical patent/JP4027917B2/en
Publication of JP2005353661A publication Critical patent/JP2005353661A/en
Application granted granted Critical
Publication of JP4027917B2 publication Critical patent/JP4027917B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Light Receiving Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor photodetector capable of efficiently entering a light signal to the same extent as in the case of entering it aslant or in parallel, from the semiconductor layer side, even when it is used by making a light signal incident aslant from the substrate side, while the damage generated by a cleavage is less likely to reach the photoelectric converter. <P>SOLUTION: On a semiconductor substrate 1, a photoelectric converter 5 consisting of an n-InP layer 2, an i-InGaAs (light absorption layer) 3, and a p-InP layer 4 is formed. In an end-face incident semiconductor photodetector 100, wherein a light signal 11 enters from the end face side of a photoelectric converter 5, the end face of photoelectric converter 5 is formed almost at right angles to the surface of the semiconductor substrate 1 by etching, and has a light-receiving surface 12 for receiving the light signal 11. The semiconductor substrate 1 or a semiconductor layer comprises a tilted terrace 13 located at the outside of the light-receiving surface 12 of the photoelectric converter 5, and a level terrace 14 located between the tilted terrace 13 and the surface 12 of the photoelectric converter 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体受光素子に関し、特に、光通信ネットワーク等で光信号を電気信号に変換するための半導体受光素子に関する。   The present invention relates to a semiconductor light receiving element, and more particularly to a semiconductor light receiving element for converting an optical signal into an electric signal in an optical communication network or the like.

近年、光通信用の半導体受光素子として、導波路型の半導体受光素子(以下、導波路型半導体受光素子という。)の研究開発および実用化が促進されてきた。これは、導波路型半導体受光素子が、端面から光信号を入射させる方式の半導体受光素子であり、半導体層に垂直な方向から光信号を入射させる面入射型の半導体受光素子よりも高速な信号応答性と高い光電変換効率を両立させやすいことによるものである。   In recent years, research and development and practical application of waveguide-type semiconductor light-receiving elements (hereinafter referred to as waveguide-type semiconductor light-receiving elements) have been promoted as semiconductor light-receiving elements for optical communication. This is a semiconductor light-receiving element in which a waveguide-type semiconductor light-receiving element makes an optical signal incident from the end face, and the signal is faster than a surface-incident semiconductor light-receiving element that makes the optical signal incident from a direction perpendicular to the semiconductor layer. This is because it is easy to achieve both responsiveness and high photoelectric conversion efficiency.

近年、図8に示す断面構造を有する導波路型半導体受光素子800が開示された(例えば、特許文献1参照。)。導波路型半導体受光素子800は、半絶縁性InP基板81上に、n+−InPバッファ層82、n+−InGaAsP中間屈折率層83、光吸収層84、p+−InGaAsPバンド不連続緩和層85、p+−InPクラッド層86、および、p+−InGaAsコンタクト層87が順に積層された層構造を有する。 In recent years, a waveguide type semiconductor light receiving element 800 having a cross-sectional structure shown in FIG. A waveguide type semiconductor light receiving element 800 includes an n + -InP buffer layer 82, an n + -InGaAsP intermediate refractive index layer 83, a light absorption layer 84, and a p + -InGaAsP band discontinuous relaxation layer on a semi-insulating InP substrate 81. 85, p + -InP cladding layer 86, and p + -InGaAs contact layer 87 are sequentially stacked.

また、導波路型半導体受光素子800は、ウェットエッチングにより順メサ構造のV溝が形成され、このV溝の一方の面が受光面とされ、V溝の底を利用してへきかいが行われて素子分離される構造となっている。受光面から入射された光信号は、光吸収層84を伝播しながら吸収され、電気信号に変換されて電極88、89を介して出力される。
特開平11−68127号公報
Further, in the waveguide type semiconductor light receiving element 800, a V groove having a forward mesa structure is formed by wet etching, and one surface of the V groove is used as a light receiving surface, and scratching is performed using the bottom of the V groove. It has a structure in which elements are separated. The optical signal incident from the light receiving surface is absorbed while propagating through the light absorption layer 84, converted into an electrical signal, and output through the electrodes 88 and 89.
Japanese Patent Laid-Open No. 11-68127

しかし、このような従来のV溝を形成する半導体受光素子では、ウェットエッチングによって形成されたV溝を利用して受光面とへきかい面が形成され、受光面とへきかい面とを隔てて形成することができないため、素子分離のへきかいにより発生するダメージが半導体受光素子の光信号を電気信号に変換する部分(以下、光電変換部という。)に及ぶことがあるという問題があった。また、光信号を半導体基板側から斜めに入射させる場合は、光信号が受光面に鋭角に入射することになるため、半導体層側から斜めに入射させる場合や半導体層と平行に入射させる場合に比して光信号が反射されやすく、かつ、受光面における入射光のスポットサイズが大きくなり、単位面積あたりの光パワーが低くなり、効率的に入射されないという問題があった。   However, in such a conventional semiconductor light-receiving element that forms a V-groove, the light-receiving surface and the cleavage plane are formed using the V-groove formed by wet etching, and the light-receiving surface and the cleavage plane are separated from each other. Therefore, there is a problem in that damage caused by the separation of the element may reach the part (hereinafter referred to as a photoelectric conversion unit) that converts the optical signal of the semiconductor light receiving element into an electric signal. In addition, when an optical signal is incident obliquely from the semiconductor substrate side, the optical signal is incident on the light receiving surface at an acute angle. Therefore, when the optical signal is incident obliquely from the semiconductor layer side or incident parallel to the semiconductor layer. Compared with this, there is a problem that the optical signal is more easily reflected, the spot size of incident light on the light receiving surface is increased, the optical power per unit area is reduced, and the light is not efficiently incident.

また、V溝を形成しない従来の半導体受光素子では、素子分離のへきかいの位置精度が低く光電変換部端面付近でへきかいされることがあり、へきかいにより発生するダメージが半導体受光素子の光電変換部に及ぶことが多いという問題があった。そして、へきかいの位置を光電変換部から十分離しダメージを回避する構成の場合は、光信号が半導体基板に遮られるため、光信号を半導体基板側から斜めに入射させる用途には用いることができないという問題があった。   Further, in the conventional semiconductor light receiving element in which no V-groove is formed, the position accuracy of the device separation gap is low, and the crack may be scratched in the vicinity of the end face of the photoelectric conversion unit. There was a problem that it often occurred. And, in the case of a configuration in which the position of the scratch is sufficiently separated from the photoelectric conversion unit to avoid damage, the optical signal is blocked by the semiconductor substrate, so that it cannot be used for an application in which the optical signal is incident obliquely from the semiconductor substrate side. There was a problem.

本発明はこのような問題を解決するためになされたもので、従来の導波路型半導体受光素子よりも、へきかいにより発生するダメージが光電変換部に及びにくいと共に、光信号を基板側から斜めに入射させて使用する場合でも半導体層側から斜めに入射させて使用する場合や半導体層に平行に入射させて使用する場合と同程度に効率的に光信号を入射させることが可能な半導体受光素子を提供するものである。   The present invention has been made to solve such a problem, and the damage caused by scratching is less likely to reach the photoelectric conversion portion than in the conventional waveguide type semiconductor light receiving element, and the optical signal is obliquely inclined from the substrate side. A semiconductor light-receiving element capable of causing an optical signal to be incident as efficiently as it is when used by being incident obliquely from the semiconductor layer side or when used by being incident parallel to the semiconductor layer. Is to provide.

以上の点を考慮して、請求項1に係る発明は、半導体基板上に光吸収層を含む複数の半導体層からなる光電変換部が形成され、光信号が前記光電変換部の端面側から入射する端面入射型の半導体受光素子において、前記光電変換部の端面は、エッチングによって前記半導体基板の表面にほぼ垂直に形成され、前記光信号を受光する受光面を有し、前記光電変換部の端面よりも外側に位置する前記半導体基板または前記半導体基板上の前記半導体層は、前記光電変換部の受光面よりも外側に位置する傾斜テラス部と、前記光電変換部の受光面と前記傾斜テラス部との間に位置する水平テラス部とを備えた構成を有している。   In view of the above points, the invention according to claim 1 is configured such that a photoelectric conversion unit including a plurality of semiconductor layers including a light absorption layer is formed on a semiconductor substrate, and an optical signal is incident from an end face side of the photoelectric conversion unit. In the edge-incident semiconductor light-receiving element, the end surface of the photoelectric conversion unit is formed substantially perpendicular to the surface of the semiconductor substrate by etching, has a light-receiving surface that receives the optical signal, and the end surface of the photoelectric conversion unit The semiconductor substrate located on the outer side or the semiconductor layer on the semiconductor substrate includes an inclined terrace portion located on the outer side of the light receiving surface of the photoelectric conversion unit, the light receiving surface of the photoelectric conversion unit, and the inclined terrace portion And a horizontal terrace portion located between the two.

この構成により、光電変換部の端面がエッチングにより半導体基板の表面にほぼ垂直に形成され、へきかい位置が受光面から水平テラス部と傾斜テラス部とを隔てた位置に設けられるため、従来の導波路型半導体受光素子よりも、へきかいにより発生するダメージが光電変換部に及びにくいと共に、光信号を基板側から斜めに入射させて使用する場合でも半導体層側から斜めに入射させて使用する場合や半導体層に平行に入射させて使用する場合と同程度に効率的に光信号を入射させることが可能な半導体受光素子を実現することができる。   With this configuration, the end face of the photoelectric conversion part is formed almost perpendicularly to the surface of the semiconductor substrate by etching, and the scratching position is provided at a position separating the horizontal terrace part and the inclined terrace part from the light receiving surface. Damage caused by scratching is less likely to reach the photoelectric conversion part than a type semiconductor light receiving element, and even when an optical signal is incident obliquely from the substrate side and used obliquely from the semiconductor layer side or a semiconductor It is possible to realize a semiconductor light-receiving element capable of making an optical signal incident as efficiently as in the case where the light is incident parallel to the layer.

また、請求項2に係る発明は、請求項1において、前記傾斜テラス部の前記光電変換部側の辺から前記光電変換部の受光面までの距離である前記水平テラス部の幅をCとし、前記水平テラス部の表面から前記光吸収層の基板側の界面までの距離をDとし、前記受光面に垂直な軸よりも前記半導体基板よりの角度から入射する前記光信号の進行方向と前記受光面に垂直な軸とがなす角を入射角αとし、前記傾斜テラス部の面と前記受光面に垂直な軸とがなす角を傾斜角βとしたとき、前記入射角αが前記傾斜角β以下であり、前記水平テラスの幅Cが、C≦D/tanαの関係を満たすようにした構成を有している。   The invention according to claim 2 is the invention according to claim 1, wherein the width of the horizontal terrace portion, which is the distance from the photoelectric conversion portion side edge of the inclined terrace portion to the light receiving surface of the photoelectric conversion portion, is C. The distance from the surface of the horizontal terrace portion to the interface on the substrate side of the light absorption layer is D, and the traveling direction of the optical signal and the light reception incident from an angle from the semiconductor substrate with respect to an axis perpendicular to the light receiving surface The angle formed by the axis perpendicular to the surface is the incident angle α, and the angle formed by the surface of the inclined terrace portion and the axis perpendicular to the light receiving surface is the tilt angle β, the incident angle α is the tilt angle β. The horizontal terrace has a configuration in which the width C of the horizontal terrace satisfies the relationship C ≦ D / tan α.

この構成により、請求項1の効果に加え、入射角αが傾斜角β以下であり、水平テラスの幅CがC≦D/tanαの関係を満たすため、上記の受光面となる領域を光電変換部の端面中に適切に確保することが可能な半導体受光素子を実現することができる。   With this configuration, in addition to the effect of the first aspect, the incident angle α is equal to or smaller than the inclination angle β, and the horizontal terrace width C satisfies the relationship C ≦ D / tan α. A semiconductor light receiving element that can be appropriately secured in the end face of the portion can be realized.

また、請求項3に係る発明は、請求項1または請求項2において、前記半導体受光素子が、少なくとも前記光電変換部の端面を覆う保護膜8を有し、前記保護膜が前記受光面において、前記光信号に対して低反射膜として機能するようにした構成を有している。   According to a third aspect of the present invention, in the first or second aspect, the semiconductor light receiving element includes a protective film 8 that covers at least an end face of the photoelectric conversion unit, and the protective film is provided on the light receiving surface. The optical signal is configured to function as a low reflection film.

この構成により、請求項1または請求項2の効果に加え、低反射膜を兼ねるように保護膜を形成するため、別途低反射膜を形成する工程を省くことが可能な半導体受光素子を実現することができる。   With this configuration, in addition to the effects of the first or second aspect, a protective film is formed so as to also serve as a low reflection film, so that a semiconductor light receiving element that can omit a separate step of forming a low reflection film is realized. be able to.

また、請求項4に係る発明は、請求項3において、前記受光面における前記保護膜の平均の厚さをdとし、前記受光面における前記保護膜の屈折率をnとし、前記光信号の波長をλとし、前記保護膜を伝搬する光と前記受光面に垂直な軸とがなす角度θをarcsin(sinα/n)としたとき、前記受光面における前記保護膜の平均の厚さdがλ/(4ncosθ)近傍の厚さであって、前記受光面における前記保護膜が前記低反射膜として機能する厚さにした構成を有している。   According to a fourth aspect of the present invention, in the third aspect, the average thickness of the protective film on the light receiving surface is d, the refractive index of the protective film on the light receiving surface is n, and the wavelength of the optical signal Is λ, and arcsin (sin α / n) is an angle θ between light propagating through the protective film and an axis perpendicular to the light receiving surface, the average thickness d of the protective film on the light receiving surface is λ / (4n cos θ) in the vicinity, wherein the protective film on the light receiving surface has a thickness that functions as the low reflection film.

この構成により、請求項3の効果に加え、受光面における保護膜の平均の厚さdがλ/(4ncosθ)近傍の厚さであって、受光面における保護膜が低反射膜として機能する厚さにしたため、適切な反射率を達成することが可能な半導体受光素子を実現することができる。   With this configuration, in addition to the effect of the third aspect, the average thickness d of the protective film on the light receiving surface is a thickness in the vicinity of λ / (4n cos θ), and the protective film on the light receiving surface functions as a low reflection film. As a result, a semiconductor light receiving element capable of achieving an appropriate reflectance can be realized.

また、請求項5に係る発明は、請求項3または請求項4において、前記保護膜が、少なくとも前記光電変換部の端面を覆い、前記傾斜テラス部上の領域を覆わないように形成されている構成を有している。   According to a fifth aspect of the present invention, in the third or fourth aspect, the protective film is formed so as to cover at least an end face of the photoelectric conversion unit and not cover a region on the inclined terrace portion. It has a configuration.

この構成により、請求項3または請求項4の効果に加え、保護膜が傾斜テラス部上の領域を覆わないように形成されているため、この保護膜を、傾斜テラス部を化学エッチングで形成するときのマスクとすることができ、マスク形成工程を省略することが可能な半導体受光素子を実現することができる。   With this configuration, in addition to the effect of claim 3 or claim 4, since the protective film is formed so as not to cover the region on the inclined terrace portion, this protective film is formed by chemical etching of the inclined terrace portion. It is possible to realize a semiconductor light-receiving element that can be used as a mask and can omit the mask formation step.

また、請求項6に係る発明は、請求項1ないし請求項5のいずれか1項において、前記光電変換部は、pn接合を有し、前記pn接合が前記光電変換部の端面に及ばない構成を有している。   The invention according to claim 6 is the structure according to any one of claims 1 to 5, wherein the photoelectric conversion unit has a pn junction, and the pn junction does not reach an end face of the photoelectric conversion unit. have.

この構成により、請求項1ないし請求項5のいずれか1項の効果に加え、光電変換部中のpn接合が光電変換部の端面に及ばないため、光電変換部の端面近傍の欠陥により発生する暗電流を低減することが可能な半導体受光素子を実現することができる。   According to this configuration, in addition to the effect of any one of claims 1 to 5, the pn junction in the photoelectric conversion unit does not reach the end surface of the photoelectric conversion unit, and therefore, it is generated due to a defect near the end surface of the photoelectric conversion unit. A semiconductor light receiving element capable of reducing dark current can be realized.

本発明は、光電変換部の端面がエッチングにより半導体基板の表面にほぼ垂直に形成され、へきかい位置が受光面から水平テラス部と傾斜テラス部とを隔てた位置に設けられるため、従来の導波路型半導体受光素子よりも、へきかいにより発生するダメージが光電変換部に及びにくいと共に、光信号を基板側から斜めに入射させて使用する場合でも半導体層側から斜めに入射させて使用する場合や半導体層に平行に入射させて使用する場合と同程度に効率的に光信号を入射させることができるという効果を有する半導体受光素子を提供することができるものである。   In the present invention, the end face of the photoelectric conversion portion is formed almost perpendicularly to the surface of the semiconductor substrate by etching, and the scratching position is provided at a position separating the horizontal terrace portion and the inclined terrace portion from the light receiving surface. Damage caused by scratching is less likely to reach the photoelectric conversion part than a type semiconductor light receiving element, and even when an optical signal is incident obliquely from the substrate side and used obliquely from the semiconductor layer side or a semiconductor It is possible to provide a semiconductor light receiving element having an effect that an optical signal can be made to enter as efficiently as the case where it is made incident on a layer in parallel.

以下、本発明の実施の形態について、PIN構造を有する端面入射型の半導体受光素子を例にとり、図面を用いて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking as an example an edge-incident semiconductor light-receiving element having a PIN structure.

(第1の実施の形態)
図1は、本発明の第1の実施の形態に係る半導体受光素子の概略の構造を示す断面図である。図1において、半導体受光素子100は、n−InPからなる半導体基板1の(100)面の上に、n−InP層2、i−InGaAs層3、および、p−InP層4が、この順番に積層された層構成を有する。ここで、i−InGaAs層3は入射した光信号11が吸収される半導体層であり、光吸収層と称される。
(First embodiment)
FIG. 1 is a cross-sectional view showing a schematic structure of a semiconductor light receiving element according to a first embodiment of the present invention. In FIG. 1, a semiconductor light receiving element 100 includes an n-InP layer 2, an i-InGaAs layer 3, and a p-InP layer 4 in this order on the (100) plane of a semiconductor substrate 1 made of n-InP. Have a layered structure. Here, the i-InGaAs layer 3 is a semiconductor layer that absorbs the incident optical signal 11 and is referred to as a light absorption layer.

半導体基板1、半導体層2〜4の表面上には、保護膜7が形成されている。なお、半導体層4上の保護膜7には、p電極6とp−InP層4との電気的接触を確保するためにコンタクトホールが形成されている。p電極6とp−InP層4との間に、例えばn−InGaAsからなるコンタクト層を設け、良好な電気的接触を確保するようになっているのでもよい。また、半導体層2〜4が形成された面と反対側の半導体基板1の面には、n電極8が形成されている。 A protective film 7 is formed on the surfaces of the semiconductor substrate 1 and the semiconductor layers 2 to 4. Note that a contact hole is formed in the protective film 7 on the semiconductor layer 4 in order to ensure electrical contact between the p-electrode 6 and the p-InP layer 4. A contact layer made of, for example, n + -InGaAs may be provided between the p-electrode 6 and the p-InP layer 4 to ensure good electrical contact. An n-electrode 8 is formed on the surface of the semiconductor substrate 1 opposite to the surface on which the semiconductor layers 2 to 4 are formed.

以下、n−InP層2、i−InGaAs層(光吸収層)3、および、p−InP層4からなる半導体層を光電変換部5という。ここで、光電変換部5の端面は、半導体基板1の表面(以下、基板面という。)にほぼ垂直に形成され、光信号11を受光する受光面12を有する。受光面12は、光信号を光電変換部5に適切に入射させるための端面の領域である(図1参照)。半導体基板1は、光電変換部5の受光面よりも外側に傾斜テラス部13と、光電変換部5の受光面12と傾斜テラス部13との間に水平テラス部14とが形成されている。   Hereinafter, a semiconductor layer including the n-InP layer 2, the i-InGaAs layer (light absorption layer) 3, and the p-InP layer 4 is referred to as a photoelectric conversion unit 5. Here, the end surface of the photoelectric conversion unit 5 is formed substantially perpendicular to the surface of the semiconductor substrate 1 (hereinafter referred to as the substrate surface) and has a light receiving surface 12 that receives the optical signal 11. The light receiving surface 12 is a region of an end surface for appropriately allowing an optical signal to enter the photoelectric conversion unit 5 (see FIG. 1). In the semiconductor substrate 1, an inclined terrace portion 13 is formed outside the light receiving surface of the photoelectric conversion portion 5, and a horizontal terrace portion 14 is formed between the light receiving surface 12 and the inclined terrace portion 13 of the photoelectric conversion portion 5.

ここで、図1に示すように、光信号11は、受光面12に垂直な軸よりも半導体基板1寄りの角度で入射するものとする。したがって、受光面12に垂直な軸は、ほぼ基板面とほぼ水平になっている。また、光信号11の進行方向と受光面12に垂直な軸とがなす角をα(以下、入射角という。)とし、傾斜テラス部13が基板面となす角をβ(以下、傾斜角という。)とする(図1参照)。   Here, as shown in FIG. 1, the optical signal 11 is incident at an angle closer to the semiconductor substrate 1 than the axis perpendicular to the light receiving surface 12. Therefore, the axis perpendicular to the light receiving surface 12 is substantially horizontal to the substrate surface. In addition, an angle formed by the traveling direction of the optical signal 11 and an axis perpendicular to the light receiving surface 12 is α (hereinafter referred to as an incident angle), and an angle formed by the inclined terrace portion 13 and the substrate surface is β (hereinafter referred to as an inclination angle). (See FIG. 1).

傾斜テラス部13の光電変換部5側の辺から光電変換部5の受光面12までの距離である水平テラス部14の幅をCとし、水平テラス部14の表面からi−InGaAs層(光吸収層)3の半導体基板1側の界面までの距離をDとする(図1参照)。   The width of the horizontal terrace portion 14 that is the distance from the side of the inclined terrace portion 13 on the photoelectric conversion portion 5 side to the light receiving surface 12 of the photoelectric conversion portion 5 is C, and the i-InGaAs layer (light absorption) from the surface of the horizontal terrace portion 14 The distance to the interface of the layer 3 on the semiconductor substrate 1 side is defined as D (see FIG. 1).

以下では、この距離Dがn−InP層2の層厚に等しいものとして説明する。ここで、光信号11の入射角αは傾斜テラス部13の傾斜角β以下であり、水平テラス部14の幅C、n−InP層2の層厚D、および、光信号11の入射角αとの間には、C≦D/tanα、の関係が成り立つものとする。   In the following description, it is assumed that the distance D is equal to the layer thickness of the n-InP layer 2. Here, the incident angle α of the optical signal 11 is equal to or smaller than the inclined angle β of the inclined terrace portion 13, the width C of the horizontal terrace portion 14, the layer thickness D of the n-InP layer 2, and the incident angle α of the optical signal 11. It is assumed that a relationship of C ≦ D / tan α is established.

各層2〜4用の半導体膜(以下、エピタキシャル膜という。)は、例えば、MOVPE(MetalOrganic Vapor Phase Epitaxy)、MBE(Molecular Beam Epitaxy)等の技術を用いて形成される。また、n型の不純物として、例えば、Sn、S等を用い、p型の不純物として、例えば、Zn等を用いるのでもよい。   A semiconductor film (hereinafter referred to as an epitaxial film) for each of the layers 2 to 4 is formed using a technique such as MOVPE (Metal Organic Vapor Phase Epitaxy) or MBE (Molecular Beam Epitaxy). Further, for example, Sn or S may be used as the n-type impurity, and Zn or the like may be used as the p-type impurity.

各層2〜4用のエピタキシャル膜の厚さは、半導体基板1側からp−InP層4に向かって、それぞれ、例えば、0.5〜1μm、0.5〜4μm、および、0.5〜2μmとする。また、n−InP層2、および、p−InP層4用のエピタキシャル膜の不純物濃度は、例えば、5×1017〜1×1018(cm−3)の範囲内のいずれかとする。なお、これらの膜厚および不純物濃度の値は、一例であり、これらに限定されるものではない。 The thicknesses of the epitaxial films for the layers 2 to 4 are, for example, 0.5 to 1 μm, 0.5 to 4 μm, and 0.5 to 2 μm from the semiconductor substrate 1 side toward the p-InP layer 4, respectively. And Further, the impurity concentration of the epitaxial film for the n-InP layer 2 and the p-InP layer 4 is, for example, in the range of 5 × 10 17 to 1 × 10 18 (cm −3 ). Note that these values of film thickness and impurity concentration are examples, and are not limited to these.

次に、受光面の形成、素子分離等について図2および図3を用いて説明する。図2および図3は、受光面の形成、素子分離等について説明するための工程図である。図2および図3に示す断面図は、(0−11)面を断面とする図である。以下では、(011)面が受光面12となるように光電変換部5を形成するものとする。ここで、上記のp電極6は、光電変換部5の端面近傍の領域を除いた光電変換部5の表面に形成され、(011)面が受光面12となるように形成されているものとする。   Next, formation of the light receiving surface, element isolation, and the like will be described with reference to FIGS. 2 and 3 are process diagrams for explaining formation of a light receiving surface, element isolation, and the like. The cross-sectional views shown in FIGS. 2 and 3 are cross-sections taken along the (0-11) plane. In the following, it is assumed that the photoelectric conversion unit 5 is formed so that the (011) plane becomes the light receiving surface 12. Here, the p-electrode 6 is formed on the surface of the photoelectric conversion unit 5 excluding the region in the vicinity of the end face of the photoelectric conversion unit 5, and the (011) plane is formed to be the light receiving surface 12. To do.

まず、CVD(Chemical Vapor Deposition)等の技術を用いてp−InP層4用のエピタキシャル膜L4の表面にSiOまたはSiNの膜を堆積し、フォトリソグラフィ技術を用いて光電変換部5を形成するためのマスク21を形成する(図2(a)参照)。ここで、マスク21の形状は、1つの辺が[0−11]軸方向にほぼ平行な矩形とする。 First, a SiO 2 or SiN x film is deposited on the surface of the epitaxial film L4 for the p-InP layer 4 using a technique such as CVD (Chemical Vapor Deposition), and the photoelectric conversion portion 5 is formed using a photolithography technique. A mask 21 is formed (see FIG. 2A). Here, the shape of the mask 21 is a rectangle whose one side is substantially parallel to the [0-11] axis direction.

ただし、マスク21の形状は、この矩形には限られず、多角形や、扇形、その他の形状でもよい。次に、マスク21を用いてドライエッチングを行い、n−InP層2、i−InGaAs層3およびp−InP層4用のエピタキシャル膜L2、L3、L4を除去し、光電変換部5を形成する(図2(b)参照)。   However, the shape of the mask 21 is not limited to this rectangle, and may be a polygon, a sector, or other shapes. Next, dry etching is performed using the mask 21 to remove the epitaxial films L2, L3, and L4 for the n-InP layer 2, the i-InGaAs layer 3, and the p-InP layer 4, and the photoelectric conversion unit 5 is formed. (See FIG. 2 (b)).

光電変換部5が形成されたら、マスク21を除去する(図2(c)参照)と共に、保護膜用にSiN、SiO等の膜(以下、パッシベーション膜という。)22を堆積する(図2(d)参照)。このパッシベーション膜22は、受光面12において、いわゆる低反射(Low Reflection。以下、LRという。)膜となるように形成するものとする。すなわち、堆積の際に、パッシベーション膜22が受光面12にまわり込むように堆積される。 When the photoelectric conversion unit 5 is formed, the mask 21 is removed (see FIG. 2C), and a film (hereinafter referred to as a passivation film) 22 such as SiN x , SiO 2 or the like is deposited as a protective film (FIG. 2). 2 (d)). The passivation film 22 is formed to be a so-called low reflection (hereinafter referred to as LR) film on the light receiving surface 12. In other words, during the deposition, the passivation film 22 is deposited so as to go around the light receiving surface 12.

パッシベーション膜22は、受光面12においてLR膜として機能するために、受光面12における膜厚dが、d=λ/(4ncosθ)程度の膜厚であって、反射率が10%程度以下となるいずれかの膜厚に決定される。ここで、記号nはパッシベーション膜22用の材料の屈折率であり、記号λは光信号の波長であり、記号θはパッシベーション膜22を伝搬する光と受光面12に垂直な軸とがなす角度であり、arcsin(sinα/n)である。パッシベーション膜22用の材料としては、上記のようにSiN、SiO等を用いることができるが、他の材料を用いるのでも、これらの材料からなる多層膜とするのでもよい。また、パッシベーション膜22は、電子ビーム蒸着等の蒸着、その他の成膜方法によって形成するのでもよい。 Since the passivation film 22 functions as an LR film on the light receiving surface 12, the film thickness d on the light receiving surface 12 is about d = λ / (4n cos θ), and the reflectance is about 10% or less. Either film thickness is determined. Here, the symbol n is the refractive index of the material for the passivation film 22, the symbol λ is the wavelength of the optical signal, and the symbol θ is the angle formed between the light propagating through the passivation film 22 and the axis perpendicular to the light receiving surface 12. Arcsin (sin α / n). As the material for the passivation film 22, SiN x , SiO 2 or the like can be used as described above, but other materials may be used, or a multilayer film made of these materials may be used. Further, the passivation film 22 may be formed by vapor deposition such as electron beam vapor deposition or other film forming methods.

次に、フォトリソグラフィ技術を用いて、p電極6とp−InP層4との電気的接触を確保するためにコンタクトホール、および、[011]方向に隣り合う半導体受光素子間を分離するウェットエッチング用のマスク(以下、素子分離用マスクという。)を形成する(図2(e)参照)。素子分離用マスクは、保護膜7をマスクとして用いるものであるため、以下では、素子分離用マスク(保護膜7)と記す。   Next, in order to ensure electrical contact between the p-electrode 6 and the p-InP layer 4 using photolithography technology, wet etching that separates the contact holes and the semiconductor light-receiving elements adjacent in the [011] direction is performed. A mask (hereinafter referred to as an element isolation mask) is formed (see FIG. 2E). Since the element isolation mask uses the protective film 7 as a mask, the element isolation mask is hereinafter referred to as an element isolation mask (protective film 7).

ここで、素子分離用マスク(保護膜7)の開口部、すなわち、半導体基板1上に堆積されたパッシベーション膜22の開口部を利用してウェットエッチングすることによって、傾斜テラス部13が得られる形状を有する。ただし、素子分離用マスクの形状は、ウェットエッチングにより傾斜テラス部13が得られるものであればよく、縞状や島状の形状であっても、その他の形状であってもよい。   Here, the shape of the inclined terrace portion 13 is obtained by wet etching using the opening of the element isolation mask (protective film 7), that is, the opening of the passivation film 22 deposited on the semiconductor substrate 1. Have However, the element isolation mask may have any shape as long as the inclined terrace portion 13 can be obtained by wet etching, and may have a stripe shape, an island shape, or other shapes.

図2(e)に示す工程が完了した後、フォトリソグラフィ技術を用いて、コンタクトホールを介してp−InP層4と電気的に接触するようにp電極6を形成する(図2(f)参照)。p電極6を形成した後、レジスト膜を形成し、フォトリソグラフィ技術を用いて、p電極6を覆うようにレジスト膜(以下、保護用レジスト膜という。)23を残す(図3(g)参照)。この保護用レジスト膜23は、上記の順メサ構造の溝を形成する際のエッチングによる侵食からp電極6を保護するためのものである。   After the process shown in FIG. 2E is completed, a p-electrode 6 is formed so as to be in electrical contact with the p-InP layer 4 through the contact hole by using a photolithography technique (FIG. 2F). reference). After the p-electrode 6 is formed, a resist film is formed, and a resist film (hereinafter referred to as a protective resist film) 23 is left so as to cover the p-electrode 6 by using a photolithography technique (see FIG. 3G). ). This protective resist film 23 is for protecting the p-electrode 6 from etching erosion when forming the above-mentioned groove having the forward mesa structure.

保護用レジスト膜23を形成した後、塩酸・リン酸系やBr・メタノール系等の溶液をエッチャントとし、素子分離用マスクを用いてウェットエッチングを行い、順メサ構造を形成する(図3(h)参照)。ここで、上記のエッチャントは、必ずしもこれらの溶液に限られるものではなく、順メサを形成できるものであればその他の溶液であってもよい。上記のエッチングで得られた順メサの部分が傾斜テラス部13である。   After the protective resist film 23 is formed, a solution of hydrochloric acid / phosphoric acid or Br / methanol is used as an etchant, and wet etching is performed using an element isolation mask to form a forward mesa structure (FIG. 3 (h) )reference). Here, the above-mentioned etchant is not necessarily limited to these solutions, and other solutions may be used as long as they can form a forward mesa. The portion of the forward mesa obtained by the above etching is the inclined terrace portion 13.

隣り合う半導体受光素子間を分離する順メサ(傾斜テラス部13)が形成されたら、保護用レジスト膜を除去する(図3(i)参照)。次に、半導体基板1における光電変換部5が形成されていない面(以下、裏面という。)の研磨を行い(図3(j)参照)、研磨後の裏面上にn電極8を形成する(図3(k)参照)。n電極8は、例えば、AuGeNi合金からなるのでもよい。なお、n電極8の形成は、必ずしもこの順番に行われる必要はなく、他の工程に先立って行われるのでも、その他の順番で行われるのでもよい。また、必要であれば、アロイ工程を含んでもよい。   When the forward mesa (inclined terrace portion 13) that separates the adjacent semiconductor light receiving elements is formed, the protective resist film is removed (see FIG. 3I). Next, the surface of the semiconductor substrate 1 where the photoelectric conversion portion 5 is not formed (hereinafter referred to as the back surface) is polished (see FIG. 3J), and the n-electrode 8 is formed on the polished back surface (see FIG. (See FIG. 3 (k)). The n electrode 8 may be made of, for example, an AuGeNi alloy. Note that the formation of the n-electrode 8 is not necessarily performed in this order, and may be performed prior to other processes or may be performed in another order. Further, if necessary, an alloy process may be included.

[011]方向に隣り合う半導体受光素子間の分離は、図3(k)に示すへきかい位置、すなわち、順メサの溝が最も深くなっている位置でへきかいすることによって行うことができる。なお、上記では、傾斜テラス部13上にパッシベーション膜22が堆積されていない半導体受光素子100の製作工程について説明したが、以下に、図4および図5を用いて傾斜テラス部13上にパッシベーション膜22が堆積されている半導体受光素子100の製作工程について説明する。   Separation between adjacent semiconductor light receiving elements in the [011] direction can be performed by scratching at the cracking position shown in FIG. 3 (k), that is, at the position where the forward mesa groove is deepest. In the above description, the manufacturing process of the semiconductor light receiving element 100 in which the passivation film 22 is not deposited on the inclined terrace portion 13 has been described. Hereinafter, the passivation film on the inclined terrace portion 13 will be described with reference to FIGS. 4 and 5. A manufacturing process of the semiconductor light receiving element 100 on which 22 is deposited will be described.

図4(a)〜(d)に示す工程は、図2(a)〜(d)に示す工程と同様であり、その説明を省略する。パッシベーション膜22が形成されたら、レジスト膜を形成し、フォトリソグラフィ技術を用いて、素子分離用マスクを形成するためのレジストパターン24を形成する(図4(e')参照)。次に、レジストパターン24をマスクとしてエッチングし、素子分離用マスク25を形成する(図4(f')参照)。   The steps shown in FIGS. 4A to 4D are the same as the steps shown in FIGS. 2A to 2D, and the description thereof is omitted. After the passivation film 22 is formed, a resist film is formed, and a resist pattern 24 for forming an element isolation mask is formed by using a photolithography technique (see FIG. 4E ′). Next, etching is performed using the resist pattern 24 as a mask to form an element isolation mask 25 (see FIG. 4F ′).

素子分離用マスク25を形成した後、塩酸・リン酸系やBr・メタノール系等の溶液をエッチャントとし、素子分離用マスク25を用いてウェットエッチングを行い、順メサ構造を形成する(図5(g')参照)。これによって、傾斜テラス部13が形成される。傾斜テラス部13が形成されたら、レジストパターン24および素子分離用マスク25を除去する(図5(h')参照)。   After the element isolation mask 25 is formed, a solution of hydrochloric acid / phosphoric acid or Br / methanol is used as an etchant, and wet etching is performed using the element isolation mask 25 to form a forward mesa structure (FIG. 5 ( g ′)). Thereby, the inclined terrace portion 13 is formed. When the inclined terrace portion 13 is formed, the resist pattern 24 and the element isolation mask 25 are removed (see FIG. 5 (h ′)).

次に、パッシベーション膜26を堆積し(図5(i')参照)、フォトリソグラフィ技術を用いて、コンタクトホールを形成する(図5(j')参照)。これによって、保護膜7'が形成される。コンタクトホールを形成したら、フォトリソグラフィ技術を用いて、コンタクトホールを介してp−InP層4と電気的に接触するようにp電極6を形成する(図5(k')参照)。   Next, a passivation film 26 is deposited (see FIG. 5 (i ′)), and contact holes are formed using a photolithography technique (see FIG. 5 (j ′)). Thereby, the protective film 7 ′ is formed. After the contact hole is formed, a p-electrode 6 is formed so as to be in electrical contact with the p-InP layer 4 through the contact hole by using a photolithography technique (see FIG. 5 (k ′)).

p電極6を形成した後、半導体基板1の裏面の研磨を行い、研磨後の裏面上にn電極8を形成する(図5(l')参照)。なお、n電極8の形成は、必ずしもこの順番に行われる必要はなく、他の工程に先立って行われるのでも、その他の順番で行われるのでもよい。また、必要であれば、アロイ工程を含んでもよい。   After the p-electrode 6 is formed, the back surface of the semiconductor substrate 1 is polished, and the n-electrode 8 is formed on the polished back surface (see FIG. 5 (l ′)). Note that the formation of the n-electrode 8 is not necessarily performed in this order, and may be performed prior to other processes or may be performed in another order. Further, if necessary, an alloy process may be included.

従来、LR膜の作製は、光電変換部が形成されたウェーハをへきかいして半導体受光素子アレイを作製し、この半導体受光素子アレイの光入射端面に電子ビーム蒸着法を用いてLR膜を形成していた。LR膜形成後、半導体受光素子アレイをへきかいして半導体受光素子を素子分離していた。そのため、半導体受光素子を破損する可能性が増大すること、光信号が入射する端面を汚してしまう可能性が増大すること、これらの工程に要する治具が必要になること、工程の遂行に手間取ること等、重大な問題が生じていた。上記のように、LR膜を兼ねた保護膜を形成することによって、係る問題を回避することが可能となる。   Conventionally, the LR film is manufactured by making a semiconductor light receiving element array by cleaving the wafer on which the photoelectric conversion portion is formed, and forming the LR film on the light incident end face of the semiconductor light receiving element array by using an electron beam evaporation method. It was. After the formation of the LR film, the semiconductor light-receiving element array was separated by scratching the semiconductor light-receiving element array. Therefore, the possibility that the semiconductor light receiving element is damaged increases, the possibility that the end surface on which the optical signal is incident increases, the jig necessary for these steps is required, and it takes time to perform the steps. There was a serious problem. As described above, it is possible to avoid such a problem by forming the protective film that also serves as the LR film.

また、受光面12を半導体基板1に垂直に形成したため、光信号11を半導体基板1側から斜めに入射させる場合でも、半導体層側から斜めに入射させる場合や半導体層に平行に入射させて使用する場合と同程度に効率的に光信号11が入射される。さらに、傾斜テラス部13を設けて光信号11が半導体基板1に遮られないようにしたため、光信号11を半導体基板1側から斜めに入射させる用途にも用いることができる。   In addition, since the light receiving surface 12 is formed perpendicular to the semiconductor substrate 1, even when the optical signal 11 is incident obliquely from the semiconductor substrate 1 side, the optical signal 11 is incident obliquely from the semiconductor layer side or incident parallel to the semiconductor layer. The optical signal 11 is incident as efficiently as it does. Furthermore, since the inclined terrace portion 13 is provided so that the optical signal 11 is not blocked by the semiconductor substrate 1, the optical signal 11 can also be used for an oblique incidence from the semiconductor substrate 1 side.

さらに、本発明の出願人と同一の出願人に係る発明である特開2004−55620号公報に開示された半導体受光素子の構造を採用することによって、半導体層側から斜めに入射させる場合、および、半導体層と平行に入射させる場合より、高効率で光信号を入射させることができる。   Further, by adopting the structure of the semiconductor light receiving element disclosed in Japanese Patent Application Laid-Open No. 2004-55620, which is an invention related to the same applicant as the present applicant, the light is incident obliquely from the semiconductor layer side, and The optical signal can be incident with higher efficiency than in the case where it is incident in parallel with the semiconductor layer.

以下、本発明の第1の実施の形態に係る半導体受光素子100の動作について説明する。まず、受光面12を経由して光電変換部5に入射した光信号11は、導波路を形成する光電変換部5内を伝播しながらi−InGaAs層(光吸収層)3で吸収され、電子正孔対を生成する。i−InGaAs層(光吸収層)3内で生成された電子正孔対のうち、正孔はp電極6の方向に移動し、電子はn電極8の方向に移動し、それぞれ電気信号として検出される。   The operation of the semiconductor light receiving element 100 according to the first embodiment of the present invention will be described below. First, the optical signal 11 incident on the photoelectric conversion unit 5 via the light receiving surface 12 is absorbed by the i-InGaAs layer (light absorption layer) 3 while propagating through the photoelectric conversion unit 5 forming the waveguide, and is thus electronic. Generate hole pairs. Of the electron-hole pairs generated in the i-InGaAs layer (light absorption layer) 3, holes move in the direction of the p electrode 6, electrons move in the direction of the n electrode 8, and are detected as electric signals. Is done.

以上説明したように、本発明の第1の実施の形態に係る半導体受光素子は、光電変換部の端面がエッチングにより半導体基板の表面にほぼ垂直に形成され、へきかい位置が受光面から水平テラス部と傾斜テラス部とを隔てた位置に設けられるため、従来の導波路型半導体受光素子よりも、へきかいにより発生するダメージが光電変換部に及びにくいと共に、光信号を基板側から斜めに入射させて使用する場合でも半導体層側から斜めに入射させて使用する場合や半導体層に平行に入射させて使用する場合と同程度に効率的に光信号を入射させることができる。   As described above, in the semiconductor light receiving element according to the first embodiment of the present invention, the end surface of the photoelectric conversion unit is formed substantially perpendicular to the surface of the semiconductor substrate by etching, and the scratch position is from the light receiving surface to the horizontal terrace portion. And the sloped terrace part are separated from each other, so that damage caused by scratches is less likely to reach the photoelectric conversion part than the conventional waveguide type semiconductor light receiving element, and an optical signal is incident obliquely from the substrate side. Even when it is used, an optical signal can be made to be incident as efficiently as when it is used obliquely incident from the semiconductor layer side or when it is used incident parallel to the semiconductor layer.

また、入射角αが傾斜角β以下であり、水平テラスの幅CがC≦D/tanαの関係を満たすため、上記の受光面となる領域を光電変換部の端面中に適切に確保することができる。   In addition, since the incident angle α is equal to or smaller than the inclination angle β and the width C of the horizontal terrace satisfies the relationship of C ≦ D / tan α, the above-described region serving as the light receiving surface should be appropriately secured in the end surface of the photoelectric conversion unit. Can do.

また、低反射膜を兼ねるように保護膜を形成するため、別途低反射膜を形成する工程を省くことができ、半導体受光素子を破損する可能性が増大するという問題、光信号が入射する端面を汚してしまう可能性が増大するという問題等を回避することができる。   In addition, since a protective film is formed so as to also serve as a low-reflection film, it is possible to omit a separate process of forming a low-reflection film, which increases the possibility of damaging the semiconductor light receiving element, and an end face on which an optical signal is incident It is possible to avoid the problem that the possibility of fouling increases.

また、受光面における保護膜の平均の厚さdがλ/(4ncosθ)近傍の厚さであって、受光面における保護膜が低反射膜として機能する厚さにしたため、適切な反射率を達成できる。   In addition, the average thickness d of the protective film on the light receiving surface is a thickness in the vicinity of λ / (4n cos θ), and the protective film on the light receiving surface has a thickness that functions as a low reflection film, so that an appropriate reflectance is achieved. it can.

また、保護膜が傾斜テラス部上の領域を覆わないように形成されているため、この保護膜を、傾斜テラス部を化学エッチングで形成するときのマスクとすることができ、マスク形成工程を省略することができる。   Further, since the protective film is formed so as not to cover the region on the inclined terrace portion, this protective film can be used as a mask when the inclined terrace portion is formed by chemical etching, and the mask forming step is omitted. can do.

なお、上記では、半導体受光素子として、PIN構造を有する半導体受光素子を例にとり説明したが、端面入射型の半導体受光素子であれば、pn接合を有する半導体受光素子でも、アバランシェフォトダイオードでも、その他の半導体受光素子でもよい。また、上記では、本発明を単体の半導体受光素子に適用した例について説明したが、アレーPDについても適用できるものである。   In the above description, the semiconductor light receiving element having the PIN structure is described as an example of the semiconductor light receiving element. However, any semiconductor light receiving element having a pn junction, an avalanche photodiode, or the like can be used as long as it is an edge incident type semiconductor light receiving element. The semiconductor light receiving element may be used. In the above description, the example in which the present invention is applied to a single semiconductor light receiving element has been described. However, the present invention can also be applied to an array PD.

(第2の実施の形態)
図6は、本発明の第2の実施の形態に係る半導体受光素子の概略の構造を示す断面図である。図6において、半導体受光素子600は、上記のp−InP層4の代わりにi−InP層またはn- −InP層からなる半導体層42が設けられ、半導体層42の中央領域にp型不純物が拡散された領域43が形成されている。以下、半導体層42をi−InP層とし、領域43をp型不純物拡散領域43という。
(Second Embodiment)
FIG. 6 is a cross-sectional view showing a schematic structure of a semiconductor light receiving element according to the second embodiment of the present invention. In FIG. 6, a semiconductor light receiving element 600 is provided with a semiconductor layer 42 made of an i-InP layer or an n -InP layer instead of the p-InP layer 4, and p-type impurities are present in the central region of the semiconductor layer 42. A diffused region 43 is formed. Hereinafter, the semiconductor layer 42 is referred to as an i-InP layer, and the region 43 is referred to as a p-type impurity diffusion region 43.

p型不純物拡散領域43の不純物濃度は、上記のp−InP層4の不純物濃度と同じオーダーである。また、p型不純物拡散領域43は、i−InGaAs層3と接するか、または、i−InGaAs層3に及ぶものとするが、光電変換部52(図6参照)の端面には及ばないものとする。そして、p型不純物拡散領域43と、i−InGaAs層3およびp型不純物拡散領域43の周囲のi−InP層との境界領域にpn接合が形成される。このように構成することによって、pn接合は光電変換部52の端面に露出しない構造となっている。   The impurity concentration of the p-type impurity diffusion region 43 is in the same order as the impurity concentration of the p-InP layer 4 described above. The p-type impurity diffusion region 43 is in contact with the i-InGaAs layer 3 or extends to the i-InGaAs layer 3 but does not reach the end face of the photoelectric conversion unit 52 (see FIG. 6). To do. A pn junction is formed in the boundary region between the p-type impurity diffusion region 43 and the i-InP layer 3 and the i-InP layer around the p-type impurity diffusion region 43. With this configuration, the pn junction is not exposed to the end face of the photoelectric conversion unit 52.

以下、p型不純物拡散領域43の形成方法について、図7を用いて説明する。図7は、p型不純物拡散領域43の形成方法を説明するための工程図である。p型不純物拡散領域43の形成は、まず、SiNの膜をi−InP層用のエピタキシャル膜L42上に堆積し、フォトリソグラフィ技術、エッチング技術等を用いて、上記のSiNの膜をエッチングし、所定の形状の窓を有するマスク71を形成する(図7(a)参照)。 Hereinafter, a method of forming the p-type impurity diffusion region 43 will be described with reference to FIG. FIG. 7 is a process diagram for explaining a method of forming the p-type impurity diffusion region 43. The p-type impurity diffusion region 43 is formed by first depositing a SiN x film on the epitaxial film L42 for the i-InP layer, and etching the SiN x film using a photolithography technique, an etching technique, or the like. Then, a mask 71 having a window with a predetermined shape is formed (see FIG. 7A).

次に、上記のSiNのマスク71を用いて、i−InP層用のエピタキシャル膜L42の表面直下の不純物濃度が、例えば、1〜5×1018(cm−3)程度となるように不純物を拡散させる(図7(b)参照)。ここで、拡散は気相中で熱拡散によって行うものとし、Znを拡散させる不純物として用いるのが好適である。気相中でのZnの熱拡散は公知であり、その説明は省略する。最後に、SiNからなるマスク71を除去してp型不純物拡散領域43が形成される(図7(c)参照)。 Next, using the SiN x mask 71 described above, the impurity concentration immediately below the surface of the epitaxial film L42 for the i-InP layer is, for example, about 1 to 5 × 10 18 (cm −3 ). Is diffused (see FIG. 7B). Here, the diffusion is performed by thermal diffusion in the gas phase, and it is preferable to use it as an impurity for diffusing Zn. The thermal diffusion of Zn in the gas phase is known and will not be described. Finally, the p-type impurity diffusion region 43 is formed by removing the mask 71 made of SiN x (see FIG. 7C).

以上説明したように、本発明の第2の実施の形態に係る半導体受光素子は、本発明の第1の実施の形態に係る半導体受光素子の効果に加え、p型不純物拡散領域を設け、光電変換部中のpn接合が光電変換部の端面に及ばないまたは露出しないため、光電変換部の端面近傍の欠陥により発生する暗電流を低減することができる。   As described above, the semiconductor light receiving element according to the second embodiment of the present invention is provided with a p-type impurity diffusion region in addition to the effect of the semiconductor light receiving element according to the first embodiment of the present invention. Since the pn junction in the conversion part does not reach or be exposed to the end face of the photoelectric conversion part, dark current generated due to defects near the end face of the photoelectric conversion part can be reduced.

なお、上記の各実施の形態において、n−InP層2と半導体基板1との界面位置を水平テラス部14位置としたが、界面位置は、これに限定されるものではなく、例えば、界面位置が傾斜部の途中に形成される構造でも、光電変換部5の一部に形成される構造でもよい。   In each of the above embodiments, the interface position between the n-InP layer 2 and the semiconductor substrate 1 is the horizontal terrace portion 14 position. However, the interface position is not limited to this, for example, the interface position May be formed in the middle of the inclined portion, or may be formed in a part of the photoelectric conversion portion 5.

本発明に係る半導体受光素子は、従来の導波路型半導体受光素子よりも、へきかいにより発生するダメージが光電変換部に及びにくいと共に、光信号を基板側から斜めに入射させて使用する場合でも半導体層側から斜めに入射させて使用する場合や半導体層に平行に入射させて使用する場合と同程度に効率的に光信号を入射させることができるという効果が有用な半導体受光素子等の用途にも適用できる。   The semiconductor light-receiving element according to the present invention is less susceptible to damage caused by scratches than the conventional waveguide-type semiconductor light-receiving element, and even when used with an optical signal obliquely incident from the substrate side. For applications such as semiconductor light-receiving elements that have the effect of allowing an optical signal to be incident as efficiently as when entering obliquely from the layer side or when entering parallel to a semiconductor layer Is also applicable.

本発明の第1の実施の形態に係る半導体受光素子の概略の構造を示す断面図Sectional drawing which shows the general | schematic structure of the semiconductor light receiving element concerning the 1st Embodiment of this invention 本発明の第1の実施の形態に係る半導体受光素子(傾斜テラス部上に保護膜が存在しない構造)の受光面の形成、素子分離等について説明するための工程図Process diagram for explaining formation of a light-receiving surface, element isolation, and the like of a semiconductor light-receiving element (structure having no protective film on an inclined terrace portion) according to the first embodiment of the present invention 本発明の第1の実施の形態に係る半導体受光素子(傾斜テラス部上に保護膜が存在しない構造)の受光面の形成、素子分離等について説明するための工程図Process diagram for explaining formation of a light-receiving surface, element isolation, and the like of a semiconductor light-receiving element (structure having no protective film on an inclined terrace portion) according to the first embodiment of the present invention 本発明の第1の実施の形態に係る半導体受光素子(傾斜テラス部を保護膜が覆う構造)の受光面の形成、素子分離等について説明するための工程図Process drawing for demonstrating formation, element isolation, etc. of the light-receiving surface of the semiconductor light-receiving element according to the first embodiment of the present invention (a structure in which the inclined terrace portion is covered with a protective film) 本発明の第1の実施の形態に係る半導体受光素子(傾斜テラス部を保護膜が覆う構造)の受光面の形成、素子分離等について説明するための工程図Process drawing for demonstrating formation, element isolation, etc. of the light-receiving surface of the semiconductor light-receiving element according to the first embodiment of the present invention (a structure in which the inclined terrace portion is covered with a protective film) 本発明の第2の実施の形態に係る半導体受光素子の概略の構造を示す断面図Sectional drawing which shows the general | schematic structure of the semiconductor photodetector which concerns on the 2nd Embodiment of this invention p型不純物拡散領域43の形成方法を説明するための工程図Process diagram for explaining a method of forming p-type impurity diffusion region 43 従来の半導体受光素子の構造を示す断面図Sectional view showing the structure of a conventional semiconductor light receiving element

符号の説明Explanation of symbols

1 半導体基板
2 n−InP層
3 i−InGaAs層(光吸収層)
4 p−InP層
5、52 光電変換部
6、88 p電極
7、7' 保護膜
8、89 n電極
11 光信号
12 受光面
13 傾斜テラス部
14 水平テラス部
21、25 マスク
22、26 パッシベーション膜
23 保護用レジスト膜
42 半導体層
81 半絶縁性InP基板
82 n+−InPバッファ層
83 n+−InGaAsP中間屈折率層
84 光吸収層
85 p+−InGaAsPバンド不連続緩和層
86 p+−InPクラッド層
87 p+−InGaAsコンタクト層
100、600、800 半導体受光素子
L2 n−InP層用のエピタキシャル膜
L3 i−InGaAs層用のエピタキシャル膜
L4 p−InP層用のエピタキシャル膜
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 n-InP layer 3 i-InGaAs layer (light absorption layer)
4 p-InP layer 5, 52 photoelectric conversion part 6, 88 p electrode 7, 7 'protective film 8, 89 n electrode 11 optical signal 12 light receiving surface 13 inclined terrace part 14 horizontal terrace part 21, 25 mask 22, 26 passivation film 23 Protective resist film 42 Semiconductor layer 81 Semi-insulating InP substrate 82 n + -InP buffer layer 83 n + -InGaAsP intermediate refractive index layer 84 Light absorbing layer 85 p + -InGaAsP band discontinuous relaxation layer 86 p + -InP cladding Layer 87 p + -InGaAs contact layer 100, 600, 800 Semiconductor light receiving element L2 Epitaxial film for n-InP layer L3 Epitaxial film for i-InGaAs layer L4 Epitaxial film for p-InP layer

Claims (6)

半導体基板(1)上に光吸収層(3)を含む複数の半導体層からなる光電変換部(5)が形成され、光信号(11)が前記光電変換部の端面側から入射する端面入射型の半導体受光素子(100)において、
前記光電変換部の端面は、エッチングによって前記半導体基板の表面にほぼ垂直に形成され、前記光信号を受光する受光面を有し、前記光電変換部の端面よりも外側に位置する前記半導体基板または前記半導体基板上の前記半導体層は、前記光電変換部の受光面よりも外側に位置する傾斜テラス部(13)と、前記光電変換部の受光面と前記傾斜テラス部との間に位置する水平テラス部(14)とを有することを特徴とする半導体受光素子。
An end face incident type in which a photoelectric conversion part (5) composed of a plurality of semiconductor layers including a light absorption layer (3) is formed on a semiconductor substrate (1), and an optical signal (11) is incident from the end face side of the photoelectric conversion part. In the semiconductor light receiving element (100) of
The end surface of the photoelectric conversion unit is formed substantially perpendicularly to the surface of the semiconductor substrate by etching, has a light receiving surface that receives the optical signal, and the semiconductor substrate positioned outside the end surface of the photoelectric conversion unit or The semiconductor layer on the semiconductor substrate includes an inclined terrace portion (13) positioned outside a light receiving surface of the photoelectric conversion portion, and a horizontal position positioned between the light receiving surface of the photoelectric conversion portion and the inclined terrace portion. A semiconductor light-receiving element comprising a terrace portion (14).
前記傾斜テラス部の前記光電変換部側の辺から前記光電変換部の受光面までの距離である前記水平テラス部の幅をCとし、前記水平テラス部の表面から前記光吸収層の基板側の界面までの距離をDとし、前記受光面に垂直な軸よりも前記半導体基板よりの角度から入射する前記光信号の進行方向と前記受光面に垂直な軸とがなす角を入射角αとし、前記傾斜テラス部の面と前記受光面に垂直な軸とがなす角を傾斜角βとしたとき、前記入射角αが前記傾斜角β以下であり、前記水平テラスの幅Cが、C≦D/tanαの関係を満たすようにしたことを特徴とする請求項1に記載の半導体受光素子。   The width of the horizontal terrace portion, which is the distance from the side of the inclined terrace portion on the photoelectric conversion portion side to the light receiving surface of the photoelectric conversion portion, is C, and from the surface of the horizontal terrace portion to the substrate side of the light absorption layer The distance to the interface is D, and the angle between the traveling direction of the optical signal incident from the angle from the semiconductor substrate with respect to the axis perpendicular to the light receiving surface and the axis perpendicular to the light receiving surface is the incident angle α. When the angle formed by the surface of the inclined terrace portion and the axis perpendicular to the light receiving surface is an inclination angle β, the incident angle α is equal to or less than the inclination angle β, and the width C of the horizontal terrace is C ≦ D 2. The semiconductor light receiving element according to claim 1, wherein a relationship of / tan [alpha] is satisfied. 前記半導体受光素子は、少なくとも前記光電変換部の端面を覆う保護膜(7)を有し、前記保護膜が前記受光面において、前記光信号に対して低反射膜として機能するようにしたことを特徴とする請求項1または請求項2に記載の半導体受光素子。   The semiconductor light receiving element has a protective film (7) covering at least an end face of the photoelectric conversion unit, and the protective film functions as a low reflection film for the optical signal on the light receiving surface. 3. The semiconductor light receiving element according to claim 1, wherein the semiconductor light receiving element is characterized in that 前記受光面における前記保護膜の平均の厚さをdとし、前記受光面における前記保護膜の屈折率をnとし、前記光信号の波長をλとし、前記保護膜を伝搬する光と前記受光面に垂直な軸とがなす角度θをarcsin(sinα/n)としたとき、前記受光面における前記保護膜の平均の厚さdがλ/(4ncosθ)近傍の厚さであって、前記受光面における前記保護膜が前記低反射膜として機能する厚さにしたことを特徴とする請求項3に記載の半導体受光素子。   The average thickness of the protective film on the light receiving surface is d, the refractive index of the protective film on the light receiving surface is n, the wavelength of the optical signal is λ, and the light propagating through the protective film and the light receiving surface When the angle θ formed by the axis perpendicular to the axis is arcsin (sin α / n), the average thickness d of the protective film on the light receiving surface is a thickness in the vicinity of λ / (4n cos θ), and the light receiving surface The semiconductor light-receiving element according to claim 3, wherein the protective film has a thickness that functions as the low-reflection film. 前記保護膜は、少なくとも前記光電変換部の端面を覆い、前記傾斜テラス部上の領域を覆わないように形成されていることを特徴とする請求項3または請求項4に記載の半導体受光素子。   5. The semiconductor light receiving element according to claim 3, wherein the protective film covers at least an end face of the photoelectric conversion unit and does not cover a region on the inclined terrace unit. 6. 前記光電変換部は、pn接合を有し、前記pn接合が前記光電変換部の端面に及ばないようにしたことを特徴とする請求項1ないし請求項5のいずれか1項に記載の半導体受光素子。   6. The semiconductor light receiving device according to claim 1, wherein the photoelectric conversion unit has a pn junction, and the pn junction does not reach an end face of the photoelectric conversion unit. 7. element.
JP2004169871A 2004-06-08 2004-06-08 Semiconductor photo detector Expired - Fee Related JP4027917B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004169871A JP4027917B2 (en) 2004-06-08 2004-06-08 Semiconductor photo detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004169871A JP4027917B2 (en) 2004-06-08 2004-06-08 Semiconductor photo detector

Publications (2)

Publication Number Publication Date
JP2005353661A true JP2005353661A (en) 2005-12-22
JP4027917B2 JP4027917B2 (en) 2007-12-26

Family

ID=35587900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004169871A Expired - Fee Related JP4027917B2 (en) 2004-06-08 2004-06-08 Semiconductor photo detector

Country Status (1)

Country Link
JP (1) JP4027917B2 (en)

Also Published As

Publication number Publication date
JP4027917B2 (en) 2007-12-26

Similar Documents

Publication Publication Date Title
JP5045436B2 (en) Avalanche photodiode
JP4609430B2 (en) Avalanche photodiode
US7476598B2 (en) Photodiode and method of manufacturing the same
KR101777225B1 (en) Avalanche photo diode and manufacturing method of the same
JP2008153547A (en) Embedded waveguide-type photodetector
US6020620A (en) Semiconductor light-receiving device with inclined multilayer structure
US8519501B2 (en) Semiconductor light detecting element with grooved substrate
KR100464333B1 (en) Photo detector and method for fabricating thereof
JP3717785B2 (en) Semiconductor light receiving device and manufacturing method thereof
KR20110068041A (en) Avalanche photodetector integrated micro lens
JP3589878B2 (en) Back-illuminated light-receiving device and method of manufacturing the same
JP4985298B2 (en) Avalanche photodiode
JP4027917B2 (en) Semiconductor photo detector
WO2023062766A1 (en) Waveguide-type light receiving element, waveguide-type light receiving element array, and method for producing waveguide-type light receiving element
JP4217855B2 (en) Semiconductor photo detector
JP6660282B2 (en) Light receiving element
JP6041120B2 (en) Manufacturing method of semiconductor light receiving element
JP7409489B2 (en) Light receiving device
JP2005108955A (en) Semiconductor device, manufacturing method thereof, and optical communication module
JPH0272679A (en) Semiconductor photodetector having optical waveguide
US12132131B2 (en) Backside illuminated avalanche photodiode and manufacturing method thereof
JP2001308366A (en) Photodiode
JP2001308367A (en) Photodiode
JPH11163383A (en) Semiconductor light-receiving element
EP0889529A1 (en) Semiconductor light-receiving device and method of fabricating the same

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071004

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071009

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071010

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101019

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111019

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121019

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131019

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees