JP2005346912A - Semiconductor integrated circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus in which a plurality of transistors having different thickness of gate oxide films are integrated in one chip without deteriorating a transistor property. <P>SOLUTION: A plurality of external terminals (output terminals) of a semiconductor substrate in which a plurality of transistors having gate oxide film thickness of different two kinds or more are formed are connected to an internal circuit through an interface circuit. For example, a transistor other than a transistor having the thinnest gate oxide film is used for a transistor connected directly to the external terminal for control circuit controlling each node. Thus, a thick film gate oxide film transistor is used for a node coming into contact with an external power source and requiring high breakdown voltage, and a thin film gate oxide film transistor is used for a transistor not coming into contact with the external power source. Thereby, in the thin film gate oxide film transistor, as only voltage of a range controllable by internal voltage drop is applied, the degree of freedom of device/circuit design is widened remarkably. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device in which transistors having a plurality of gate oxide film thicknesses are integrated on one chip.

In conventional semiconductor integrated circuit devices, most devices use one kind of gate oxide film, and transistors using a plurality of gate oxide film thicknesses are not integrated on one chip. However, the situation is different in a device such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) that requires a high voltage for writing / erasing a memory cell.
In the case of a NOR type flash memory, as shown in FIG. 17, the voltage used for writing / erasing inside is 3 V or more with respect to 3 V of the power supply voltage, and the difference is 3 times or more. is there. FIG. 17 shows a circuit diagram of transistors used in the NOR flash memory and applied voltages at the time of reading, writing, and erasing of the memory cells. A flash EEPROM is a semiconductor memory that includes stacked gate type nonvolatile memory cells and is electrically writable and erased collectively.

In general, the breakdown voltage of a gate oxide film of a transistor is about 10 MV / cm (the breakdown voltage of the gate oxide film is an electric field when the oxide film is destroyed when an electric field higher than that is applied). The voltage applied to the transistor determines how far the gate oxide film can be thinned. Usually, an electric field of about 5 MV / cm, which is less than half that leads to destruction at most, is defined as the upper limit of the electric field that can be applied to the gate oxide film.
The performance of the transistor strongly depends on the gate oxide film thickness, and the performance improves as the film thickness decreases. This is due to the scaling law of the device (for the scaling law, see “Ultra-high-speed MOS device” on pages 6 to 12 (Baifukan)).
In the case of a NOR type flash memory, a different voltage of 3 times or more, 3V / 10V, is applied depending on the mode. Considering the transistor parameters accordingly, when the applied voltage is 10V, it is necessary to form an oxide film 3.3 times thicker than that when the applied voltage is 3V.

If one type of gate oxide film is to satisfy all applications, the above-mentioned breakdown voltage of the gate oxide film must be taken into consideration, so the lower limit of the usable oxide film thickness is about 20 nm. When all transistors are formed with an oxide film thickness corresponding to 10V application, the following problems occur in the 3V application transistor.
1. Degradation of transistor characteristics occurs. Since the gate oxide film is thick, gm does not increase. 2. The threshold cannot be lowered. Since the threshold voltage Vth of the transistor is proportional to the square root of the impurity concentration of the channel and the gate oxide film thickness, a 10V applied transistor has a high threshold and lacks a circuit margin for a low voltage. 3. Layout area increases. Since a high voltage is applied to a 10V specification transistor, various design rules are widened, and the transistor size is increased. In particular, problems 1 and 2 are serious problems in recent memory / flash memory mixed logic devices in which the power supply voltage has been lowered.

For this reason, particularly in a flash memory that operates with a power supply voltage (Vdd) of 3 V or less, a 3 V transistor that operates with a power supply voltage Vdd of 3 V and a 10 V transistor element that operates with a power supply voltage Vdd of 10 V are created separately. It is common to use a process that completely separates the gate oxide film including the gate oxide film. FIG. 18 shows the proper use of transistor symbols. A thin gate portion (FIG. 18A) is a transistor using a thin gate oxide film (hereinafter referred to as a thin film gate oxide transistor), and a thin gate portion (FIG. 18B) is A transistor using a thick gate oxide film (hereinafter referred to as a thick film gate oxide transistor). Thus, for example, in a recent flash EEPROM, it is common to use a gate oxide film formation process.
Hereinafter, the thin film gate oxide transistor is referred to as a low voltage transistor, and the thick gate oxide transistor is also referred to as a high voltage transistor.
Conventionally, a low-voltage transistor has been used as a transistor to which a power supply voltage Vdd is directly applied, a transistor to which a voltage equivalent to the power supply voltage is applied, or an interface-related transistor such as an input buffer / output buffer. . This is to improve the chip performance by improving the performance of the transistor operating with the power supply voltage Vdd as much as possible.

However, this method has several problems as follows.
First, 1. As transistor miniaturization advances and internal step-down operation is generally performed with the internal operation at a voltage lower than the external power supply voltage Vdd, the low-voltage transistor itself may have a withstand voltage lower than the power supply voltage Vdd. .
FIG. 19 is a simplified block diagram of a power supply system in the case of performing internal voltage step-down. In the figure, Vdd is a voltage supplied to the chip from the outside as a power supply voltage, and is supplied to each step-down circuit and each circuit related to the interface. The internal main circuit is supplied with a voltage determined by a step-down circuit and operates as a step-down potential system.
Since the external interface (data output buffer) operates at the power supply voltage Vdd, the internal step-down potential formed by the step-down circuit is supplied to the low-voltage system circuit, and the signal whose potential is converted by the level shifter from the low-voltage system circuit is Given to O buffer. FIG. 20 is an example of an internal power supply voltage drop circuit (voltage stepdown circuit).

In the power supply system shown in FIG. 19, considering the voltage applied to the transistor, the power supply voltage Vdd can reduce the stress applied to the transistor by internal step-down, but the power supply voltage Vdd is directly applied to the interface. Become. Therefore, the breakdown voltage of the interface portion is regulated, and the miniaturization of the transistor is hindered. Here, the interface is a portion to which the power supply voltage Vdd is directly supplied in the input / output buffer and the step-down circuit.
Next, in the same way, in relation to the interface, ternary control, which is common in flash EEPROM (when a high voltage far exceeding Vdd is applied to the input pin (input terminal) is detected as the third value state. 21 shows an example of a high-potential detection circuit that detects the input of the third value, where 12V is normally used as the voltage of the third value, but the power supply voltage Vdd is 3V. For a transistor, a voltage that is four times the rated voltage is applied, which is more severe than problem 1.

Furthermore, there is also a problem regarding 3. ESD stress tolerance. There is a mode (Electro-Static Discharge) in which a high voltage is instantaneously applied to pins (terminals) of a semiconductor integrated circuit device due to the effect of static electricity on the package. As shown in the circuit diagram of FIG. 22 and the semiconductor substrate cross-sectional view, the normal input pin (input terminal) is excessively large in the integrated circuit by arranging a protective element (reverse diode / parasitic bipolar element) near the pad (input terminal). This prevents the voltage from being applied. In FIG. 22, a protective bipolar (FIG. 22A), a parasitic npn bipolar transistor between n ⁺ diffusion region-n ⁺ diffusion region (FIG. 22B), and a parasitic using surface breakdown of a MOS transistor are used as protective elements. An npn bipolar transistor (FIG. 22C) or the like is used.
The reverse diode is composed of a PN junction, but the breakdown voltage is not scaled in proportion to the miniaturization of the gate oxide film. As the film thickness decreases, the voltage at which the oxide film breaks may be less than the breakdown voltage of the PN junction. Therefore, ESD stress is a very serious problem for miniaturized devices.

Also, the node to which the power supply voltage Vdd is directly applied when the voltage is internally stepped down is a problem. Even when the internal voltage is stepped down, there is naturally a node in contact with the power supply voltage Vdd. For this node, if an excessive voltage is applied like other interfaces, the oxide film is destroyed, and even if it is not destroyed, it becomes a big problem in device reliability. Therefore, there may be a case where the oxide film cannot be scaled because the interface portion is a neck.
Patent Document 1 discloses a series of capacitive elements that use an FET having the same gate insulating film thickness as an insulated gate field effect transistor (FET) in a memory device as a capacitor for stabilizing a high voltage generated by a booster circuit. A semiconductor memory device composed of a body is described.
JP-A-6-188387

  The present invention provides a semiconductor integrated circuit device in which a low-voltage transistor and a high-voltage transistor, that is, a plurality of transistors having different gate oxide thicknesses are integrated on one chip without impairing transistor characteristics.

One embodiment of a semiconductor integrated circuit device of the present invention includes a memory cell array formed on a semiconductor substrate, and a plurality of memory cells formed on the semiconductor substrate and constituting the memory cell array. And a control circuit for controlling, and the gate of the Y selector in the control circuit is supplied with an internally boosted potential during reading.
Another embodiment of the semiconductor integrated circuit device of the present invention is a memory cell array formed on the semiconductor substrate and connected to a plurality of memory cells formed on the semiconductor substrate and constituting the memory cell array. And a control circuit that controls each node, and an internal boosted potential is applied to the NMOS driver gate of the source decoder in the control circuit during reading.
That is, in the present invention, a thick gate oxide transistor is used for a node that is in contact with an external power supply and requires a high breakdown voltage, and a thin film gate oxide transistor is used for a transistor that is not in contact with the external power supply. As a result, only a voltage within a range that can be controlled by the internal step-down voltage is applied to the thin-film gate oxide film transistor, so that the degree of freedom in device / circuit design is greatly expanded.

  As described in detail above, according to the present invention, a device using a thin film gate oxide transistor can be controlled by internal step-down by using a thick gate oxide transistor having a high breakdown voltage at the node in contact with the outside. Only a voltage in the range is applied, and the degree of freedom in device / circuit design is greatly expanded. Further, since the electric field becomes weaker as the gate oxide film is thicker, the ESD protection withstand voltage can be set higher.

  Hereinafter, embodiments of the invention will be described with reference to examples.

Embodiment 1 will be described with reference to the drawings.
FIG. 1 is a plan view schematically showing the surface of a semiconductor substrate such as silicon on which a semiconductor integrated circuit device is formed. For example, a plurality of input / output terminals 23, a power supply terminal (Vdd) 21, and a ground terminal (GND) 22 are arranged around the semiconductor substrate 1. An internal circuit 4 constituting an integrated circuit such as a memory cell array is formed inside the semiconductor substrate 1, and the internal circuit 4 is connected to the external terminal 2 via an interface circuit 3 such as an input circuit or an output circuit. .
At least a thick gate oxide transistor (see FIG. 18B) is used as the MOS transistor directly connected to the power supply terminal 21. A power supply line 24 and a ground line 25 connected to the power supply terminal 21 and the ground terminal 22 are formed on the semiconductor substrate 1. The oxide film thickness of the thick gate oxide transistor exceeds 10 nm. 12 to 20 nm is preferable. With this thickness, 5V can be applied. On the other hand, the oxide film thickness of the thin-film gate oxide transistor that is not directly connected to the power supply terminal 21 does not need to be applied with 5 V, and is 10 nm or less, preferably about 8 nm or less.

  FIG. 2 is a circuit diagram of the data output buffer circuit and the level shifter formed on the semiconductor substrate. An internal output signal of a step-down potential formed by a step-down circuit (not shown) is input to a level shifter and output from an output terminal (I / O) to an external terminal via an output buffer. The level shifter includes PMOS transistors P1 and P2, NMOS transistors N1 and N2, and an inverter circuit INV. The output buffer is composed of PMOS transistors P3, P4, P5 and NMOS transistors N3, N4, N5. The PMOS transistors P1 and P2 connected to the source of the power supply voltage Vdd are thick gate oxide transistors. The NMOS transistors N1 and N2 whose drains are connected to the drains of the PMOS transistors P1 and P2 are also formed of thick gate oxide transistors. The inverter circuit INV is connected between the gates of the NMOS transistors N1 and N2 so that the output of the inverter circuit is input to the gate of the NMOS transistor N2. The gate of the PMOS transistor P1 is connected to the connection portion between the PMOS transistor P2 and the NMOS transistor N2. The gate of the PMOS transistor P2 is connected to the connection portion between the PMOS transistor P1 and the NMOS transistor N1.

The power source voltage Vdd is connected to the sources of the PMOS transistor P3 constituting the inverter circuit of the output buffer, the PMOS transistor P4 constituting the inverter circuit, and the PMOS transistor P5 connected to the output terminal. Therefore, these PMOS transistors P3, P4 and P5 are formed of thick film gate oxide transistors, and the NMOS transistors N3, N4 and N5 connected to these transistors also use thick film gate oxide transistors.
In this way, all transistors prior to the level shifter are formed by thick gate oxide transistors, that is, high voltage transistors. The other transistors are thin film gate oxide transistors.
In this example, an output signal of an internal voltage is received and a signal is given to the output buffer transistor after level shifting to the power supply voltage Vdd level. Even when there is no internal voltage drop, it may be possible to form an output buffer transistor directly connected to the external terminal I / O in a high potential system. This alone has a sufficient effect on the insufficient ESD withstand voltage, which is the third problem of the prior art.

FIG. 3 is a circuit diagram of the input buffer formed on the semiconductor substrate.
As in the case of FIG. 2, the power supply voltage Vdd is applied to the first input stage, which is sufficiently effective as an ESD countermeasure. The PMOS transistor P6 and NMOS transistor N6, whose gates are connected to the input terminals, have an inverter structure, both of which are made of thick gate oxide transistors. The source of the PMOS transistor P6 is connected to the power supply voltage Vdd. These transistors are connected to an internal circuit via an inverter INV.
FIG. 4 is a circuit diagram of an output buffer formed on the semiconductor substrate.
Here, from the viewpoint of increasing the ESD withstand voltage, a thick gate oxide transistor is used only in the final stage of the output buffer directly connected to the output terminal. This final stage includes a PMOS transistor P7 and an NMOS transistor N7 connected in series, and a power supply voltage Vdd is applied to the source of the PMOS transistor P7. As transistors constituting the inverters INV1 and INV2 connected to these transistors, thin-film gate oxide transistors, that is, low-potential transistors are used.

FIG. 5 is a circuit diagram of the high potential detection circuit. The circuit configuration is the same as that of the conventional high potential detection circuit shown in FIG. 21, but in this circuit, a thick gate oxide transistor is used for the transistor connected to the input terminal and the transistor to which the power supply voltage Vdd is applied to the gate. It is different from the conventional one. That is, the thick gate oxide transistor includes a PMOS transistor P8 having a source having the same potential as the substrate potential connected to the input terminal, a gate connected to the drain, and a PMOS transistor P9 having a source connected to the drain of the PMOS transistor P8, The drain is connected to the drain of the PMOS transistor P8, and the source is used for the NMOS transistor N8 having the ground potential Vss. The ternary level detection signal is output via inverters INV1 and INV2.
In the flash EEPROM to which the present invention is applied, ternary control (when the third state is detected when a high voltage far exceeding Vdd is applied to the input terminal) is a problem. Although the voltage of 12V is normally used as the third voltage, the power supply voltage Vdd is 4 times higher than the rated voltage for 3V type transistors, which is more severe than problem 1. This problem can be avoided by applying a gate oxide transistor to this detection circuit.

FIG. 6 is a circuit diagram of an internal power supply voltage drop circuit (step-down circuit).
The circuit configuration is the same as that of the conventional step-down circuit shown in FIG. 21, but this circuit differs from the conventional one by using a thick gate oxide film transistor as the transistor to which the power supply voltage Vdd is applied. FIG. 19 is a simplified block diagram of a power supply system in the case of performing internal voltage step-down. Vdd is a voltage supplied to the chip from the outside as a power supply voltage, and is supplied to each step-down circuit and each interface-related circuit. The internal main circuit is supplied with a voltage determined by a step-down circuit and operates as a step-down potential system.

This step-down circuit has a differential amplifier AMP having a negative input to the reference voltage Vref generated by the reference voltage generation circuit, a PMOS transistor P10 having a gate connected to the output of the differential amplifier AMP and a source connected to the power supply voltage Vdd. The NMOS transistor N10 has a drain and a gate connected to the drain of the PMOS transistor P10. The NMOS transistor N9 has a gate connected to the drain of the PMOS transistor P10 and a source connected to the power supply voltage Vdd. It is composed of resistors R1 and R2 connected to the positive input of the dynamic amplifier AMP, and an internal power supply voltage VddINT is generated from this step-down circuit.
In this embodiment, the thick gate oxide transistor which is a feature of the present invention is used for the PMOS transistor P10 and the NMOS transistors N9 and N10. On the other hand, a thin film gate oxide transistor is used for a transistor that is directly connected to the step-down circuit and operates in a step-down potential system.

Next, referring to the manufacturing process sectional views shown in FIG. 7 to FIG. 10, a semiconductor integrated circuit device in which a thick gate oxide transistor (low voltage transistor) and a thin gate oxide transistor (high voltage transistor) are mixedly mounted is manufactured. A method will be described. This semiconductor integrated circuit device is, for example, a multi-power supply device including a logic in which a NOR flash memory is embedded. The semiconductor substrate 1 includes a high-voltage transistor region 20 that operates at, for example, 10V, and a low-voltage transistor region 30 that operates at, for example, 3V.
First, a field oxide film 5 having a thickness of 550 nm is formed on the surface of a semiconductor substrate 1 such as a silicon semiconductor by LOCOS method. In order to form this, an element formation region on the surface of the semiconductor substrate 1 is masked, and heat treatment is performed to form an element isolation region. By forming the field oxide film 5, the semiconductor substrate 1 is separated into a high-voltage transistor region 20 and a low-voltage transistor region 30 (FIG. 7A). Thereafter, a dummy gate oxide film 6 having a thickness of about 15 nm is formed in the element region on the semiconductor substrate 1 by thermal oxidation (FIG. 7B). Thereafter, a photoresist 7 having a pattern exposing the high-voltage transistor region 20 is formed on the semiconductor substrate 1.

Then, channel ion implantation 8 for implanting boron ions, for example, under conditions of 60 KeV and 6 × 10 ¹² atoms / cm ² is performed below the dummy gate oxide film 6 in the high-voltage transistor region 20 using the photoresist 7 as a mask. (FIG. 8 (a)). Next, after removing the photoresist 7 on the semiconductor substrate 1 by acid treatment or the like, a photoresist 9 having a pattern in which the low-voltage transistor region 30 is exposed is formed on the semiconductor substrate 1. Then, for example, boron ions are first implanted deeply under the conditions of 80 KeV and 1.5 × 10 ¹² atoms / cm ² under the dummy gate oxide film 6 in the low-voltage transistor region 30 using the photoresist 9 as a mask. Boron ions are implanted shallowly under the conditions of 40 KeV and 2.5 × 10 ¹² atoms / cm ² to perform channel ion implantation 11 (FIG. 8B).
Next, after removing the photoresist 9 by acid treatment, the dummy gate oxide film 6 is removed by dilute HF treatment. Next, a gate oxide film 12 having a thickness of about 18 nm is formed in the high-voltage transistor region 20 and the low-voltage transistor region 30 (FIG. 9A). Next, a photoresist 13 covering the high-voltage transistor region 20 is formed on the semiconductor substrate 1, and using this as a mask, the gate oxide film 12 in the low-voltage transistor region 30 is removed by dilute HF treatment (FIG. 9B).

  Next, after removing the photoresist 13 by acid treatment, the semiconductor substrate 1 is heat-treated to form a gate oxide film having a thickness of about 10 nm on the surfaces of the high-voltage transistor region 20 and the low-voltage transistor region 30. That is, in the high-voltage transistor region 20, an oxide film is further stacked on the gate oxide film 12 to form a gate oxide film 15 having a thickness of about 20 nm. In the low-voltage transistor region 30, the surface of the semiconductor substrate 1 is heated. Oxidation is performed to form a thin gate oxide film 14 having a thickness of about 10 nm. By this method, gate oxide films having different thicknesses are formed. Next, after depositing a polysilicon film 18 serving as a gate electrode material on the entire surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method or the like, impurities such as phosphorus are diffused into the polysilicon film 18 (FIG. a)). Thereafter, the polysilicon film 18 is patterned to selectively form an impurity diffusion region in the surface region of the semiconductor substrate 1. As a result, in the high-voltage transistor region 20, an NMOS transistor is formed that includes the source / drain region 16, the gate oxide film 15 formed therebetween, and the gate electrode 18 formed thereon. In the low-voltage transistor region 30, an NMOS transistor is formed which includes a source / drain region 17, a gate oxide film 14 formed therebetween, and a gate electrode 18 formed thereon ( FIG. 10B).

As a means for forming the gate oxide film, a method of forming a gate oxide film having a predetermined thickness for each region can be used without taking the method of forming the above-described oxide film in an overlapping manner.
Also, here, a case where a transistor having two types of gate oxide film thicknesses is formed is shown. For example, a low-voltage transistor is separately formed into a power supply voltage Vdd system and a step-down potential system having the thinnest gate oxide film. A transistor having three or more gate oxide film thicknesses may be formed. In this case, the transistors of the interface circuit and the step-down circuit may be composed of either Vdd type or high voltage type transistors.
Next, an embodiment in which the present invention is applied to a control circuit constituting a flash EEPROM will be described.
First, internal boosting in the flash EEPROM will be described.
In a circuit having a large analog element such as a read system of a semiconductor memory, the power supply margin is often narrower than that of a normal CMOS logic portion. In particular, as the voltage of the device is lowered, it is necessary to devise a circuit to make up for the shortage of the power supply margin in the analog portion.

Hereinafter, a read circuit of the flash EEPROM will be described. FIG. 11 is a cross-sectional view of a memory cell and an equivalent circuit diagram of a flash EEPROM, and FIG. 12 is a circuit diagram of a cell array. In the figure, VG is a gate voltage, VS is a source voltage, and VD is a drain voltage. Data writing / erasing to the memory cell is performed by injecting electrons into the floating gate and extracting them. In the state where electrons are present in the floating gate, the threshold value seen from the control gate is increased and turned off, and in the state where no electrons are present, the threshold value seen from the control gate is lowered and turned on. The on-state threshold is generally about 2V.
In the conventional flash EEPROM, the power supply voltage is generally Vdd = 5V, and Vdd = 5V is directly applied to the control gate (VG) of the memory cell at the time of reading. In such a case, the cell current Icell detected in the memory cell in the on state at the time of reading is expressed by the following equation (1).
Icell = kVD (Vdd-VTHcell- 1/2 · VD 2) ··· (1)
Here, k is a proportionality constant. When VTHcell = 2V, Vdd−VTHcell = 3V and sufficient cell current Icell can be obtained. However, when the voltage is lowered and Vdd = 3V, Vdd−VTHcell = 1V, so that a sufficient cell current cannot be obtained.

For this reason, at the time of reading, for example, a technique has been proposed in which the voltage applied to the word line of the memory cell is set to about 5 V by internal boosting using a booster circuit as shown in FIG. FIG. 13 is composed of a plurality of diodes connected in series and a capacitor connected between the anode / cathode of the diodes, and an antiphase signal from the ring oscillator is applied to the capacitor.
Although the necessity of boosting the gate voltage of the memory cell has been described above, the same thing occurs in the column at the time of reading.
FIG. 14 is a schematic circuit diagram of a read circuit of the flash EEPROM. Vbias is set to about 2 V, and the upper limit of the bit line voltage at the time of reading is limited. The drain voltage VD is approximately 1V.
The minute amplitudes of the bit lines BL and / BL are amplified by the load R and input to the sense amplifier AMP to determine “1” / “0” (on state / off state) of the memory data.

A problem with the lowering of the potential is the resistance of the Y selector. In the conventional 5V operation, the power supply voltage Vdd is applied to the Y selector gate Tr1 during reading. Since the bias of the Y selector gate is VG = 5V and VS = 1V, the resistance of the Y selector is sufficiently smaller than the equivalent resistance of the cell.
However, when the power supply voltage Vdd is lowered to 2.7 V or less, VG = 2.7 V and VS = 1 V, so VGS = 1.7 V, and the equivalent resistance of the Y selector becomes very large. come. That is, there is a problem that the resistance of the Y selector is so high that it cannot be ignored compared to the cell, and the resistance value of the Y selector has a large power supply voltage dependency. As a result, the Vddmin margin of the read circuit is greatly impaired.
As a countermeasure against such a problem, the voltage applied to the Y selector at the time of reading also uses the boosted potential. Since the boosted potential can be set to a constant potential that does not depend on the external power supply, the cell periphery (word line + Y selector) operates in the same bias relation even in a wide power supply voltage range, and a stable read operation can be obtained.
Further, the boosted potential described above can be applied to a source decoder. This is because the resistance of the NMOS driver of the source decoder becomes a problem as with the Y selector as the read potential is lowered.

FIG. 15 is a block diagram of the flash EEPROM, and FIG. 16 is a simplified block diagram of a control circuit for the memory cell of the flash EEPROM. In such a control circuit, the source decoder is a circuit that outputs a high level at the time of erasing, and outputs a low level otherwise. In FIG. 16, the function of the source decoder is simplified and expressed as an inverter, but actually has various configurations.
In addition, since a high voltage is applied to both the Y selector and the source decoder at the time of writing and erasing, a thick gate oxide film transistor, that is, a high voltage transistor that is generally not suitable for low voltage operation is used as the transistor here. . Therefore, the use of the boosted potential for the gate of the Y selector and the NMOS driver gate of the source decoder is very effective in achieving stable operation during reading.

In the present invention, the following operations are recognized by the above-described configuration.
(1) Interface relations With the miniaturization of devices, the voltage reduction is progressing, but some systems still use 5V. Therefore, it is important that the power supply voltage range that can be operated as a function required for the device is wide. This appears to be an adverse effect on the progress of miniaturization. In general, when the device operation is guaranteed in a wide power supply voltage range such as 2 V to 5 V, an internal step-down circuit is used so that the internal power supply voltage does not increase excessively. Excessive voltage stress is applied exclusively to the voltage drop circuit, but the interface relationship is also different, and the power supply voltage itself is applied to the transistor. Therefore, if all the transistors are regulated by the breakdown voltage of the interface part, the interface part becomes a bottleneck because the device is scaled to achieve high performance, but the interface part becomes a bottleneck, and the device can be scaled. The end of things that happen to end up happening. On the other hand, if a thick gate oxide transistor with a high breakdown voltage is used for the node that is in contact with the outside in the interface circuit, the thin film device can only be applied with a voltage that can be controlled by internal step-down. The degree of freedom is greatly expanded.

(2) Three-value control As in the case of (1), it is a very serious problem that a third value of 12V is applied to a thin film device that must be internally stepped down. Regarding the internal voltage of the chip, it is possible to prevent excessive stress from being applied by controlling the internal power supply. However, since the external voltage is directly applied to the interface portion, the stress cannot be reduced by circuit measures. If a transistor having a breakdown voltage of 10 V or more can be used in such a case, the problem of stress applied to the oxide film can be solved at once.
(3) ESD
If the gate oxide film is thick, the electric field becomes weak, so the ESD protection withstand voltage can be set high.
(4) The voltage stress applied to the node in contact with the power supply voltage Vdd when the power supply voltage drop circuit is used also reduces the electric field by increasing the thickness of the gate oxide film.

1 is a plan view of a semiconductor integrated circuit device of the present invention. FIG. 3 is an output buffer circuit and level shifter circuit diagram of the semiconductor integrated circuit device of the present invention. FIG. 3 is an input buffer circuit diagram of the semiconductor integrated circuit device of the present invention. 1 is an output buffer circuit diagram of a semiconductor integrated circuit device of the present invention. 1 is a circuit diagram of high potential detection (three-value control) of a semiconductor integrated circuit device of the present invention. The internal power supply step-down circuit diagram of the semiconductor integrated circuit device of the present invention. Sectional drawing of the manufacturing process of the semiconductor integrated circuit device of this invention. Sectional drawing of the manufacturing process of the semiconductor integrated circuit device of this invention. Sectional drawing of the manufacturing process of the semiconductor integrated circuit device of this invention. Sectional drawing of the manufacturing process of the semiconductor integrated circuit device of this invention. Sectional drawing of a non-volatile memory cell, and its equivalent circuit schematic. The circuit diagram of the memory cell array of flash EEPROM. FIG. 3 is a boost circuit diagram of a flash EEPROM. FIG. 3 is a read circuit diagram of a flash EEPROM. A circuit block diagram of a flash EEPROM. The control circuit diagram of a flash EEPROM cell. FIG. 4 is a diagram illustrating an NOR-type flash EEPROM cell and operating voltage in each mode. FIG. 10 is an explanatory diagram of symbols of transistors used in the present invention. The power supply system figure in the case of using internal power supply step-down. The circuit diagram which shows an internal power supply step-down circuit. The circuit diagram which shows the circuit which detects the input of the 3rd value. The circuit diagram which shows the protection element of a terminal, and a semiconductor substrate sectional drawing.

Explanation of symbols

1 ... Semiconductor substrate, 2 ... External terminal,
3 ... interface circuit, 4 ... internal circuit,
5 ... Field oxide film, 6 ... Dummy gate oxide film,
7, 9, 13 ... photoresist, 8, 11 ... ion implantation,
12, 14, 15 ... gate oxide film,
16, 17 ... source / drain region, 18 ... gate electrode,
20 ... High-voltage transistor region, 21 ... Power supply terminal,
22 ... grounding terminal, 23 ... input or output terminal,
24 ... Power line 25 ... Grounding line
30: Low-voltage transistor region.

Claims (4)

A memory cell array formed on a semiconductor substrate;
A control circuit formed on the semiconductor substrate, connected to a plurality of memory cells constituting the memory cell array, and controlling each node of the memory cells;
A semiconductor integrated circuit device, wherein an internal boosted potential is applied to a gate of a Y selector in the control circuit during reading. 12. A plurality of transistors having two or more different gate oxide film thicknesses are formed on the semiconductor substrate, and a transistor other than a transistor having the thinnest gate oxide film is used for the Y selector. The semiconductor integrated circuit device described. A memory cell array formed on the semiconductor substrate;
A control circuit formed on the semiconductor substrate, connected to a plurality of memory cells constituting the memory cell array, and controlling each node of the memory cells;
A semiconductor integrated circuit device, wherein an internal boosted potential is applied to an NMOS driver gate of a source decoder in the control circuit during reading. 14. The semiconductor substrate according to claim 13, wherein a plurality of transistors having two or more different gate oxide film thicknesses are formed on the semiconductor substrate, and a transistor other than a transistor having the thinnest gate oxide film is used as the source decoder. The semiconductor integrated circuit device described.

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