JP2005345612A - Electrooptical device and its manufacturing method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a decrease in display quality due to resistance of an auxiliary capacity line. <P>SOLUTION: The surface of an intermediate electrode layer 183 is covered with a dielectric layer 185. A two-terminal type nonlinear element 14 is arranged in the gap between a data line 13 and a pixel electrode 16. To a 2nd conductive layer 142 of the two-terminal type nonlinear element 14, a 1st electrode part 181 is coupled which constitutes a 1st auxiliary capacitor 18a by facing the intermediate electrode layer 183 across the dielectric layer 185. The auxiliary capacity line 17 has a 1st layer 171 and a 2nd layer 172. The 1st layer 171 is covered with an insulating layer 175 which is formed of the same material as the dielectric layer 185 to nearly the same thickness. The 2nd layer 172 is formed of a material having lower resistivity than the 1st layer 171 and conducts to the 1st layer 171 through a contact hole CH1 of the insulating layer 175. A 2nd electrode part 182 of the 2nd layer 172 constitutes a 2nd auxiliary capacitor 18b opposite the intermediate electrode layer 183 across the dielectric layer 185. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for controlling the optical characteristics of an electro-optical material such as liquid crystal using a non-linear element.

  2. Description of the Related Art An active matrix type electro-optical device using a two-terminal nonlinear element such as a TFD (Thin Film Diode) element has been conventionally proposed as a nonlinear element for controlling the behavior of an electro-optic material. In this type of electro-optic device, a capacitance (hereinafter referred to as “pixel capacitance”) having an electro-optic material interposed between electrodes and a two-terminal nonlinear element are connected in series between a scanning line and a data line. It is common. Under this configuration, the resistance value of the two-terminal nonlinear element changes according to the voltage applied to the scanning line and the data line, and charges corresponding to the resistance value are accumulated in the pixel capacitance, so that the electro-optics The optical properties (eg, transmittance) of the material are controlled.

In this configuration, the voltage applied to the scanning line and the data line is capacitively divided by the capacitance associated with the two-terminal nonlinear element and the pixel capacitance. Therefore, if the capacitance of the two-terminal nonlinear element is sufficiently smaller than the pixel capacitance (that is, if the ratio between the pixel capacitance and the capacitance of the two-terminal nonlinear element is sufficiently large), the voltage between the scanning line and the data line Most of the voltage is applied to the two-terminal nonlinear element, so that the resistance value of the two-terminal nonlinear element can be quickly and surely reduced to accumulate a sufficient charge in the pixel capacitor. However, there is a limit to increasing the ratio between the pixel capacitance and the capacitance of the two-terminal nonlinear element (hereinafter sometimes simply referred to as “capacitance ratio”) by reducing the capacitance of the two-terminal nonlinear element or increasing the pixel capacitance. is there. That is, first, in order to reduce the capacitance of the two-terminal nonlinear element, it is necessary to reduce the size of the two-terminal nonlinear element. Second, in order to increase the pixel capacity, it is necessary to increase the pixel area. However, the increase in the area may cause a result contrary to the demand for higher definition of the display image. In addition, when a sufficient capacity ratio cannot be ensured, a desired voltage is not applied to the two-terminal nonlinear element, so that the two-terminal nonlinear element cannot be appropriately operated, and as a result, the display quality is deteriorated. There's a problem. In order to solve this problem, for example, Patent Document 1 proposes a configuration in which an auxiliary capacitor is arranged in parallel with a pixel capacitor. The auxiliary capacitance is formed by making a pixel electrode constituting the pixel capacitance and an auxiliary capacitance line face each other with an insulating layer interposed therebetween.
JP-A-5-19302 (paragraph 0025 and FIG. 2)

  However, under such a configuration, there is a problem of deterioration in display quality due to the resistance of the auxiliary capacitance line. That is, since the resistance from the portion to which the voltage is applied in the auxiliary capacitance line to each auxiliary capacitance is different, even if the same gradation is displayed on all the pixels, the voltage applied to each auxiliary capacitance is This is different for each pixel, and consequently, the voltage applied to each two-terminal nonlinear element varies. As a result, the error between the gradation actually displayed by each pixel and the original gradation is different for each pixel, resulting in a deterioration in display quality. In particular, as described in Patent Document 1, when the auxiliary capacitance line is formed of a conductive material such as tantalum (Ta) having a high resistance value, variation in the voltage applied to each auxiliary capacitance is remarkable. Therefore, the deterioration of display quality becomes more serious. The present invention has been made in view of such circumstances, and an object thereof is to suppress deterioration in display quality due to the resistance of the auxiliary capacitance line.

  In order to achieve this object, an electro-optical device according to the present invention includes a scanning line and a data line extending in directions intersecting each other, and a nonlinear element having one end connected to one of the scanning line and the data line. A pixel electrode connected to the other end of the nonlinear element and facing the other of the scanning line and the data line with an electro-optic material interposed therebetween, an intermediate electrode layer whose surface is covered with a dielectric layer, and a pixel electrode A first electrode portion constituting a first auxiliary capacitor facing the intermediate electrode layer across the dielectric layer, and a second auxiliary capacitor facing the intermediate electrode layer across the dielectric layer A second electrode portion. This electro-optical device is used as a display device for various electronic devices.

  In a preferred aspect of the present invention, an auxiliary capacitance line having a first layer partially covered by an insulating layer and a second layer in contact with a portion of the first layer not covered by the insulating layer is provided. . The second layer and the second electrode portion may be continuous portions. For example, the second layer and the second electrode portion are integrally formed by selectively removing a single conductive film. In addition, if the insulating layer covering the first layer and the dielectric layer covering the intermediate electrode layer are formed with substantially the same film thickness with the same material, they are compared with the case where they are formed with different materials in separate steps. Thus, the manufacturing process can be simplified and the manufacturing cost can be reduced.

  In this aspect, since the auxiliary capacitance line includes not only the first layer but also the second layer having a resistivity lower than that of the first layer, the auxiliary capacitance line includes only the first layer. The resistance of the auxiliary capacitance line is reduced as compared with the above configuration. Therefore, a reduction in display quality (particularly variations in display gradation) due to the resistance of the auxiliary capacitance line is suppressed. By the way, in order to bring the second layer into contact (conduction) with the first layer covered with the insulating layer, it is necessary to selectively remove the insulating layer to expose the first layer. However, when the thickness of the insulating layer is large, it is difficult to completely remove the portion where the first layer and the second layer are to conduct. Therefore, it is desirable that the insulating layer is thin from the viewpoint of ensuring conduction between the first layer and the second layer. Here, as a configuration for sufficiently securing a voltage applied to the nonlinear element, an auxiliary capacitor having a first layer of the auxiliary capacitor line and a conductive layer opposed to the first layer of the auxiliary capacitor line is arranged. A configuration is conceivable (see FIG. 12). However, in this configuration (hereinafter referred to as “proportional”), if the insulating layer is thinned from the viewpoint of ensuring conduction between the first layer and the second layer, the insulating layer as the dielectric of the auxiliary capacitor becomes thin and the resistance is reduced. As a result, current leakage occurs between the electrodes. As described above, it is difficult to achieve both ensuring the conduction between the first layer and the second layer and reducing the leakage current under the comparative configuration. On the other hand, according to the present invention, since a plurality of auxiliary capacitances such as the first auxiliary capacitance and the second auxiliary capacitance are interposed between the pixel electrode and the auxiliary capacitance line, the first layer and the second layer Even if the dielectric layer and the insulating layer are thinned in order to ensure the conduction, leakage current can be suppressed. For example, even if the thicknesses of the insulating layer and the dielectric layer are halved, the resistance itself from the pixel electrode to the auxiliary capacitance line does not change. Thus, according to the present invention, it is possible to achieve both ensuring of conduction between the first layer and the second layer and reduction of leakage current.

  The electro-optical material in the present invention is a material that converts electrical energy into an optical action. A typical example of such a substance is a liquid crystal whose transmittance changes according to an applied voltage, but the range to which the present invention is applied is not limited to a liquid crystal device. In addition, the nonlinear element in the present invention means that a current flowing between two terminals changes nonlinearly with respect to a change in voltage applied between two terminals (that is, a resistance value changes nonlinearly with respect to a change in voltage). ) Element. A typical example of the nonlinear element is a two-terminal nonlinear element such as a TFD element, but the present invention can also be applied to an electro-optical device using a three-terminal nonlinear element such as a TFT (Thin Film Transistor) element.

  In the present invention, the two auxiliary capacitors, the first auxiliary capacitor and the second auxiliary capacitor, are used as components. However, a configuration in which other auxiliary capacitors are further formed is also included in the scope of the present invention. In this configuration, one of the plurality of auxiliary capacitors corresponds to the first auxiliary capacitor in the present invention, and the other auxiliary capacitor corresponds to the second auxiliary capacitor in the present invention. The effect of the present invention that the thickness of the dielectric layer can be reduced while suppressing the leakage current is more remarkable as the number of auxiliary capacitors connected in series is electrically increased.

  In a desirable aspect of the present invention, the intermediate electrode layer and the first layer are made of the same material, and the first layer includes a plurality of portions formed such that each end portion faces the intermediate electrode layer. The second layer is formed so as to connect each of the plurality of portions. According to this configuration, each portion of the first layer and the second layer extend linearly, while the second electrode portion of the second layer overlaps the intermediate electrode layer, whereby the second auxiliary capacitance is Composed. Therefore, the space required for disposing each component compared to the configuration in which the intermediate electrode layer is formed at a position different from the auxiliary capacitance line in plan view (so as not to overlap the straight line on which the auxiliary capacitance line extends). Is reduced.

  The nonlinear element in the present invention typically includes a first conductive layer, an interlayer insulating layer, and a second conductive layer made of a conductive material having a resistivity lower than that of the first conductive layer. For example, the nonlinear element in the present invention is a two-terminal nonlinear element (so-called TFD element) formed by laminating a first conductive layer, an interlayer insulating layer, and a second conductive layer. In this configuration, if at least one of the intermediate electrode layer and the first layer is formed of the same material as the second conductive layer of the nonlinear element, the intermediate electrode layer or the first layer is formed in a process common to the second conductive layer. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with a structure in which each of these layers is formed of a separate material (that is, a structure in which each layer is formed in a separate process). The same effect can be obtained by a configuration in which at least one of the first electrode portion and the second layer is formed of the same material as the second conductive layer of the nonlinear element. Furthermore, if the first electrode portion and the second conductive layer of the nonlinear element are integrally formed under this configuration, the effects of simplifying the manufacturing process and reducing the manufacturing cost become more remarkable.

  Further, the dielectric layer and the insulating layer may be formed of the same material as the interlayer insulating layer of the nonlinear element. However, if the thicknesses of the dielectric layer and the insulating layer are equal to the thickness of the interlayer insulating layer, the intermediate electrode layer and the first electrode portion facing each other across the dielectric layer are also opposed across the dielectric layer. The intermediate electrode layer and the second electrode portion that act as non-linear elements, and as a result, current leakage in the first auxiliary capacitor and the second auxiliary capacitor can be significant. Further, if a wiring (for example, one of the scanning line and the data line) is formed so as to face the first layer with the insulating layer interposed therebetween, the portion where the first layer and the wiring face each other functions as a nonlinear element. Therefore, also in this case, current leakage becomes a problem. Therefore, in a desirable mode of the present invention, the film thickness of the dielectric layer and the insulating layer is made larger than the film thickness of the interlayer insulating layer of the nonlinear element. According to this aspect, current leakage through the dielectric layer and the insulating layer is suppressed.

  The electro-optical device according to the invention includes a first step of forming the intermediate electrode layer and the first layer of the auxiliary capacitance line by selectively removing the conductive film made of the first conductive material, and the intermediate electrode layer A second step of forming a dielectric layer covering the first layer and an insulating layer partially covering the first layer with the same material so as to have substantially the same film thickness; opposed to the intermediate electrode layer with the dielectric layer interposed therebetween; and a pixel electrode And a second layer that has a second electrode portion that faces the intermediate electrode layer across the dielectric layer and contacts a portion of the first layer that is not covered by the insulating layer. And a third step of forming by selectively removing the conductive film made of the second conductive material having a lower resistivity than the first conductive material. According to this manufacturing method, the intermediate electrode layer and the first layer of the auxiliary capacitance line, the dielectric layer and the insulating layer, and the first electrode portion and the second layer of the auxiliary capacitance line are formed in a common process. The manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the method of forming these layers in separate processes.

  In a specific aspect of this manufacturing method, the second step includes a step of removing a part of the insulating layer formed so as to cover the entire surface of the first layer. As described above, according to the configuration of the electro-optical device of the present invention, it is possible to reduce the film thickness of the insulating layer, so that the desired portion of the insulating layer can be accurately removed in the second step.

  In the first step and the third step, each layer forming the nonlinear element can also be formed collectively. That is, in a desirable aspect of the present invention, the first step forms the intermediate electrode layer, the first layer, and the first conductive layer in a lump by selectively removing the conductive film made of the first conductive material. The third step is a step of collectively forming the first electrode portion, the second layer, and the second conductive layer by selectively removing the conductive film made of the second conductive material. is there. According to this aspect, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the method in which the non-linear element and the other components are formed in separate steps.

  In another aspect of the present invention, the second step includes an insulating layer forming step of forming the dielectric layer, the insulating layer, and the interlayer insulating layer by anodizing the intermediate electrode layer, the first layer, and the first conductive layer. including. More specifically, the first step is a step of forming the first conductive layer so as to be continuous with the intermediate electrode layer or the first layer, and the insulating layer forming step is a step of forming the intermediate electrode layer, the first layer, and the first layer. A first oxidation step for anodizing the conductive layer at once, a second oxidation step for anodizing the intermediate electrode layer and the first layer, and separation for separating the first conductive layer from the intermediate electrode layer or the first layer Process. According to this aspect, the first conductive layer is anodized to form an interlayer insulating layer, and the intermediate electrode layer and the first layer are anodized to form a dielectric layer and an insulating layer. Compared with the case where it implements separately, the time which formation of each insulating layer can be shortened.

  In this embodiment, the order in which the first oxidation step, the second oxidation step, and the separation step are performed can be arbitrarily selected. For example, the intermediate electrode layer and the first layer are first anodized in the second oxidation step, and then the intermediate electrode layer, the first layer, and the first conductive layer are anodized in the first oxidation step, and then separated. A mode for carrying out the process may be adopted. Alternatively, the intermediate electrode layer, the first layer, and the first conductive layer are first anodized in the first oxidation step, and then the intermediate electrode layer and the first layer are anodized in the second oxidation step, and then separated. An embodiment in which the process is performed can also be adopted. However, when the second oxidation step is performed prior to the separation step as in these embodiments, it is necessary to take some measures so that the first conductive layer is not anodized during the second oxidation step. For example, the second oxidation step is performed after the first conductive layer is covered with a protective layer such as a resist. However, in this case, since a step of forming a protective layer is required, the manufacturing cost increases accordingly. On the other hand, according to the aspect in which the separation process is performed prior to the second oxidation process, the first conductive layer is anodized in the second oxidation process without covering the first conductive layer with the protective layer. Never happen. Therefore, it is desirable that the separation process is performed between the first oxidation process and the second oxidation process.

<A: Liquid crystal device>
First, an embodiment in which the present invention is applied to a liquid crystal device as an electro-optical material employing liquid crystal will be described. In the drawings shown below, the dimensions and scales of the elements are different from actual ones for convenience.

<A-1: Configuration of liquid crystal device>
FIG. 1 is a block diagram showing an electrical configuration of the liquid crystal device according to the present embodiment. This liquid crystal device D is an active matrix type display device using a two-terminal type non-linear element as a non-linear element for controlling the voltage applied to the liquid crystal, and extends in the X direction as shown in FIG. A plurality of scanning lines 21 and a plurality of data lines 13 extending in the Y direction orthogonal to the X direction and connected to the data line driving circuit 33. Among the plurality of scanning lines 21, the even-numbered scanning lines 21 counted from above in FIG. 1 are connected to the left scanning line drive circuit 31, while the odd-numbered scanning lines 21 counted from above in FIG. Connected to the scanning line driving circuit 31 on the right side. Furthermore, the liquid crystal device D according to the present embodiment includes a plurality (the same number as the scanning lines 21) of auxiliary capacitance lines 17 paired with each scanning line 21. Each of these auxiliary capacitance lines 17 is a wiring extending in the X direction similarly to each scanning line 21, and is electrically connected to the scanning line 21. Accordingly, each auxiliary capacitance line 17 has substantially the same potential as the scanning line 21 corresponding thereto.

  Pixels P are arranged at each position where the scanning line 21 and the data line 13 intersect. Therefore, these pixels P are arranged in a matrix in the display area Ad over the X direction and the Y direction. Each pixel P includes a two-terminal nonlinear element 14, a pixel capacitor (liquid crystal capacitor) G, a first auxiliary capacitor 18a, and a second auxiliary capacitor 18b. Among these, the two-terminal nonlinear element 14 is an element whose resistance value changes nonlinearly according to the voltage applied between both ends, and one end is connected to the data line 13. The pixel capacitance G is a capacitance in which a liquid crystal is interposed between the scanning line 21 and the pixel electrode formed for each pixel P, and is interposed between the other end of the two-terminal nonlinear element 14 and the scanning line 21. Has been. On the other hand, the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are connected in parallel to the pixel capacitor G in a state of being connected in series with each other. That is, the first auxiliary capacitor 18 a and the second auxiliary capacitor 18 b are interposed between the connection terminal N of the two-terminal nonlinear element 14 and the pixel capacitor G and the auxiliary capacitor line 17. The first auxiliary capacitor 18a and the second auxiliary capacitor 18b have substantially the same capacitance.

  FIG. 2 is an electrical equivalent circuit diagram of each pixel P. As shown in the figure, each pixel P includes a two-terminal nonlinear element 14 formed by connecting a capacitor Ctfd and a variable resistor Rtfd in parallel, and a pixel capacitor G formed by connecting a capacitor Clcd and a resistor Rlcd in parallel. Are connected in series between the data line 13 and the scanning line 21, and a first auxiliary capacitor 18a (capacitor Cs1) and a second auxiliary capacitor 18b (capacitor Cs2 (= Cs1)) are connected in parallel to the pixel capacitor G. It is understood as a connected circuit. In this configuration, since the voltage applied between the scanning line 21 and the data line 13 is capacitively divided by each capacitor, in order to apply a sufficient voltage to the two-terminal nonlinear element 14, the connection point N Accordingly, it is necessary to ensure a large capacitance ratio α (= C / Ctfd) between the capacitance C on the scanning line 21 side and the capacitance Ctfd of the two-terminal nonlinear element 14. According to the configuration in which the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are arranged in parallel with the pixel outline G as in the present embodiment, the capacitor C is a combined capacitor Cs of the first auxiliary capacitor 18a and the second auxiliary capacitor 18b. (= Cs1 / 2 = Cs2 / 2) and the added value (Clcd + Cs) of the capacitance Clcd, the first auxiliary capacitance 18a is compared with the capacitance ratio α (= Clcd / Ctfd) when these are not provided. Further, the capacity ratio α (= (Clcd + Cs) / Ctfd) is increased by the amount of the second auxiliary capacity 18b. As a result, a sufficient voltage is applied to the two-terminal nonlinear element 14, so that the two-terminal nonlinear element 14 is quickly and reliably changed to the on state, and the expected voltage is accurately applied to the pixel capacitor G. As a result, the display quality (particularly contrast) can be maintained at a high level.

  Next, FIG. 3 is a plan view showing the configuration of the liquid crystal device D, and FIG. 4 is a cross-sectional view showing the configuration of the display region Ad in the liquid crystal device D. As shown in these drawings, the liquid crystal device D includes a first substrate 10 and a second substrate bonded together so as to face each other via a frame-shaped sealing material 35 (a hatched portion in FIG. 3). And a substrate 20. The 1st board | substrate 10 and the 2nd board | substrate 20 are plate-shaped members which have light transmittances, such as glass and a plastics. As shown in FIG. 4, a liquid crystal 36 is sealed in a space surrounded by both substrates and the sealing material 35. Each scanning line 21 is formed on the surface of the second substrate 20 facing the liquid crystal 36. These scanning lines 21 are band-like electrodes made of a light-transmitting conductive material such as ITO (Indium Tin Oxide). On the other hand, each data line 13 is formed on the surface of the first substrate 10 facing the liquid crystal 36. In practice, a plurality of color filters and a black matrix that shields the gaps between the pixels P are formed on the surface of the first substrate 10 or the second substrate 20, and the surfaces of the first substrate 10 and the second substrate 20 are further formed. In FIG. 4, an alignment film for defining the alignment direction of the liquid crystal 36 is formed, but these elements are not shown in FIG. 4 and the following drawings.

  As shown in FIG. 3, the first substrate 10 has a larger outer dimension than the second substrate 20. A scanning line driving circuit 31 and a data line driving circuit 33 are formed by COG (Chip On Glass) technology in a region (hereinafter referred to as “projecting region”) 10 a that extends from the edge of the second substrate 20 in the first substrate 10. Has been implemented. An end portion of each data line 13 drawn to the overhanging region 10 a is connected to the data line driving circuit 33.

  FIG. 5 is a plan view showing the configuration of elements formed on the surface of the first substrate 10 facing the liquid crystal 36. Although only the elements related to one pixel P are shown in the figure, the other pixels P have the same configuration. As shown in FIGS. 3 to 5, a plurality of pixel electrodes 16 are arranged in a matrix in the display area Ad of the first substrate 10 in the X direction and the Y direction. Each pixel electrode 16 is a substantially rectangular electrode formed of a conductive material such as ITO similarly to the scanning line 21. Each scanning line 21 on the second substrate 20 (the outer shape is indicated by a two-dot chain line in FIG. 5) is opposed to one row of pixel electrodes 16 arranged in the X direction with the liquid crystal 36 interposed therebetween. The pixel capacitor G shown in FIG. 1 includes a pixel electrode 16, a scanning line 21 facing the pixel electrode 16, and a liquid crystal 36 sandwiched between the two. On the other hand, the data line 13 extends in the Y direction in the gap between the pixel electrodes 16. As shown in FIG. 5, a two-terminal nonlinear element 14 is disposed in the gap between each pixel electrode 16 and the data line 13 adjacent thereto.

6 is a cross-sectional view taken along line VI-VI in FIG. 5, and FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. As shown in FIGS. 5 to 7, the two-terminal nonlinear element 14 includes a long first conductive layer 141 that intersects the data line 13 with the X direction as a longitudinal direction, and the surface of the first conductive layer 141. Insulating layer 145 formed by anodizing (hereinafter referred to as “interlayer insulating layer”) 145 and second conductive layers 131 and 142 formed on the surface of interlayer insulating layer 145 so as to be separated from each other. Of these, the first conductive layer 141 is formed of various conductive materials such as a single metal such as tantalum (Ta) or an alloy containing tantalum as a main component and a metal such as tungsten (W). When the first conductive layer 141 is formed of tantalum, the interlayer insulating layer 145 obtained by anodizing the first conductive layer 141 is made of tantalum oxide (TaO _x ).

  The second conductive layer 131 corresponds to a portion of the data line 13 that overlaps the first conductive layer 141 with the interlayer insulating layer 145 interposed therebetween. On the other hand, the second conductive layer 142 extends in the Y direction so as to overlap the first conductive layer 141 with the interlayer insulating layer 145 interposed therebetween. As shown in FIG. 5, the end of the second conductive layer 142 is connected to a portion (hereinafter referred to as “connecting portion”) 143 extending in the Y direction toward the pixel electrode 16. The pixel electrode 16 described above is formed so as to overlap the tip of the connection portion 143 and is electrically connected to the second conductive layer 142 via the connection portion 143. Furthermore, a portion (hereinafter referred to as “first electrode portion”) 181 extending in the X direction is coupled to the base end portion of the connection portion 143. The first electrode portion 181 is a portion that functions as one electrode of the first auxiliary capacitor 18a. The second conductive layer 142, the connection portion 143, and the first electrode portion 181 are integrally formed by selectively removing a single conductive film. Further, the data line 13 including the second conductive layer 131 and the second conductive layer 142 (and the connection portion 143 and the first electrode portion 181) are made of a conductive material having a lower resistivity than the first conductive layer 141. It is formed. Examples of such a conductive material include simple metals such as chromium (Cr) and aluminum (Al), and alloys containing these as main components.

  The two-terminal nonlinear element 14 shown in FIG. 1 includes a first element 14a and a second element 14b. That is, as shown in FIG. 7, the first element 14a includes the second conductive layer 131 (data line 13), the interlayer insulating layer 145, and the first conductive layer 141 stacked in this order as viewed from the data line 13 side. It becomes the composition. Thus, since the first element 14a has a metal / insulator / metal sandwich structure, it exhibits diode switching characteristics in both positive and negative directions. On the other hand, the second element 14b has a configuration in which the first conductive layer 141, the interlayer insulating layer 145, and the second conductive layer 142 are stacked in this order when viewed from the first substrate 10 side. Therefore, the second element 14b exhibits a diode switching characteristic opposite to that of the first element 14a. As described above, the two-terminal nonlinear element 14 has a configuration in which two diodes are connected in series so as to be opposite to each other. Compared with the case of using only one), the current-voltage nonlinear characteristic is symmetric in both positive and negative directions. With this configuration, when the scanning line 21 is selected by supplying a scanning signal (horizontal scanning period), a two-terminal nonlinear element 14 is supplied by supplying a data signal corresponding to a desired gradation to the data line 13. When is turned on, charges corresponding to the data signal are accumulated in the pixel capacitor G, and the alignment direction of the liquid crystal 36 changes. In this way, by controlling the behavior of the liquid crystal 36 for each pixel P, a desired image is displayed. Therefore, the pixel capacity G is grasped as an element that is a minimum unit of the display image. On the other hand, since the two-terminal nonlinear element 14 is turned off after the charge is accumulated, the charge by the pixel capacitor G is held.

  As shown in FIG. 5, on the surface of the first substrate 10 facing the liquid crystal 36, the auxiliary capacitance line 17 extending in the X direction in the gap between the pixel electrodes 16 is formed. Here, FIG. 8 is a sectional view taken along line VIII-VIII in FIG. As shown in FIGS. 5 and 8, the auxiliary capacitance line 17 includes a first layer 171 and a second layer 172. Among these, the first layer 171 is composed of a plurality of portions arranged in the X direction at substantially the same interval as the horizontal width (width in the X direction) of the pixel electrode 16. As shown in FIGS. 5 and 8, each data line 13 extends in the Y direction so as to straddle the first layer 171 of the auxiliary capacitance line 17.

  The first layer 171 is a film body formed of the same material in the same process as the first conductive layer 141 of the two-terminal nonlinear element 14. Therefore, as shown in FIGS. 6 and 8, the first layer 171 is covered with an insulating layer 175 formed by anodic oxidation of the surface. However, the film thickness D 2 of the insulating layer 175 is larger than the film thickness D 1 of the interlayer insulating layer 145 of the two-terminal nonlinear element 14. Here, as shown in FIG. 5 and FIG. 8, the portion where the first layer 171 and the data line 13 of the auxiliary capacitance line 17 intersect is called metal / insulator / metal like the two-terminal nonlinear element 14. A laminated structure will be formed. However, since the insulating layer 175 covering the first layer 171 is thicker than the interlayer insulating layer 145, this portion does not function as a non-linear element, and thus electrical insulation between the auxiliary capacitance line 17 and the data line 13 is ensured. .

  On the other hand, the second layer 172 of the auxiliary capacitance line 17 is a film body formed for each pixel P in order to electrically connect each part of the first layer 171. As shown in FIG. The layers 171 extend in the X direction so as to connect portions adjacent to each other. More specifically, the second layer 172 extends over a portion from a position slightly away from the data line 13 to the pixel electrode 16 side to the vicinity of the data line 13 adjacent to the data line 13, and both ends thereof. The portion faces the end 171a of each portion of the first layer 171 with the insulating layer 175 interposed therebetween. As shown in FIGS. 5 and 8, a contact hole CH1 is formed in a portion of the insulating layer 175 covering the end 171a of each portion of the first layer 171. The contact hole CH1 is a hole formed by partially removing the insulating layer 175. The first layer 171 is exposed from the insulating layer 175 through the contact hole CH1. Both ends of the second layer 172 covering the insulating layer 175 enter the contact hole CH 1 and come into contact with the first layer 171. In this way, each portion of the first layer 171 is electrically connected by the second layer 172, whereby the auxiliary capacitance line 17 is configured.

  The second layer 172 is formed of the same material in the same process as the data line 13 and the second conductive layer 142. Therefore, the second layer 172 is made of a conductive material having a lower resistivity than the first layer 171. By using a material having a low resistivity as a part of the auxiliary capacitance line 17 in this way, the auxiliary capacitance line 17 is compared with a configuration including only the first layer 171 (for example, a configuration described in Patent Document 1). Thus, the resistance value of the auxiliary capacitance line 17 is reduced.

  As shown in FIG. 5, an intermediate electrode layer 183 is formed for each pixel P in the gap between the adjacent data lines 13. The intermediate electrode layer 183 is a substantially rectangular film body that overlaps the first electrode portion 181 and the second layer 172 of the auxiliary capacitance line 17 when viewed from the direction perpendicular to the surface of the first substrate 10, and is a two-terminal nonlinear element. The same material (for example, tantalum) is formed in the same process as the 14 first conductive layers 141. Here, FIG. 9 is a sectional view taken along line IX-IX in FIG. As shown in FIGS. 8 and 9, the intermediate electrode layer 183 is covered with an insulating layer (hereinafter referred to as “dielectric layer”) 185 formed by anodizing the surface thereof. The film thickness D3 of the dielectric layer 185 is substantially the same as the film thickness D2 of the insulating layer 175, and is therefore thicker than the interlayer insulating layer 145 of the two-terminal nonlinear element 14.

  As shown in FIGS. 5 and 9, the first electrode portion 181 overlaps the intermediate electrode layer 183 with the dielectric layer 185 interposed therebetween. Thus, the first auxiliary capacitor 18a is configured by the first electrode portion 181 and the intermediate electrode layer 183 facing each other with the dielectric layer 185 as a dielectric interposed therebetween. On the other hand, in the first layer 171 of the auxiliary capacitance line 17, end portions 171 a of adjacent portions face each other with the intermediate electrode layer 183 sandwiched in the X direction. Therefore, the second layer 172 formed so as to connect these portions has a portion (hereinafter referred to as “second electrode portion”) 182 that overlaps the intermediate electrode layer 183 with the dielectric layer 185 interposed therebetween. The second auxiliary capacitor 18b is configured by the second electrode portion 182 facing each other with the dielectric layer 185 as a dielectric interposed therebetween.

  Next, a configuration for electrically connecting the auxiliary capacitance line 17 and the scanning line 21 will be described. 10 is an enlarged plan view showing the vicinity of the end of the scanning line 21 (region A surrounded by a broken line in FIG. 3), and FIG. 11 is a cross-sectional view taken along the line XI-XI in FIG. 10 and 11, only the vicinity of the even-numbered scanning lines 21 is shown, but the odd-numbered scanning lines 21 have the same configuration.

  As shown in FIGS. 10 and 11, the first layer 171 of the auxiliary capacitance line 17 is drawn so as to reach a region of the first substrate 10 covered with the sealing material 35 (hereinafter referred to as “seal covering region”). It is turned. The end portion 17b reaching the seal coating region is wider than the other portion of the auxiliary capacitance line 17. A large number of contact holes CH2 are formed in the end portion 17b so as to penetrate the first layer 171 and the insulating layer 175 covering it. On the other hand, the wiring 41 (hereinafter referred to as “leading wiring”) 41 shown in FIGS. 3, 10, and 11 is formed from the end portion 411 positioned in the seal coating region, as shown in FIG. In the inner region, the end that extends in the Y direction along one side of the sealing material 35 and reaches the overhanging region 10 a is connected to the output end of the scanning line driving circuit 31. The routing wiring 41 is a wiring formed of the same material in the same process as the data line 13 and the second conductive layer 142. As shown in FIG. 10, the end portion 411 of the routing wiring 41 is formed so as to overlap the end portion 17 b of the auxiliary capacitance line 17 when viewed from the direction perpendicular to the plate surface of the first substrate 10. As shown in FIG. 5, the contact hole CH2 provided in the end portion 17b enters the contact hole CH2 and comes into contact with the inner peripheral surface of the first layer 171. With this configuration, conduction between the auxiliary capacitance line 17 and the routing wiring 41 is achieved. Further, as shown in FIG. 11, the end portion 411 of the lead wiring 41 is covered with a conductive layer 43. The conductive layer 43 is a film body formed of the same material in the same process as the pixel electrode 16. In FIG. 10, the conductive layer 43 is not shown in order to prevent the drawing from being complicated.

  On the other hand, as shown in FIGS. 10 and 11, the end of the scanning line 21 reaching the seal coating region on the second substrate 20 faces the end 411 of the routing wiring 41. As shown in FIG. 11, conductive particles 351 are interposed in the gap between the end of the scanning line 21 and the end 411 (more strictly speaking, the conductive layer 43) of the routing wiring 41. The conductive particles 351 are conductive particles dispersed in the sealing material 35, and function as a spacer for maintaining a constant gap (that is, a cell gap) between the first substrate 10 and the second substrate 20 as well as a scanning line. The scanning line 21 and the routing wiring 41 are electrically connected by contacting the end portion 21 and the conductive layer 43. With the above configuration, both the scanning line 21 and the auxiliary capacitance line 17 are connected to the scanning line drive circuit 31 via the routing wiring 41 (see FIG. 1). As a result, the auxiliary capacitance line 17 is substantially the same as the scanning line 21. It becomes the same potential.

  As described above, in the present embodiment, the auxiliary capacitance line 17 includes not only the first layer 171 but also the second layer 172 having a resistivity lower than that of the first layer 171. A reduction in display quality due to the resistance of the capacitor line 17 is suppressed. In addition, in the present embodiment, the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are formed by forming the first electrode part 181 and the second electrode part 182 so as to face one intermediate electrode layer 183. Therefore, there is an advantage that the film thickness of the dielectric layer 185 and the insulating layer 175 can be reduced while suppressing the leakage of current in the first auxiliary capacitor 18a and the second auxiliary capacitor 18b. This effect will be described in detail as follows.

  Here, as a configuration for interposing the auxiliary capacitance between the pixel electrode 16 and the auxiliary capacitance line 17, the configuration shown in FIG. 12 (hereinafter referred to as “proportional”) is also conceivable. In this configuration, the first layer 171 covered by the insulating layer 175 branches into a portion (hereinafter referred to as a “straight portion”) 71a linearly extending over the pixels P for one row and branches from this portion for each pixel P. Part (hereinafter referred to as “capacitance line side electrode part”) 71b. Further, the second conductive layer 142 of the two-terminal nonlinear element 14 is connected to a portion (hereinafter referred to as a “pixel capacitance side electrode portion”) 142a facing the capacitance line side electrode portion 71b with the insulating layer 175 interposed therebetween. . In this way, the storage capacitor 18 is configured by the capacitor line side electrode portion 71b and the pixel capacitor side electrode portion 142a facing each other with the insulating layer 175 as a dielectric interposed therebetween. On the other hand, a contact hole CH is formed in the insulating layer 175 covering the straight portion 71a of the first layer 171, and the second layer 172 extending in the X direction so as to cover the straight portion 71a is interposed via the contact hole CH. To the first layer 171. Also with this configuration, the resistance of the auxiliary capacitance line 17 is reduced by forming the second layer 172 with a conductive material having a low resistivity, and the voltage applied to the two-terminal nonlinear element 14 is sufficiently increased by the auxiliary capacitance 18. Can be secured.

  In this configuration, the contact hole CH is formed by selectively removing the insulating layer 175 covering the first layer 171 by the photolithography technique and the etching technique. Here, if the thickness of the insulating layer 175 is large, when the contact hole CH is formed, the insulating layer 175 cannot be completely removed by etching, or the resist that covers the insulating layer 175 is damaged during the etching. For example, a part that should not be removed may be removed. In such a case, there is a problem that conduction between the first layer 171 and the second layer 172 is hindered or the first layer 171 is disconnected, which may cause a decrease in yield. The same situation applies to the contact hole CH2 formed in the end portion 17b (see FIG. 10) of the auxiliary capacitance line 17. From the viewpoint of preventing such problems, it is desirable that the thickness of the insulating layer 175 be as small as possible so that it can be easily removed by etching.

  However, since the insulating layer 175 functioning as a dielectric of the auxiliary capacitor 18 and the insulating layer 175 covering the first layer 171 have substantially the same film thickness, when the film thickness of the insulating layer 175 is reduced, the capacitance line The gap between the side electrode portion 71b and the pixel capacitance side electrode portion 142a is reduced, and a problem that current leakage in the auxiliary capacitance 18 is likely to occur may occur. Here, FIG. 13 is an equivalent circuit diagram of the pixel P in which the resistance component of the insulating layer 175 is taken into consideration in the comparative configuration. As shown in the figure, the auxiliary capacitor 18 is grasped as an element in which a capacitor Cs and a resistor Rs are connected in parallel. When the film thickness of the insulating layer 175 is reduced, this resistance Rs decreases, and current leakage in the auxiliary capacitor 18 becomes particularly significant. As described above, it is difficult to achieve both improvement in accuracy of removing the insulating layer 175 and reduction of leakage current in the auxiliary capacitor 18 under the comparative configuration.

  On the other hand, in the present embodiment, the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are arranged by arranging the first electrode part 181 and the second electrode part 182 so as to face one intermediate electrode layer 183. Is configured. FIG. 14 is an equivalent circuit diagram of the pixel P in consideration of the resistance component of the insulating layer 175 in the configuration of the present embodiment. As shown in the figure, the first auxiliary capacitor 18a is grasped as an element in which a capacitor Cs1 and a resistor Rs1 are connected in parallel, and the second auxiliary capacitor 18b is an element in which a capacitor Cs2 and a resistor Rs2 are connected in parallel. As grasped. Under such a configuration, a case is assumed in which the film thicknesses of the dielectric layer 185 and the insulating layer 175 are halved, for example, from the viewpoint of improving the accuracy with which the insulating layer 175 is removed. In this case, both the resistance Rs1 and the resistance Rs2 are reduced compared to the resistance Rs shown in FIG. Here, the actual resistance Rs1 and resistance Rs2 are substantially proportional to the logarithmic value of the film thickness of the dielectric layer 185. To explain this in a very simplified manner, the resistance values of the resistance Rs1 and the resistance Rs2 are as follows. Approximately half of the resistance Rs. However, the total resistance value inserted in the path from the connection point N to the auxiliary capacitance line 17 is (Rs1 + Rs2), which is substantially equal to the resistance Rs. Therefore, the degree to which the current leaks is maintained equivalent to the proportional configuration. Thus, according to the present embodiment, the accuracy of manufacturing the contact holes CH1 and CH2 can be improved by reducing the film thickness of the dielectric layer 185 while suppressing the generation of leakage current.

  Incidentally, in the present embodiment, since the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are connected in series, the film thickness of the dielectric layer 185 is substantially the same as the film thickness of the insulating layer 175 in FIG. Assuming that, the capacitance from the connection point N to the auxiliary capacitance line 17 is reduced as compared with the configuration in which only one of the first auxiliary capacitance 18a and the second auxiliary capacitance 18b is arranged. However, considering that the film thickness of the dielectric layer 185 as the dielectric of the first auxiliary capacitor 18a and the second auxiliary capacitor 18b is reduced, the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are connected in series. That said, the overall capacity will not decrease significantly. This will be described in detail as follows.

  First, as illustrated in FIG. 13, a comparative configuration in which one auxiliary capacitor 18 is interposed between the connection point N and the auxiliary capacitor line 17 is assumed. Now, assuming that the area of each electrode of the auxiliary capacitor 18 is “S”, the distance between the electrodes is “d”, and the dielectric constant of the dielectric (insulating layer 175) is “ε”, the capacitance value Cs is “ε · S / d ". Next, in the configuration of the present embodiment shown in FIG. 14, the area of the first auxiliary capacitor 18a and the second auxiliary capacitor 18b is “S”, the dielectric constant of the dielectric layer 185 is “ε”, and the distance between the electrodes. Is “d / 2” which is half of “d”, the capacitance value Cs1 of the first auxiliary capacitor 18a and the capacitance value Cs2 of the second auxiliary capacitor 18b are “2ε · S / d”, respectively. In the present embodiment, since the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are connected in series, the combined capacity is “Cs1 / 2 = Cs2 / 2”, that is, “ε · S / d”. Eventually, it becomes equal to the capacitance value Cs of the auxiliary capacitor 18 shown in FIG. Thus, according to the present embodiment, there is an advantage that leakage current can be suppressed and the dielectric layer 185 can be thinned without reducing the capacitance connected in parallel to the pixel capacitance G.

<A-2: Manufacturing method>
Next, a manufacturing method of the liquid crystal device D will be described by paying attention to the manufacturing process of each pixel P. FIG. 15A to FIG. 15D are plan views showing the state of the pixel P in each step.

First, as shown in FIG. 15A, a conductive film 61 is formed on the surface of the first substrate 10. More specifically, the conductive film 61 is formed by patterning a tantalum thin film formed on the surface of the first substrate 10 by a film forming technique such as sputtering using a photolithography technique and an etching technique. The conductive film 61 is connected to the first layer 171 and the intermediate electrode layer 183 of the auxiliary capacitance line 17 extending in the X direction via a portion 611, and to the first layer 171 of the auxiliary capacitance line 17 and two terminals. The outer shape is such that the first conductive layer 141 of the type nonlinear element 14 is connected via the portion 612. In FIG. 15A, hatched portions 611 and 612 are portions to be removed in a later step. Further, as shown in FIG. 16, the conductive film 61 formed in this step includes a connecting portion 62 that extends in the Y direction and is connected to the first layers 171 of all the auxiliary capacitance lines 17. Yes. Note that an insulating film made of tantalum oxide (Ta ₂ O ₅ ) or the like may be formed on the surface of the first substrate 10 before the conductive film 61 is formed. If the conductive film 61 is formed with this insulating film as a base, the adhesion between the conductive film 61 and the first substrate 10 can be improved and the diffusion of impurities from the first substrate 10 to the conductive film 61 can be suppressed. .

  Next, the first anodic oxidation is performed on the surface of the conductive film 61. More specifically, the first conductive layer 141 and the first layer 171 are applied by immersing the first substrate 10 in the electrolytic solution and applying a predetermined voltage between the electrolytic solution and the connecting portion 62. The surface of the entire conductive film 61 including the intermediate electrode layer 183 is oxidized. In this step, the oxide film formed on the surface of the first conductive layer 141 becomes the interlayer insulating layer 145 of the two-terminal nonlinear element 14. Thereafter, as shown in FIG. 15B, a portion 612 connecting the first layer 171 and the first conductive layer 141 is removed by a photolithography technique and an etching technique. As a result, the first conductive layer 141 constituting the two-terminal nonlinear element 14 and the interlayer insulating layer 145 formed on the surface thereof are separated from the auxiliary capacitance line 17. As shown in FIG. 17, at this stage, the first layer 171 and the intermediate electrode layer 183 of all the auxiliary capacitance lines 17 remain connected to the connecting portion 62.

  Next, the second anodic oxidation is performed on the surface of the conductive film 61 by the same procedure as the first anodic oxidation. By this anodic oxidation, the oxidation of the surfaces of the first layer 171 and the intermediate electrode layer 183 further proceeds and the thickness of the oxide film increases. On the other hand, the oxidation of the first conductive layer 141 separated from the conductive film 61 does not proceed. By this process, the insulating layer 175 covering the first layer 171 and the dielectric layer 185 covering the intermediate electrode layer 183 (both insulating layers are integrated at this stage) have substantially the same film thickness. The film thickness is larger than that of the insulating layer 145.

  Thereafter, as shown in FIG. 15C, the portions 611 connecting the first layer 171 and the intermediate electrode layer 183 are removed by photolithography and etching techniques, and the first layer 171 and the intermediate electrode layer 183 are removed. And are separated. Further, in this step, as shown in FIG. 18, the first layer 171 of the auxiliary capacitance line 17 of each row is separated by removing the connecting portion 62 and the dielectric layer 185 covering the first layer 171 is removed. Of these, contact holes CH1 and CH2 are formed by selectively removing a portion located at the end 171a and a portion located at the end 17b of each first layer 171 (see FIG. 15C). . As described above, according to the present embodiment, the film thicknesses of the dielectric layer 185 and the insulating layer 175 are reduced as compared with the proportionality. Therefore, these insulating layers can be removed with high accuracy.

  Next, as shown in FIG. 15D, the first electrode portion 181 and the second layer 172 of the auxiliary capacitance line 17 are formed together with the data line 13 and the second conductive layer 142. More specifically, these elements are formed by patterning a chromium thin film formed on the surface of the first substrate 10 by a film forming technique such as sputtering using a photolithography technique and an etching technique. In this step, the data line 13 and the second conductive layer 142 are formed so as to cover the first conductive layer 141 and the interlayer insulating layer 145, whereby the first element 14a and the second element 14b are connected in series. A two-terminal nonlinear element 14 is obtained. Further, the first electrode portion 181 and the second electrode portion 182 of the second layer 172 are formed so as to cover the intermediate electrode layer 183 and the insulating layer 175, whereby the first auxiliary capacitance 18a connected in series with each other. The second auxiliary capacitor 18b is formed. Then, the pixel electrode 16 shown in FIG. 5 is formed by patterning an ITO thin film formed by a film forming technique such as sputtering.

  As described above, in the present embodiment, each layer of the auxiliary capacitance line 17 and each layer of the intermediate electrode layer 183 are formed of the same material in the same process as each layer of the two-terminal nonlinear element 14. Compared with the method of forming the auxiliary capacitance line 17 and the two-terminal nonlinear element 14 in separate steps, the manufacturing process can be simplified and the manufacturing cost can be reduced. Further, the entire surface of the conductive film 61 is oxidized by the first anodic oxidation, and the first layer 171 and the intermediate electrode layer 183 are oxidized by the second anodic oxidation performed thereafter, whereby the dielectric layer is formed. Since the insulating layer 175 and the insulating layer 175 are formed, the time required for forming these insulating layers is shortened as compared with the method in which the dielectric layer 185 and the insulating layer 175 are formed separately from the interlayer insulating layer 145.

<B: Modification>
Various modifications may be added to the above embodiment. An example of a specific modification is as follows. In addition, you may combine each aspect shown below suitably.

(1) In the above embodiment, the configuration in which the two-terminal nonlinear element 14 is connected to the data line 13 and the pixel capacitor G is connected to the scanning line 21 is illustrated. However, as shown in FIG. A configuration in which the capacitor G is connected to the data line 13 and the two-terminal nonlinear element 14 is connected to the scanning line 21 can also be adopted. In this case, the storage capacitor line 17 composed of the first layer 171 and the second layer 172 is connected to the data line 13, and the first storage capacitor 18 a and the second storage capacitor 18 b are connected to the connection point N and the storage capacitor line 17. It will be inserted between. In the above embodiment, the two-terminal nonlinear element 14 formed by connecting the first element 14a and the second element 14b in series is illustrated, but the two-terminal nonlinear element 14 composed of only one element is also employed. Can be done.

(2) In the above embodiment, the configuration in which each layer of the auxiliary capacitance line 17 and the intermediate electrode layer 183 is formed in the same process as each layer of the two-terminal nonlinear element 14 is illustrated. It may be formed of different materials in the step. Further, the specific forms of the first auxiliary capacitor 18a and the second auxiliary capacitor 18b are not questioned. For example, in the above-described embodiment, the configuration in which the first electrode portion 181 is integrally formed with the second conductive layer 142 is illustrated. However, these portions may be configured as separate members.

(3) In the above embodiment, the contact hole CH1 is formed in the insulating layer 175 that covers the first layer 171 of the auxiliary capacitance line 17, and the first layer 171 and the second layer 172 are electrically connected. The configuration for conducting the first layer 171 and the second layer 172 is not limited to this. For example, as shown in FIG. 20 (cross-sectional view corresponding to FIG. 8), the insulating layer 175 covering the edge surface 171b of the first layer 171 is removed, and the first layer 171b is in contact with the edge surface 171b exposed from this portion. A configuration in which two layers 172 are formed may also be employed.

(4) A method for making the film thickness of the interlayer insulating layer 145 of the two-terminal nonlinear element 14 different from the film thickness of the dielectric layer 185 and the insulating layer 175 is arbitrary. For example, in the process of FIG. 15A, the first conductive layer 141 is formed away from the first layer 171 or the intermediate electrode layer 183, and the first conductive layer 141, the first layer 171 and the intermediate electrode layer 183 are different. A method in which the thickness of each insulating layer is made different by anodizing separately under conditions may be employed. In addition, after the first anodic oxidation in the above embodiment, the first conductive layer 141 is covered with a resist, and then the second anodic oxidation is performed. Thereafter, the first conductive layer 141 is removed from the first layer 171. It is good also as a process to separate. In this case, since the oxidation of the first conductive layer 141 covered with the resist does not proceed during the second anodic oxidation, the film thickness of the interlayer insulating layer 145, the dielectric layer 185, and the like The thickness of the insulating layer 175 can be different. In the above embodiment, as illustrated in FIG. 15A, the configuration in which the first conductive layer 141 is connected to the first layer 171 is illustrated, but the first conductive layer 141 is used as the intermediate electrode layer 183. A connected configuration may also be employed.

(5) In the above-described embodiment, the two-terminal nonlinear element 14 is illustrated, but a three-terminal nonlinear element such as a TFT element may be used instead. In an active matrix type liquid crystal device using TFT elements, a plurality of scanning lines and a plurality of data lines are formed on the surface of a substrate (hereinafter referred to as “element substrate”) so as to intersect each other. A TFT element is formed at each intersection with the data line, and a substantially rectangular pixel electrode is connected to each TFT element. Further, a counter electrode is formed over substantially the entire surface of the substrate (hereinafter referred to as “counter substrate”) facing the element substrate with the liquid crystal sandwiched therebetween, facing the pixel electrode. A pixel capacity that is a minimum unit of a display image is configured by each pixel electrode, a counter electrode, and a liquid crystal sandwiched between the electrodes. When the scanning signal supplied to the scanning line becomes an active level, the TFT elements connected to the scanning line are turned on at the same time, and the voltage applied to each data line at this time is supplied to the pixel via the TFT element. When applied to the electrodes, charges corresponding to the intended gradation are accumulated in the pixel capacitor.

FIG. 21 is a cross-sectional view showing a configuration of elements formed on the element substrate in the liquid crystal device. In the figure, only elements relating to one pixel are shown, but the other pixels have the same configuration. A TFT element 54 shown in FIG. 21 is a so-called bottom gate nonlinear element, and includes a first conductive layer (gate electrode) 541 formed on the element substrate 11 and an interlayer insulating layer (covering the first conductive layer 541). Gate insulating layer) 545 and a semiconductor layer 543 facing the first conductive layer 541 with the interlayer insulating layer 545 interposed therebetween. Of these, the first conductive layer 541 is a portion branched from the scanning line, and is formed of a conductive material such as tantalum or an alloy thereof. The interlayer insulating layer 545 is a film formed so as to cover substantially the entire surface of the element substrate 11 and is formed of an insulating material such as silicon oxide (SiO _x ) or silicon nitride (SiN _x ). On the other hand, the semiconductor layer 543 is formed of a semiconductor material such as amorphous silicon or polysilicon.

A second conductive layer (drain electrode) 542a and a second conductive layer (source electrode) 542b are formed on the surface of the semiconductor layer 543 so as to be separated from each other. Of these, the second conductive layer 542a is a portion branched from the data line. On the other hand, the second conductive layer 542 b is formed to extend in a direction away from the TFT element 54. The second conductive layers 542a and 542b are formed of a conductive material (eg, chromium or aluminum) having a lower resistivity than the first conductive layer 541. In the gap between each of the second conductive layers 542a and 542b and the semiconductor layer 543, an n ^{+ -type} amorphous silicon layer 544 is interposed.

  On the other hand, an intermediate electrode layer 583 (corresponding to the intermediate electrode layer 183 in the above embodiment) is formed on the surface of the element substrate 11. The intermediate electrode layer 583 is a film body made of the same material (eg, tantalum) in the same process as the first conductive layer 541. The interlayer insulating layer 545 described above has a portion 585 (a portion corresponding to the dielectric layer 185 in the above embodiment; hereinafter referred to as “dielectric layer”) covering the intermediate electrode layer 583. Further, the second conductive layer 542 b includes a portion (hereinafter referred to as “first electrode portion”) 581 that overlaps the intermediate electrode layer 583 with the dielectric layer 585 interposed therebetween. As described above, the intermediate electrode layer 583 and the first electrode portion 581 are opposed to each other with the dielectric layer 585 serving as a dielectric interposed therebetween, so that the first auxiliary capacitor 58a is configured. 21 is formed of the same material in the same process as the second conductive layer 542b (including the first electrode portion 581) and the data line (including the second conductive layer 542a). And is overlapped with the intermediate electrode layer 583 with the dielectric layer 585 interposed therebetween. As described above, the second auxiliary capacitor 58b is configured by the second electrode portion 582 and the intermediate electrode layer 583 facing each other with the dielectric layer 585 serving as a dielectric interposed therebetween. The second electrode portion 582 is electrically connected to, for example, a counter electrode or a power supply line (particularly a ground line) on the counter substrate.

  The surface of the element substrate 11 on which these elements are formed is covered with an insulating layer 547 made of an insulating material such as silicon oxide or silicon nitride. The pixel electrode 56 constituting the pixel capacitor is provided on the surface of the insulating layer 547 and is electrically connected to the second conductive layer 542b (here, the first electrode portion 581) through the contact hole CH3 of the insulating layer 547. With the above structure, in the TFT element 54, the first conductive layer 541 that is a gate electrode is connected to a scanning line, the second conductive layer 542a that is a drain electrode is connected to a data line, and the second conductive layer 542b that is a source electrode is a pixel. It will be connected to the electrode 56. In the configuration of FIG. 21 as well, the first auxiliary capacitor 58a and the second auxiliary capacitor 58b connected in series with each other are arranged in parallel to the pixel capacitor as in the above embodiment. Therefore, it is possible to obtain an effect that the film thickness of the dielectric layer 585 can be reduced while suppressing current leakage in the first auxiliary capacitor 58a and the second auxiliary capacitor 58b. Note that the bottom gate TFT element 54 is illustrated here, but the present invention is similarly applied to a liquid crystal device using a top gate TFT element.

(6) Although the liquid crystal device D is illustrated in the above embodiment, the present invention is also applied to a device using an electro-optical material other than the liquid crystal. An electro-optical material is a material whose optical characteristics such as transmittance and luminance change when an electric signal (current signal or voltage signal) is supplied. For example, a display device using an OLED (Organic Light Emitting Diode) element such as an organic EL (Electro Luminescence) light-emitting polymer as an electro-optical material, or a liquid in which black fine particles and white fine particles are dispersed is sealed. An electrophoretic display device using microcapsules as an electro-optical material, a twist ball display using a twist ball painted in different colors for each region of different polarity, and a black toner as an electro-optical material The present invention can also be applied to various electro-optical devices such as a toner display or a plasma display panel using an inert gas such as neon or xenon as an electro-optical material.

<C: Electronic equipment>
Next, an electronic apparatus including the electro-optical device according to the invention as a display device will be described. FIG. 22 is a perspective view showing a configuration of a mobile phone having the liquid crystal device D according to the embodiment. As shown in this figure, a cellular phone 1200 includes a plurality of operation buttons 1202 operated by a user, a mouthpiece 1204 for outputting voice received from another terminal device, and voice transmitted to the other terminal device. In addition to the mouthpiece 1206 for inputting, a liquid crystal device D for displaying various images is provided.

  Note that, as an electronic device in which the liquid crystal device according to the present invention can be used, in addition to the mobile phone shown in FIG. 22, a notebook personal computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video. Examples include a recorder, a digital camera, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device equipped with a touch panel.

It is a block diagram which shows the electric constitution of the liquid crystal device which concerns on embodiment of this invention. 2 is an equivalent circuit diagram focusing on one pixel in the liquid crystal device. FIG. 2 is a plan view showing an overall configuration of the liquid crystal device. FIG. FIG. 3 is a cross-sectional view illustrating a configuration of a display region in the liquid crystal device. It is a top view which shows the structure of one pixel. It is sectional drawing seen from the VI-VI line in FIG. It is sectional drawing seen from the VII-VII line in FIG. It is sectional drawing seen from the VIII-VIII line in FIG. It is sectional drawing seen from the IX-IX line in FIG. It is a top view which expands and shows the part A in FIG. It is sectional drawing seen from the XI-XI line in FIG. It is a top view which shows the structure of one pixel in contrast. It is the equivalent circuit diagram which paid its attention to one pixel in contrast. FIG. 3 is an equivalent circuit diagram focusing on one pixel in the liquid crystal device. It is a top view which shows a mode that the electrically conductive film was formed. It is a top view which shows a mode that the 1st conductive layer was cut | disconnected among the electrically conductive films. It is a top view which shows a mode that the 1st layer and the intermediate | middle electrode layer were cut away. It is a top view which shows a mode that the 2nd layer of the 2nd conductive layer and the auxiliary capacity line was formed. It is a top view which shows a mode that the electrically conductive film was formed. It is a top view which shows a mode that the 1st conductive layer was cut | disconnected among the electrically conductive films. It is a top view which shows a mode that the 1st layer of each auxiliary capacitance line was cut away. It is a block diagram which shows the electric constitution of the liquid crystal device which concerns on a modification. It is sectional drawing which shows the structure for connecting a 1st layer and a 2nd layer among the liquid crystal devices which concern on a modification. It is sectional drawing which shows the structure of one pixel among the liquid crystal devices which concern on a modification. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device which concerns on this invention.

Explanation of symbols

D ... Liquid crystal device, P ... Pixel, 10 ... First substrate, 11 ... Element substrate, 13 ... Data line, 131 ... Second conductive layer, 14 ... Two-terminal nonlinear element (nonlinear element) , 14a... First element, 14b... Second element, 141, 541... First conductive layer, 145, 545... Interlayer insulating layer, 142, 542a, 542b. Part, 16, 56... Pixel electrode, 17... Auxiliary capacitance line, 171... First layer, 171 a .. end, 172... Second layer, 175 .. insulating layer, 18 a, 58 a. Auxiliary capacitance, 18b, 58b ... second auxiliary capacitance, 181,581 ... first electrode portion, 182,582 ... second electrode portion, 183,583 ... intermediate electrode layer, 185,585 ... dielectric layer , G: Pixel capacity, 20: Second substrate, 21: Scan line, 31: Scan Drive circuit 33... Data line drive circuit 35... Sealing material 351... Conductive particles 36. Liquid crystal 41. Lead-out wiring 54. TFT element (nonlinear element) 543 Semiconductor Layers, 547... Insulating layers.

Claims (15)

Scan lines and data lines extending in directions intersecting each other;
A nonlinear element having one end connected to one of the scanning line and the data line;
A pixel electrode connected to the other end of the non-linear element and facing the other of the scanning line and the data line with an electro-optic material interposed therebetween;
An intermediate electrode layer whose surface is covered by a dielectric layer;
A first electrode part connected to the pixel electrode and constituting a first auxiliary capacitor across the dielectric layer and facing the intermediate electrode layer;
An electro-optical device comprising: a second electrode portion that constitutes a second auxiliary capacitor facing the intermediate electrode layer with the dielectric layer interposed therebetween. A first layer partially covered by an insulating layer; and a second layer contacting a portion of the first layer not covered by the insulating layer, wherein the second layer is the second electrode portion. The electro-optical device according to claim 1, further comprising an auxiliary capacitance line including The intermediate electrode layer and the first layer are made of the same material,
The first layer includes a plurality of portions formed such that end portions thereof face each other across the intermediate electrode layer, and the second layer is formed so as to connect each of the plurality of portions. The electro-optical device according to claim 2. The nonlinear element includes a first conductive layer, an interlayer insulating layer, and a second conductive layer made of a conductive material having a lower resistivity than the first conductive layer,
The electro-optical device according to claim 2, wherein at least one of the intermediate electrode layer and the first layer is made of the same material as the first conductive layer of the nonlinear element. The nonlinear element includes a first conductive layer, an interlayer insulating layer, and a second conductive layer made of a conductive material having a lower resistivity than the first conductive layer,
The electro-optical device according to claim 2, wherein at least one of the first electrode portion and the second layer is made of the same material as the second conductive layer of the nonlinear element. The electro-optical device according to claim 5, wherein the first electrode portion is formed integrally with a second conductive layer of the nonlinear element. The nonlinear element includes a first conductive layer, an interlayer insulating layer, and a second conductive layer made of a conductive material having a lower resistivity than the first conductive layer,
The electro-optical device according to claim 2, wherein the dielectric layer and the insulating layer are made of the same material as the interlayer insulating layer of the nonlinear element. The electro-optical device according to claim 7, wherein film thicknesses of the dielectric layer and the insulating layer are larger than a film thickness of an interlayer insulating layer of the nonlinear element.   An electronic apparatus comprising the electro-optical device according to claim 1. A non-linear element having one end connected to one of the scanning lines and the data lines extending in a direction crossing each other, and the other of the scanning lines and the data lines connected to the other end of the non-linear element A method of manufacturing an electro-optical device including a pixel electrode facing a wiring,
A first step of forming the intermediate electrode layer and the first layer of the auxiliary capacitance line by selectively removing the conductive film made of the first conductive material;
A second step of forming the dielectric layer covering the intermediate electrode layer and the insulating layer partially covering the first layer with the same material in substantially the same film thickness;
A first electrode portion facing the intermediate electrode layer with the dielectric layer interposed therebetween and electrically connected to the pixel electrode; and a second electrode portion facing the intermediate electrode layer sandwiched with the dielectric layer, A conductive layer made of a second conductive material having a lower resistivity than the first conductive material is selectively used as a second layer that contacts a portion of the first layer that is not covered by the insulating layer. And a third step of forming by removing the electro-optical device. The method of manufacturing an electro-optical device according to claim 10, wherein the second step includes a step of removing a part of an insulating layer formed so as to cover the entire surface of the first layer. The nonlinear element includes a first conductive layer, an interlayer insulating layer, and a second conductive layer,
The first step is a step of forming the intermediate electrode layer, the first layer, and the first conductive layer in a lump by selectively removing the conductive film made of the first conductive material. ,
The third step is a step of forming the second electrode portion, the second layer, and the second conductive layer together by selectively removing the conductive film made of the second conductive material. The method for manufacturing an electro-optical device according to claim 10. The second step includes an insulating layer forming step of forming the dielectric layer, the insulating layer, and the interlayer insulating layer by anodizing the intermediate electrode layer, the first layer, and the first conductive layer. A method for manufacturing an electro-optical device according to claim 12. The first step is a step of forming the first conductive layer so as to be continuous with the intermediate electrode layer or the first layer,
The insulating layer forming step includes a first oxidation step in which the intermediate electrode layer, the first layer, and the first conductive layer are anodized together, and an anodization of the intermediate electrode layer and the first layer. The method of manufacturing an electro-optical device according to claim 13, comprising: a second oxidation step; and a separation step of separating the first conductive layer from the intermediate electrode layer or the first layer. The method of manufacturing an electro-optical device according to claim 14, wherein the separation step is performed between the first oxidation step and the second oxidation step.

Images