JP2005340424A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably provide a semiconductor device provided with an excellently reliable capacity element. <P>SOLUTION: The semiconductor device 200 is provided with a semiconductor substrate 220; a lower electrode 202 formed on the upper part of the semiconductor substrate 220; a capacity film 203 formed on the upper part of the lower electrode 202; an upper electrode 204 formed on the upper part of the capacity film 203, and having a rugged upper surface; and a conductive film 212 formed on the upper part of the upper electrode 204 having an upper surface flatter than the upper surface of the upper electrode 204, and having a melting point lower than that of the upper electrode 204. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

A ferroelectric memory is a memory that uses a ferroelectric as a capacitor (hereinafter referred to as FeRAM as appropriate), and uses polarization inversion of the ferroelectric for a memory holding function. Examples of the ferroelectric material used for FeRAM include Pb (Zr, Ti) O ₃ , PbTiO ₃ , and BaTiO ₃ . As a method for producing such a ferroelectric thin film, a vacuum deposition method, a sputtering method, a sol-gel method, a metal organic chemical vapor deposition method (MOCVD method), and the like have been studied.

  At this time, if the upper surface of the ferroelectric thin film is uneven, an upper electrode and a barrier film are formed when an upper electrode and a barrier film are formed on the upper surface of the ferroelectric thin film in order to apply an electric field to the ferroelectric thin film. The upper surface of the surface may also be uneven.

  On the other hand, as a conventional flattening method of the upper surface of the ferroelectric thin film, there is one described in Patent Document 1. This document describes a technique of flattening after irradiating the upper surface of a ferroelectric thin film with an excimer laser and rapidly heating and quenching after the ferroelectric film is formed (before the upper electrode is formed).

Further, as a conventional flattening method of the upper surface of the ferroelectric thin film, there is one described in Patent Document 2. This document describes a method of flattening irregularities on the upper surface of a ferroelectric thin film by etching.
JP 2002-334970 A Japanese Patent Laid-Open No. 7-038003

  However, the prior art described in the above document has room for improvement in the following points.

  First, as a method for flattening the unevenness of the upper surface of the ferroelectric thin film, Patent Document 1 discloses that the upper surface of the ferroelectric thin film is irradiated with an excimer laser to be rapidly heated and rapidly cooled, whereby the ferroelectric thin film It is described that the upper surface of the substrate can be flattened. However, in the method described in Patent Document 1, it is necessary to use a new dedicated apparatus for excimer laser irradiation, and the number of processes increases, so there is room for improvement in terms of manufacturing stability. In this method, the upper surface of the ferroelectric thin film is exposed to an excimer laser. For this reason, since a damaged layer is formed on the upper surface of the ferroelectric thin film, there is room for improvement in terms of electrical characteristics of the ferroelectric thin film.

  Second, as a method for flattening the unevenness on the surface of the ferroelectric thin film, Patent Document 2 describes that the unevenness on the upper surface of the ferroelectric thin film can be flattened by etching. However, in the method described in Patent Document 2, the upper surface of the ferroelectric thin film is exposed to plasma generated by a dry etching apparatus. For this reason, a damage layer may be formed on the upper surface of the ferroelectric thin film, and the electrical characteristics of the ferroelectric thin film may deteriorate. In addition, in this method, the production stability may be lowered due to an increase in the number of steps.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to stably provide a semiconductor device including a capacitive element having excellent reliability.

  According to the present invention, a semiconductor substrate, a lower electrode provided on the upper portion of the semiconductor substrate, a capacitive film provided on the upper portion of the lower electrode, and an upper surface provided with irregularities on the upper portion of the capacitive film. There is provided a semiconductor device comprising: an upper electrode having an upper electrode; and a conductive film that is provided on the upper electrode and has an upper surface that is flatter than the upper surface of the upper electrode and has a lower melting point than the upper electrode.

  According to this configuration, since the conductive film having the upper surface flatter than the upper surface of the upper electrode is provided, variations in electrical characteristics and dimensions of the conductive film and members formed on the conductive film are reduced, and reliability is improved. A semiconductor device including a capacitive element that is superior to the above is stably provided.

  In addition, according to the present invention, a step of forming a lower electrode on an upper portion of a semiconductor substrate, a step of forming a capacitive film on the upper portion of the lower electrode, and an upper electrode having an upper surface with irregularities on the upper portion of the capacitive film. Forming a conductive film having an upper surface with irregularities on the upper electrode and having a melting point lower than that of the upper electrode; heat-treating the upper surface of the conductive film; And a step of planarizing the upper electrode from the upper surface thereof.

  According to this method, the upper surface of the conductive film is heat treated, and the upper surface of the conductive film is flattened more than the upper surface of the upper electrode. Thus, a semiconductor device including a capacitive element with reduced reliability and excellent reliability can be stably provided.

  As mentioned above, although the structure of this invention was demonstrated, what combined these structures arbitrarily is effective as an aspect of this invention. Moreover, what converted the expression of this invention into the other category is also effective as an aspect of this invention.

  For example, the capacitive element configured by the lower electrode, the capacitive film, the upper electrode, and the like may be a capacitive element having a planar capacitor structure, but is not particularly limited. For example, a capacitive element having a stacked capacitor structure or the like may be used.

  Even in such a case, irregularities may occur on the upper surfaces of the capacitor film and the upper electrode. At this time, if a conductive film having a flattened upper surface is provided above the upper electrode in the stacking direction, variations in electrical characteristics and dimensions of the conductive film and members formed on the conductive film are reduced, and reliability is improved. A semiconductor device including a capacitive element with excellent properties is stably provided.

  According to the present invention, since the conductive film having the upper surface flatter than the upper surface of the upper electrode is provided, a semiconductor device including a capacitive element with excellent reliability is stably provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a cross-sectional view schematically showing the configuration of the ferroelectric capacitor according to the embodiment.

  The semiconductor device 200 according to the present embodiment includes an interlayer insulating film 220 in which a tungsten plug 215 is embedded on a semiconductor substrate (not shown), a lower electrode 202 provided on the interlayer insulating film 220, and a lower electrode 202. The capacitor film 203 is provided on the upper portion of the capacitor film 203, and the upper electrode 204 is provided on the capacitor film 203 and has an upper surface with unevenness. The semiconductor device 200 further includes a conductive film 212 having an upper surface flatter than the upper surface of the upper electrode 204 and having a melting point lower than that of the upper electrode 204 above the upper electrode 204.

  In the semiconductor device 200, an upper electrode 204 is formed on a capacitor film 203 made of a ferroelectric capacitor film or the like, and a conductive film 212 made of an AlCu film or the like is further formed thereon. Then, the upper surface of the conductive film 212 is planarized by heating by a method such as reflow. As described above, the planarization of the upper surface of the conductive film 212 reduces variation in electrical characteristics and dimensions of the conductive film 212 and members formed on the conductive film 212, and includes a highly reliable capacitor element. The apparatus 200 can be obtained stably.

  Here, in order to planarize the upper surface of the conductive film 212, it is effective to heat-treat the upper surface of the conductive film 212 for a specific time under a specific temperature condition. This temperature condition can be, for example, 300 ° C. or higher, and particularly preferably 420 ° C. or higher. Moreover, this temperature condition can be 500 degrees C or less, for example, Most preferably, it is 480 degrees C or less. Within these temperature ranges, the upper surface of the conductive film 212 can be sufficiently planarized while suppressing the influence on the characteristics of the semiconductor device 200.

  Moreover, said heating time can be made into 1 minute or more, for example, Most preferably, it is 3 minutes or more. Moreover, this heating time can be made into 10 minutes or less, for example, Especially preferably, it is 8 minutes or less. When the heating time is within these ranges, the upper surface of the conductive film 212 can be sufficiently flattened while suppressing the influence on the characteristics of the semiconductor device 200.

  The conductive film 212 can be a metal film containing Al, such as an AlCu film. According to this configuration, since the melting point of the conductive film 212 is lower than the melting point of the upper electrode 204 made of a normal material, it can be easily flattened by heating the upper surface of the conductive film 212 by a method such as reflow. . In this manner, when the conductive film 212 has a structure in which the top surface is planarized by heat treatment, variations in electrical characteristics and dimensions of the conductive film 212 and members formed over the conductive film 212 are reduced.

  The surface roughness maximum height Rmax of the upper surface of the conductive film 212 is, for example, 30 nm or less, and preferably 10 nm or less. When the surface roughness maximum height Rmax on the upper surface of the conductive film 212 is within these ranges, variations in electrical characteristics and dimensions of the conductive film 212 and members formed on the conductive film 212 are further reduced. Here, Rmax means the maximum height defined by JIS B 0601 (2001). Further, Rmax of the upper surface of the conductive film 212 can be measured using an AFM (atomic force microscope) or the like.

  The upper electrode 204 can include one or more metal elements selected from the group consisting of Pt, Ir, and Ru. According to this configuration, since the conductivity of the upper electrode 204 is improved, the electrical characteristics are improved. Since these materials have high melting points, changes in characteristics and structure of the upper electrode 204 can be suppressed even when the upper surface of the conductive film 212 is heated by a method such as reflow. In addition, since these materials have weak affinity with oxygen, it is possible to suppress a decrease in spontaneous polarization characteristics of the capacitor film 203 due to oxygen deficiency.

  The surface roughness maximum height Rmax on the upper surface of the upper electrode 204 is, for example, 50 nm or more, and may be 100 nm or more. As described above, even when the surface of the upper electrode 204 has a large unevenness, the upper surface of the conductive film 212 is heated and planarized by a method such as reflow to thereby form the conductive film 212 and a member formed thereon. Variations in electrical characteristics and dimensions such as are further reduced. For this reason, even if the unevenness of the upper surface of the upper electrode 204 is large, the semiconductor device 200 including the capacitive element with excellent reliability can be stably obtained.

The capacitor film 203 can include an oxide of one or more metal elements selected from the group consisting of Pb, Zr, Ti, and Ba. For example, a configuration including Pb (Zr, Ti) O ₃ (PZT), (Ba, Sr) TiO ₃ (BST), SrTiO ₃ (ST), and the like can be employed. By using these materials, the capacitor film 203 made of a ferroelectric thin film can be formed, so that the capacitance of the capacitor can be improved.

  The capacitor film 203 may be formed by a CVD method. In particular, when the capacitor film 203 is made of a PZT thin film, the use of a normal sol-gel method or sputtering method increases the necessity of heating at 600 ° C. or higher in order to obtain a good PZT thin film. However, when the PZT thin film is formed at such a high temperature, the metal wiring may be disconnected or the resistance may be increased. Therefore, if the film is formed at a low temperature of about 450 ° C. like the CVD method, the influence on the metal wiring can be suppressed. For example, a PZT thin film can form a film having a good crystal state (crystal grain size of about 50 nm or more) in a temperature range of 350 ° C. to 500 ° C. by a CVD method.

  The surface roughness maximum height Rmax on the upper surface of the capacitive film 203 is, for example, 50 nm or more, and may be 100 nm or more. As described above, when the surface unevenness on the upper surface of the capacitor film 203 is large, the surface unevenness on the upper surface of the upper electrode 204 is similarly increased, but the upper surface of the conductive film 212 is heated and flattened by a method such as reflow. As a result, variations in electrical characteristics and dimensions of the conductive film 212 and the members formed thereon are further reduced. For this reason, even if the surface roughness of the upper surface of the capacitor film 203 is large, the semiconductor device 200 including the capacitor element with excellent reliability can be stably obtained.

  The semiconductor device 200 may further include a barrier film 205 containing Ti or TiN between the upper electrode 204 and the conductive film 212. If the barrier film 205 is provided, the mutual reaction and mutual diffusion between the Pt element, Ir element, Ru element, and the like of the upper electrode 204 and the Al element, Cu element, and the like of the conductive film 212 can be suppressed.

  The semiconductor device 200 may further include an upper contact 211 connected to the conductive film 212. In the semiconductor device 200, since the upper surface of the conductive film 212 is flattened, the contact property between the conductive film 212 and the upper contact 211 is good. For this reason, in the semiconductor device 200 that constitutes a ferroelectric memory (Fe-RAM) or the like using the capacitor film 203 made of a ferroelectric as a capacitor, a leak current is suppressed and stable electrical characteristics can be obtained.

  The configuration of this embodiment has been described above, but any combination of these configurations is also effective as an aspect of this embodiment. Moreover, what converted the expression of this embodiment into another category is also effective as an aspect of this embodiment.

  For example, in the above embodiment, the upper surface of the conductive film 212 is heated and flattened by reflow, but any reflow method can be used.

  Further, even if a heating method other than reflow is used, any method can be used as long as the upper surface of the conductive film 212 can be efficiently heated. Even in this case, since the upper surface of the conductive film 212 can be sufficiently flattened, variations in electrical characteristics and dimensions of the conductive film 212 and members formed thereon are reduced.

  Hereinafter, although an example explains the present invention still more using a drawing, the present invention is not limited to these. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

<Example 1>
FIG. 2A to FIG. 5K are process cross-sectional views for explaining the outline of the manufacturing method of the ferroelectric capacitor of this example.

First, a barrier film 1 made of Ti, TiN or the like is formed on an interlayer insulating film 14 in which a tungsten plug 15 on a silicon substrate (not shown) is embedded. A lower electrode 2 made of a noble metal such as Pt, Ir, or Ru or a conductive oxide film such as IrO ₂ or RuO _{2 is} formed thereon by a sputtering method or other methods (FIG. 2A).

Next, a ferroelectric thin film 3 is formed on the lower electrode 2. As the ferroelectric thin film 3, there are Pb (Zr, Ti) O ₃ , PbTiO ₃ , BaTiO ₃ and the like. When formed by the MOCVD method or the like as in the conventional technique, crystal grains grow in the film by crystallization. Therefore, irregularities are generated on the surface of the ferroelectric thin film 3 (FIG. 2B).

  Next, TiN is formed on the ferroelectric thin film 3 as the upper electrode 4 and the barrier film 5 by the same method as the lower electrode. At this time, the TiN surface as the barrier film 5 is also uneven as in the ferroelectric thin film (FIG. 2C).

  Next, an AlCu film 12 is formed on the barrier film 5 made of TiN by a sputtering method, and reflow is performed at 450 ° C. for 5 minutes to flatten the surface of the AlCu film 12. TiN to be a barrier film 13 is further formed on the planarized AlCu film 12. At this time, the surface of the barrier film 13 made of TiN is flat (FIG. 3D).

  Subsequently, as will be described later, when dry etching is performed, it is difficult to obtain an etching rate-to-resist selection ratio as in the prior art, and therefore it is desirable to form the oxide film hard mask 6 as a mask ( FIG. 3 (e)). Thereafter, the lower electrode 2, the ferroelectric thin film 3, the upper electrode 4, and the AlCu film 12 are processed by an etching process to form a capacitor structure. In dry etching, it is possible to etch each film with a separate apparatus or with one apparatus. Further, the etching gas is changed as appropriate in accordance with the material of the film to be etched (FIGS. 3F and 4G).

  Next, after forming an interlayer insulating film 8 on the ferroelectric capacitor (FIG. 4H), the interlayer insulating film 8 is planarized by CMP or the like (FIG. 4I), and a resist mask is formed by a dry etching process. Using 9 as an etching mask, a contact hole is formed above the capacitor (FIG. 5 (j)). Since the upper surface of the AlCu film 12 is flattened by the deposition and reflow of the AlCu film 12 at the upper part of the capacitor at this time, the upper surfaces of other films formed above the AlCu film 12 are also flattened. Become. Thereafter, a metal contact plug 11 such as tungsten is buried (FIG. 5 (k)) with a barrier film 10 such as TiN provided on the side wall of the contact hole, and a metal wiring (not shown) is formed thereon.

  According to the present embodiment, the AlCu film 12 is formed on the ferroelectric thin film 3 where the irregularities are formed, and the upper surface of the AlCu film 12 is planarized by reflow. As a result, in the upper part of the capacitor structure, other films formed on the AlCu film 12 are flattened and unevenness is suppressed.

  Specifically, as described above, the maximum surface roughness height Rmax of the upper surface of the AlCu film 12 after the heat treatment by reflow is, for example, 30 nm or less, and preferably 10 nm or less. When the surface roughness maximum height Rmax on the upper surface of the AlCu film 12 is within these ranges, the variation in electrical characteristics and dimensions of the AlCu film 12 and the members formed thereon are further reduced. Here, Rmax means the maximum height defined by JIS B 0601 (2001). Further, Rmax of the upper surface of the AlCu film 12 can be measured using an AFM (atomic force microscope) or the like.

  In this embodiment, the thickness of the AlCu film 12 may be, for example, 50 nm or more, particularly preferably 100 nm or more. The film thickness may be, for example, 300 nm or less, and particularly preferably 200 nm or less. If this film thickness is within these ranges, the AlCu film 12 is heated by reflow while satisfying the demand for miniaturization of the semiconductor device, thereby relaxing the irregularities on the upper surface of the upper electrode 4 and the upper surface of the AlCu film 12. Can be sufficiently flattened.

  Since the semiconductor device of the present embodiment has the above-described configuration, the metal contact plug 11 is connected to the AlCu film 12 having a flat upper surface when a contact hole is formed by etching. For this reason, since the contact property between the metal contact plug 11 and the AlCu film 12 is improved, the leakage current is suppressed and stable electrical characteristics are realized. In addition, the need for a high selection ratio between TiN of the barrier film 5 and the interlayer insulating film 8 and the oxide film hard mask 6 is also reduced.

  In addition, the AlCu film 12 can have a sufficient selection ratio with the interlayer insulating film 8 in a dry etching process when forming a contact hole. For this reason, since the etching gas is blocked in the AlCu film 12, it is possible to suppress the upper electrode 4 from being scraped by the etching gas. Therefore, the necessity of using an expensive dry etching apparatus that generates a plasma of medium density or higher at low pressure is reduced. Therefore, the contact hole can be etched with sufficient accuracy by an inexpensive dry etching apparatus such as a commonly used RIE method.

  As described above, according to the present embodiment, the AlCu film 12 is produced when a semiconductor device including a capacitor element having a configuration of TiN / Al—Cu / TiN / Ru / PZT / Ru / Ti / TiN / Ti is manufactured. Can be flattened. Specifically, as a method of reducing the unevenness of the surface after the ferroelectric thin film 3 is formed, after the upper electrode 4 is formed, Al (or an alloy containing Al as a main component) is formed thereon. By reflowing, the upper surface of the conductive film containing Al is flattened. For this reason, in a ferroelectric memory (Fe-RAM) using a ferroelectric as a capacitor, it is possible to obtain stable electrical characteristics in which leakage is suppressed.

<Example 2>
The manufacturing method of the ferroelectric capacitor according to the second embodiment is basically the same as the manufacturing method of the ferroelectric capacitor according to the first embodiment, but differs in the following points.

  FIG. 6 is a process cross-sectional view illustrating the manufacturing method of the ferroelectric capacitor according to this example in the order of processes. In Example 2, similarly to Example 1, an AlCu film 12 is formed and reflowed (FIG. 6A). Thereafter, the AlCu film 12 is thinned by etching the entire surface (FIG. 6B).

  Then, TiN of the barrier film 13 is formed thereon (FIG. 6C). Thereafter, in the same manner as in Example 1, the oxide hard mask 6 is used as a mask, and the lower electrode 2, the ferroelectric thin film 3, the upper electrode 4, and the AlCu film 12 are sequentially dry etched when forming the capacitor structure. To do.

  The film thickness of the AlCu film 12 after being thinned by etching can be, for example, 100 nm or less, and particularly preferably 50 nm or less. Moreover, this film thickness can be 10 nm or more, for example, Most preferably, it is 30 nm or more. If the film thickness after this etching is within these ranges, the AlCu film 12 can be stably formed while side etching of the AlCu film 12 is sufficiently suppressed.

  Also in the present embodiment, as in the case of the first embodiment, when manufacturing a semiconductor device including a capacitive element having a configuration such as TiN / Al-Cu / TiN / Ru / PZT / Ru / Ti / TiN / Ti. The upper surface of the AlCu film 12 can be planarized. Specifically, as a method of reducing the unevenness of the surface after the ferroelectric thin film 3 is formed, after the upper electrode 4 is formed, Al (or an alloy containing Al as a main component) is formed thereon. By reflowing, the upper surface of the conductive film containing Al is flattened. For this reason, in a ferroelectric memory (Fe-RAM) using a ferroelectric as a capacitor, it is possible to obtain stable electrical characteristics in which leakage is suppressed.

  Further, in the method for manufacturing a ferroelectric capacitor according to the present embodiment, as shown in FIG. 6B, the thickness of the AlCu film 12 is reduced, so that the side of the AlCu film 12 is not removed during the dry etching. Etching can be suppressed. Further, by suppressing the side etch of the AlCu film 12, the electrical characteristics of the AlCu film 12 are improved, and a specific effect that the reliability of the semiconductor device is further improved is obtained.

<Comparative Example 1>
FIG. 7A to FIG. 9I are schematic cross-sectional views for explaining a method for manufacturing a ferroelectric capacitor having a structure not including a conductive film having a flat upper surface.

First, a barrier film 101 made of Ti, TiN or the like is formed on an interlayer insulating film 114 formed with a W plug 115 on a silicon substrate (not shown). A lower electrode 102 made of a noble metal such as Pt, Ir or Ru or a conductive oxide film such as IrO ₂ or RuO _{2 is} formed thereon by sputtering or other methods (FIG. 7A).

Next, a ferroelectric thin film 103 is formed on the lower electrode 102. As a material of the ferroelectric thin film 103, Pb (Zr, Ti) O ₃ , PbTiO ₃ , BaTiO ₃ or the like is used. Further, as a method for manufacturing the ferroelectric thin film 103, a vacuum deposition method, a sputtering method, a sol-gel method, a metal organic chemical vapor deposition method (MOCVD method), or the like is used.

  As such a method, the ferroelectric thin film 103 is obtained by crystallizing the film during film formation by raising the substrate temperature at the time of film formation, etc. There are two methods for obtaining the body thin film 103. In any case, since crystal grains grow in the film by crystallization, the surface of the ferroelectric thin film 103 is uneven by either of the above methods (FIG. 7B).

  Next, the upper electrode 104 is formed on the ferroelectric thin film 103 by the same method as the lower electrode 102. At this time, as will be described later, a barrier film such as TiN is formed on the upper electrode in order to prevent the upper electrode 104 from being scraped by the material on the upper electrode 104 in the resist 107 peeling step after the oxide film hard mask 106 is formed. It is desirable to form 105 (FIG. 7C).

  Subsequently, as will be described later, when dry etching is performed, it is desirable to form an oxide film hard mask 106 as a mask because a selection ratio of etching rate to resist 107 cannot be obtained. Then, a resist 107 having a predetermined pattern is formed on the oxide film hard mask 106, and an oxide film hard mask pattern is formed by etching (FIG. 8D). Note that the resist 107 is removed after the etching.

  Thereafter, the barrier film 101, the lower electrode 102, the ferroelectric thin film 103, and the upper electrode 104 are processed by etching using the oxide film hard mask 106 as a mask to form a capacitor structure (FIG. 8E).

  Next, an interlayer film 108 is formed on the ferroelectric capacitor (FIG. 8F). Thereafter, the upper surface of the interlayer film 108 is flattened by CMP or the like (FIG. 9G).

  Next, a resist mask 109 having a predetermined pattern is formed on the interlayer film 108. Then, using the resist mask 109 as a mask, a contact hole is formed in the upper portion of the capacitor by etching (FIG. 9H). Thereafter, a metal contact plug 111 such as tungsten (W) is buried in the contact hole, and a metal wiring (not shown) or the like is formed on the upper portion (FIG. 9 (i)).

  At this time, as shown in FIG. 7B, if the upper surface of the ferroelectric thin film 103 is uneven, an upper electrode 104 is formed on the upper surface of the ferroelectric thin film 103 in order to apply an electric field to the ferroelectric thin film 103. When the barrier film 105 is formed, the upper surfaces of the upper electrode 104 and the barrier film 105 may be uneven as shown in FIG.

  Here, in the technique according to the comparative example shown in FIG. 7A to FIG. 9I, as described above, the electric field is applied to the ferroelectric thin film 103 on the upper surface of the ferroelectric thin film 103. When the upper electrode 104 is formed, if the upper surface of the ferroelectric thin film 103 is uneven, the upper surfaces of the upper electrode 104 and the barrier film 105 may also be uneven.

  At this time, as shown in FIG. 9H, after the next interlayer insulating film 108 is formed, an etching residue for opening the contact hole reaching the barrier film 105 on the upper electrode 104 is made to eliminate the etching residue in the recess. Then, the amount of abrasion of the barrier film 105 at the convex portion on the upper surface of the barrier film 105 is increased. Therefore, compared with the case of the embodiment, the amount of shaving of the barrier film 105 at the convex portion is large, and if the contact hole penetrates the barrier film 105 at the convex portion, a part of the upper electrode 104 is damaged by etching. There is a case to receive.

  When a part of the upper electrode 104 is damaged in this manner, the contact property between the upper contact made of the metal 111 such as W and the capacitor and the capacitor is deteriorated as compared with the case of the embodiment. The reliability of the semiconductor device is lowered.

  On the other hand, in order to suppress damage to the upper electrode 104, it is necessary to perform etching under a condition having a high selection ratio between the interlayer insulating film 108 and the oxide film hard mask 106 and the barrier film 105. For this reason, compared with the case of an Example, the necessity of using the expensive dry etching apparatus which produces | generates a plasma more than a medium density at low pressure increases, and the technique of a dry etching process becomes difficult, and manufacturing stability falls. .

  In the above, this invention was demonstrated based on the Example. It is to be understood by those skilled in the art that this embodiment is merely an example, and that various modifications are possible and that such modifications are within the scope of the present invention.

It is sectional drawing which shows typically the structure of the ferroelectric capacitor which concerns on embodiment. 6 is a process cross-sectional view illustrating the manufacturing method of the ferroelectric capacitor according to Example 1. FIG. 6 is a process cross-sectional view illustrating the manufacturing method of the ferroelectric capacitor according to Example 1. FIG. 6 is a process cross-sectional view illustrating the manufacturing method of the ferroelectric capacitor according to Example 1. FIG. 6 is a process cross-sectional view illustrating the manufacturing method of the ferroelectric capacitor according to Example 1. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a ferroelectric capacitor according to Example 2. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a ferroelectric capacitor according to Comparative Example 1. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a ferroelectric capacitor according to Comparative Example 1. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a ferroelectric capacitor according to Comparative Example 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Barrier film 2 Lower electrode 3 Ferroelectric thin film 4 Upper electrode 5 Barrier film 6 Oxide film hard mask 7 Resist mask 8 Interlayer insulation film 9 Resist mask 10 Barrier film 11 Tungsten plug 12 AlCu film 13 Barrier film 14 Interlayer insulation film 15 Tungsten Plug 101 Barrier film 102 Lower electrode 103 Ferroelectric thin film 104 Upper electrode 105 Barrier film 106 Oxide film hard mask 107 Resist 108 Interlayer film 109 Resist mask 110 Barrier layer 111 Metal 114 Interlayer insulating film 115 W plug 200 Semiconductor device 201 Barrier layer 202 Lower electrode 203 Capacitor film 204 Upper electrode 205 Barrier film 211 Upper contact 212 Conductive film 213 Barrier layer 215 Tungsten plug 216 Hard mask 220 Interlayer insulating film

Claims (20)

A semiconductor substrate;
A lower electrode provided on the semiconductor substrate;
A capacitive film provided on the lower electrode;
An upper electrode provided on the capacitor film and having an upper surface with irregularities;
A conductive film provided on top of the upper electrode, having an upper surface flatter than the upper surface of the upper electrode and having a lower melting point than the upper electrode;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device, wherein the conductive film is a metal film containing Al. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the conductive film has an upper surface planarized by heat treatment. The semiconductor device according to claim 1,
The semiconductor device, wherein the maximum surface roughness Rmax of the upper surface of the conductive film is 30 nm or less. The semiconductor device according to claim 1,
The upper electrode includes one or more metal elements selected from the group consisting of Pt, Ir, and Ru. The semiconductor device according to claim 1,
The maximum height Rmax of the surface roughness of the upper surface of the upper electrode is 50 nm or more. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the capacitor film includes an oxide of one or more metal elements selected from the group consisting of Pb, Zr, Ti, and Ba. The semiconductor device according to claim 1,
The semiconductor device, wherein the capacitor film is a CVD film. The semiconductor device according to claim 1,
The maximum roughness Rmax of the surface roughness of the upper surface of the capacitor film is 50 nm or more. The semiconductor device according to claim 1,
A semiconductor device, further comprising a barrier film containing Ti or TiN provided between the upper electrode and the conductive film. The semiconductor device according to claim 1,
The semiconductor device further comprising an upper contact connected to the conductive film. Forming a lower electrode on the semiconductor substrate;
Forming a capacitive film on the lower electrode;
Forming an upper electrode having an upper surface with irregularities on the capacitor film;
Forming a conductive film having an upper surface with irregularities on the upper electrode and having a melting point lower than that of the upper electrode;
Heat treating the upper surface of the conductive film, and planarizing the upper surface of the conductive film from the upper surface of the upper electrode;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, wherein the step of forming the conductive film includes a step of forming a metal film containing Al. In the manufacturing method of the semiconductor device according to claim 12 or 13,
The method for planarizing the upper surface of the conductive film includes a step of performing heat treatment by reflowing the upper surface of the conductive film. The method of manufacturing a semiconductor device according to claim 12,
The step of planarizing the upper surface of the conductive film includes a step of heat-treating the upper surface of the conductive film for 1 minute to 10 minutes under a temperature condition of 300 ° C. to 500 ° C. Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 12,
The step of forming the upper electrode includes a step of forming an upper electrode containing one or more metal elements selected from the group consisting of Pt, Ir, and Ru. The method for manufacturing a semiconductor device according to claim 12,
The step of forming the capacitor film includes a step of forming a capacitor film containing an oxide of one or more metal elements selected from the group consisting of Pb, Zr, Ti, and Ba. Method. In the manufacturing method of the semiconductor device in any one of Claims 12 thru | or 17,
The method of manufacturing a semiconductor device, wherein the step of forming the capacitor film includes a step of forming a capacitor film by a CVD method. The method for manufacturing a semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, further comprising a step of forming a barrier film containing Ti or TiN between the upper electrode and the conductive film. The method for manufacturing a semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, further comprising forming an upper contact connected to the conductive film on the conductive film.

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