JP2005340266A - Semiconductor device and method for forming insulating film thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming insulating film of semiconductor device which can be manufactured by preventing the occurrence of pinch-off in formation of a wire-to-wire insulating film, and reducing undulation over the interlayer insulating film even when ultra-fine wires are laid. <P>SOLUTION: A lyophilic film 14 is formed at the surface of substrate and the wiring surface. The lyophilic film 14 forms, for example, an oxide film through oxygen plasma at the substrate surface and wiring surface. Since wettability can be improved by forming the lyophilic film 14, the SOG liquid coated thereafter can easily flow into a groove between the wires to fill the region between the wires, and undulation of a wiring pattern can be alleviated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming an insulating film of a semiconductor device and a semiconductor device.

  In a conventional method for forming an insulating film of a semiconductor device, a wiring is formed on a substrate, an insulating film is formed on the substrate and the wiring, and then the undulations on the insulating film are flattened. Various methods are used for flattening the undulations on the insulating film.

  For example, according to Patent Document 1, a photoresist film is formed only on a wiring formed on a substrate, an insulating material is then applied between the wirings, and then the photoresist film is removed, and then the insulating film is removed. The material is fired to form an inter-wiring insulating film. Thereafter, a method of flattening the interlayer insulating film by forming an interlayer insulating film on the wiring and the inter-wiring insulating film is disclosed (see Patent Document 1). However, the above-described method has a problem that a process for forming and removing a photoresist film is required, and the number of processes increases.

Further, according to Patent Document 2, with the miniaturization of wiring, it becomes difficult to fill a liquid insulating material between the wirings. Therefore, the insulating film between the wirings fills the fine gaps between the wirings. Is formed of an SOG (Spin on Glass) film accompanied by application of a liquid insulating material. The liquid insulating material is applied by a rotation method (spin coating method) in which the wafer is rotated for application. After the SOG film is formed so as to cover the upper surface of the wiring, the entire surface is etched to the upper surface of the wiring.
Thereafter, a method of flattening by forming an O ₃ -TEOS (tetraethoxysilane) oxide film as an interlayer insulating film on the entire surface is disclosed. However, the above-described method has a problem that a large number of inter-wiring insulating films must be used for etching the entire surface. Further, since the entire surface is etched, there is a problem that time efficiency is poor and facilities are increased. Further, since the wafer is rotated, the SOG liquid flows from between the wirings depending on the direction of the wiring pattern formed on the substrate, and there are some places depending on the places between the wirings, which may hinder flattening. .

  Further, in order to improve the wettability between the wirings, there is a technique in which a hydrophilic treatment is performed on the wirings by a plasma CVD (Chemical Vapor Deposition) method so that an insulating material is easily applied between the wirings. In the hydrophilic treatment, for example, a hydrophilic film is formed by plasma CVD. However, due to the miniaturization of the wiring, there is a problem that contact (pinch-off) occurs in the vicinity of the upper part of the wiring when the inter-wiring insulating film is formed after the hydrophilic treatment even when the thickness of the hydrophilic film is about 130 nm. .

  Therefore, for example, in the method of forming by high density plasma CVD (HDP (High Density Plasma) CVD), sputter etching is performed to prevent abnormal growth from the corner of the wiring, and the excessively grown portion is selectively removed. However, an inter-wiring insulating film is formed. Thereafter, an interlayer insulating film is formed on the inter-wiring insulating film by normal plasma CVD.

JP-A-5-291249 Japanese Patent Laid-Open No. 10-92934

  However, when the wiring is further miniaturized (for example, 130 nm), there is a problem that pinch-off occurs in the upper part of the wiring in the oxide film formation performed by high-density plasma CVD. Since the upper opening is closed before the lower portion between the wirings is filled by pinch-off, there is a problem that cavities (hereinafter referred to as voids) are formed between the wirings.

  An object of the present invention is to solve any of the above-mentioned problems, and even if the wiring is miniaturized, the occurrence of pinch-off in the formation of the insulating film between wirings is prevented, and the undulations on the upper part of the interlayer insulating film are reduced. It is an object of the present invention to provide an insulating film forming method for a semiconductor device and a semiconductor device that can be manufactured.

  In order to solve the above problems, an insulating film forming method for a semiconductor device according to the present invention forms an insulating film including an inter-wiring insulating film and an interlayer insulating film, which flattens unevenness due to wiring formed on a substrate. A method for forming an insulating film of a semiconductor device, comprising the steps of performing a lyophilic treatment accompanied by surface modification of the surface of the wiring and the surface of the substrate, and a liquid material on the surface subjected to the lyophilic treatment. Forming the inter-wiring insulating film with application, forming the interlayer insulating film on the wiring and the inter-wiring insulating film, and polishing and planarizing the upper surface of the inter-layer insulating film; Have

  According to this configuration, after forming the wiring on the substrate, the surface of the wiring and the surface of the substrate are subjected to lyophilic treatment with surface modification, so that the thickness of the formed oxide film can be reduced, It becomes possible to fill a liquid insulating material applied thereafter between the wirings. Further, by performing the lyophilic treatment, a liquid material can easily flow between the wirings and can be filled between the wirings, and the undulation of the wiring pattern can be reduced. Therefore, undulations on the interlayer insulating film formed on the wiring and the inter-wiring insulating film can be suppressed, and the polishing amount for polishing the upper surface can be reduced.

  In the method for forming an insulating film of a semiconductor device according to the present invention, it is desirable that the lyophilic treatment is performed by surface modification with oxygen plasma.

  According to this configuration, after the wiring is formed on the substrate, the surface of the wiring and the surface of the substrate are subjected to surface modification by oxygen plasma, so that the thickness of the lyophilic treatment applied can be reduced, and thereafter The liquid insulating material to be applied can be filled between the wirings.

  In the method for forming an insulating film of a semiconductor device according to the present invention, it is preferable that the lyophilic treatment is surface modification by UV irradiation.

  According to this configuration, after forming the wiring on the substrate, the surface of the wiring and the surface of the substrate are irradiated with UV to oxidize and fly the existing organic matter, so that the thickness of the applied lyophilic treatment is reduced. It is possible to fill between the wirings with a liquid insulating material applied thereafter.

  In the insulating film forming method for a semiconductor device according to the present invention, the liquid material is preferably applied by a scan coating method.

  According to this configuration, since the liquid insulating material is applied by the scan coating method, an appropriate amount of liquid insulating material can be selectively applied between the wirings, so that the liquid insulating material is not wasted. It becomes possible to improve the utilization factor of the material.

  In the insulating film forming method for a semiconductor device according to the present invention, the liquid insulating material is preferably applied in a solvent atmosphere.

  According to this configuration, since the liquid insulating material is applied in a solvent atmosphere, the fluidity of the insulating material can be maintained long even when an insulating material having a high drying property is applied between fine wirings. . Therefore, the insulating material on the upper part of the wiring can be poured between the wirings.

  In the method for forming an insulating film of a semiconductor device according to the present invention, the inter-wiring insulating film is preferably an SOG solution.

  According to this configuration, since the SOG liquid suitable for viscosity and fluidity is used for filling between the wirings, it is possible to fill even between fine wirings. Therefore, no cavity is generated between the wirings, and the electrical reliability of the wiring can be improved.

  In the method for forming an insulating film of a semiconductor device according to the present invention, the step of forming the interlayer insulating film includes a plasma CVD process.

  According to this configuration, the multilayer wiring can be formed because the insulating film is deposited on the wiring and the substrate.

  In the insulating film forming method for a semiconductor device according to the present invention, the formation of the inter-wiring insulating film includes a high-density plasma CVD process.

  According to this configuration, even when the aspect ratio of the gap between the wirings is high, the aspect ratio can be reduced by filling the liquid material between the wirings. Therefore, even if a high-density plasma CVD process is subsequently performed, the inter-wiring insulating film can be formed without generating voids. Therefore, even after the interlayer insulating film is formed by the plasma CVD process, it can be formed without causing large undulations.

  A semiconductor device according to the present invention is a semiconductor device having an insulating film including an inter-wiring insulating film and an interlayer insulating film for flattening irregularities due to wiring formed on a substrate, and comprising: It has an insulating film formed by the insulating film forming method described in one item.

  According to this semiconductor device, the same operational effects as those of the above-described method invention can be obtained at the time of manufacture.

  Embodiments of an insulating film forming method for a semiconductor device according to the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing the semiconductor device of this embodiment. Hereinafter, the semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device 1 according to this embodiment includes a substrate 11, a wiring 12, a conductive part 13, and an insulating film 20.

As the substrate 11, for example, a silicon wafer or a glass substrate is used. Further, the substrate 11 may include an insulating film 20 provided on a silicon wafer or a glass substrate. For example, when the insulating film 20 is provided in two or more layers, the wiring 12 is formed on the insulating film 20 in the second or more layers, and the substrate including the insulating film 20 in the lower layer where the wiring 12 is formed is also provided. And When the insulating film 20 is provided in two or more layers, the semiconductor device 1 having the insulating film 20 formed by the insulating film forming method can be obtained in any layer including the insulating film 20 shown in FIG.
Hereinafter, the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIG.

  2 to 4 are sectional views schematically showing a method for forming an insulating film of a semiconductor device. Hereinafter, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS.

  In step 1 shown in FIG. 2, the wiring 12 is formed on the substrate 11. The wiring 12 is made of a metal (for example, aluminum or copper to which silicon is added) or an oxide conductive film (for example, ITO). The wiring 12 is formed by a well-known photolithography process and etching process (cleaning, film formation, cleaning, photosensitive material application, exposure, development, etching, photosensitive material peeling).

Step 2 forms a lyophilic film 14 that is a lyophilic treatment on the substrate surface 11a and the wiring surface 12a. The lyophilic film 14 in the present embodiment is surface modification that improves wettability to facilitate application of a liquid material to be described later. The lyophilic film 14 is formed, for example, by oxidizing the substrate surface 11a and the wiring surface 12a.
In order to form the lyophilic film 14, first, the substrate 11 is placed in a chamber (not shown), and then oxygen is introduced into the chamber, and oxygen plasma is applied to plasmatize and activate the oxygen. Introducing microwave. Thereby, an oxide film as the lyophilic film 14 is formed on the substrate surface 11a and the wiring surface 12a. The oxide film is formed to be 10 nm or less, for example.

In step 3, an SOG (spin ong lass) liquid 21 as a liquid material is applied on the lyophilic film 14 formed on the substrate surface 11a and the wiring surface 12a. First, the substrate 11 is placed in a chamber 31 (see FIG. 5) for applying the SOG liquid 21. Next, the container 38 (see FIG. 5) provided with the solvent liquid 21a used in the SOG liquid 21 provided in the chamber is vibrated to vaporize the solvent liquid 21a, and the chamber is filled with the SOG liquid. The solvent atmosphere is the same as the solvent of 21.
Next, the SOG liquid 21 is applied on the lyophilic film 14 in the same solvent atmosphere as the solvent of the SOG liquid 21. The application method is performed, for example, by a scan application method (see FIG. 5). Since the wettability is improved by forming the lyophilic film 14 described above, the SOG liquid 21 is easily applied to the substrate surface 11a and the wiring surface 12a. In addition, since the SOG liquid 21 is applied in the solvent atmosphere of the SOG liquid 21, the drying speed (solvent vaporization speed) is slowed down, and the fluidity of the SOG liquid 21 is maintained long even at fine portions 12b between the wirings. It becomes possible to apply while. Also, since the SOG liquid 21 applied on the wiring 12 can be prevented from drying, the SOG liquid 21 can be collected in the wiring 12b. The application of the SOG liquid 21 is repeated until reaching the vicinity of the upper surface line of the wiring 12.

  In step 4, the SOG liquid 21 is dried to form the SOG film 22 that is one of the inter-wiring insulating films. First, in a chamber (not shown), the SOG liquid 21 applied between the wirings 12b is dried and cured. Thereby, the SOG liquid 21 applied to the vicinity of the upper surface line of the wiring 12 is condensed and the film is reduced. For example, the SOG film 22 is reduced to about 1/2 of the height of the wiring 12.

  Step 5 forms an interlayer insulating film 15 on the lyophilic film 14 on the wiring 12 and the SOG film 22 formed between the wirings 12b. The interlayer insulating film 15 is formed by plasma CVD using silicon oxide (for example, TEOS (tetraethoxysilane)) as a raw material. By forming the SOG film 22 between the wirings 12b, the undulations due to the wirings 12 are alleviated, and the undulations on the upper surface 15a of the interlayer insulating film can be suppressed.

  Step 6 is polishing for flattening the undulations on the interlayer insulating film upper surface 15a. The relief of the upper surface 15a of the interlayer insulating film is planarized by performing, for example, chemical mechanical polishing (hereinafter referred to as CMP). Since the SOG film 22 is formed between the wirings 12b as described above, the unevenness of the wiring pattern can be alleviated, so that the undulations generated on the upper surface 15a of the interlayer insulating film can be suppressed. Therefore, it is possible to reduce the polishing amount for planarizing the interlayer insulating film 15 by the CMP process.

  Step 7 forms a hole 13 a for forming the conductive portion 13 on the wiring 12. The hole 13a is formed by, for example, plasma etching or laser processing.

  Step 8 forms the conductive portion 13 in the hole 13a. The conductive portion is formed in the hole 13a by, for example, a well-known aluminum sputtering method after heating reflow, a tungsten CVD method, or a Cu damascene method. Further, polysilicon doped with impurities may be used as the conductive portion.

  FIG. 5 is a schematic diagram showing a scan coating apparatus as an apparatus for coating a liquid material. (A) is the schematic perspective view which showed schematic structure of the scan coating device. (B) is the schematic sectional side view which showed schematic structure of the scan coating device. Hereinafter, the scan coating apparatus 30 will be described with reference to FIG.

  The scan coating apparatus 30 includes a substrate holding unit 32 for holding the semiconductor device (semiconductor wafer) 1 in a sealed chamber 31 for creating the same solvent atmosphere as the solvent of the SOG liquid 21, and a coating liquid. The nozzle 33, the first motor 34, the driving machine body 35, the ball screw portion 36, the second motor 37, the container 38, the vibration mechanism 39, and the control unit 40 are configured.

  The substrate holding part 32 is used for holding the semiconductor device 1. The substrate holding unit 32 is provided with an unillustrated adsorption unit, and adsorbs the lower side of the semiconductor device 1 with the surface on the wiring 12 side formed in the semiconductor device 1 facing upward. The semiconductor device 1 is adsorbed and kept in a horizontal state.

The coating liquid nozzle 33 is used to apply the SOG liquid 21 to the substrate surface 11a and the wiring surface 12a. The SOG liquid 21 is supplied to the coating liquid nozzle 33 from a coating liquid supply pipe (not shown). A discharge port (not shown) for discharging the SOG liquid 21 is formed at the tip of the coating liquid nozzle 33. The diameter of the discharge port is, for example, 30 to 60 μm.
Further, the discharge amount of the SOG liquid 21 discharged from the discharge port is controlled by the control unit 40.

  The first motor 34 is used to move the coating liquid nozzle 33 in the X direction. The rotation of the first motor 34 causes a drive pulley (not shown) connected to the first motor 34 to rotate. As the drive pulley rotates, an endless belt (not shown) connected to the drive pulley slides in the X direction. By sliding the endless belt in the X direction, the coating liquid nozzle 33 connected to the endless belt is slid in the X direction.

  The driving machine body 35 is used to move the semiconductor device 1 in the Y direction and the Z direction. The semiconductor device 1 is moved in the Y direction and the Z direction by the driving body 35 via the substrate holding part 32.

  The ball screw portion 36 is used to move the semiconductor device 1 in the Y direction together with the driving machine body 35. Due to the rotation of the ball screw portion 36, the driving machine body 35 connected to the ball screw portion 36 slides in the Y direction. As the drive body 35 slides in the Y direction, the semiconductor device 1 also slides in the Y direction in conjunction with the drive body 35.

  The second motor 37 is used for rotating the ball screw portion 36. By the rotation of the second motor 37, the ball screw portion 36 connected to the second motor 37 rotates. The rotation of the ball screw portion 36 moves the semiconductor device 1 in the Y direction in conjunction with the operation of the driving machine body 35 described above.

  The container 38 is provided in the chamber 31 for storing the solvent solution (including water) 21a of the SOG solution 21. For example, two containers 38 are provided in the chamber 31. A vibration mechanism 39 for volatilizing the solvent liquid 21a of the SOG liquid 21 stored in the container 38 by vibration is provided below the container 38. The two vibration mechanisms 39 are connected to the control unit 40, and the control unit 40 adjusts the vibration so that the same solvent atmosphere as the solvent of the SOG liquid 21 in the chamber 31 is constant.

  FIG. 6 is a schematic diagram showing a path for applying the SOG liquid to the semiconductor device by the scan coating apparatus. Hereinafter, an application route for applying the SOG liquid 21 to the semiconductor device 1 will be described with reference to FIG.

  The zigzag line shown in FIG. 6 indicates the locus of the coating liquid nozzle 33 when the SOG liquid 21 is applied to the semiconductor device 1 by the coating liquid nozzle 33. The application start position S <b> 1 is a position where application of the SOG liquid 21 to the semiconductor device 1 is started by the application liquid nozzle 33. When application to the SOG liquid application line 121a in the first row is completed by application of the SOG liquid 21 from the coating liquid nozzle 33, the process proceeds to the SOG liquid application line 121b in the second row. When the application to the SOG liquid application line 121b in the second row is completed, the process moves to the SOG liquid application line 121b in the third row, and thereafter, the application is repeated until the SOG liquid application line 121z in the last row. When the coating liquid nozzle 33 reaches the coating end position E1, the application of the SOG liquid 21 to the semiconductor device 1 is completed.

  As described above, the SOG liquid 21 is applied to the semiconductor device 1 in the manner of one stroke writing from the application start position S1 to the application end position E1. The SOG liquid 21 is applied to the upper surface of the wiring 12 and between the wirings 12b. That is, the SOG liquid 21 is always discharged during application in the manner of one-stroke writing. In addition to the application to the SOG liquid application lines 121a to 121z, the semiconductor device 1 is again applied so as to apply between the SOG liquid application lines 121a to 121z in accordance with the required amount of application of the SOG liquid 21. You may make it apply | coat to.

  Further, since the scan coating apparatus 30 is provided with a discharge control unit capable of controlling the coating amount of the SOG liquid 21 applied from the coating liquid nozzle 33, for example, where the gap between the wirings 12b is large. It is possible to control to increase the application amount of the SOG liquid 21. Thereby, it is possible to apply the SOG liquid 21 with little variation between the wirings 12b without depending on the size of the gap between the wirings 12b.

Hereinafter, a method of coating the semiconductor device 1 by the scan coating apparatus 30 will be described with reference to FIGS.
First, the semiconductor device 1 is put into the chamber 31 of the scan coating apparatus 30 described above. The direction of the semiconductor device 1 is determined by matching notches (not shown) provided in the semiconductor device 1. In this state, the semiconductor device 1 is fixed by being attracted to the attracting portion of the substrate holding portion 32 (see FIG. 5).

  Next, the vibration mechanism 39 provided in the container 38 is vibrated by the control unit 40. By vibrating the container 38, the solvent liquid 21a of the SOG liquid 21 stored in the container 38 is vibrated and vaporized. Due to the vaporization of the solvent liquid 21a of the SOG liquid 21 from the two containers 38 provided in the chamber 31, the inside of the chamber 31 is in the atmosphere of the solvent liquid 21a (see FIG. 5B).

  Next, the discharge port of the coating liquid nozzle 33 is moved to the coating start point S <b> 1 of the semiconductor device 1 by rotating the first motor 34 and the second motor 37 from the position of the coating liquid nozzle 33. Let Next, as described above, application of the SOG liquid 21 is started on the entire surface of the semiconductor device 1 in the manner of one-stroke writing.

  By forming the lyophilic film 14 on the semiconductor substrate surface 11 a and the wiring surface 12 a, the wettability of the SOG liquid 21 is high, and the SOG liquid 21 spreads on the upper surface of the wiring 12. Therefore, the SOG liquid 21 applied on the upper surface of the wiring 12 can flow into the wiring 12b. Further, since the SOG liquid 21 is applied in an atmosphere of the same solvent liquid 21 a as the SOG liquid 21, drying of the SOG liquid 21 can be suppressed and the fluidity of the SOG liquid 21 can be maintained for a long time. It becomes possible to flow between the wirings from the state in which 21 is placed. Thereby, it is possible to suppress the SOG liquid 21 from remaining on the upper surface of the wiring 12, and to reduce the step between the SOG liquid 21 applied between the wiring 12 and the wiring 12 b.

  Next, the SOG liquid 21 is dried to form the SOG film 22, and the interlayer insulating film 15 is formed thereon. Since the SOG film 22 is formed between the wirings 12b, the undulation of the upper surface of the interlayer insulating film 15a is suppressed, and the amount of polishing for flattening the undulation on the interlayer insulating film 15 can be reduced.

Further, by applying the SOG liquid 21 to the semiconductor device 1 by the scan coating method, the direction of the wiring pattern formed on the substrate 11 and the gap between the wirings 12b are wider than those of the spin coating method described above. It is possible to perform coating with little variation regardless of the thickness.
In addition, by applying the SOG liquid 21 to the semiconductor device 1 in a one-stroke manner, it is not necessary to apply more SOG liquid 21 than necessary, and the amount of SOG liquid 21 used can be suppressed. .

As described above in detail, according to the insulating film forming method and the semiconductor device of the semiconductor device of the present embodiment, the following effects can be obtained.
(1) According to the present embodiment, the SOG liquid 21 can be made to conform to the lyophilic film 14 by forming the lyophilic film 14 by applying oxygen plasma to the substrate surface 11a and the wiring surface 12a. As a result, the SOG liquid 21 on the upper surface of the wiring 12 can be poured between the wirings. Further, since the lyophilic film 14 is formed by oxygen plasma, the thickness of the lyophilic film 14 can be reduced to 10 nm or less, and the occurrence of pinch-off due to the contact of the lyophilic film 14 on the adjacent wiring 12 is prevented. can do. As a result, the wiring 12b can be applied and filled with the SOG liquid 21, so that there is no problem in electrical conduction and the reliability of the wiring 12 can be improved. In addition, the wiring 12 can be made finer.

  (2) According to the present embodiment, the SOG liquid 21 is applied to the substrate surface 11a and the wiring surface 12a in a manner of a single stroke by the scan coating method, so that it is not necessary to use the SOG liquid 21 more than necessary. It becomes possible to apply efficiently, and the utilization rate of the SOG liquid 21 can be increased.

  (3) According to this embodiment, since the SOG liquid 21 is applied to the substrate surface 11a and the wiring surface 12a by the scan coating method, the direction (wiring pattern) of the wiring 12 formed on the substrate 11, The SOG liquid 21 can be embedded in the inter-wiring 12b regardless of the width of the inter-wiring 12b. Therefore, it is possible to prevent the coating amount of the SOG liquid 21 accumulated between the wirings 12b from being greatly varied, and to reduce the undulations of the wiring pattern. Therefore, the undulations on the upper portion of the interlayer insulating film 15 formed thereafter can be reduced. Can be suppressed. Therefore, it is possible to reduce the amount of CMP polishing performed to planarize the upper portion of the interlayer insulating film 15, and to reduce the polishing time.

  (4) According to the present embodiment, in the step of applying the SOG liquid 21, since the application is performed in the same solvent atmosphere as the solvent of the SOG liquid 21, the SOG liquid 21 is applied when the SOG liquid 21 is applied to the semiconductor substrate 11. Thus, the SOG liquid 21 applied to the upper part of the wiring 12 can be poured into the fine wiring 12b without being dried. Therefore, variation in the application amount of the SOG liquid 21 embedded between the wirings can be suppressed. Therefore, it is possible to suppress undulations on the upper portion of the interlayer insulating film 15 formed thereafter, and the amount of polishing for planarization can be reduced.

(Second Embodiment)
7 to 9 are cross-sectional views schematically showing the method for manufacturing the semiconductor device of this embodiment. Hereinafter, the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS. In the present embodiment, when the wiring is further miniaturized as compared with the first embodiment, the inter-wiring insulating film is formed by high-density plasma CVD in addition to the formation of the SOG film. Is different. In the present embodiment, an insulating film forming method in a state in which the gap is narrower than that in the first embodiment (a state in which the aspect ratio is high) will be described. Note that the wiring heights shown in FIGS. 7 to 9 differ depending on the magnification, but are set in the same manner as the wiring heights of the first embodiment.

  In step 11 shown in FIG. 7, the wiring 112 is formed on the substrate 111. Similar to the first embodiment, the wiring 112 is made of a metal or an oxide conductive film, and is formed by a photolithography process and an etching process. In addition, as described above, the gap between the wirings 112b is narrower than that in the first embodiment.

  Step 12 forms a lyophilic film 114 on the surfaces of the substrate 111 and the wiring 112. The method for forming the lyophilic film 114 is performed by applying oxygen plasma to the semiconductor substrate 111 as in the first embodiment.

  In step 13, the SOG liquid 121 is applied on the lyophilic film 114 formed on the substrate surface 111a and the wiring surface 112a. The method of applying the SOG liquid 121 is performed using a scan coating apparatus in the same solvent atmosphere as the solvent of the SOG liquid 121 as in the first embodiment (see FIG. 5). The SOG liquid 121 applied between the wirings 112b and the upper surface of the wiring 112 is improved in wettability because the lyophilic film 114 is formed on the semiconductor substrate surface 111a and the wiring surface 112a. It is easy to become familiar with 114. Further, since the SOG liquid 121 is applied in the same solvent atmosphere as the solvent of the SOG liquid 121, it is possible to apply the SOG liquid 121 while maintaining the fluidity of the SOG liquid 121 for a long time. Therefore, the SOG liquid 121 applied to the upper surface of the wiring 112 is suppressed from drying and spreads thinly, and can be collected between the wirings 112b. The application of the SOG liquid 121 is repeatedly performed until the vicinity of the upper surface line of the wiring 112 is reached.

  In step 14, the SOG film 122 is formed by drying the SOG liquid 121 applied between the wirings 112b. As in the first embodiment, the drying method is to dry and cure the SOG liquid 121 applied between the wirings 112b in a chamber (not shown). As a result, the SOG liquid 121 applied to the vicinity of the upper surface line of the wiring 112 is reduced to a SOG film 122 that has been reduced to, for example, about ½ of the wiring height.

Step 15 forms a silicon oxide film, which is an insulating film 123, on the lyophilic film 114 on the wiring 112 and the SOG film 122 formed between the wirings 112b by a high-density plasma CVD method.
The high-density plasma CVD method is, for example, by reacting a reaction gas based on SiH ₄ (silane), O ₂ (oxygen), and Ar (argon) at a predetermined plasma density, and insulating while sputtering in an Ar atmosphere. In this method, the film 123 is deposited.
In a high-density plasma CVD apparatus (not shown) for performing high-density plasma CVD, a sputter etching mechanism is provided in addition to a normal plasma generation mechanism, and an inert gas is ionized to form a deposited convex portion. The protrusion can be physically scraped off by collision. That is, it becomes possible to suppress the pinch-off at the upper part of the wiring 112 that is likely to occur when the gap between the wirings 112b is small.

  First, the semiconductor device is put into a high-density plasma CVD apparatus that can generate plasma with a predetermined electron density. Next, the semiconductor device 101 is adsorbed by an adsorbing portion provided on a substrate holding table (see FIG. 5) and held in a horizontal state. Next, the insulating film 123 is formed using the predetermined gas described above while performing sputtering from an oblique direction of 45 °, for example. Since the SOG film 122 formed in step 14 is embedded at the root of the inter-wiring line 112b, the remaining gap height between the inter-wiring lines 112b becomes shallow (the aspect ratio becomes small). Therefore, even when an insulating film is formed by high-density plasma CVD, it is possible to suppress the occurrence of voids due to pinch-off occurring at the upper portion of the wiring 112. Further, the insulating film 123 formed by high density plasma CVD is formed on the SOG film 122 formed in step 14 and on the wiring. Therefore, the gap between the wirings can be filled and the wiring pattern can be relaxed.

  Step 16 forms an interlayer insulating film 115 on the insulating film 123 formed by high-density plasma CVD. The interlayer insulating film 115 is formed by plasma CVD as in the first embodiment. Since the SOG film 122 and the insulating film 123 are embedded between the wirings on the upper surface of the interlayer insulating film 115, the undulations are alleviated.

  Step 17 is polishing to flatten the undulations on the upper surface of the interlayer insulating film 115. In the polishing method, as in the first embodiment, the undulations generated on the interlayer insulating film 115 by CMP polishing are polished and flattened. Since the SOG film 122 and the insulating film 123 are formed between the wirings 112b, undulations generated on the interlayer insulating film 115 can be suppressed, so that the amount of polishing of the interlayer insulating film 115 by CMP polishing can be reduced. Is possible.

  Step 18 forms a hole 113 a for forming the conductive portion 113 on the wiring 112. As in the first embodiment, the hole 113a is formed by plasma etching or laser processing.

  Step 19 forms the conductive portion 113 in the hole 113a. The method for forming the conductive portion 113 is the same as in the first embodiment.

As described above in detail, according to the insulating film forming method and the semiconductor device of the semiconductor device of this embodiment, the following effects can be obtained in addition to the effects (1) to (4) of the first embodiment.
(5) According to the present embodiment, when the aspect ratio of the gap between the wirings 112b is large, the aspect ratio can be reduced by filling the SOG liquid 121 in the wirings 112b. Therefore, even if a high-density plasma CVD process is performed thereafter, the insulating film 123 can be formed between the wirings without generating voids. Further, by forming the insulating film 123 between the wirings 112b by the SOG film 122 and the high-density plasma CVD, the dependency on the wiring pattern is alleviated, so that the interlayer insulating film 115 is formed even after the interlayer insulating film 115 is formed by the plasma CVD process. Unevenness of the upper surface of the insulating film 115 can be suppressed, and the amount of polishing in the CMP process can be reduced.

  (6) According to the present embodiment, even when the insulating film is formed between the wirings 112b, even when the insulating film is formed by high-density plasma CVD, the SOG film 122 is formed before the high-density plasma CVD process, so It is possible to suppress the occurrence of pinch-off between the wirings 112b to be connected. Therefore, the inter-wiring insulating film can be formed without generating a void in the inter-wiring 112b. Therefore, the reliability of the wiring 112 can be improved without any problem in electrical conduction. Further, miniaturization of the wiring 112 can be dealt with.

In addition, this embodiment is not limited above, It can also implement with the following forms.
(Modification 1) In the above embodiment, the lyophilic treatment forms the lyophilic film 14 accompanied by surface modification by applying oxygen plasma to the wiring surface 12a and the substrate surface 11a. By applying UV irradiation, the lyophilic film 14 accompanied by surface modification may be formed on the wiring surface 12a and the substrate surface 11a. According to this, since the organic substance existing on the substrate 11 can be oxidized and blown off, the thickness of the applied lyophilic film 14 can be reduced, and the SOG liquid 21 applied thereafter is filled between the wirings. It becomes possible to do.

(Modification 2) In the above-described embodiment, in the step of performing the scan coating, the container 38 in which the same solvent liquid 21a as the solvent of the SOG liquids 21 and 121 is volatilized by the vibration mechanism 39, and the inside of the chamber 31 is filled with the SOG liquid The solvent atmosphere is the same as that of the solvents 21 and 121. This may be vaporized using a device that heats the same solvent liquid 21 a as the solvent of the SOG liquids 21 and 121, and the inside of the chamber 31 may be made the same solvent atmosphere as the solvent of the SOG liquids 21 and 121. According to this, similarly to the above-described embodiment, it is possible to maintain the fluidity of the SOG liquids 21 and 121 for a long time even in a portion where the gap between the wirings 112b is small, and the SOG liquids 21 and 121 are connected between the wirings 112b. Can be collected.

(Modification 3) In the above embodiment, the SOG films 22 and 122 are formed by using the SOG liquids 21 and 121 as one of the materials of the inter-wiring insulating film. This is not limited to the SOG liquids 21 and 121, and a SiO ₂ coating forming coating liquid or a low-k material (low dielectric constant insulating film material) may be used.

FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a process for forming a semiconductor device. FIG. 6 is a schematic cross-sectional view illustrating a process for forming a semiconductor device. FIG. 6 is a schematic cross-sectional view illustrating a process for forming a semiconductor device. The schematic diagram which shows the structure of the scanning application | coating apparatus which is an apparatus which apply | coats a liquid insulating material. (A) is a schematic perspective view of a scan coating apparatus. (B) is a schematic sectional side view of a scan coating apparatus. The schematic diagram which shows the locus | trajectory of application | coating to the wafer by a scanning application | coating apparatus. FIG. 9 is a schematic cross-sectional view showing a process for forming a semiconductor device in a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating a process for forming a semiconductor device. FIG. 6 is a schematic cross-sectional view illustrating a process for forming a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Board | substrate, 11a ... Substrate surface, 12 ... Wiring, 12a ... Wiring surface, 12b ... Between wiring, 13 ... Conductive part, 13a ... Hole, 14 ... Lipophilic film, 15 ... Interlayer insulation film, 20 Insulating film, 21 ... SOG liquid as a liquid material, 21a ... Solvent liquid, 22 ... SOG film which is one of insulating films between wirings.

Claims (9)

An insulating film forming method for a semiconductor device, wherein an insulating film including an inter-wiring insulating film and an interlayer insulating film is formed to flatten unevenness due to wiring formed on a substrate,
Applying lyophilic treatment with surface modification of the surface of the wiring and the surface of the substrate;
Forming the inter-wiring insulating film with application of a liquid material on the surface subjected to the lyophilic treatment; and
Forming the interlayer insulating film on the wiring and the inter-wiring insulating film;
And a step of polishing and planarizing the upper surface of the interlayer insulating film. The method for forming an insulating film of a semiconductor device according to claim 1,
The method for forming an insulating film in a semiconductor device, wherein the lyophilic treatment is performed by surface modification with oxygen plasma. The method for forming an insulating film of a semiconductor device according to claim 1,
In the method for forming an insulating film of a semiconductor device, the lyophilic treatment is performed by surface modification by UV irradiation. In the insulating-film formation method of the semiconductor device as described in any one of Claims 1-3,
The method for forming an insulating film of a semiconductor device, wherein the liquid material is applied by a scan coating method. In the insulating film formation method of the semiconductor device as described in any one of Claims 1-4,
The method for forming an insulating film of a semiconductor device, wherein the application of the liquid material is performed in a solvent atmosphere. In the insulating-film formation method of the semiconductor device as described in any one of Claims 1-5,
The method for forming an insulating film of a semiconductor device, wherein the liquid material is an SOG liquid. In the insulating film formation method of the semiconductor device as described in any one of Claims 1-6,
The method for forming an insulating film of a semiconductor device, wherein the step of forming the interlayer insulating film includes a plasma CVD process. In the insulating-film formation method of the semiconductor device as described in any one of Claims 1-7,
An insulating film forming method for a semiconductor device, wherein the formation of an insulating film between wirings includes a high-density plasma CVD process. A semiconductor device having an insulating film including an inter-wiring insulating film and an interlayer insulating film for flattening irregularities due to wiring formed on a substrate,
A semiconductor device comprising an insulating film formed by the insulating film forming method according to claim 1.

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