JP2005339623A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device which operates at a high-speed and which can shorten the test time. <P>SOLUTION: The storage devices is provided with a command decoder 1 for decoding an external command input COM and for detecting the command for performing the initial mode setting, and a delay circuit 3a for delaying the start timing of the bit line sensing in a memory core 4, relative to the normal operation, when the command for performing the initial mode setting is detected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a storage device capable of high speed operation.

  In DRAMs, synchronous DRAMs (SDRAMs), double data rate (DDR) -SDRAMs, etc., a refresh cycle is required to rewrite the capacitor charge at regular intervals. During refresh, it is necessary to activate a plurality of word lines at the same time, resulting in insufficient supply of power supply voltage. As a first background art for ensuring a sufficient period from the activation of the word line to the activation of the sense amplifier, the refresh operation is performed in accordance with the delay of the operation timing due to the drop of the power supply voltage by delaying a predetermined signal at the time of refresh. A technique for performing this has been proposed (see, for example, Patent Document 1).

  On the other hand, high-speed cycle RAM and DDR-high-speed cycle RAM in which access to a memory core and precharge operation are pipelined are known as memories capable of operating at high speed as compared with DRAM, SDRAM, and DDR-SDRAM. In the high-speed cycle RAM, the command is determined by a combination of the first command and the second command. As a second background technology capable of improving the operation speed of the high-speed cycle RAM, a method of starting the operation of the memory core by determining whether to perform reading or writing with a first command has been proposed (for example, patents). Reference 2). In this case, when the first command is a command for reading (hereinafter referred to as “read active command RDA”), either the read or mode register set is selected by the second command. When the first command is a command for performing writing (hereinafter referred to as “write active command WRA”), either writing or auto-refreshing is selected by the second command.

In the second background art, when the first command is the read active command RDA, the word line is activated even in the mode register setting operation. That is, the same operation as the refresh is performed in the mode register setting operation. Further, since the high-speed cycle RAM performs a pipeline operation, it is necessary to strictly control the operation timing. Therefore, it is necessary to perform a test similar to the read and write operations even in the mode register set and the auto refresh where high speed operation is not required. For this reason, the test time of the high-speed cycle RAM is increased. A similar problem occurs when the first background art is applied to the second background art. Therefore, realization of a high-speed cycle RAM capable of reducing the test time is desired.
JP 11-66844 A JP 2001-189077 A

  The present invention provides a storage device that operates at high speed and can reduce the test time.

  A feature of the present invention is that a command decoder for decoding a command input from the outside and detecting a command for setting an initial mode, and a bit line sense in a memory core when a command for setting an initial mode is detected The gist of the present invention is that the storage device includes a delay circuit that delays the start timing of the first and second timings as compared with the normal operation.

  According to the present invention, it is possible to provide a storage device that operates at high speed and can reduce the test time.

  Next, first and second embodiments of the present invention will be described with reference to the drawings. In the descriptions of the drawings in the first and second embodiments, the same or similar parts are denoted by the same or similar reference numerals.

(First embodiment)
As shown in FIG. 1, the storage device according to the first embodiment of the present invention includes a command decoder 1, a delay circuit 3a, a mode register 5, a control circuit 2, and a memory core 4. The command decoder 1 decodes an external command input COM and detects a command for setting an initial mode (hereinafter referred to as “mode register set command MRS”). Here, “initial mode setting” means setting, for example, the burst length, burst type, column address strobe (CAS) latency, etc. applied at the time of reading in the mode register 5. In addition, the command decoder 1 detects a command (hereinafter referred to as “auto-refresh command REF”) for automatically performing refresh. When the mode register set command MRS is detected, the delay circuit 3a delays the bit line sense start timing in the memory core 4 as compared with the normal operation. Here, “bit line sense” means, for example, an operation of activating a sense amplifier in the memory core 4. “Normal operation” means, for example, a read operation or a write operation.

  Furthermore, when the mode register set command MRS is detected, the delay circuit 3a delays the start timing of the bit line equalization in the memory core 4 as compared with the normal operation time. “Bit line equalization” means, for example, an operation of activating an equalization circuit inside the memory core 4. The command decoder 1 sequentially receives a first command and a second command as a command input COM. The control circuit 2 controls peripheral circuits such as a sense amplifier in the memory core 4 and row systems. To the control circuit 2, the row address of the memory core 4 is supplied as an upper address simultaneously with the input of the first command, and the column address of the memory core 4 is supplied as the lower address simultaneously with the input of the second command.

  As shown in FIG. 2, the command decoder 1 detects whether the second command is the lower address latch command LAL or the auto-refresh command REF when the first command is the write active command WRA. When the first command is the write active command WRA and the second command is the lower address latch command LAL, the control circuit 2 shown in FIG. 1 executes the write operation. On the other hand, when the first command is the read active command RDA, the command decoder 1 detects whether the second command is the lower address latch command LAL or the mode register set command MRS. When the first command is the read active command RDA and the second command is the lower address latch command LAL, the control circuit 2 executes a read operation. In this way, since it is determined whether to perform reading or writing by the first command, the operation of the memory core 4 shown in FIG. 1 can be started simultaneously with the input of the first command.

  Further, the command decoder 1 generates the first command detection signal bACTV when the first command is input. The command decoder 1 detects a read active command RDA, a write active command WRA, and a mode register set command MRS, and generates a read active detection signal bCTRU, a write active detection signal bCTWU, and a mode register set detection signal bMSET. The first command detection signal bACTV, the read active detection signal bCTRU, and the write active detection signal bCTWU generated by the command decoder 1 are transmitted to the control circuit 2, respectively. The mode register set detection signal bMSET is transmitted to the mode register 5 and the delay circuit 3a.

  The control circuit 2 shown in FIG. 1 includes an upper address driver 21, a bank timer 22, a predecoder control circuit 23, a redundancy control circuit 24, an upper address predecoder 25, a first driver 26, a redundancy predecoder 27, and a second driver. 28, and a sense amplifier control circuit 29. The predecoder control circuit 23 is connected between the bank timer 22 and the upper address predecoder 25. The redundancy control circuit 24 has inputs connected to the bank timer 22 and the upper address driver 21. The upper address predecoder 25 is connected between the upper address driver 21 and the memory core 4. The first driver 26 and the redundancy predecoder 27 are respectively connected between the redundancy control circuit 24 and the memory core 4.

  Further, the bank timer 22 generates a bank timer signal BNK based on the clock CLK, the bank select signal BSEL, and the first command detection signal bACTV, and determines the end timing of the row address strobe (RAS) restoration and the start timing of the RAS precharge. To do. Here, “RAS restore” means operations such as bit line sensing and word line activation. “RAS precharge” means operations such as bit line equalization and word line deactivation. When the write active detection signal bCTWU is supplied, the upper address driver 21 transfers the row address AD captured when the write active command WRA of the previous cycle is input to the redundancy control circuit 24 and the upper address predecoder 25. On the other hand, when the read active detection signal bCTRU is supplied, the upper address driver 21 transfers the row address AD input from the outside to the redundancy control circuit 24 and the upper address predecoder 25 as they are.

  The upper address predecoder 25 divides the transfer row address RAD1 from the upper address driver 21 into two, and transfers the divided first transfer row address RAD2 to the memory core 4. Further, when the predecoder control signal XPD is supplied from the predecoder control circuit 23, the upper address predecoder 25 transfers the divided transfer row address RAD3 in the latter half to the memory core 4. The predecoder control circuit 23 generates a predecoder control signal XPD in response to the bank timer signal BNK and controls the upper address predecoder 25. The redundancy control circuit 24 determines switching to the redundant memory cell for the transfer row address RAD1 according to preset fuse information. When the determination is completed, the redundancy determination end signal FPRG is raised to a high level.

  Further, the redundancy control circuit 24 generates a normal cell selection signal bFDWAI when it is determined not to replace with a redundant memory cell, and generates a redundant cell selection signal RARm when it is determined to replace with a redundant memory cell. When it is determined that both the normal memory cell and the redundant memory cell are used, the redundancy control circuit 24 generates the combination instruction signal HIT. The normal cell selection signal bFDWAI and the combination instruction signal HIT are transferred to the memory core 4 via the first driver 26, respectively. The redundant cell selection signal RARm is transferred to the memory core 4 via the redundancy predecoder 27.

  The sense amplifier control circuit 29 generates a sense amplifier on control signal bQSAON, a sense amplifier off control signal bQSAOFF, and a cell array selection control signal bQMUXB according to the timing control signal QSAE from the delay circuit 3a. Here, the timing control signal QSAE is generated when the delay circuit 3a delays the redundancy determination end signal FPRG from the redundancy control circuit 24. The bit line sense start timing is determined by the sense amplifier on control signal bQSAON. The sense amplifier off control signal bQSAOFF determines the deactivation timing of the sense amplifier in the memory core 4 and the bit line equalization start timing. The cell array selection control signal bQMUXB is used to select one of a plurality of memory cell arrays inside the memory core 4. The sense amplifier on control signal bQSAON, the sense amplifier off control signal bQSAOFF, and the cell array selection control signal bQMUXB are transmitted to the memory core 4 via the second driver 28, respectively.

  The delay circuit 3a further includes a word line activation simulation circuit 31, a bit line sense simulation circuit 32a, and a delay control circuit 33a. An input of the word line activation simulation circuit 31 is connected to the redundancy control circuit 24. The delay control circuit 33a has inputs connected to the outputs of the command decoder 1, bank timer 22, and bit line sense simulation circuit 32a. The bit line sense simulation circuit 32 a has an input connected to the word line activation simulation circuit 31 and the delay control circuit 33 a and an output connected to the sense amplifier control circuit 29. The word line activity simulation circuit 31 delays the redundancy determination end signal FPRG for a predetermined time to generate a delay signal SWLIN. Here, the word line activation simulation circuit 31 delays the redundancy determination end signal FPRG by a time corresponding to the word line activation operation. The delay control circuit 33a generates the delay control signal DCNT when the mode register set detection signal bMSET is supplied from the command decoder 1. The delay control circuit 33a stops generating the delay control signal DCNT when the supply of the mode register set detection signal bMSET, the bank timer signal BNK, and the redundancy determination end signal FPRG is stopped. The bit line sense simulation circuit 32a generates the timing control signal QSAE by delaying the delay signal SWLIN for a predetermined time. When the delay control signal DCNT is supplied from the delay control circuit 33a, the bit line sense simulation circuit 32a greatly delays the timing control signal QSAE as compared with the normal operation.

  As shown in FIG. 3, the delay control circuit 33 a includes a flip-flop control circuit 331, a flip-flop 332, and an output buffer 333. The flip-flop control circuit 331 includes inverters 331a and 331c, and a three-input NAND circuit (NOR). The flip-flop 332 includes two-input NAND circuits 332a and 332b. The output buffer 333 includes inverters 333a and 333b. The flip-flop 332 generates a high-level output signal when the low-level mode register set detection signal bMSET is supplied. The flip-flop control circuit 331 controls the data holding period of the flip-flop 332 based on the redundancy determination end signal FPRG, the bank select signal BSEL, and the mode register set detection signal bMSET. The output buffer 333 buffers the output signal of the flip-flop 332 and generates a delay control signal DCNT.

  As shown in FIG. 4, the word line activation simulation circuit 31 simulates a part of the configuration of the memory cells in the memory core 4 shown in FIG. Specifically, the word line activation simulation circuit 31 includes a plurality of (first to kth) simulation memory cells 31a to 31k (k; an integer of 2 or more). The first simulated memory cell 31a includes a cell capacitor C1 having one end connected to the cell plate PL, and a cell transistor Tr1 connected between the equalizing power source VEQ and the other end of the cell capacitor C1. The potential of the equalizing power source VEQ is set to about ½ of the potential of the high potential power source VDD, for example. The second simulated memory cell 31b to the kth simulated memory cell 31k are configured similarly to the first simulated memory cell 31a.

  On the other hand, the bit line sense simulation circuit 32a includes a data read simulation circuit 320, a buffer circuit 321, a timing control circuit 322, and an output selection circuit 323. The data read simulation circuit 320 delays the delay signal SWLIN by a time corresponding to the data read operation from the cell transistor in the memory core 4 shown in FIG. 1 to the bit line. The buffer circuit 321 buffers the delayed signal SWLIN delayed by the data read simulation circuit 320. The timing control circuit 322 delays the rising and falling timings of the output signal of the buffer circuit 321. The output selection circuit 323 selects either the output signal of the timing control circuit 322 or the output signal of the buffer circuit 321 based on the delay control signal DCNT. That is, the output selection circuit 323 selects the output signal of the timing control circuit 322 during the period when the delay control signal DCNT is at a high level. One of the output signal of the timing control circuit 322 selected by the output selection circuit 323 and the output signal of the buffer circuit 321 is supplied to the sense amplifier control circuit 29 shown in FIG. 1 as the timing control signal QSAE.

  Further, the data read simulation circuit 320 includes a precharge transistor Tr11 and a cell transistor Tr12 connected between the high level power supply VDD and the equalize power supply VEQ. For example, a pMOS transistor can be used as the precharge transistor Tr11. The cell transistor Tr12 simulates the cell transistor in the memory core 4 shown in FIG. A node between the precharge transistor Tr11 and the cell transistor Tr12 simulates a bit line in the memory core 4. The buffer circuit 321 includes inverters 321a and 321b connected in two stages. The timing control circuit 322 includes four stages of inverters 322a, 322b, 322c, and 322d, a first delay transistor Tr13, and a second delay transistor Tr14. The first delay transistor Tr13 has a source and a drain connected to the high-level power supply VDD, and a gate connected to a connection node of the inverters 322b and 322c. The second delay transistor Tr14 has a source and a drain connected to the low power supply VSS and a gate connected to a connection node of the inverters 322b and 322c. The output selection circuit 323 includes inverters 323a and 323b connected in two stages, a first OR circuit 323e, a second OR circuit 323c, and a NAND circuit 323d. The first OR circuit 323e has inputs connected to the respective outputs of the inverters 322d and 323a. The second OR circuit 323c has inputs connected to the outputs of the inverters 321b and 323b. The input of the NAND circuit 323d is connected to the respective outputs of the first OR circuit 323e and the second OR circuit 323c.

  On the other hand, the memory core 4 includes, for example, a row decoder 41, a cell array 42 connected to the row decoder 41, and a peripheral circuit 43 connected to the cell array 42, as shown in FIG. The peripheral circuit 43 includes, for example, a sense amplifier 43a, a selection circuit 43b, and an equalize circuit 43c. Although not shown, in practice, the selection circuit, the equalization circuit, and the cell array are symmetrically arranged with the sense amplifier 43a as the center. In addition to the cell array 42, a redundant cell array is provided. The row decoder 41 selects one of a plurality of (first to nth) word lines WL1 to WLn (n; an integer equal to or greater than 2). The cell array 42 includes first to nth memory cells 42a to 42n. The first memory cell 42a has a cell capacitor C20 having one end connected to the cell plate PL, a drain connected to the first bit line BL, a gate connected to the first word line WL1, and the other end of the cell capacitor C20. A cell transistor Tr20 having a source connected thereto is provided. The second memory cell 42a to the nth memory cell 42n are configured similarly to the first memory cell 42a.

  Further, the equalize circuit 43c precharges the potentials of the first bit line BL and the second bit line bBL to the potential of the equalize power source VEQ during the RAS precharge according to the equalize control signal EQL. The selection circuit 43b separates the cell array on the opposite side from the cell array that performs bit line sensing based on the cell array selection signal MUX during RAS restore. As a result, the sense amplifier is connected only to the cell array that performs bit line sensing. At the time of RAS precharge, the cell array on the opposite side is connected again to the cell array that performs bit line sensing. Thereby, the bit line equalization is performed in all the cell arrays. At the time of reading data, one memory cell is selected from the cell array 42 by selectively activating any of the first to nth word lines WL1 to WLn and the first bit line BL and the second bit line bBL. Is done. The potentials of the first bit line BL and the second bit line bBL are slightly changed by the potential corresponding to the data stored in the cell capacitor of the selected memory cell. The sense amplifier 43a amplifies the potentials of the first bit line BL and the second bit line bBL.

  Further, the sense amplifier 43a includes a first sense transistor Tr30 to a fourth sense transistor Tr33. For example, nMOS transistors can be used as the first sense transistor Tr30 and the second sense transistor Tr31. As the third sense transistor Tr32 and the fourth sense transistor Tr33, for example, pMOS transistors can be used. The first sense transistor Tr30 and the second sense transistor Tr31, and the third sense transistor Tr32 and the fourth sense transistor Tr33 are connected in series between the first bit line BL and the second bit line bBL, respectively. . The gates of the first sense transistor Tr30 and the third sense transistor Tr32 are connected to the second bit line bBL. The gates of the second sense transistor Tr31 and the fourth sense transistor Tr33 are connected to the first bit line BL.

  The selection circuit 43b includes a first selection transistor Tr34 provided on the first bit line BL and a second selection transistor Tr35 provided on the second bit line bBL. For example, nMOS transistors can be used as the first selection transistor Tr34 and the second selection transistor Tr35. The equalizing circuit 43c includes a first equalizing transistor Tr36 to a third equalizing transistor Tr38. As each of the first equalizing transistor Tr36 to the third equalizing transistor Tr38, for example, an nMOS transistor can be used. The first equalizing transistor Tr36 is connected between the first bit line BL and the second bit line bBL. The second equalizing transistor Tr37 and the third equalizing transistor Tr38 are connected between the first bit line BL and the second bit line bBL, and the first equalizing transistor Tr36 and the gate are connected to each other. A connection node between the second equalizing transistor Tr37 and the third equalizing transistor Tr38 is connected to the equalizing power source VEQ.

  Next, the operation of the storage device according to the first embodiment will be described with reference to the time chart shown in FIG. However, a case where the read active command RDA is supplied as the first command and the mode register set command MRS is supplied as the second command will be described as an example.

  (A) First, at time t1 in FIG. 6, immediately before the rising of the clock CLK shown in FIG. 6A, the read active command RDA is supplied as the first command as shown in FIG. 6B. At time t2, the clock CLK rises to a high level. When the first command is supplied, the command decoder 1 shown in FIG. 1 generates the first command detection signal bACTV in synchronization with the rising edge of the clock CLK. The first command detection signal bACTV is supplied to the bank timer 22 shown in FIG. Further, at time t3, the command decoder 1 detects that the first command is the read active command RDA, and lowers the read active detection signal bCTRU shown in FIG. 6C to a low level. The read active detection signal bCTRU is supplied to the upper address driver 21 shown in FIG.

  (B) As shown in FIG. 6E, when the first command detection signal bACTV is supplied, the bank timer 22 raises the bank timer signal BNK to a high level at time t4. When the bank timer signal BNK and the read active detection signal bCTRU are supplied, the upper address driver 21 transfers the row address AD transmitted from the outside at time t4 to the redundancy control circuit 24 and the upper address predecoder 25 shown in FIG. Transfer as row address RAD1. As shown in FIG. 6F, the upper address predecoder 25 transfers the first half row address RAD2 obtained by dividing the transfer row address RAD1 to the memory core at time t4.

  (C) When the transfer row address RAD1 and the bank timer signal BNK are supplied, the redundancy control circuit 24 shown in FIG. 1 determines switching to the redundant cell array in the memory core 4. When the determination is completed, the redundancy control circuit 24 raises the redundancy determination end signal FPRG to a high level at time t5 as shown in FIG. 6 (j). The redundancy determination end signal FPRG is supplied to the word line activation simulation circuit 31 and the second driver 28 shown in FIG. Further, when bank timer signal BNK rises to a high level, predecoder control circuit 23 shown in FIG. 1 raises predecoder control signal XPD to a high level at time t5. When the predecoder control signal XPD rises to a high level, the upper address predecoder 25 transfers the latter row address RAD3 obtained by dividing the transfer row address RAD1 to the memory core 4 at time t6, as shown in FIG. To do.

  (D) When the redundancy determination end signal FPRG rises to a high level, the second driver 28 raises the word line activation enable signal WLE to a high level at time t7 as shown in FIG. 6 (k). When the word line activation enable signal WLE rises to a high level, as shown in FIG. 6 (u), the word line potential rises to a high level at time t8. Further, the redundancy determination end signal FPRG is delayed by the word line activation simulation circuit 31. As a result, the delay signal SWLIN shown in FIG. 6 (l) rises to a high level at time t8 after a lapse of a fixed time from time t5 when the redundancy determination end signal FPRG rises.

  (E) At time t9 in FIG. 6B, the mode register set command MRS is supplied as the second command. At time t11 in FIG. 6A, the clock CLK rises to a high level. As a result, the command decoder 1 causes the mode register set detection signal bMSET to fall to a low level at time t11 as shown in FIG. 6 (m). When the mode register set detection signal bMSET falls to a low level, the delay control circuit 33a shown in FIG. 1 raises the delay control signal DCNT to a high level at time t11 as shown in FIG. 6 (n). The delay control signal DCNT is supplied to the bit line sense simulation circuit 32a shown in FIG.

  (F) When the delay control signal DCNT is supplied to the bit line sense simulation circuit 32a, the bit line sense simulation circuit 32a delays the delay signal SWLIN, and raises the timing control signal QSAE to a high level at time t13. Here, at the time of writing and reading, the timing control signal QSAE rises at time t10. That is, when the mode register is set, the delay time is set to be longer than when writing and reading. The timing control signal QSAE is supplied to the sense amplifier control circuit 29 shown in FIG.

  (G) When the timing control signal QSAE rises to a high level, the sense amplifier control circuit 29 outputs a low level sense amplifier on signal bSAON via the second driver 28 at time t14, as shown in FIG. This is transmitted to the memory core 4. When the sense amplifier on signal bSAON is transmitted to the memory core 4, the activation of the sense amplifier 43a shown in FIG. 5, that is, bit line sensing is executed. Further, as shown in FIG. 6 (q), the sense amplifier control circuit 29 transmits the low level cell array selection signal bMUXB to the memory core 4 via the second driver 28 at time t18.

  (H) At time t22, the bank timer 22 causes the bank timer signal BNK shown in FIG. 6 (e) to fall to a low level. When the bank timer signal BNK falls to a low level, the RAS precharge period starts. As a result, at time t23, the redundancy determination end signal FPRG shown in FIG. 6 (j) and the delay signal SWLIN shown in FIG. 6 (l) fall to a low level. When the delay signal SWLIN falls to a low level, the bit line sense simulation circuit 32a falls the timing control signal QSAE to a low level at time t27 as shown in FIG. 6 (o).

  (R) When the timing control signal QSAE falls to a low level, the sense amplifier control circuit 29, as shown in FIG. 6 (r), at time t29, the low level sense amplifier off signal bSAOFF is passed through the second driver 28. Is transmitted to the memory core 4. When the sense amplifier off signal bSAOFF is transmitted to the memory core 4, activation of the equalize circuit 43c shown in FIG. 5, that is, bit line equalization is executed. Here, as shown in FIG. 6 (s), the rise time t29 of the equalize control signal EQL is delayed by a fixed time compared to the rise time t27 of the equalize control signal EQL at the time of writing and reading.

  As described above, in the memory device according to the first embodiment, when the mode register is set, the start timings of the bit line sense and the bit line equalization are delayed as compared with normal operations such as write and read. . Therefore, according to the memory device of the first embodiment, a sufficient period from word line activation to bit line sensing can be secured. Since a sufficient operation margin for bit line sensing can be secured in the mode register setting operation, when testing the memory device according to the first embodiment, it is necessary to confirm the operation margin for bit line sensing during the mode register setting operation. No testing is required.

  As shown in FIG. 7, when the memory device shown in FIG. 1 is integrated on a semiconductor chip 60 and covered with a mold resin 90 to form a packaged semiconductor integrated circuit, two memory devices as shown in FIG. The first command can be input only by using the pin. That is, command input is executed by applying a voltage to each of the pins 64 and 63. In the example shown in FIG. 7, the pins 61 and 62 are also used as address inputs.

(Second Embodiment)
As shown in FIG. 9, the storage device according to the second embodiment of the present invention supplies the auto-refresh detection signal bREFR to the delay circuit 3b when the command decoder 1 detects the auto-refresh command REF. Different from 1. The delay circuit 3b is shown in FIG. 1 in that when the mode register set detection signal bMSET and the auto-refresh detection signal bREFR are supplied, the delay timing of the bit line sense in the memory core 4 is delayed as compared with the normal operation. Different from the device. However, the delay circuit 3b has the same bit line equalization start timing in the memory core 4 as that in the normal operation. Other configurations are the same as those of the storage device shown in FIG.

  Further, the delay control circuit 33b is different from FIG. 3 in that it further includes an input logic circuit 334 that performs a logical operation on the mode register set detection signal bMSET and the auto-refresh detection signal bREFR, as shown in FIG. Specifically, the input logic circuit 334 includes a NAND circuit 334a that performs a NAND operation on the mode register set detection signal bMSET and the auto-refresh detection signal bREFR, and an inverter 334b that inverts an output signal of the NAND circuit 334a. Other configurations are the same as those of the delay control circuit 33a shown in FIG.

  Further, as shown in FIG. 11, the bit line sense simulation circuit 32b is different from the bit line sense simulation circuit 32a shown in FIG. 4 in the configurations of the timing control circuit 3220 and the output selection circuit 3230. The timing control circuit 3220 includes a NAND circuit 3221 instead of the inverter 322a shown in FIG. The timing control circuit 3220 does not include the first delay transistor Tr13 shown in FIG. The output selection circuit 3230 does not include the inverters 323a and 323b and the OR circuit 323c illustrated in FIG. Other configurations are the same as those of the bit line sense simulation circuit 32a shown in FIG.

  Next, the operation of the storage device according to the second embodiment will be described with reference to the time chart shown in FIG. However, redundant description of operations similar to those of the storage device according to the first embodiment is omitted. An example will be described in which the write active command WRA is supplied as the first command and the auto-refresh command REF is supplied as the second command.

  (A) First, at time t1 in FIG. 12, immediately before the clock CLK shown in FIG. 12A rises, the write active command WRA shown in FIG. 12B is supplied as the first command. At time t3, the command decoder 1 detects the write active command WRA, and lowers the write active detection signal bCTWU shown in FIG. 12C to a low level. The write active detection signal bCTWU is supplied to the upper address driver 21 shown in FIG. When the bank timer signal BNK and the write active detection signal bCTWU are supplied, the upper address driver 21 uses the redundancy control circuit 24 and the upper address prefetch as the row address fetched at the time of input of the write active command WRA of the previous cycle at time t4. Transfer to the decoder 25.

  (B) At time t9 in FIG. 12B, the auto-refresh command REF is supplied as the second command. At time t11 in FIG. 12A, the clock CLK rises to a high level. As a result, the command decoder 1 causes the auto-refresh detection signal bREFR to fall to a low level at time t11 as shown in FIG. When the auto-refresh detection signal bREFR falls to a low level, the delay control circuit 33b shown in FIG. 9 raises the delay control signal DCNT to a high level at time t11 as shown in FIG. 12 (n). The delay control signal DCNT is supplied to the bit line sense simulation circuit 32b shown in FIG. As a result, the start timing of bit line sensing can be delayed as compared with normal operations such as writing and reading.

  (C) At time t22, the bank timer 22 causes the bank timer signal BNK shown in FIG. 12 (e) to fall to a low level. As a result, at time t24, the redundancy determination end signal FPRG shown in FIG. 12 (j) and the delay signal SWLIN shown in FIG. 12 (l) fall to a low level. When the delay signal SWLIN falls to a low level, the bit line sense simulation circuit 32b falls the timing control signal QSAE to a low level at time t25 as shown in FIG. 12 (o). Here, the falling timing of the timing control signal QSAE is set to the same timing as during normal operations such as reading and writing.

  (D) When the timing control signal QSAE falls to a low level, the sense amplifier control circuit 29, as shown in FIG. 12 (r), detects the low level sense amplifier off signal bSAOFF via the second driver 28 at time t27. Is transmitted to the memory core 4. When the sense amplifier off signal bSAOFF is transmitted to the memory core 4, activation of the equalize circuit 43c shown in FIG. 5, that is, bit line equalization is executed. Therefore, since the falling timing of the timing control signal QSAE is the same timing as in the normal operation such as read and write, the start timing of the bit line equalization is also the same as that in the normal operation such as read and write.

  As described above, in the memory device according to the second embodiment, the start timing of bit line sensing is delayed as compared with normal operations such as writing and reading during mode register set and refresh. Therefore, when testing the memory device according to the second embodiment, a test for confirming the operation margin of the bit line sense at the time of mode register set and refresh can be made unnecessary. Also, by setting the bit line equalization start timing to the same timing as normal operations such as writing and reading, a sufficient time can be secured for bit line equalization.

(First Modification of Second Embodiment)
As shown in FIG. 13, the storage device according to the first modification of the second embodiment of the present invention is for executing a test mode in response to a mode register set detection signal bMSET and an external address input. 9 is different from FIG. 9 in that it further includes a test circuit 7 for generating a plurality of (first and second) test signals TM1 and TM2. The test circuit 7 uses the first and second test signals TM1 and TM2 to change the delay time set in the bit line sense simulation circuit 32c step by step. When the test circuit 7 enters the test mode, the command decoder 1 can repeat the same operation as the second command even after the third cycle. As an address input supplied to the test circuit 7, for example, an upper address, a lower address input to the storage device, a bank address for decoding the bank select signal BEL, and the like can be used. Other configurations are the same as those of the storage device shown in FIG.

  Furthermore, as shown in FIG. 14, the delay control circuit 33c includes the delay control circuit 33a and the delay control circuit 33b shown in FIGS. The delay control circuit 33c generates the first timing control signal DCNT1 when the mode register set detection signal bMSET is input, and when either the mode register set detection signal bMSET or the auto-refresh detection signal bREFR is input. Generates the second timing control signal DCNT2. Specifically, the delay control circuit 33c includes a first flip-flop control circuit 3310, a first flip-flop 3320, a first output buffer 3330, an input logic circuit 334, a second flip-flop control circuit 3311, a second flip-flop 3321, and A second output buffer 3331 is provided. The first output buffer 3330 outputs the first delay control signal DCNT1. A second delay control signal DCNT2 is output from the second output buffer 3331. Other configurations are the same as those of the delay control circuit 33a and the delay control circuit 33b shown in FIGS.

  Further, as shown in FIG. 15, the bit line sense simulation circuit 32c is different from FIG. 11 in that it includes a first timing control circuit 3240 and a second timing control circuit 3250a in place of the timing control circuit 3220 shown in FIG. The first timing control circuit 3240 delays the output signal of the buffer circuit 321 when the second delay control signal DCNT2 is supplied. The second timing control circuit 3250a delays the output signal of the buffer circuit 321 stepwise by a combination of the first delay control signal DCNT1, the first test signal TM1, and the second test signal TM2.

  The first timing control circuit 3240 includes a NAND circuit 3221, inverters 322b and 322c, and a second delay transistor Tr14. The second timing control circuit 3250a includes switching transistors Tr41 to Tr44, inverters 3251, 3252, 3256, and 3257, OR circuits 3253 and 3254, and a third delay transistor Tr15. The switching transistors Tr41 and Tr42 and the switching transistors Tr43 and Tr44 constitute transfer gates, respectively. For example, a pMOS transistor can be used as each of the switching transistors Tr41 and Tr43. As each of the switching transistors Tr42 and Tr44 and the third delay transistor Tr15, for example, an nMOS transistor can be used.

  As described above, according to the storage device shown in FIG. 13, the delay set in the bit line sense simulation circuit 32c by enabling one of the first and second test signals TM1 and TM2 at the time of test mode entry. Time can be controlled step by step.

(Second modification of the second embodiment)
As shown in FIG. 16, the memory device according to the second modification of the second embodiment of the present invention generates a plurality of (first and second) fuse signals FUSE1 and FUSE2 to simulate bit line sense. 9 is different from FIG. 9 in that it further includes a fuse circuit 8 that changes the delay period set in the circuit 32d stepwise. Further, the storage device shown in FIG. 16 further includes a test circuit 7 for generating the first and second test signals TM1 and TM2, as in FIG. Other configurations are the same as those of the storage device shown in FIG.

  Further, as shown in FIG. 17, the fuse circuit 8 includes a first fuse signal generation circuit 8a that generates a first fuse signal FUSE1 and a second fuse signal generation circuit 8b that generates a second fuse signal FUSE2. The first fuse signal generation circuit 8a includes a first switching transistor Tr51, a second switching transistor Tr52, a fuse 89, and a latch circuit 80a. The first fuse signal generation circuit 8a generates either a high level signal or a low level signal depending on whether or not the fuse 89 is blown. For example, a pMOS transistor can be used as the first switching transistor Tr51. For example, an nMOS transistor can be used as the second switching transistor Tr52. The latch circuit 80a includes inverters 81, 82, and 83. The first switching transistor Tr51 is turned on in response to a first power-on signal bFPUP from a power supply circuit (not shown). The second switching transistor Tr52 is turned on in response to the second power-on signal FPUN.

  Also, the first power-on signal bFPUP and the second power-on signal FPUN are each at a high level after power-on, as shown in FIGS. 18 (a) and 18 (b). In the example shown in FIG. 18, the first power-on signal bFPUP rises to a high level at time t1, as shown in FIG. Before the time t1, since the first switching transistor Tr51 is in the on state, the node n1 is short-circuited to the high-level power supply VDD. Therefore, the first fuse signal FUSE1 is at a high level.

  As shown in FIG. 18B, the second power-on signal FPUN rises to a high level at time t2. The second power-on signal FPUN falls to a low level at time t3, but the first power-on signal bFPUP maintains a high level. Here, when the fuse 89 is not cut, the first switching transistor Tr51 shown in FIG. 17 is turned off and the second switching transistor Tr52 is turned on at time t3 in FIG. 18, and the node n1 is short-circuited with the low-level power supply VSS. Thus, the potential becomes a low level. As shown in FIG. 18C, the latch circuit 80a holds the low level signal from the node n1. As a result, the first fuse signal FUSE1 becomes low level.

  On the other hand, when the fuse 89 is cut, the node n1 is not short-circuited with the low-level power supply VSS even when the second switching transistor Tr52 is turned on at time t3 in FIG. Therefore, the first fuse signal FUSE1 is maintained at a high level. The second fuse signal generation circuit 8b is configured in the same manner as the first fuse signal generation circuit 8a.

  Further, as shown in FIG. 19, the bit line sense simulation circuit 32d differs from the second timing control circuit 3250a shown in FIG. 15 in the configuration of the second timing control circuit 3250b. Specifically, the second timing control circuit 3250b shown in FIG. 19 has a configuration in which an exclusive OR (EXOR) circuit 3258 and switching transistors Tr45 to Tr48 are added to the second timing control circuit 3250a shown in FIG. The switching transistors Tr45 and Tr46 and the switching transistors Tr47 and Tr48 constitute transfer gates, respectively. The EXOR circuit 3258 has inputs connected to the switching transistors Tr41 to Tr48.

  As described above, according to the memory device shown in FIG. 16, by using the first fuse signal FUSE1 and the second fuse signal FUSE2 generated by the fuse circuit 8, the delay of the bit line sense simulation circuit 32d is similar to the test circuit 7. You can change the number of steps.

(Other embodiments)
As described above, the present invention has been described according to the first and second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the first embodiment described above, an example has been described in which the start timing of each of the bit line sense and the bit line equalization is delayed as compared with that in the normal operation when the mode register is set. In the second embodiment, an example has been described in which only the start timing of bit line sensing is delayed compared to that during normal operation during mode register set and refresh. However, when the mode register is set, the start timing of only the bit line sense may be delayed as compared with the normal operation. Further, the start timing of each of the bit line sense and the bit line equalization at the time of mode register setting and refresh may be delayed as compared with the normal operation.

  In the first modification of the second embodiment already described, an example in which the test circuit 7 generates two test signals, that is, the first and second test signals TM1 and TM2, has been described. However, the test circuit 7 may generate three or more test signals. By increasing the number of test signals, the number of delay steps set in the bit line sense simulation circuit 31c can be further increased. Similarly, in the second modification of the second embodiment, an example in which the fuse circuit 8 generates two fuse signals, that is, the first and second fuse signals FUSE1 and FUSE2, has been described. However, three or more fuse signals may be generated.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

It is a block diagram which shows the structure of the memory | storage device which concerns on 1st Embodiment. It is a figure which shows the mode of the command transition of the memory | storage device which concerns on 1st Embodiment. 1 is a circuit diagram showing a configuration of a delay control circuit according to a first embodiment. FIG. FIG. 3 is a circuit diagram showing configurations of a word line activation simulation circuit and a bit line sense simulation circuit according to the first embodiment. FIG. 3 is a circuit diagram showing a part of the configuration of the memory core according to the first embodiment. It is a time chart which shows operation | movement of the memory | storage device which concerns on 1st Embodiment. It is a schematic diagram which shows pin arrangement at the time of packaging the memory | storage device which concerns on 1st Embodiment. 8 is a function table showing the relationship between the state diagram of FIG. 2 and the pin arrangement of FIG. It is a block diagram which shows the structure of the memory | storage device which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the delay control circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the word line active simulation circuit and bit line sense simulation circuit 32a which concern on 2nd Embodiment. 6 is a time chart illustrating an operation of the storage device according to the second embodiment. It is a block diagram which shows the structure of the memory | storage device which concerns on the 1st modification of 2nd Embodiment. It is a circuit diagram which shows the structure of the delay control circuit which concerns on the 1st modification of 2nd Embodiment. It is a circuit diagram which shows the structure of the bit line sense simulation circuit which concerns on the 1st modification of 2nd Embodiment. It is a block diagram which shows the structure of the memory | storage device which concerns on the 2nd modification of 2nd Embodiment. It is a circuit diagram which shows the structure of the fuse circuit which concerns on the 2nd modification of 2nd Embodiment. It is a time chart which shows operation | movement of the fuse circuit which concerns on the 2nd modification of 2nd Embodiment. It is a circuit diagram which shows the structure of the bit line sense simulation circuit which concerns on the 2nd modification of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Command decoder 2 ... Control circuit 3a-3d ... Delay circuit 4 ... Memory core 5 ... Mode register 7 ... Test circuit 8 ... Fuse circuit

Claims (5)

A command decoder that decodes command input from the outside and detects a command for initial mode setting;
And a delay circuit that delays a bit line sense start timing in the memory core as compared with a normal operation when a command for performing the initial mode setting is detected.   2. The delay circuit according to claim 1, wherein, when a command for performing the initial mode setting is detected, the delay circuit delays the start timing of bit line equalization in the memory core as compared with the time of the normal operation. The storage device described.   The command decoder further detects a command for automatically performing a refresh, and the delay circuit detects a start timing of the bit line sense when the command for automatically performing the refresh is detected. The storage device according to claim 1, wherein the storage device is delayed with respect to time.   2. The test circuit according to claim 1, further comprising a test circuit that generates a plurality of test signals for executing a test based on an external address input and changes a delay time set in the delay circuit in a stepwise manner. The memory | storage device of any one of -3.   The storage device according to claim 1, further comprising a fuse circuit that generates a plurality of fuse signals and changes a delay time set in the delay circuit in a stepwise manner.

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