JP2005333667A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus which achieves a highly-accuracy inverter control, a semiconductor apparatus which achieves short-circuiting protection and an over-temperature protection with high accuracy, and to provide a semiconductor apparatus which properly sets the slopes of the rise and fall of the collector current of an output device. <P>SOLUTION: The over-temperature protection is achieved with high accuracy, by having a semiconductor-switching element (1), a temperature-detecting means (8) to detect the operating temperature of the semiconductor-switching element, an over-temperature protecting means (7) for stopping the operation of the semiconductor switching element, when a detection signal from the temperature detecting means exceeds a specified trip level, and a characteristics correcting means (5) for correcting the trip level. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a circuit configuration of a semiconductor device, and more particularly to a circuit for trimming electrical characteristics of a power module for driving an insulated gate semiconductor switching element such as an IGBT.

  FIG. 13 shows the configuration of a power module for an inverter circuit. The drive control circuit uses UPin, VPin, WPin, UNin, VNin, and WNin as input signals, and drive signals UPout, VPout, WPout, UNout, VNout, and WNout for each IGBT1 to IGBT6 (only UPout and UNout are specified in FIG. 13). Is output. Although FIG. 13 shows an example of a power module that drives six IGBTs with one drive control circuit, there is also a module equipped with a plurality of drive control circuits.

  The diode bridge on the upper right in the figure is a rectifier circuit for supplying DC power to this module. Further, the current detection resistor Rs is inserted in the emitter circuit of the IGBT 2. However, since the current loss increases, generally, it is inserted in the second emitter circuit as shown in FIG. The

  FIG. 14 shows an input / output operation timing chart relating to the input signals UPin and UNin. t1 is a delay time required from the level inversion of the input signal UPin from high to low to the level inversion of the output signal UPout from low to high. Then, as can be seen from the output current Iup of the IGBT 1, the IGBT 1 is switched on with a delay time of tonP. The former delay time t1 is due to the drive control circuit, and the latter delay time tonP is due to the response time of the IGBT. Therefore, the IGBT 1 is switched on after tconP after the level inversion of the input signal UPin from high to low.

  t2 is a delay time required from the level inversion of the input signal UPin from low to high to the level inversion of the output signal UPout from high to low. As can be seen from the output current Iup of the IGBT 1, the IGBT 1 is switched off with a delay time of toffP. Accordingly, the IGBT 1 is switched off after tcoffP from the level inversion of the input signal UPin from low to high.

  Similarly, IGBT2 is switched off after tcoffN (= t3 + toffN) from level inversion of input signal UNin from low to high, and IGBT2 is switched after level inversion of input signal UNin from high to low after tconN (= t4 + tonN). Turn on. As can be seen from FIG. 14, the levels of the output signals UPout and UNout are inverted with respect to the input signals UPin and UNin.

  The delay times of t1 to t4 and tonP, toffP, toffN, and tonN described above are not constant and vary depending on the drive control circuit and the IGBT. Therefore, in any case, the off period of IGBT 2 is made longer than the on period of IGBT 1 so that IGBT 1 and IGBT 2 are not switched on simultaneously.

  For this purpose, it is necessary to set the high period of the input signal UNin as shown in the figure with respect to the low period of the input signal UPin. As a result, the input signal UNin includes an input pause time period (Tdead). This was a hindrance to accurate inverter control.

  FIG. 15 shows an overcurrent protection circuit included in the drive control circuit of FIG. When the current Irs flows through the sense resistor Rs connected to the IGBT 2, a potential of VRs = Rs · Irs is generated at one end of the sense resistor. When the potential VRs exceeds a predetermined trip level, it is detected by the overcurrent protection circuit 3 ′ that a short circuit has occurred, the operation of the drive control means 4 ′ is stopped, and the short circuit protection functions. However, there is a variation in the sense resistance, and there is also a variation in the trip level set in the overcurrent protection circuit 3 ′. For this reason, the short-circuit current protection value also varies, making accurate short-circuit protection difficult.

  Further, when the slope of the current change at the rise and fall of the collector current of each IGBT is increased, a large amount of noise is generated. On the other hand, when the slope is gentle, the switching loss is increased. Thus, there is a trade-off relationship between noise generation and switching loss. Therefore, conventionally, an optimum drive control circuit is required for each IGBT so that driving suitable for the actual use state of the IGBT can be performed.

The present invention has been made to solve the above-described problems,
By trimming the electrical characteristics of the device, there is no variation between each device, and a semiconductor device capable of highly accurate inverter control,
A semiconductor device capable of performing short-circuit protection and over-temperature protection with high accuracy;
An object of the present invention is to provide a semiconductor device capable of optimally setting the rising and falling slopes of the collector current of the output device.

  The present invention is characterized in that a semiconductor device used for driving a semiconductor switching element has characteristic correction means for correcting the characteristic of the semiconductor switching element based on a characteristic correction input signal.

  According to a first aspect of the present invention, a semiconductor switching element, a drive control means for controlling the driving of the semiconductor switching element based on an input signal, and a transmission delay time for the drive control means based on an input signal for characteristic correction are optionally set. And characteristic correction means for eliminating variations in delay time in each semiconductor element.

  According to a second aspect of the present invention, there is provided a semiconductor switching element, a current detection means for detecting a current flowing through the semiconductor switching element, and the semiconductor switching element when a detection signal from the current detection means exceeds a specified trip level. It has overcurrent protection means for stopping the operation of the element, and characteristic correction means for correcting the trip level.

  According to a third aspect of the invention (corresponding to claim 1), the semiconductor switching element, the temperature detecting means for detecting the operating temperature of the semiconductor switching element, and the detection signal from the temperature detecting means have exceeded a specified trip level. And an over-temperature protection means for stopping the operation of the semiconductor switching element, and a characteristic correction means for correcting the trip level.

According to a fourth aspect of the present invention, there is provided a semiconductor device comprising a semiconductor switching element and drive control means for controlling the drive of the semiconductor switching element based on an input signal
The drive control means includes a plurality of drive devices having different drive capacities, and any one or more of the drive devices are selected and used to correct the operating characteristics of the semiconductor switching element. The correction means is provided.

  In the present invention, since the characteristics of the semiconductor switching element are corrected, various variations in each semiconductor device can be corrected, and a highly accurate inverter device can be provided.

  According to the first aspect of the present invention, the delay time variation in the semiconductor switching element is eliminated by setting an appropriate delay time in the drive circuit, so that it is not necessary to set the input pause time period (Tdead). High-precision inverter control is possible.

  According to the second aspect of the present invention, the trip level used as an overcurrent determination criterion can be arbitrarily corrected, so that short circuit protection can be performed with high accuracy.

  According to the third aspect of the present invention, the trip level used as the overtemperature determination criterion can be arbitrarily corrected, so that overtemperature protection can be performed with high accuracy.

  According to the fourth aspect of the present invention, the drive circuit includes a plurality of drive devices having different current capacities, and an appropriate one can be selected from the drive devices, so that the collector current rises and falls in the semiconductor switching element. Can be set at will.

  The characteristic correction means can be easily realized by a non-volatile memory as in claim 2 or a one-time ROM as in claim 3. Further, the characteristic correction means realized by these nonvolatile memories and one-time ROM can be easily integrated and built in the semiconductor device as in the fourth aspect.

Embodiment 1
FIG. 1 is a control block diagram showing a first embodiment of the present invention. The drive control circuit 1 is a U-phase IGBT 1 serially connected between P2 and N2 which are output terminals of the power module, based on an input signal UPin from the signal input terminal and an input signal UNin from the signal input terminal. , Output signals UPout and UNout are supplied to the respective gates of IGBT2. In FIG. 1, only the U-phase is described, but a circuit for driving the V-phase IGBT 3 and IGBT 4 and the W-phase IGBT 5 and IGBT 6 is included.

  A detailed circuit diagram of the drive control circuit 1 and the characteristic correction circuit 2 is shown in FIG. In the drive control circuit 1, the logic circuit 11 outputs the input signal UPin to the line L1 in the delay insertion circuit 12 as a logic signal. In the delay insertion circuit 12, capacitances C1, C2, and C3 are connected to the line L1 and the ground through switches S1, S2, and S3, respectively. Further, the current I1 is supplied to the line L1.

  The line L1 is connected to the line L2 in the delay insertion circuit 13 via the inverter INV1. Also in the delay insertion circuit 13, capacitances C4, C5, and C6 are connected between the line L2 and the ground via switches S4, S5, and S6, respectively. Further, the current I2 is supplied to the line L2. The line L2 is connected to the drive circuit 14 via the inverter INV2. A drive signal UPout for driving the IGBT 1 is output from the drive circuit 14.

  The capacitances of the capacitances C1, C2, C3 and the capacitances C4, C5, C6 may be the same, or may be different from each other. Further, the number of capacitances is not limited to three.

  In the characteristic correction circuit 2, the characteristic correction signal is written into the EPROM 22 by the writing circuit 21, and the data in the EPROM 22 is latched in the register 23. The latch data d1 to d6 from the register 23 are supplied as drive signals for the switches S1 to S6. Therefore, the switches S1 to S6 can be switched on and off in a desired state by the characteristic correction signal.

  The operation of the drive control circuit 1 of FIG. 2 will be described according to the timing chart of FIG. Unlike the one shown in FIG. 14, the input signal UNin does not include the input pause time (Tdead) and is completely synchronized with the input signal UPin only by inverting the level. The delay time t11 is a delay time in the drive control circuit 1 required from the level inversion of the input signal UPin from high to low to the level inversion of the output signal UPout from low to high. When OFF, the delay time in the delay insertion circuit 12 is 0, and the magnitude of the delay time t11 at this time corresponds to the delay time t1 in FIG.

  The delay time t12 is a delay time in the drive control circuit 1 required from the level inversion of the input signal UPin from low to high to the level inversion of the output signal UPout from high to low, and all the switches S4 to S6 are used. Since the delay time in the delay insertion circuit 33 is 0 when it is off, the magnitude of the delay time t12 at this time corresponds to the delay time t2 in FIG.

  In the drive control circuit 1 of FIG. 2, only the circuit for the input signal UPin is shown, and the same circuit (delay insertion circuit and characteristic correction circuit) is also provided for the other input signals UNin, VPin, VNin, WPin, WNin. Prepare. Therefore, the delay time t13 is a delay time from the level inversion of the input signal UNin from low to high to the level inversion of the output signal UNout from high to low, and the delay time t14 is from high to low of the input signal UNin. Is the delay time from the level inversion until the level inversion of the output signal UNout from low to high. These delay times can also be arbitrarily set similarly to t11 and t12.

  In the IGBT 1, the output signal UPout is inverted from low to high after a delay time t 11 from the inversion level of UPin from high to low, and the IGBT 1 is switched on after tonP (response time of the IGBT 1). Therefore, the IGBT 1 is switched on after tconP from the level inversion of the input signal UPin from high to low.

  In the IGBT 1, the output signal UPout is inverted from high to low after a delay time t 12 from the inversion level of UPin from low to high, and the IGBT 1 is switched off after toffP (response time of the IGBT 1). Accordingly, the IGBT 1 is switched off after tcoffP from the level inversion of the input signal UPin from low to high.

  Similarly, in the IGBT 2, the output signal UNout is inverted in level from high to low after a delay time t13 from the inversion level of UNin from low to high, and the IGBT 2 is switched off after toffN (response time of IGBT2). Accordingly, the IGBT 2 is switched off after tcoffN from the level inversion of the input signal UNin from low to high.

  Then, after the delay time t14 from the inversion level of UNin from high to low, the output signal UNout is inverted from low to high, and the IGBT2 is switched on after tonN (also the response time of the IGBT2). Accordingly, the IGBT 1 is switched on after tconN from the level inversion of the input signal UNin from high to low.

  Even if the input signals UPin and UNin are synchronized as shown in FIG. 3, the delay time in the drive control circuit 1 and the reaction time of the IGBT itself vary, so that tconP ≠ tcoffN, and the IGBT 1 is switched on and the IGBT 2 is switched off. Does not match. Similarly, since tcoffP ≠ tconN, the switch-off of IGBT1 and the switch-on of IGBT2 do not match.

However, with the characteristic correction signal,
All switches off Any one switch on Any two switches on All switches on By selecting either of the switches, the delay time of t11 and t13 can be adjusted. By this operation, as shown in FIG. If tconP≈tcoffN, IGBT1 is switched on and IGBT2 is switched off at the same timing. Similarly, if the delay times t12 and t14 are adjusted so that tcoffP≈tconN, IGBT1 is switched off and IGBT2 is switched on at the same timing.

  Thus, if tconP≈tcoffN and tcoffP≈tconN, it is possible to eliminate variations in the delay time of the entire device including the response time of the drive control means 1 and the IGBT itself. ) Is unnecessary, and highly accurate inverter control is possible. Since the delay time drifts slightly due to temperature changes and aging changes, it is desirable to set Tdead so as to cover the drift. However, since Tdead in this case is much shorter than the conventional one, it does not become an obstacle when performing highly accurate inverter control.

  A non-volatile memory or a one-time ROM can be used for the EPROM 22 of the characteristic correction circuit 2, and such a characteristic correction circuit 2 can be integrated and incorporated in the drive control circuit 1.

Embodiment 2
FIG. 4 is a control block diagram showing a second embodiment of the present invention, and details thereof are shown in FIG. The drive control circuit 4 includes a logic circuit 41 that outputs an input signal C as a logic signal, and a drive circuit 42 that outputs a drive signal c in accordance with the logic signal.

  The overcurrent protection circuit 3 includes a comparator 31, and Vs generated at one end of the sense resistor Rs connected to the second emitter of the IGBT 2 is input to a non-inverting input portion thereof. The reference voltage Vref is divided by four series-connected resistors, and the divided voltages Vref1 to Vref3 are selected by the switches S1 to S3 and input to the inverting input unit of the comparator 31 as a trip level. The output of the comparator 31 is output to the logic circuit 41 as a cutoff signal.

  The characteristic correction circuit 5 is a circuit for turning on one of the switches S1 to S3, and its circuit configuration is the same as that of the characteristic correction circuit 2 of FIG. The characteristic correction circuit 5 can also use a non-volatile memory or a one-time ROM as an EPROM, and can be integrated in the drive control circuit 4.

  As described above, conventionally, there are individual variations in the sense resistor Rs, the trip level set in the overcurrent protection circuit 3 and the shunt ratio of the emitter, so that the short-circuit current protection value also varies, and an accurate short circuit occurs. Although it was difficult to protect, in this embodiment, as shown in FIG. 6, the trip level can be changed to Vref1, Vref2, and Vref3, and an accurate trip level is set by setting an appropriate trip level based on the actual measurement result. Current protection is possible. The number of trip levels that can be changed is not limited to three.

Embodiment 3
FIG. 7 is a control block diagram showing a third embodiment of the present invention, and details of FIG. 7 are shown in FIG. 7 and 8, elements common to those in FIGS. 4 and 5 are denoted by common reference numerals. The overtemperature protection circuit 7 itself has the same circuit configuration as the overcurrent protection circuit 3, but the temperature signal Vt detected by the temperature detection means 8 is taken into the non-inverting input portion of the comparator 71.

  When the operating temperature of the IGBT 1 becomes high and the temperature signal Vt exceeds a predetermined trip level, a predetermined cutoff signal is supplied to the drive control circuit 4 so that the drive signal d is cut off from the input signal D. However, in this overtemperature protection circuit 7 as well, there are variations in overtemperature protection trip level and temperature detection means 8, so accurate overtemperature protection is difficult.

  Therefore, in the present embodiment, as shown in FIG. 9, the trip level can be changed to Vref1, Vref2, and Vref3, and an appropriate trip level is set based on the actual measurement result, thereby enabling accurate overtemperature protection.

Embodiment 4
FIG. 10 is a control block diagram showing a fourth embodiment of the present invention, and details thereof are shown in FIG. The drive control circuit 9 includes a logic circuit 91 that outputs an input signal E as a logic signal, and a drive circuit 92. The drains of the N-type FET transistors T1, T3, T5 are connected to the output terminal of the drive control circuit 9, and the gates are connected to the output part of the logic circuit 91 via the switches S1, S3, S5. Connected to the source of the transistor.

  The drains of the P-type FET transistors T2, T4, T6 are connected to the output terminal of the drive control circuit 9, and the gates are connected to the output part of the logic circuit 91 via the switches S2, S4, S6. Connected to the source of the transistor. Each of the switches S1 to S6 is driven by signals d1 to d6 from a register of the characteristic correction circuit 10.

  Of the transistors T1, T3, and T5, the transistor connected to the output portion of the logic circuit 91 is driven by the falling edge of the input signal E, and when the input signal E rises, the transistors T2, T4, and T6 Among them, the transistors connected to the output part of the logic circuit 91 are driven, and the output current of these driven transistors is output as the drive signal e.

  A timing chart at this time is shown in FIG. The drive signal e1 is when the transistors T1 and T2 are driven, and the drive signal e2 is when the transistors T3 and T4 are driven. The driving capabilities of the transistors T3 and T4 are larger than those of the transistors T1 and T2, and therefore the rising and falling edges of the driving signal e2 are looser than the driving signal e1. The collector currents of the IGBT2 in the drive signals e1 and e2 are indicated by I1 and I2.

  Conventionally, it has been necessary to change the drive capability of the drive control circuit for each current capacity of the IGBT, but according to the present embodiment, by selecting an appropriate one from among IGBTs having various drive capacities, The rising and falling slopes of the collector (output) current of the IGBT 2 can be arbitrarily selected. This characteristic correction circuit 10 can also use a non-volatile memory or a one-time ROM as an EPROM, and can be integrated in the drive control circuit 9.

  In addition to the combination of T1-T2, T3-T4, and T5-T6, the transistor to be driven may be a combination such as T1-T4, or a plurality of transistors may be simultaneously formed as (T1 + T3)-(T2 + T4). Combinations such as driving are also possible.

Control block diagram showing the first embodiment of the present invention Circuit diagram showing details of FIG. Signal timing chart in FIG. Control block diagram showing a second embodiment of the present invention Circuit diagram showing details of FIG. Timing chart of signals in FIG. Control block diagram showing a third embodiment of the present invention Circuit diagram showing details of FIG. Signal timing chart in FIG. Control block diagram showing a fourth embodiment of the present invention Circuit diagram showing details of FIG. Timing chart of signals in FIG. Circuit diagram showing the configuration of a conventional power module Timing chart showing input / output operation in FIG. Timing chart showing short-circuit protection operation

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Drive control circuit, 2 characteristic correction circuit, 3 overcurrent protection circuit, 4 drive control circuit, 5 characteristic correction circuit, 7 overtemperature protection circuit, 8 temperature detection means, 9 drive control circuit, 10 characteristic correction circuit, 11 logic circuit , 12 Delay insertion circuit, 13 Delay insertion circuit, 21 Write circuit, 22 EPROM, 23 Register, 91 Logic circuit, 92 Drive circuit

Claims (4)

  Semiconductor switching element, temperature detecting means for detecting an operating temperature of the semiconductor switching element, and over temperature protection for stopping the operation of the semiconductor switching element when a detection signal from the temperature detecting means exceeds a specified trip level And a characteristic correcting means for correcting the trip level.   The semiconductor device according to claim 1, wherein the characteristic correction unit is a nonvolatile memory.   The semiconductor device according to claim 1, wherein the characteristic correction unit is a one-time ROM. 4. The semiconductor device according to claim 2, wherein the characteristic correction means realized by a non-volatile memory or a one-time ROM is integrated and incorporated.

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