JP2005327178A - Processor, its compiler, and information processor including it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor capable of reducing power consumption in a peak time. <P>SOLUTION: This processor includes an instruction decode part 11 decoding a fetched instruction and a plurality of computing units from 12-1 to 12-4 executing computing according to a decode result by the instruction decode part 11. The instruction decode part 11 retracts dependent data to a register to use them when fetched instructions are parallel instructions including a plurality of instructions and there is dependency between a plurality of instructions. In this way, the parallel instructions are sequentially operated by a part of the computing units among the plurality of computing units from 12-1 to 12-4. Therefore, a part of the computing units are not required to be operated, and consequently, power consumption in the peak time can be lowered. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a processor capable of simultaneously executing a plurality of instructions such as a VLIW (Very Long Instruction Word) method and a superscalar, a processor capable of reducing power consumption, a compiler thereof, and information including the same The present invention relates to a processing apparatus.

  In recent years, with the progress of informatization in society, there has been a demand for improving the performance of processors for performing advanced information processing. One method for realizing such an improvement in processor performance is that one processor executes a plurality of instructions simultaneously. As such a processor, a processor such as a VLIW system or a superscalar is known.

  A VLIW processor has a plurality of computing units. A compiler detects parallelism of instructions when compiling a program, and generates instructions that can be executed in parallel. The processor can execute instructions that can be executed in parallel by a plurality of arithmetic units in parallel, thereby improving the processing speed.

  The superscalar has a plurality of pipelines for processing instructions, and detects instruction level parallelism from a program described as sequential instructions by hardware at the time of instruction execution. The scheduler inputs the instructions that can be executed in parallel into each pipeline, thereby improving the processing speed.

  On the other hand, LSIs (Large Scale Integrated circuits) in which large-scale circuits are integrated are often used not only in workstations and personal computers but also in household electrical products such as televisions and mobile phones. In such household electric products, it is required to reduce the power consumption of the products, and this is particularly noticeable in mobile phones and the like. Along with this, low power consumption is also required in LSIs. As related technologies, Non-Patent Document 1 regarding the reduction in power consumption of a VLIW processor and Non-Patent Document 2 regarding the reduction of power consumption of a multimedia processor can be cited.

In addition, in the data processing device described in Patent Document 1, a detection unit that decodes an instruction and detects that the instruction is an instruction that executes a plurality of operations, and an instruction that executes a plurality of operations by the detection unit When a certain number of operations is detected, a field rearrangement unit that rearranges some fields of the instruction based on the operation order based on a predetermined number of operations, and a plurality of cycles in synchronization with the order of the rearranged fields A decoder including an arithmetic control unit that performs control for executing an operation in the computer, and an arithmetic unit that executes an operation by dividing an instruction into a plurality of cycles based on control from the arithmetic control unit.
JP-A-7-253888 Low-Power VLIW Processors: A High-Level Evaluation. JM Puiatti, C. Piguet, E. Sanchez, J. Llosa. Proc. Of Int. Workshop-Power and Timing Modeling, Optimization and Simulation) Low-Power Architectures for Programmable Multimedia Processors. Takao NISHITANI. IEICE TRANS. FUNDAMENTALS, VOL.E82-A, NO.2 Feb. 1999)

  In the above-described VLIW processor and superscalar, a plurality of arithmetic units always operate. For this reason, there is a problem in that power consumption increases even under operating conditions that do not require high processing capacity or under operating conditions where it is desired to reduce power consumption.

  Further, the data processing apparatus described in Patent Document 1 provides a compact and low power consumption data processing apparatus by processing a composite instruction having a plurality of operations corresponding to or divided into several execution units. be able to. However, since it is not disclosed under what conditions the compound instruction is divided and processed, this data processing apparatus cannot be incorporated into the system as it is.

  The present invention has been made to solve the above problems, and a first object of the present invention is to provide a processor capable of reducing power consumption at a peak time and an information processing apparatus including the processor. is there.

  A second object is to provide a compiling device that generates instruction code so that power consumption at a peak time in a processor can be reduced.

  According to one aspect of the present invention, a processor capable of executing a plurality of instructions simultaneously, an instruction decoding unit for decoding a fetched instruction, and an operation according to a decoding result by the instruction decoding unit The instruction decoding means is a parallel instruction including a plurality of instructions and there is a dependency between the plurality of instructions. By saving certain data in a register and using it, a parallel instruction is sequentially executed by some of the arithmetic means.

  According to another aspect of the present invention, a processor capable of simultaneously executing a plurality of instructions, an instruction decoding unit for decoding a fetched instruction, and a decoding result by the instruction decoding unit, A plurality of arithmetic means for performing an operation, and the instruction decoding means determines that an exception is given if the fetched instruction is a parallel instruction including a plurality of instructions and there is a dependency between the plurality of instructions. By generating and emulating parallel instructions by software, the parallel instructions are sequentially executed by some of the arithmetic means.

  According to still another aspect of the present invention, there is provided a processor capable of executing a plurality of instructions at the same time, according to an instruction decoding means for decoding a fetched instruction, and a decoding result by the instruction decoding means. A plurality of arithmetic means for executing an operation and a storage means for storing an instruction, wherein the instruction decoding means is a parallel instruction in which the fetched instruction includes a plurality of instructions, and the plurality of instructions When there is a dependency between the parallel instructions, the parallel instructions are converted into sequential instruction groups, stored in the storage means, and the sequential instruction groups are sequentially read out, so that the parallel instructions are partially calculated among the plurality of calculation means. Are executed sequentially.

  According to still another aspect of the present invention, there is provided a processor capable of executing a plurality of instructions at the same time, according to an instruction decoding means for decoding a fetched instruction, and a decoding result by the instruction decoding means. The instruction decoding means generates an exception and emulates the coprocessor instruction in software by generating an exception if the fetched instruction is a coprocessor instruction. A processor instruction is executed by a plurality of arithmetic means.

  According to still another aspect of the present invention, a compiler for compiling a program executed by a processor capable of executing a plurality of instructions simultaneously, wherein the instructions are parallel instructions including a plurality of instructions, and Condition determining means for determining whether or not there is a dependency between a plurality of instructions, and when the condition determining means determines that there is a dependency, the parallel instruction is converted into an instruction code of a sequential instruction and output Instruction code generation means.

  According to still another aspect of the present invention, a compiler for compiling a program executed by a processor capable of executing a plurality of instructions simultaneously, wherein the instructions are parallel instructions including a plurality of instructions, and Condition determining means for determining whether or not the power consumption of a plurality of instructions is greater than or equal to a predetermined value, and when the condition determination means determines that the power consumption is greater than or equal to a predetermined value, the parallel instructions are sequentially instructions Instruction code generation means for converting the code into a code and outputting the code.

  According to still another aspect of the present invention, a compiler for compiling a program executed by a processor capable of executing a plurality of instructions simultaneously, wherein the instructions are parallel instructions including a plurality of instructions, and Condition determining means for determining whether or not the power consumption of a plurality of instructions is greater than or equal to a predetermined value, and when the condition determination means determines that the power consumption is greater than or equal to a predetermined value, the plurality of instructions included in the parallel instruction Instruction code generation means for generating an instruction code by replacing any of the instructions with the preceding and succeeding instructions.

  According to still another aspect of the present invention, there is provided an information processing apparatus including a processor capable of executing a plurality of instructions simultaneously and a measuring unit for measuring temperature, wherein the processor is fetched An instruction decoding means for decoding an instruction, and a plurality of operation means for executing an operation according to a result of decoding by the instruction decoding means, and when the temperature measured by the measuring means is a predetermined value or more, the instruction If the fetched instruction is a parallel instruction including a plurality of instructions, the decoding means converts the parallel instruction into a sequential instruction so that the parallel instruction is sequentially transferred to a part of the plurality of arithmetic means. To run.

  According to still another aspect of the present invention, there is provided an information processing apparatus including a processor capable of executing a plurality of instructions at the same time and a measurement unit for measuring current, wherein the processor is fetched An instruction decoding means for decoding an instruction and a plurality of arithmetic means for executing an operation according to a decoding result by the instruction decoding means, and a current supplied to the information processing device measured by the measuring means When the value is equal to or greater than the predetermined value, the instruction decoding means converts the parallel instruction into one of the plurality of arithmetic means by converting the parallel instruction into a sequential instruction if the fetched instruction is a parallel instruction including a plurality of instructions. Are sequentially executed by the operation means of the unit.

  According to still another aspect of the present invention, there is provided an information processing apparatus including a processor capable of simultaneously executing a plurality of instructions, the processor comprising: instruction decoding means for decoding the fetched instruction; A plurality of arithmetic means for executing an operation according to a result of decoding by the instruction decoding means, and when an externally input signal indicates a predetermined value, the instruction decoding means includes a plurality of fetched instructions If the instruction includes a parallel instruction, the parallel instruction is converted into a sequential instruction, whereby the parallel instruction is sequentially executed by some of the arithmetic means.

  According to still another aspect of the present invention, an information processing apparatus including a processor capable of executing a plurality of instructions simultaneously and a rewritable register, wherein the processor decodes a fetched instruction Instruction decoding means for performing the operation and a plurality of operation means for executing the operation according to the result of decoding by the instruction decoding means, and when the predetermined value is stored in the register, the instruction decoding means is fetched If the received instruction is a parallel instruction including a plurality of instructions, the parallel instruction is sequentially executed by some of the plurality of operation means by converting the parallel instruction into a sequential instruction.

  According to an aspect of the present invention, the instruction decoding unit registers the dependent data when the fetched instruction is a parallel instruction including a plurality of instructions and there is a dependency between the plurality of instructions. By saving and using, the parallel instructions are sequentially executed by some of the computing means among the plurality of computing means, so there is no need to operate a part of the computing means and the power consumption at the peak time is reduced. It became possible to reduce.

  According to another aspect of the present invention, the instruction decoding means generates an exception when the fetched instruction is a parallel instruction including a plurality of instructions and there is a dependency between the plurality of instructions, and performs parallel processing. By emulating instructions with software, parallel instructions are executed sequentially by some of the computing means, eliminating the need to operate some of the computing means and power consumption during peak hours Can be reduced.

  According to still another aspect of the present invention, when the instruction decode means is a parallel instruction including a plurality of instructions and the dependency is between the plurality of instructions, the parallel instruction is sequentially processed. By converting the data into groups and storing them in the storage means, and sequentially reading out the sequential instruction group, the parallel instructions are sequentially executed by some of the arithmetic means. It is no longer necessary to operate, and it is possible to reduce power consumption during peak hours.

According to yet another aspect of the present invention, if the instruction decoding means is a coprocessor instruction, the instruction decoding means generates an exception and emulates the coprocessor instruction in software, thereby generating a plurality of coprocessor instructions. According to still another aspect of the present invention, there is a dependency depending on the condition determination means. If it is determined that the instruction code is generated, the instruction code generation means converts the parallel instruction into the instruction code of the sequential instruction and outputs the instruction code, so that the instruction code is generated so that the power consumption at the peak time of the processor can be reduced. It became possible.

  According to still another aspect of the present invention, when the condition determining unit determines that the power consumption is equal to or greater than a predetermined value, the instruction code generating unit converts the parallel instruction into an instruction code of a sequential instruction and outputs the instruction code. The instruction code can be generated so that the power consumption at the peak time of the processor can be reduced.

  According to still another aspect of the present invention, when the condition determination unit determines that the power consumption is equal to or greater than a predetermined value, the instruction code generation unit replaces any of the plurality of instructions included in the parallel instruction with the preceding and following instructions. Therefore, the instruction code can be generated so that the power consumption at the peak time of the processor can be reduced.

  According to still another aspect of the present invention, when the temperature measured by the measuring unit is equal to or higher than a predetermined value, the instruction decoding unit outputs the parallel instruction if the fetched instruction includes a plurality of instructions. By converting to sequential instructions, parallel instructions are sequentially executed by some of the computing means among a plurality of computing means, so that the temperature of the information processing device can be prevented from becoming higher than necessary, and the processor malfunctions. Etc. can be prevented.

  According to still another aspect of the present invention, when the current supplied to the information processing apparatus measured by the measuring unit is equal to or greater than a predetermined value, the instruction decoding unit is configured to execute a parallel instruction in which the fetched instruction includes a plurality of instructions. If so, by converting the parallel instruction into the sequential instruction, the parallel instruction is executed sequentially by some of the arithmetic means, so that the current supplied to the information processing device is more than necessary. It is possible to prevent the processor from becoming large and to prevent malfunction of the processor.

  According to still another aspect of the present invention, when the signal input from the outside indicates a predetermined value, the instruction decoding means outputs the parallel instruction if the fetched instruction includes a plurality of instructions. By converting to sequential instructions, the parallel instructions are sequentially executed by some of the plurality of computing means, so that the low power consumption mode can be switched from the outside.

  According to still another aspect of the present invention, when a predetermined value is stored in the register, the instruction decoding means converts the parallel instruction into a sequential instruction if the fetched instruction is a parallel instruction including a plurality of instructions. By converting, the parallel instructions are sequentially executed by some of the arithmetic means among the plurality of arithmetic means, so that the low power consumption mode can be switched by the program.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a VLIW processor according to the first embodiment of the present invention. The VLIW processor includes an instruction decode unit 11 that decodes an instruction sequence fetched by an instruction fetch unit (not shown), and a plurality of arithmetic units (PUs) 12 that execute an instruction sequence according to a decoding result by the instruction decode unit 11. -1 to 12-4.

  FIG. 2 is a diagram illustrating an example of an instruction format executed by the VLIW processor according to the first embodiment of this invention. This instruction format is composed of 32 bits. When the MSB (Most Significant Bit) 21 is “0”, it is composed of two 16-bit instructions, and when the MSB 21 is “1”, it is composed of one 32-bit instruction.

  Further, when the MSB 21 is “0” and the MSB 22 is “0”, two 16-bit instructions are sequentially executed. Further, when the MSB 21 is “0” and the MSB 22 is “1”, it indicates that two 16-bit instructions are executed in parallel. In FIG. 2, the MSB 21 indicates one 32-bit instruction or two 16-bit instructions. However, the instruction field is divided into three or more fields, and three or more instruction Sequential execution / parallel execution may be selected. Further, the number of bits of the instruction is not limited to this.

  FIG. 3 is a flowchart for explaining the processing procedure of the VLIW processor according to the first embodiment of this invention. As an example of the processing procedure, the case where the instruction shown in FIG. 2 is executed by the VLIW processor shown in FIG. 1 will be described, and only the arithmetic units 12-1 and 12-2 operate.

  First, when the instruction is two 16-bit instructions (MSB21 = 0) and executed in parallel (MSB22 = 1), the instruction decoding unit 11 determines whether or not the low power consumption mode is set according to the low power consumption mode signal. Is determined (S11). When the instruction is one 32-bit instruction (MSB21 = 1), the instruction decoding unit 11 outputs the decoding result to the arithmetic unit 12-1 or 12-2 to execute the 32-bit instruction.

  In the case of sequential execution of two 16-bit instructions (MSB21 = 0, MSB22 = 0), the instruction decoding unit 11 sends the decoding result of the higher-order 16-bit instruction to the arithmetic unit 12-1 or 12-2 in the first cycle. The first 16-bit instruction is executed by outputting, and the decoding result of the lower 16-bit instruction is output to the arithmetic unit 12-1 or 12-2 in the next cycle, so that the next 16-bit instruction is executed.

  When not in the low power consumption mode (S11, No), the instruction decoding unit 11 outputs two 16-bit instructions in parallel by simultaneously outputting the decoding results of the two 16-bit instructions to the arithmetic units 12-1 and 12-2. (S15).

  In the case of the low power consumption mode (S11, Yes), the instruction decoding unit 11 determines whether there is a dependency between the two 16-bit instructions by decoding the two 16-bit instructions (S12). ).

  If there is no dependency between two 16-bit instructions, that is, the destination operand of one 16-bit instruction is not the source operand of the other 16-bit instruction and one 16-bit instruction is If the condition bit is changed and the other 16-bit instruction does not refer to the condition bit (S12, No), the process proceeds to step S14.

  Also, if there is a dependency between two 16-bit instructions, that is, if the destination operand of one 16-bit instruction is the source operand of the other 16-bit instruction, or one 16-bit instruction When the instruction changes the condition bit and the other 16-bit instruction refers to the condition bit (Yes in S12), the instruction decoding unit 11 saves the operand value and the condition bit value in the backup register ( S13).

  In step S14, the instruction decoding unit 11 ignores the value of the MSB 22 and assumes that it is “0”, and sequentially executes two 16-bit instructions. That is, the instruction decoding unit 11 executes the first 16-bit instruction by outputting the decoding result of the upper 16-bit instruction to the arithmetic unit 12-1 or 12-2 in the first cycle, and lower-order in the next cycle. By outputting the decoding result of the 16-bit instruction to the arithmetic unit 12-1 or 12-2, the next 16-bit instruction is executed.

  When there is a dependency relationship between two 16-bit instructions, the instruction decoding unit 11 performs an operation using the value saved in the backup register when the arithmetic unit executes the second instruction. Two 16-bit instructions are operated by the same arithmetic unit, and the other arithmetic unit does not operate.

  Here, there are cases where two 16-bit instructions are instructions that change the condition bit, but since it is prohibited to generate such instructions that are executed in parallel originally, There is no need to consider the case.

  In addition, power consumption can be further reduced by stopping the supply of a clock, a power supply, and the like to a computing unit that is no longer used.

  In addition, when trying to use a resource such as a computing unit that has stopped supplying a clock or power, an exception may be generated and emulated by software.

  Also, if you try to use a resource such as a computing unit that has stopped supplying clocks and power, etc., restart the supply of clocks and power to that resource, make them available, and then issue an instruction. You may make it perform.

  As described above, according to the VLIW processor of the present embodiment, the instruction decode unit 11 is set to 2 when it is in the low power consumption mode and two 16-bit instructions are executed in parallel. Since one 16-bit instruction is sequentially executed by one arithmetic unit, it is not necessary to operate some arithmetic units. As a result, it is not necessary to operate a circuit such as an arithmetic unit at the same time, and the power consumption at the peak time can be reduced.

(Second Embodiment)
The schematic configuration of the VLIW processor in the second embodiment of the present invention is the same as the schematic configuration of the VLIW processor in the first embodiment shown in FIG. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  FIG. 4 is a flowchart for explaining the processing procedure of the VLIW processor according to the second embodiment of the present invention. First, when the instruction is two 16-bit instructions (MSB21 = 0) and executed in parallel (MSB22 = 1), the instruction decoding unit 11 determines whether or not the low power consumption mode is set according to the low power consumption mode signal. Is determined (S21).

  When not in the low power consumption mode (S21, No), the instruction decode unit 11 outputs the two 16-bit instructions in parallel by simultaneously outputting the decoding results of the two 16-bit instructions to the arithmetic units 12-1 and 12-2. This is executed (S26).

  In the case of the low power consumption mode (S21, Yes), the instruction decoding unit 11 determines whether there is a dependency between the two 16-bit instructions by decoding the two 16-bit instructions (S22). ).

  If there is no dependency between two 16-bit instructions, that is, the destination operand of one 16-bit instruction is not the source operand of the other 16-bit instruction and one 16-bit instruction is If the condition bit is changed and the other 16-bit instruction does not refer to the condition bit (No at S22), the instruction decode unit 11 ignores the value of the MSB 22 and assumes that it is “0”, and two 16-bit instructions Are sequentially executed (S25).

  Also, if there is a dependency between two 16-bit instructions, that is, if the destination operand of one 16-bit instruction is the source operand of the other 16-bit instruction, or one 16-bit instruction When the instruction changes the condition bit and the other 16-bit instruction refers to the condition bit (S22, Yes), the instruction decoding unit 11 generates an exception and activates the exception handler (S23). By starting the exception handler, a parallel instruction is emulated, and the parallel instruction is executed as a plurality of sequential instructions (S24). It is assumed that an exception handler is stored in advance in the instruction memory.

  When executing a coprocessor instruction in the low power consumption mode, a coprocessor instruction exception may be generated regardless of the presence or absence of the coprocessor, and the coprocessor instruction may be emulated by activating an exception handler. As a result, it is not necessary to operate the coprocessor, and power consumption can be reduced.

  As described above, according to the VLIW processor in the present embodiment, it is shown that the low power consumption mode is executed, and two 16-bit instructions are executed in parallel. When there is a dependency relationship, the instruction decode unit 11 generates an exception and activates the exception handler. In addition to the effects described in the first embodiment, saving of registers and the like is not necessary. It became possible to simplify the hardware configuration.

(Third embodiment)
The schematic configuration of the VLIW processor in the third embodiment of the present invention is the same as the schematic configuration of the VLIW processor in the first embodiment shown in FIG. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  FIG. 5 is a flowchart for explaining the processing procedure of the VLIW processor according to the third embodiment of the present invention. First, when the instruction is two 16-bit instructions (MSB21 = 0) and executed in parallel (MSB22 = 1), the instruction decoding unit 11 determines whether or not the low power consumption mode is set according to the low power consumption mode signal. Is determined (S31).

  When not in the low power consumption mode (S31, No), the instruction decode unit 11 outputs two 16-bit instructions in parallel by simultaneously outputting the decoding results of the two 16-bit instructions to the arithmetic units 12-1 and 12-2. This is executed (S36).

  In the case of the low power consumption mode (S31, Yes), the instruction decoding unit 11 determines whether there is a dependency between the two 16-bit instructions by decoding the two 16-bit instructions (S32). ).

  If there is no dependency between two 16-bit instructions, that is, the destination operand of one 16-bit instruction is not the source operand of the other 16-bit instruction and one 16-bit instruction is When the condition bit is changed and the other 16-bit instruction does not refer to the condition bit (No in S32), the instruction decoding unit 11 ignores the value of the MSB 22 and assumes that the value is “0”. Are sequentially executed (S25).

  Also, if there is a dependency between two 16-bit instructions, that is, if the destination operand of one 16-bit instruction is the source operand of the other 16-bit instruction, or one 16-bit instruction When the instruction changes the condition bit and the other 16-bit instruction refers to the condition bit (S32, Yes), the parallel instruction having this dependency relation is converted into a sequential instruction group having the same meaning operation, and the high-speed operation is performed. It is stored in an accessible memory (cache memory, SRAM (Static Random Access Memory)). In the memory capable of high-speed access, an area for storing the sequential instruction group is secured in advance, and the sequential instruction group is fetched by the instruction fetch unit reading the sequential instruction group directly from this area. .

  Then, the instruction decode unit 11 sequentially decodes the fetched sequential instruction group, and outputs the decoded result to the same arithmetic unit, so that sequential execution is performed (S34).

  As described above, according to the VLIW processor in the present embodiment, it is shown that the low power consumption mode is executed, and two 16-bit instructions are executed in parallel. When there is a dependency relationship between the parallel instructions, the parallel instructions are converted into a sequential instruction group, stored in a memory that can be accessed at high speed, and the sequential instruction group is executed sequentially, which will be described in the first embodiment. In addition to the effects described above, it is possible to prevent a decrease in processing speed when parallel instructions are converted into sequential instructions and executed.

(Fourth embodiment)
FIG. 6 is a block diagram illustrating a configuration example of the compiling device according to the fourth embodiment of the present invention. The compiling device includes a computer main body 31, a display device 32, an FD drive 33 to which an FD (Flexible Disk) 34 is mounted, a keyboard 35, a mouse 36, and a CD to which a CD-ROM (Compact Disc-Read Only Memory) 38 is mounted. -ROM device 37 and network communication device 39 are included.

  A compile program (hereinafter referred to as a compiler) is supplied by a recording medium such as the FD 34 or the CD-ROM 38. By executing the compiler by the computer main body 31, object code is generated from the program. The compiler may be supplied to the computer main body 31 from another computer via the network communication device 39.

  The computer main body 31 shown in FIG. 6 includes a CPU (Central Processing Unit) 40, a ROM (Read Only Memory) 41, a RAM 42, and a hard disk 43. The CPU 40 performs processing while inputting / outputting data to / from the display device 32, FD drive 33, keyboard 35, mouse 36, CD-ROM device 37, network communication device 39, ROM 41, RAM 42 or hard disk 43.

  The compiler recorded in the FD 34 or the CD-ROM 38 is stored in the hard disk 43 by the CPU 40 via the FD drive 33 or the CD-ROM device 37. The CPU 40 appropriately loads a compiler from the hard disk 43 into the RAM 42 and executes it, thereby generating object code from the program.

  FIG. 7 is a block diagram showing a functional configuration of a compiling device according to the fourth embodiment of the present invention. The compiling device extracts a mode determination unit 51 that determines whether or not a low power consumption mode is selected, and extracts instructions one by one from the source file, analyzes the instructions, and determines whether or not a predetermined condition is satisfied. It includes a condition determination unit 52 for determination, and an instruction code generation unit 53 that generates an instruction code according to the determination results by the mode determination unit 51 and the condition determination unit 52 and outputs the generated instruction code.

  FIG. 8 is a flowchart for explaining the processing procedure of the compiling apparatus according to the fourth embodiment of the present invention. Note that the compiling apparatus according to the present embodiment has an option of outputting a code for reducing power consumption, and the setting of the low power consumption mode is performed by user designation or the like.

  First, the mode determination unit 51 determines whether or not the low power consumption mode is designated (S41). When the mode determination unit 51 determines that the low power consumption mode is not designated (S41, No), the instruction code generation unit 53 generates and outputs the instruction code as it is from the instruction (S44). That is, if the instruction is a parallel instruction of two 16-bit instructions, an instruction code that is executed in parallel by a VLIW processor is generated and output. If the instruction is a sequential instruction of two 16-bit instructions, an instruction code that is sequentially executed by a VLIW processor is generated and output. If the instruction is a 32-bit instruction, an instruction code of the 32-bit instruction is generated and output.

  When the mode determination unit 51 determines that the low power consumption mode is designated (S41, Yes), the condition determination unit 52 determines that two 16-bit instructions are parallel if the instruction is a parallel instruction of two 16-bit instructions. It is determined whether there is a dependency between them (S42).

  If the condition determination unit 52 determines that there is no dependency between two 16-bit instructions, that is, the destination operand of one 16-bit instruction is the source operand of the other 16-bit instruction. If one 16-bit instruction changes the condition bit and the other 16-bit instruction does not refer to the condition bit (S42, No), the process of step S44 described above is performed.

  In addition, when the condition determination unit 52 determines that there is a dependency between two 16-bit instructions, that is, the destination operand of one 16-bit instruction becomes the source operand of the other 16-bit instruction. If one of the 16-bit instructions changes the condition bit and the other 16-bit instruction refers to the condition bit (Yes in S42), the instruction code generation unit 53 executes the instruction from the parallel instruction to the sequential instruction. A code is generated and output (S43).

  FIG. 9 is a flowchart for explaining a processing procedure of a VLIW processor that executes a program compiled by a compiling apparatus according to the fourth embodiment of the present invention. The schematic configuration of the VLIW processor is the same as that of the VLIW processor in the first embodiment shown in FIG. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  First, when the instruction is two 16-bit instructions (MSB21 = 0) and executed in parallel (MSB22 = 1), the instruction decoding unit 11 determines whether or not the low power consumption mode is set according to the low power consumption mode signal. Is determined (S51).

  When not in the low power consumption mode (S51, No), the instruction decode unit 11 outputs two 16-bit instructions in parallel by simultaneously outputting the decoding results of the two 16-bit instructions to the arithmetic units 12-1 and 12-2. This is executed (S53). In the case of the low power consumption mode (S51, Yes), the instruction decode unit 11 ignores the value of the MSB 22 and assumes "0", and sequentially executes two 16-bit instructions (S52).

  In the low power consumption mode and when two 16-bit instructions are parallel instructions, the dependency is eliminated by the compiling device, and the processor simply executes the parallel instructions sequentially.

  As described above, according to the compiling apparatus in the present embodiment, the low power consumption mode is set, two 16-bit instructions are parallel instructions, and there is a dependency between the two 16-bit instructions. Since the instruction code of the sequential instruction is converted and output, the processor that executes the instruction code only needs to convert the parallel instruction into the sequential instruction and execute it, which will be described in the first embodiment. In addition to the effect, the hardware configuration can be simplified.

(Fifth embodiment)
The configuration example and the functional configuration of the compiling device in the fifth embodiment of the present invention are the same as the configuration example and the functional configuration of the compiling device in the fourth embodiment shown in FIGS. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  FIG. 10 is a flowchart for explaining the processing procedure of the compiling apparatus according to the fifth embodiment of the present invention. First, the mode determination unit 51 determines whether or not the low power consumption mode is designated (S61). When the mode determination unit 51 determines that the low power consumption mode is not designated (S61, No), the instruction code generation unit 53 generates and outputs an instruction code of a sequential instruction from the parallel instruction (S64).

  When it is determined by the mode determination unit 51 that the low power consumption mode is designated (S61, Yes), the condition determination unit 52 determines that two 16-bit instructions are used if the instruction is a parallel instruction of two 16-bit instructions. It is determined whether or not the power consumption when executed in parallel is smaller than a predetermined value (S62).

  For example, the power consumption when executing a 16-bit instruction is stored as a table, the power consumption of each of the two 16-bit instructions is extracted with reference to the table, and the parallel instructions are executed by adding them. The power consumption can be calculated.

  When the condition determination unit 52 determines that the power consumption of two 16-bit instructions is greater than or equal to a predetermined value (S62, No), the instruction code generation unit 53 generates and outputs the instruction code of the sequential instruction from the parallel instruction. (S64). When the condition determination unit 52 determines that the power consumption of the two 16-bit instructions is smaller than the predetermined value (S62, Yes), the instruction code generation unit 53 generates and outputs an instruction code of the parallel instruction ( S63).

  As described above, according to the compiling apparatus in the present embodiment, the low power consumption mode is set, two 16-bit instructions are parallel instructions, and the power consumption of the two 16-bit instructions is smaller than a predetermined value. Since the instruction code of the parallel instruction is generated and output only in the case of, and the instruction code of the sequential instruction is generated and output in other cases, it is possible to reduce the power consumption at the peak time of the processor It is now possible to generate instruction codes.

(Sixth embodiment)
The configuration example and the functional configuration of the compiling device in the sixth embodiment of the present invention are the same as the configuration example and the functional configuration of the compiling device in the fourth embodiment shown in FIGS. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  FIG. 11 is a flowchart for explaining the processing procedure of the compiling apparatus according to the sixth embodiment of the present invention. First, when the mode determination unit 51 determines that the low power consumption mode is designated, the condition determination unit 52 determines the power consumption when two 16-bit instructions are executed in parallel (S71). For example, the power consumption when executing a 16-bit instruction is stored as a table, the power consumption of each of the two 16-bit instructions is extracted with reference to the table, and the parallel instructions are executed by adding them. The power consumption can be calculated.

  When the condition determination unit 52 determines that the power consumption of two 16-bit instructions is smaller than the threshold (No in S72), the instruction code generation unit 53 generates an instruction code of a parallel instruction from the two 16-bit instructions And output (S74).

  If the condition determining unit 52 determines that the power consumption of the two 16-bit instructions is equal to or greater than the threshold value (S72, Yes), it replaces the previous and subsequent instructions within a range that does not change the meaning, and proceeds to step S71. Return and repeat the subsequent processing. For example, it is determined whether or not there is a dependency relationship between the preceding and succeeding instructions. If there is no dependency relationship, the instruction is replaced with the preceding and succeeding instructions.

  As described above, according to the compiling device in the present embodiment, the low power consumption mode is set, two 16-bit instructions are parallel instructions, and the power consumption of the two 16-bit instructions is lower than the threshold value. If it is large, the instruction code is generated by replacing the instruction, so that the instruction code can be generated so that the power consumption at the peak time of the processor can be reduced.

(Seventh embodiment)
FIG. 12 is a block diagram showing an example of a schematic configuration of a system (information processing apparatus) according to the seventh embodiment of the present invention. In this system, the output of the temperature sensor 61 provided outside is connected to the VLIW processor 1 described in the first to fourth embodiments. The processor 1 refers to the output of the temperature sensor 61 to determine whether the temperature is equal to or higher than a predetermined value. When the temperature is equal to or higher than the predetermined value, the processor 1 determines that the low power consumption mode is set.

  FIG. 13 is a block diagram illustrating another example of a schematic configuration of a system (information processing apparatus) according to the seventh embodiment of the present invention. This system is provided with a temperature sensor 61 inside. The rest is the same as the system shown in FIG.

  As described above, according to the system in the present embodiment, when the temperature is equal to or higher than a predetermined value, the system is operated in the low power consumption mode, so that the system temperature can be prevented from becoming higher than necessary. It has become possible to prevent malfunction of the processor 1 and the like.

(Eighth embodiment)
FIG. 14 is a block diagram showing an example of a schematic configuration of a system (information processing apparatus) according to the eighth embodiment of the present invention. In this system, the output of the current sensor 62 provided outside is connected to the VLIW processor 1 described in the first to fourth embodiments. The processor 1 determines whether or not the current supplied to the system is greater than or equal to a predetermined value by referring to the output of the current sensor 62. If the current is greater than or equal to a predetermined value, the processor 1 determines that the current mode is the low power consumption mode.

  FIG. 15 is a block diagram showing another example of a schematic configuration of a system (information processing apparatus) according to the eighth embodiment of the present invention. This system is provided with a current sensor 62 therein. The rest is the same as the system shown in FIG.

  As described above, according to the system in the present embodiment, when the current supplied to the system is equal to or higher than the predetermined value, the system is operated in the low power consumption mode, so that the current supplied to the system is more than necessary. It becomes possible to prevent the processor 1 from malfunctioning.

(Ninth embodiment)
FIG. 16: is a block diagram which shows schematic structure of the system (information processing apparatus) in the 9th Embodiment of this invention. In this system, a low power consumption mode signal input from the outside is connected to the VLIW processor 1 described in the first to fourth embodiments, and the low power consumption mode is switched according to the value of the external input. It is.

  As described above, according to the system in the present embodiment, whether or not to operate in the low power consumption mode is determined according to the value of the external input. It became possible to switch easily.

(Tenth embodiment)
FIG. 17 is a block diagram showing a schematic configuration of a system (information processing apparatus) according to the tenth embodiment of the present invention. In this system, a register 64 is provided, and is connected to the VLIW processor 1 described in the first to fourth embodiments. The processor 1 or the like sets a value in the register 64 to switch the low power consumption mode.

  As described above, according to the system in the present embodiment, since it is determined whether or not to operate in the low power consumption mode according to the value set in the register 64, the processor 1 determines this register 64. By setting this value, it is possible to switch low power consumption by a program.

(Eleventh embodiment)
FIG. 18 is a block diagram showing a schematic configuration of the superscalar in the eleventh embodiment of the present invention. This superscalar includes a hardware instruction scheduler 71 that performs scheduling by detecting parallelism of fetched instruction sequences, and a plurality of arithmetic units (PU) 72-1 that execute instructions scheduled by the hardware instruction scheduler 71. -72-4.

  When the low power consumption mode is set, the hardware instruction scheduler 71 performs scheduling by limiting the pipeline to be used among a plurality of pipelines, and at least one of the computing units 72-1 to 72-4. To prevent the calculator from operating. Further, the power consumption mode may be controlled more finely by giving a level to the low power consumption mode and changing the number of pipelines used in accordance with the level.

  Note that the superscalar in the present embodiment can also be applied to the seventh to tenth systems shown in FIGS. 12 to 17. In this case, instead of the VLIW processor 1, the superscalar described in the present embodiment is mounted.

  As described above, according to the superscalar in the present embodiment, when the low power consumption mode is set, scheduling is performed by limiting the number of pipelines to be used. It is no longer necessary to operate these circuits simultaneously, and the power consumption at the peak time can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing a schematic configuration of a VLIW processor according to a first embodiment of the present invention. FIG. It is a figure which shows an example of the instruction format performed by the processor of the VLIW system in the 1st Embodiment of this invention. 4 is a flowchart for explaining a processing procedure of a VLIW processor according to the first embodiment of the present invention. It is a flowchart for demonstrating the process sequence of the processor of the VLIW system in the 2nd Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the processor of the VLIW system in the 3rd Embodiment of this invention. It is a block diagram which shows the structural example of the compilation apparatus in the 4th Embodiment of this invention. It is a block diagram which shows the functional structure of the compilation apparatus in the 4th Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the compilation apparatus in the 4th Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the processor of a VLIW system which executes the program compiled by the compilation apparatus in the 4th Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the compilation apparatus in the 5th Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the compilation apparatus in the 6th Embodiment of this invention. It is a block diagram which shows an example of schematic structure of the system (information processing apparatus) in the 6th Embodiment of this invention. It is a block diagram which shows another example of schematic structure of the system (information processing apparatus) in the 7th Embodiment of this invention. It is a block diagram which shows an example of schematic structure of the system (information processing apparatus) in the 8th Embodiment of this invention. It is a block diagram which shows another example of schematic structure of the system (information processing apparatus) in the 8th Embodiment of this invention. It is a block diagram which shows schematic structure of the system (information processing apparatus) in the 9th Embodiment of this invention. It is a block diagram which shows schematic structure of the system (information processing apparatus) in the 10th Embodiment of this invention. It is a block diagram which shows schematic structure of the superscalar in the 11th Embodiment of this invention.

Explanation of symbols

  11 Instruction decoding unit, 12-1 to 12-4, 71-1 to 71-4 arithmetic unit, 21, 22 MSB, 31 computer main body, 32 display device, 33 FD drive, 34 FD, 35 keyboard, 36 mouse, 37 CD-ROM device, 38 CD-ROM, 39 network communication device, 40 CPU, 41 ROM, 42 RAM, 43 hard disk, 51 mode determination unit, 52 condition determination unit, 53 command code generation unit, 61 temperature sensor, 62 current sensor 63 Low power consumption mode, 64 registers, 71 Hardware instruction scheduler.

Claims (15)

A processor capable of executing a plurality of instructions simultaneously,
Instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means,
When the fetched instruction is a parallel instruction including a plurality of instructions and there is a dependency between the plurality of instructions, the instruction decoding means saves the dependent data in a register and uses it The processor causes the parallel instructions to be sequentially executed by some of the arithmetic means in the plurality of arithmetic means. A processor capable of executing a plurality of instructions simultaneously,
Instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means,
The instruction decoding means generates an exception and emulates the parallel instruction by software when the fetched instruction is a parallel instruction including a plurality of instructions and there is a dependency between the plurality of instructions. Accordingly, a processor that causes the arithmetic instructions to be sequentially executed by some of the arithmetic means. A processor capable of executing a plurality of instructions simultaneously,
Instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means;
Storage means for storing instructions,
The instruction decoding unit converts the parallel instruction into a sequential instruction group when the fetched instruction is a parallel instruction including a plurality of instructions and there is a dependency between the plurality of instructions. And sequentially reading out the sequential instruction group to cause the parallel instructions to be executed sequentially by some of the arithmetic means. A processor capable of executing a plurality of instructions simultaneously,
Instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means,
If the fetched instruction is a coprocessor instruction, the instruction decoding means causes the plurality of arithmetic means to execute the coprocessor instruction by generating an exception and emulating the coprocessor instruction by software. Processor.   The processor according to any one of claims 1 to 4, wherein the instruction decoding unit stops supply of a clock or power to an arithmetic unit that is not used among the plurality of arithmetic units.   6. The processor according to claim 5, wherein, when executing an instruction that uses the computing means that is not used, the instruction decoding means causes the instruction to be executed by generating an exception and emulating it by software.   6. The processor according to claim 5, wherein, when executing an instruction using the unused arithmetic means, the instruction decoding means restarts supply of a clock or power to the unused arithmetic means and executes the instruction. A compiler for compiling a program executed by a processor capable of executing a plurality of instructions simultaneously,
Condition determining means for determining whether the instruction is a parallel instruction including a plurality of instructions and whether there is a dependency between the plurality of instructions;
A compiler comprising: an instruction code generating means for converting the parallel instruction into an instruction code of a sequential instruction and outputting the instruction when the condition determining means determines that there is a dependency. A compiler for compiling a program executed by a processor capable of executing a plurality of instructions simultaneously,
Condition determining means for determining whether the instruction is a parallel instruction including a plurality of instructions and the power consumption of the plurality of instructions is equal to or greater than a predetermined value;
A compiler comprising: an instruction code generating means for converting the parallel instruction into an instruction code of a sequential instruction and outputting the parallel instruction when the condition determining means determines that the power consumption is a predetermined value or more. A compiler for compiling a program executed by a processor capable of executing a plurality of instructions simultaneously,
Condition determining means for determining whether the instruction is a parallel instruction including a plurality of instructions and the power consumption of the plurality of instructions is equal to or greater than a predetermined value;
An instruction code generating means for generating an instruction code by replacing any of the plurality of instructions included in the parallel instruction with the preceding and succeeding instructions when the condition determining means determines that the power consumption is a predetermined value or more; Including the compiler.   The condition determining means holds power consumption when executing each instruction in a table, and refers to the table to calculate the sum of power consumption of a plurality of instructions included in the parallel instruction, thereby The compiler according to claim 9, wherein the power consumption of the instruction is determined to be equal to or greater than a predetermined value. A processor capable of executing a plurality of instructions simultaneously;
An information processing apparatus including a measuring means for measuring temperature,
The processor includes instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means,
When the temperature measured by the measuring unit is a predetermined value or more, the instruction decoding unit converts the parallel instruction into a sequential instruction if the fetched instruction is a parallel instruction including a plurality of instructions, An information processing apparatus that causes some of the computing means to sequentially execute the parallel instructions. A processor capable of executing a plurality of instructions simultaneously;
An information processing apparatus including a measuring means for measuring current,
The processor includes instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means,
When the current supplied to the information processing device measured by the measuring unit is greater than or equal to a predetermined value, the instruction decoding unit determines that the fetched instruction is a parallel instruction including a plurality of instructions. An information processing apparatus that causes some of the computing means to sequentially execute the parallel instructions by converting the instructions into sequential instructions. An information processing apparatus including a processor capable of executing a plurality of instructions simultaneously,
The processor includes instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means,
When the externally input signal indicates a predetermined value, the instruction decoding means converts the parallel instruction into a sequential instruction if the fetched instruction is a parallel instruction including a plurality of instructions. An information processing apparatus that causes a part of the plurality of arithmetic means to sequentially execute parallel instructions. A processor capable of executing a plurality of instructions simultaneously;
An information processing apparatus including a rewritable register,
The processor includes instruction decoding means for decoding the fetched instruction;
A plurality of arithmetic means for performing an operation according to a result of decoding by the instruction decoding means,
When the predetermined value is stored in the register, the instruction decode means converts the parallel instruction into a sequential instruction if the fetched instruction includes a plurality of instructions, thereby converting the parallel instruction into a sequential instruction. An information processing apparatus for causing a part of the plurality of calculation means to sequentially execute the above.

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