JP2005311522A - Digital broadcast receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct synchronization timing in AV reproduction so that timing expected by a transmission system is achieved, and to perform AV synchronization reproduction by preventing the overflow or underflow of an audio buffer without using a PLL circuit. <P>SOLUTION: An AV decoder 14 comprises a PCR comparison section 5 for comparing PCR with a clock signal clk to obtain their frequency error data δf by computation of a video/audio output timing correction 10 for correcting a PTS for synchronizing video data vdata with audio data adata', based on the frequency error data δf, generates enable signals v_en, a_en based on the correction, and controls the operating timing of output data control sections 8, 11; and a PCM data correction section 9 for correcting the audio data adata based on the frequency error data δf. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital broadcast receiver that performs AV reproduction while preventing the output buffer from failing by performing AV synchronization without reproducing the system clock used in the digital broadcast transmission system on the receiver side. .

  A conventional digital broadcast receiver reproduces a system clock used in a broadcast transmission system (hereinafter referred to as a transmission system) by a PLL (Phase Lock Loop) circuit or the like, and uses the reproduced system clock for reception operation. AV synchronization is achieved.

  A conventional digital broadcast receiver includes, for example, a tuner / demodulator that performs target channel selection and demodulation from a received radio wave, a transport decoder that extracts a desired packet from a demodulated TS (Transport Stream), a transport decoder, and the like. An AV decoder that performs video decoding and audio decoding of each data output from the port decoder, a CPU that processes data such as program arrangement information and broadcast content, graphics and the like based on program information and broadcast data processed by the CPU It is composed of an OSD controller that draws characters and an image synthesizer that synthesizes video signals output from the AV decoder and the OSD controller.

  In digital broadcasting, video data and audio data are independently transmitted from a transmission system. When receiving such a broadcast, AV synchronization is required to synchronize video and audio when decoding. In order to realize this AV synchronization, a tuner of a conventional digital broadcast receiver counts with a PCR (Program Clock Reference) sent from a transmission system at a constant cycle and a receiver internal counter provided in the receiver. An STC (System Time Clock) is compared, and a PLL circuit comprising a voltage variable oscillator is used so that the PCR and STC counted on the receiver side are synchronized with accuracy within a predetermined range based on the comparison data. Thus, the STC is adjusted, and the STC synchronized with the PCR, that is, the STC on the transmission side is reproduced (for example, see Non-Patent Document 1).

  Some conventional digital broadcast receivers generate a system clock having a predetermined frequency by a fixed clock generator and operate a decoder based on the system clock to demodulate a video signal. In this apparatus, the system clock generated by the fixed clock generator is counted by the STC counter, and the output timing adjustment unit compares the STC count value with the PTS value supplied from the PTS (Presentation Time Stamp) demodulator. Based on this result, the output timing of the video signal buffered in the delay memory is adjusted and output to the decoder, the output timing of the video signal of the decoder on the receiver side and the output of the video signal of the encoder on the transmission side The timing is synchronized (for example, refer to Patent Document 1).

Japanese Patent Laying-Open No. 2003-188865 (pages 6 to 7, FIGS. 1 and 2) Edited by the Institute of Image Information and Television Engineers, “Digital Broadcasting Station Structure”, published by Ohm Publishing Co., Ltd., November 20, 2001 (pages 186 to 198, FIGS. 11.4 and 11.5)

  Since the conventional digital broadcast receiver is configured as described above, if a PLL circuit is used, it is necessary to prepare a voltage variable oscillator, and since an external voltage variable oscillator is provided, a TS decoder and an AV decoder are provided. It is difficult to make such functions into one chip. In addition, when a PLL circuit is mounted, not only an external voltage variable oscillator but also a peripheral circuit is required, which increases the number of mounted parts and becomes an obstacle to downsizing and cost reduction. there were.

  Further, the conventional digital broadcast receiver performs a receiving operation using a PTS (Presentation Time Stamp) sent from the sending system when performing AV synchronization and the STC of the sending system reproduced on the receiver side. If the reception operation is performed without reproducing the STC of the transmission system, an error occurs in AV synchronization. Furthermore, if the transmission system and the digital broadcast receiver operate asynchronously, the audio output buffer overflows or underflows during audio playback of the digital broadcast receiver, and abnormal noise occurs during AV playback. It was.

  The present invention has been made to solve the above-described problems, and corrects the AV reproduction synchronization timing so as to achieve the AV synchronization timing expected by the transmission system, and performs audio sampling without using a PLL circuit. It is an object of the present invention to obtain a digital broadcast receiver that corrects data and prevents AV buffer overflow or underflow in reception processing asynchronous with the transmission system system and performs AV synchronous reproduction.

  The digital broadcast receiver according to the present invention is a PCR comparison in which an AV decoder compares a PCR that is sequentially input with a clock signal generated by the receiver to obtain frequency error data indicating an error of the clock signal by calculation. And PTS for synchronizing the video data decoded from the PES by the video decoder and the audio data decoded from the PES by the audio decoder from the video decoder and the audio decoder, respectively, and obtaining these PTSs based on the frequency error data An output timing correction means for controlling the operation timing of the video buffer for outputting the video data and the audio buffer for outputting the audio data by generating an enable signal based on the corrected PTS and the audio buffer output from the audio decoder. The sampling number of audio data is obtained by a audio data correcting means for correcting, based on the frequency error data.

  According to the present invention, the PCR comparison means for obtaining frequency error data indicating the error between the PCR that is sequentially input to the AV decoder and the clock signal generated by the receiver, and the PTS that synchronizes the video data and the audio data. Output timing correction means for controlling the operation timing of the video buffer and the audio buffer by generating an enable signal based on the corrected PTS based on the frequency error data, and the sampling number of the audio data based on the frequency error data Audio data correcting means for correcting the error, so that AV synchronous reproduction can be performed without reproducing the transmission side STC, and the occurrence of abnormal noise can be prevented by preventing buffer breakdown due to overflow or underflow of the audio buffer. There is an effect that can be.

An embodiment of the present invention will be described below.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of a digital broadcast receiver according to Embodiment 1 of the present invention. The illustrated digital broadcast receiver includes a tuner 1 that receives a digital broadcast via an antenna 15, an OFDM (Orthogonal Frequency Division Multiplexing) demodulator 2 that demodulates an IF (Intermediate Frequency) signal output from the tuner 1, and an OFDM demodulator 2 is composed of a transport decoder 3 that decodes a TS (Transport Stream) packet output from 2, an oscillator 4 that generates an STC (System Time Clock) of the receiver, and an AV decoder 14.

  The AV decoder 14 includes a PCR (Program Clock Reference) comparison unit (PCR comparison means) 5, a video decoder 6, and an audio decoder 7. Also, an output data control unit (video buffer) 8 that controls video data output from the video decoder 6, a PCM data correction unit (audio data correction unit) 9 that corrects audio data output from the audio decoder 7, and PCM An output data control unit (audio buffer) 11 that controls the audio data output from the data correction unit 9 is provided.

  The output data control unit 8 includes a video buffer used when outputting video data, and the output data control unit 11 includes an audio buffer used when outputting audio data. The AV decoder 14 also includes a video / audio output timing correction unit (output timing correction means) 10 that controls the output data control unit 8 and the output data control unit 11 based on the comparison result of the PCR comparison unit 5. Also, a D / A converter 12 that performs D / A conversion of video data output from the output data control unit 8, and a D / A converter 13 that performs D / A conversion of audio data output from the output data control unit 11. With.

Next, the operation will be described.
The tuner 1 selects and receives a desired broadcast wave using the antenna 15, performs frequency conversion of the broadcast wave, that is, an RF (Radio Frequency) signal, and outputs an IF signal. This IF signal is input to the OFDM demodulator 2. The OFDM demodulator 2 extracts a TS packet from the IF signal and outputs the TS packet to the transport decoder 3. The transport decoder 3 extracts a PCR (Program Clock Reference) from the TS packet based on the PID (Progrm ID) included in the header information of the TS packet, data pcr <41..0> representing the PCR, and a signal pcr_det Are output to the AV decoder 14. The data pcr <41..0> illustrated here is 42-bit bus data, and the signal pcr_det is a signal used when recognizing the data pcr <41..0>.

  Further, the transport decoder 3 extracts a PES (Packetized Elementary Stream) packet from the TS packet including video data and audio data, and outputs the packet packet to the AV decoder 14. The AV decoder 14 inputs the PES packet pes_v related to the video data to the video decoder 6 and the PES packet pes_a related to the audio data to the audio decoder 7.

  The PCR comparison unit 5 of the AV decoder 14 uses the value represented by the PCR input from the transport decoder 3, that is, the value of the data pcr <41..0> on the STC (hereinafter referred to as the transmission side) used on the transmission system side. It is recognized as a count value). The PCR comparator 5 receives the clock signal clk generated by the oscillator 4 and causes the Local_CNT counter (not shown in FIG. 1) provided in the PCR comparator 5 to count the clock signal clk. In addition, it is latched at the reception timing of the PCR recognized from the signal pcr_det. In this way, the PCR comparison unit 5 compares the count value of the Local_CNT counter with the count value of the aforementioned STC on the transmission side, calculates the error of the count value of the local_cnt counter from these count values, and generates frequency error data δf is generated. The PCR comparison unit 5 notifies the generated frequency error data δf to the video / audio output timing correction unit 10 and the PCM data correction unit 9.

  The video decoder 6 separates data pts_v representing PTS (Presentation Time Stamp) related to video data and ES (Elementary Stream) in accordance with the MPEG-2 / 4 VIDEO standard from the PES packet separated by the transport decoder 3. . Thereafter, the ES is decoded to generate video data vdata and output to the output data control unit 8. Further, a PTS enable signal pts_v_w_en that identifies the data pts_v, that is, indicates the delimiter of the data pts_v, is generated and notified to the video / audio output timing correction unit 10 together with the data pts_v. Similarly, the audio decoder 7 separates data pts_a and ES representing PTS relating to audio data from the PES packet separated by the transport decoder 3, decodes the ES to generate audio data adata, and PCM data Output to the correction unit 9. Further, a PTS enable signal pts_a_w_en that identifies the data pts_a, that is, indicates a delimiter of the data pts_a, is generated and notified to the video / audio output timing correction unit 10 together with the data pts_a.

  The PCM data correction unit 9 receives the frequency error data δf from the PCR comparison unit 5, corrects the audio data adata, that is, PCM data based on the information, and performs audio thinning processing, interpolation processing, etc., audio data adata That is, the corrected PCM data is generated and output to the output data control unit 11. The PCM data correction unit 9 generates a reproduction sampling clock clk2 (not shown) based on the clock signal clk generated by the oscillator 4, and outputs the reproduction sampling clock clk2 to the output data control unit 11, D / A converter 13 and the like which are audio buffers. Supply sampling clock clk2.

  The video / audio output timing correction unit 10 includes the data pts_v input from the video decoder 6 and the PTS enable signal pts_v_w_en, the data pts_a input from the audio decoder 7 and the PTS enable signal pts_a_w_en, and the frequency error data δf input from the PCR comparison unit 5. In consideration of the data pcr <41..0>, the signal pcr_det, the counter enable signal cnt_en, and the time required for the processing operation of the PCM data correction unit 9, the video data output enable signal v_en and the audio data output enable signal a_en Generate.

  The output data control unit 8 adjusts the operation timing based on the output enable signal v_en and outputs video data to the D / A converter 12. The output data control unit 11 adjusts the operation timing based on the enable signal a_en and outputs audio data to the D / A converter 13. The D / A converter 12 performs D / A conversion of the video data input from the output data control unit 8 to generate a video signal, and the D / A converter 13 performs D / A conversion of the audio data input from the output data control unit 11. Performs conversion to generate an audio signal. As described above, the video signal output from the output data control unit 8 serving as the video buffer via the D / A converter 12 and the output from the output data control unit 11 serving as the audio buffer via the D / A converter 13 are performed. The audio signal is synchronized with the output enable signal v_en and the output enable signal a_en, and the video signal is output from the D / A converter 12 and the audio signal is output from the D / A converter 13 to a reproducing means (not shown) for AV reproduction. Do.

  The above-described transport decoder 3 and AV decoder 14 operate using the clock signal clk generated by the oscillator 4 as a system clock, that is, basically in synchronization with the clock signal clk. Further, the reset signal reset shown in FIG. 1 is a reset signal of the transport decoder 3 and the AV decoder 14, and when this reset signal reset becomes active, each register constituting the transport decoder 3 and the AV decoder 14 described later, The contents held in the counter or the like are cleared.

  Next, details of each unit constituting the digital broadcast receiver will be described. Here, a detailed description will be given of the PCR comparison unit 5, the PCM data correction unit 9, and the video / audio output timing correction unit 10 constituting the transport decoder 3 and the AV decoder 14, which are the main parts of the present invention.

  FIG. 2 is a block diagram showing the configuration of the transport decoder of the digital broadcast receiver according to the first embodiment. The transport decoder 3 illustrated in FIG. 1 includes, for example, a PID filter unit 21, a PSI (Program Specific Information) analysis unit 22, and a content data buffer 23 as illustrated in FIG. The PSI analyzing unit 22 analyzes a PAT (Program Association Table) and a PMT (Program Map Table) included in the TS packet input from the OFDM demodulating unit 2, and each data such as video, audio, PCR, content, etc. Is notified to the PID filter unit 21. From the TS packet input from the OFDM demodulator 2 according to the notified PID, the PID filter unit 21 performs video data PES packet pes_v, audio data PES packet pes_a, PCR data pcr <41..0>, and signal pcr_det. The data of the content data packet pes_c is separated. However, the separation operation is performed when the PES enable signal pes_en output from the video / audio output timing correction unit 10 becomes active except for the data pcr <41..0> representing the PCR and the signal pcr_det.

  The PID filter unit 21 extracts a total of 42 bits of PCR value base 33 bits + PCR value extension 9 bits included in the adaptation field as PCR data pcr <41..0> from the TS packet according to the PID notified as described above. . When the PES enable signal pes_en becomes active and separation of video, audio, and content data is permitted, extraction of the PES packet included in the payload of the TS packet is started. Thereafter, the PES packet pes_v of the separated and extracted video data and the PES packet pes_a of the audio data are output to the AV decoder 14 and the content data packet pes_c is output to the content data buffer 23. The content data buffer 23 stores the input packet pes_c, and appropriately outputs the packet pes_c to a control unit (not shown) that operates based on a program such as browser software. Note that the content data forming the packet pes_c handled here indicates data related to service contents or the like generally performed in digital broadcasting, and description thereof is omitted here.

  FIG. 3 is a block diagram showing the configuration of the PID filter unit of the digital broadcast receiver according to the first embodiment. The PID filter unit 21 shown in FIG. 2 receives the TS packet from the OFDM demodulator 2, and receives the PID input from the PSI analyzer 22 and the PES enable signal pes_en input from the video / audio output timing correction unit 10. Based on the TS packet analysis, the TS packet analysis / decoding unit outputs the packet data ts_v including the video data, the packet ts_a including the audio data, and the packet ts_c including the content data. 31 and PES packet extraction units 32, 33, and 34 for extracting PES packets from TS packets output from the TS header analysis / decoding unit 31, that is, packets ts_v, ts_a, and ts_c, respectively.

FIG. 4 is an explanatory diagram showing the structure of the TS header and the PES header. 4 shows an example of the bit assignment of the header portion of the TS packet input to the TS header analysis / decoding unit 31 of FIG. 3 and the header of the PES packet output from the PES packet extraction units 32 to 34, respectively. An example of the bit assignment of a part is shown.
FIG. 5 is an explanatory diagram showing the structure of the PCR. What is shown is an example of a data configuration representing PCR by 42 bits used in the above description, that is, an example of bit assignment of data pcr <41..0>.
FIG. 6 is a timing chart of PCR output from the transport decoder of the digital broadcast receiver according to the first embodiment. The timing chart of the data pcr <41..0> and the signal pcr_det representing the PCR used in the above description is shown, and the TS header analysis / decoding unit shown in FIG. The data pcr <41..0> and the signal pcr_det output from 31 are shown.

  The TS header analysis / decoding unit 31 determines whether the data included in the TS packet corresponds to video, audio, content data, or PCR according to the PID described in 13 bits in the TS header shown in FIG. Is determined. For example, when it is determined that the TS packet to be determined is a packet including video data, this packet is output to the PES packet extraction unit 32 as a packet ts_v. If it is determined that the TS packet to be determined includes audio data, this packet is output to the PES packet extraction unit 33 as a packet ts_a including audio data. If it is determined that the TS data includes content data, the content data is output. Is output to the PES packet extraction unit 34 as a packet ts_c including However, the TS header analysis / decoding unit 31 outputs only the data pcr <41..0> and the signal pcr_det until the PES enable signal pes_en output from the video / audio output timing correction unit 10 becomes active. Data pcr <41..0> is included in the adaptation field of the TS packet as a PCR value base 33 bits (data pcr_base <32..0>) and a PCR value extension 9 bits (data pcr_ext <8..0>). Therefore, the TS header analysis / decoding unit 31 extracts these from the TS packet as 42-bit data as shown in FIG. 5, and sends them to the AV decoder 14, specifically to the PCR comparison unit 5.

  In addition, the TS header analysis / decoding unit 31 generates a pulse signal indicating active each time the PCR acquired from the TS packet is updated, and outputs this as a signal pcr_det. The signal pcr_det is generated so that the pulse signal width indicating active has one clock of the clock signal clk output from the oscillator 4, and the TS header is synchronized with the timing at which the PCR is updated as shown in FIG. Output from the analysis / decoding unit 31. Note that “PCRm” shown in FIG. 6 indicates the m-th transmitted PCR.

  The PES packet extraction units 32 to 34 extract the PES packet from the TS packet as described above. In the first PES packet extraction, the PES header start code “0x000001”, for example, is detected from the contents of the PES header shown in the “TS header” shown at the left end of the TS header shown in FIG. It starts from the time. All data extracted from the TS packet before the PES header start code is detected is ignored. After detecting the PES header start code, the length of the PES packet is analyzed from the “PES packet length” indicated in the PES header in which the code is detected, and the PES packet is extracted. The PES packet extraction unit 32 that receives the TS packet packet ts_v from the TS header analysis / decoding unit 31 extracts the PES packet from the packet ts_v, and outputs the PES packet to the AV decoder 14 as the PES packet pes_v. Similarly, the PES packet extraction unit 33 that has received the packet ts_a from the TS header analysis / decoding unit 31 extracts the PES packet from the packet ts_a, and outputs this to the AV decoder 14 as a PES packet pes_a. Further, the PES packet extraction unit 34 that has received the packet ts_c from the TS header analysis / decoding unit 31 extracts the PES packet from the packet ts_c, and outputs this to the content data buffer 23 as a PES packet pes_c.

  FIG. 7 is a block diagram showing the configuration of the PCR comparison unit of the digital broadcast receiver according to the first embodiment. This figure shows the configuration of the PCR comparison unit 5 described so far. 7 includes a Local_CNT counter 71 that counts the clock signal clk output from the oscillator 4 shown in FIG. 1, a Local_REG_A register (count value register) 72 that stores the count value of the Local_CNT counter 71, and Local_REG_B register (count value register) 73, PCR_REG_A register (PCR value register) 74 for storing data pcr <41..0> representing PCR, PCR_REG_B register (PCR value register) 75, Local_CNT using the values of these registers A counter error detection unit (error detection means) 76 that detects an error in the count value output from the counter 71, shift registers 77 and 80 that shift data output from the counter error detection unit 76, and output from the shift register 77. Output from the averaging processing unit 78 for obtaining the average of the data and the shift register 80. Average processing unit 81 for obtaining the average of the data to be averaged, and δf calculation unit (frequency error data calculation means) 79 for calculating the frequency error data δf based on the data output from the averaging processing unit 78 and the averaging processing unit 81 It is configured with.

  As shown in FIG. 7, the Local_CNT counter 71 includes a clock signal clk output from the oscillator 4, a signal pcr_det output from the transport decoder 3, and data pcr <41..0 as an initial value of the count value. > Is entered. The Local_REG_A register 72 receives the signal pcr_det and the data local_cnt <41..0> indicating the count value output from the Local_CNT counter 71, and uses the data local_cnt <41..0> as the register value local_reg_a <41..0>. The register value local_reg_a <41..0> is input or output based on the signal pcr_det. The Local_REG_B register 73 receives the signal pcr_det and the register value local_reg_a <41..0> output from the Local_REG_A register 72, and uses the register value local_reg_a <41..0> as the register value local_reg_b <41..0>. The register value local_reg_b <41..0> is input or output based on the signal pcr_det. The PCR_REG_A register 74 receives the signal pcr_det and the data pcr <41..0> output from the transport decoder 3, and uses the data pcr <41..0> as the register value pcr_reg_a <41..0>. The register value pcr_reg_a <41..0> is input or output based on the signal pcr_det. The PCR_REG_B register 75 receives the signal pcr_det and the register value pcr_reg_a <41..0> output from the PCR_REG_A register 74, and uses the register value pcr_reg_a <41..0> as the register value pcr_reg_b <41..0>. The register value pcr_reg_b <41..0> is input or output based on the signal pcr_det.

  The counter error detection unit 76 inputs the register value and the signal pcr_det stored in the Local_REG_A register 72, Local_REG_B register 73, PCR_REG_A register 74, and PCR_REG_B register 75, respectively. An operation is performed using the value to obtain data diff <42..0> and a difference value δlocal_cnt <41..0>.

  The shift register 77 includes a plurality of registers, for example, includes N registers DIFF_0 to DIFF_N, shifts register values stored in order from the register DIFF_0, and outputs values stored in the registers DIFF_0 to DIFF_N. The shift register 77 receives the signal pcr_det and the data diff <42..0> from the counter error detector 76, and sequentially shifts the input data diff <42..0> based on the signal pcr_det. Store in registers DIFF_0 to DIFF_N.

  The shift register 80 includes a plurality of registers, for example, includes N registers LCNT_0 to LCNT_N, shifts the register values stored in order from the register LCNT_0, and outputs the stored values from the registers LCNT_0 to LCNT_n. The shift register 80 receives the signal pcr_det and the difference value δlocal_cnt <41..0> from the counter error detector 76. The sequentially inputted difference value Δlocal_cnt <41..0> is stored while being shifted to the registers LCNT_0 to LCNT_N based on the signal pcr_det. Note that the number of registers LCNT_0 to LCNT_N is not necessarily the same as that of the registers DIFF_0 to DIFF_N.

  FIG. 8 is a timing chart showing the operation of the PCR comparison unit of the digital broadcast receiver according to the first embodiment. This figure shows the transition of each signal, data, etc. input / output in each part constituting the PCR comparison unit 5 when the PCR comparison unit 5 shown in FIG. 7 operates.

  As shown in FIG. 8, when the signal pcr_det first changes to active and the clock signal clk rises for the first time, the Local_CNT counter 71 generates and outputs a count enable signal cnt_en indicating the activity. At this time, the data pcr <41..0> representing the PCR input to the PCR comparison unit 5 is loaded. This is an operation performed at the timing when the clock signal clk first rises after the signal pcr_det becomes active for the first time. At this time, data pcr <41..0> input to the Local_CNT counter 71 is stored in the Local_REG_A register 72 as an initial value of the count value of the counter, as will be described later. For example, the data pcr0 shown in FIG. 8 is input to the Local_CNT counter 71 as the initial value data pcr <41..0>, and the count enable signal cnt_en that is actively changed is output from the Local_CNT counter 71 at this timing.

  Thereafter, when the signal pcr_det indicating active falls, the Local_CNT counter 71 outputs the initial value local_cnt0 of the count value, that is, the data pcr0 to the Local_REG_A register 72 at that timing. The count enable signal Local_en output from the Local_CNT counter 71 is input to the video / audio output timing correction unit 10 shown in FIG.

  As shown in FIG. 8, when the signal pcr_det falls after the data pcr0 is loaded to the Local_CNT counter 71 as shown in FIG. The data pcr0 input to is loaded and stored as the initial value of the register value pcr_reg_a <41..0>.

  Thereafter, the Local_CNT counter 71 counts up the rising edge of the clock signal clk, and generates data local_cnt <41..0> representing the count value in 42 bits. Next, when the signal pcr_det becomes active, the Local_REG_A register 72 outputs the initial value local_reg0 of the register value local_reg_a <41..0>, that is, the data pcr0 to the Local_REG_B register 73 at the falling timing. The data pcr0 shifted from the Local_REG_A register 72 to the Local_REG_B register 73 is stored in the Local_REG_B register 73 as a register value local_reg_b <41..0>. At the same time, the register value pcr_reg_a <41..0> stored in the PCR_REG_A register 74 is shifted to the PCR_REG_B register 75 and stored as the register value pcr_reg_b <41..0>.

  When the input signal pcr_det becomes active, the counter error detection unit 76 receives the register value local_reg_a <41..0> from the Local_REG_A register 72 and the register value local_reg_b <41..0> from the Local_REG_B register 73. And the register value pcr_reg_a <41..0> is input from the PCR_REG_A register 74, and the register value pcr_reg_b <41..0> is input from the PCR_REG_B register 75, and calculation is performed as described later. To obtain the data diff <42..0>. Also, the difference value between the register value local_reg_a <41..0> of the Local_REG_A register 72 and the register value local_reg_b <41..0> of the Local_REG_B register 73 is obtained, and this value is output as the difference value δlocal_cnt <41..0>. To do. Data diff <42..0> expressed as 43-bit data is input to the shift register 77 and stored in the register DIFF_0. Also, the difference value δlocal_cnt <41..0> expressed as 42-bit data is input to the shift register 80 and stored in the register LCNT_0.

  When the input signal pcr_det becomes active, the shift register 77 shifts the value stored in the register DIFF_0 to the register DIFF_1, and similarly shifts the values stored in the registers DIFF_1 to DIFF_N-1 to the adjacent ones. Shift to register DIFF. This shift operation and the operation in which the data diff <42..0> is input from the counter error detection unit 76 to the register DIFF_0 are performed every time the signal pcr_det becomes active. Further, when the input signal pcr_det becomes active, the shift register 80 shifts the value stored in the register LCNT_0 to the register LCNT_1, and similarly, the value stored in each of the registers LCNT_1 to LCNT_N-1 is changed. Shift to adjacent register LCNT. This shift operation and the operation of inputting the difference value δlocal_cnt <41..0> from the counter error detection unit 76 to the register LCNT_0 are performed every time the signal pcr_det becomes active.

  The register values stored in the registers DIFF_0 to DIFF_N of the shift register 77 are sequentially output to the averaging processing unit 78 along with the shift operation and the like, and are similarly stored in the registers LCNT_0 to LCNT_N of the shift register 80. All the register values are sequentially output to the averaging processing unit 81 with the shift operation.

  The averaging processing unit 78 acquires each register value stored in the registers DIFF_0 to DIFF_N of the shift register 77, and obtains an average value diff_ave <42..0> of these values. By obtaining the average value diff <42..0>, the jitter included in the data diff <42..0> is removed. In this calculation, the upper 34 bits and the lower 9 bits of the 43-bit register value stored in each register DIFF_0 to DIFF_N are calculated separately, and finally the upper bit and the lower bit are added to generate 43-bit data. To do. This is because the data representing the PCR shown in FIG. 5 is the 33-bit PCR value base data PCR_BASE <32..0> is the count value of 90 kHz (27 MHz / 300), and the PCR value extension data PCR_EXT <8..0 > Is a count value of 9 bits, and in FIG. 5, PCR is expressed as 42-bit bus data, but the 27 MHz system clock represented by PCR is' pcr_base <32..0> × 300 + pcr_ext <8..0. > 'Sought as'. The purpose here is to detect the difference between the 27 MHz PCR used in the operation of the digital broadcast receiver and the 27 MHz STC used on the transmission system side. Considering the standard, the PCR used on the digital broadcast receiver side is replaced with the value when counted at a clock speed of 27 MHz. Therefore, when obtaining the average value of each register value output from the shift register 77, the average value is obtained by separating the upper 34 bits and the lower 9 bits, and finally the upper 34 bits and the lower 9 bits are added together as described above. An average value diff_ave_ <42..0> is obtained as a count value corresponding to a clock speed of 27 MHz.

  Similarly, the averaging processing unit 81 acquires each register value stored in the registers CNT_0 to CNT_N of the shift register 80, and obtains an average value lcnt_ave <41..0>. At this time, each register value of the registers CNT_0 to CNT_N is separated into upper 33 bits and lower 9 bits, and the calculation is performed in the same manner as in the case where the average value of the register values stored in the registers DIFF_0 to DIFF_N is obtained. It is obtained as a count value corresponding to the clock speed.

The δf calculation unit 79 receives the average value diff_ave <42..0> obtained by the averaging processing unit 78 and the average value lcnt_ave <41..0> obtained by the averaging processing unit 80, and inputs the frequency A normalized frequency error value is obtained as error data δf. The frequency error data δf obtained here is updated and output from the δf calculation unit 79 to the outside in synchronization with the falling timing of the signal pcr_det. Formulas for calculating the frequency error data δf are shown in the following formulas (1) to (3). Here, the frequency of the clock signal clk is f, and the frequency of the transmission side STC is f × (1 + δf). Further, the value of the upper 34 bits of the average value diff_ave <42..0> is represented as diff_ave <42..9>, and is represented by a two's complement. Also, diff_ave <8..0> representing the lower 9-bit value of the average value diff_ave <42..0>, lcnt_ave <41..9> representing the upper 33-bit value of the average value lcnt_ave <41..0>, Also, lcnt_ave <8..0> representing the lower 9-bit value of the average value lcnt_ave <41..0> represents a positive integer. Here, the decimal notation of the data bus is expressed as “decimal (data bus name)”. For example, the decimal notation of diff_ave <42..9> is “decimal (diff_ave <42..9>). ". Δf obtained at this time is a real number. In the following equations, T represents time.
f × (1 + δf) T−f × T =
Decimal (diff_ave <42..9>) x 300 + decimal (diff_ave <8..0>) (1)
f × δf × T = decimal (diff_ave <42..9>) × 300 + decimal (diff_ave <8..0>) (2)
(F × T = decimal (lcnt_ave <41..9>) × 300 + decimal (lcnt_ave <8..0>))
δf = (decimal (diff_ave <42..9>) x 300 + decimal (diff_ave <8..0>))
/ (Decimal (lcnt_ave <41..9>) x 300 + Decimal (lcnt_ave <8..0>)) ... (3)

  FIG. 9 is an explanatory diagram showing bit assignments of data stored in the Local_REG_A register and the Local_REG_B register of the digital broadcast receiver according to the first embodiment. This figure shows bit assignments of data local_cnt <41..0> stored in the Local_REG_A register 72 and the Local_REG_B register 73 shown in FIG. 7, that is, the count value of the Local_CNT counter 71. As shown in the figure, data local_cnt <41..0> is 42-bit bus data, count value base data local_cnt_base <41..9> represented by upper 33 bits, and count value extension data represented by lower 9 bits. It is configured by local_cnt_ext <8..0>.

  FIG. 10 is a block diagram illustrating a configuration of the Local_CNT counter of the digital broadcast receiver according to the first embodiment. This figure shows the configuration of the Local_CNT counter 71 shown in FIG. 7, which is a 300 counter that counts the value of the lower 9-bit data pcr <8..0> of the data pcr <41..0> representing PCR. 91, a local_base counter 92 that counts the value of the upper 33-bit data pcr <41..8> of the data pcr <41..0>, and an SR flip-flop that generates the count enable signal cnt_en using the signal pcr_det as the S input And a flip-flop 93 formed of a circuit.

  The 300 counter 91 receives the clock signal clk from the oscillator 4 shown in FIG. 1, and receives the data pcr <8..0> as described above. The local_base counter 92 receives the clock signal base_clk output from the 300 counter 91 and the data pcr <41..9> as described above. As described above, the signal pcr_det is input to the flip-flop 93 as the S input, and the reset signal reset is input as the R input. Based on these SR inputs, a count enable signal cnt_en is generated as a Q output, and this count enable signal cnt_en is input to the 300 counter 91 and the local_base counter 92 and output to the outside of the Local_CNT counter 71. The reset signal reset described above is also input to the 300 counter 91 and the local_base counter 92.

  The Local_CNT counter 71 receives the data pcr <41..0> as an initial value as described above, and the data pcr0 shown in FIG. 8 as the data pcr <41..0> when the signal pcr_det becomes active for the first time. To load. When the signal pcr_det indicating active is input for the first time, the flip-flop 93 outputs a count enable signal cnt_en indicating active in synchronization with the rising edge of the clock signal clk. Then, the 300 counter 91 detects the rising edge of the count enable signal cnt_en indicating active, and only when the rising edge of the count enable signal cnt_en is first detected, the lower 9 bits of data pcr <8..0 on the data bus. > Is stored in the lower 9 bits of Local_REG_A register 72 as the value of lower 9 bits of data local_cnt <8..0> of data local_cnt <41..0>, and the rising edge of clock signal clk is counted up. Start. The 300 counter 91 clears the counted value when the count-up value reaches 0x12C (“300” in decimal notation) at this time, and also outputs a pulse signal for one clock of the clock signal clk as a clock signal. Output as base_clk. Thereafter, the 300 counter 91 starts counting up every time the rising edge of the count enable signal cnt_en is detected, and outputs the count value as data local_cnt <8..0> to the Local_REG_A register 72 for storage. When the count value reaches 0x12C, the count value is cleared and the clock signal base_clk is output as described above, and such an operation is repeated.

  The Local_base counter 92 detects the rising edge of the count enable signal cnt_en indicating active, and only when the rising edge of the count enable signal cnt_en is first detected simultaneously with the 300 counter 91, the upper 33 bits of data pcr <41 on the data bus. ..9> is loaded, and this value is stored in the upper 33 bits of the Local_REG_A register 72 as the upper 33 bits of data local_cnt <41..9> of the data local_cnt <41..0> indicating the count value. Starts counting up. After that, every time the rising edge of the count enable signal cnt_en is detected, the value that started counting up is cleared and the counting up is started again, and the count value is set to the count value local_cnt <41..9> as described above. The data is output to the register 72 and stored.

  The low-order 9-bit data local_cnt <8..0> output from the 300 counter 91 and the high-order 33-bit data local_cnt <41..9> output from the Local_base counter 92 are bit-assigned as shown in FIG. It is stored in the Local_REG_A register 72 and the Local_REG_B register 73.

  FIG. 11 is a block diagram illustrating a configuration of a counter error detection unit of the digital broadcast receiver according to the first embodiment. This figure shows the configuration of the counter error detection unit 76 shown in FIG. 7. The register value local_reg_a <41..0> stored in the Local_REG_A register 72 and the register value stored in the Local_REG_B register 73 are shown. The local_reg_b <41..0> and the local_borrow signal output from the subtractor 102 are input, and the subtractor 101 that performs subtraction of the upper 33-bit data using these register values, and the register value local_reg_a <41..0 > And the register value local_reg_b <41..0>, the subtracter 102 for subtracting the lower 9-bit data of these register values, and the register value pcr_reg_a <41..0> stored in the PCR_REG_A register 74 And the register value pcr_reg_b <41..0> stored in the PCR_REG_B register 75 and the pcr_borrow signal output from the subtractor 104 are input, and subtraction is performed to subtract the upper 33-bit data using these register values. 103, similarly, the register value pcr_reg_a <41..0> and the register value pcr_reg_b <41..0> are input, and the subtracter 104 for subtracting the lower 9-bit data of these register values is output from the subtractor 101. Difference value δlocal_cnt <41..9>, the difference value δpcr <41..9> output from the subtractor 103, and the diff_borrow signal output from the subtractor 106 are input, and these values are used as the upper rank. A subtractor 105 that subtracts 34-bit data, a difference value δlocal_cnt <8..0> output from the subtractor 102, and a difference value δpcr <8..0> output from the subtractor 104 are input. And a subtractor 106 for subtracting lower 9-bit data of the value of.

The subtracters 101 and 102 differ between the register value local_reg_a <41..0> stored in the Local_REG_A register 72 and the register value local_reg_b <41..0> stored in the Local_REG_B register 73 as described above. Calculate the value. In this calculation, the subtractor 101 obtains the difference value δlocal_cnt <41..9> for the upper 33 bits, and the subtractor 102 obtains the difference value δlocal_cnt <8..0> for the lower 9 bits. When the subtracter 102 obtains the difference value δlocal_cnt <8..0>, the following two situations can be considered.
(A) local_reg_a <8..0> −local_reg_b <8..0> ≧ 0
(B) local_reg_a <8..0> −local_reg_b <8..0><0
The subtractor 102 determines which of the above conditions (a) or (b), and in the case of (a), the subtractor simply subtracts the lower 9 bits of each data, and the result is obtained. A difference value δlocal_cnt <8..0> is output, and a local_borrow signal having a logical low level (hereinafter, the low level is described as L) is generated and output to the subtractor 101. In the case of (b), a local_borrow signal of logical high level (hereinafter, high level is described as H) is generated and output to the subtractor 101, and '0x12C + local_reg_a <8..0> −local_reg_b <8 ..0>'is output as the difference value δlocal_cnt <8..0>.

  The subtractor 101 performs an operation of ‘local_reg_a <41..9> −local_reg_b <41..9> − (local_borrow signal value)’. The subtracter 101 inputs the upper 33-bit data of the register value local_reg_a <41..0> and the register value local_reg_b <41..0>, and also inputs and subtracts the local_borrow signal assigned to the lowest bit. To obtain a 34-bit calculation result in the complement expression of. As the calculation result, the most significant bit of 34 bits is not output, but the other 33 bits are output. The data output at this time is the difference value δlocal_cnt <41..9> that is the upper 33 bits of the difference value δlocal_cnt <41..0>. In this way, the difference value δlocal_cnt <41 .. <b> consisting of the 33-bit difference value δlocal_cnt <41..9> output from the subtractor 101 and the 9-bit difference value δlocal_cnt <8..0> output from the subtractor 102. 0> is written into the shift register 80 shown in FIG. Furthermore, the difference value δlocal_cnt <41..9> output from the subtractor 101 is input to the subtractor 105, and the difference value δlocal_cnt <8..0> output from the subtractor 102 is input to the subtractor 106. The

  When the subtractors 103 and 104 calculate a difference value between the register value pcr_reg_a <41..0> stored in the PCR_REG_A register 74 and the register value pcr_reg_b <41..0> stored in the PCR_REG_B register 75, The same arithmetic processing as the subtracter 101 and the subtracter 102 is performed. In the subtractor 104, as in the subtractor 102 described above, the relationship between the lower 9 bits of the input register value pcr_reg_a <41..0> and the lower 9 bits of the register value pcr_reg_b <41..0>, that is, the register value pcr_reg_a < 8. Determine the magnitude relationship between the 8..0> and the register value pcr_reg_b <8..0>. If the situation is 'pcr_reg_a <8..0> −pcr_reg_b <8..0> ≧ 0', The subtraction is simply performed as in the case of a), and the result is output as the lower 9 bits of the difference value δpcr <41..0>, that is, the difference value δpcr <8..0>. With this processing operation, a pcr_borrow signal having a logical value L is generated and output to the subtractor 103. Further, in the case of the situation of “pcr_reg_a <8..0> −pcr_reg_b <8..0> <0”, as in the case of (b) described above, “0x12C + local_reg_a <8..0> −local_Rreg_b <8 .. The calculation result of 0> ′ is output as the lower 9 bits of the difference value δpcr <41..0>, that is, the difference value δpcr <8..0>, and a pcr_borrow signal of logical value H is generated and output.

  The subtracter 103 calculates “pcr_reg_a <41..9> −pcr_reg_b <41..9> − (value of pcr_borrow signal)”. The subtractor 103 inputs the 33-bit register value pcr_reg_a <41..9> and the register value pcr_reg_b <41..9> respectively, and also inputs the pcr_borrow signal to be assigned to the least significant bit, and performs subtraction as described above. To obtain a 34-bit calculation result in 2's complement expression. Similar to the operation of the subtractor 101 described above, this calculation result outputs the other 33-bit value as the difference value δpcr <41..9> without outputting the most significant bit of 34 bits. Thus, the 33-bit difference value δpcr <41..9> output from the subtractor 103 is input to the subtractor 105, and the 9-bit difference value δpcr <8..0> output from the subtractor 104 is the subtractor. 106 is input.

  The subtractor 106 performs an operation of ‘δpcr <8..0> −δlocal_cnt <8..0>’. When performing this calculation, the subtractor 106 determines the magnitude relationship between the input difference value δlocal_cnt <8..0> and the difference value δpcr <8..0> in the same manner as the subtractor 102, and 'δpcr <8. .0> −δlocal_cnt <8..0> ≧ 0 ′, the calculation result is simply output as the lower 9 bits of the data diff <42..0> as in the case of (a) described above, and the logic A diff_borrow signal of value L is generated and output to the subtractor 105. Further, in the case of δpcr <8..0> −δlocal_cnt <8..0> <0, the calculation result of 0x12C + δpcr <8..0> −δlocal_cnt <8..0> is data diff <42 .. 0> is output as lower 9 bits, and a diff_borrow signal of logical value H is generated and output.

  The subtractor 105 performs an operation of “δpcr <41..9> −δlocal_cnt <41..9> − (value of diff_borrow signal)”. The subtractor 105 receives the difference value δlocal_cnt <41..9> from the subtractor 101, receives the difference value δpcr <41..9> from the subtractor 103, and further subtracts the pcr_borrow signal assigned to the least significant bit. The data is input from the calculator 106 and subtracted as described above to obtain a 34-bit calculation result in 2's complement expression. This calculation result is output as the upper 34 bits of the data diff <42..0>. The upper 34-bit data of the data diff <42..0> output from the subtractor 105 and the lower 9-bit data of the data diff <42..0> output from the subtractor 106 are combined into a 43-bit data diff. It is output to the shift register 77 as <42..0>.

  FIG. 12 is a block diagram showing the configuration of the video / audio output timing correction unit of the digital broadcast receiver according to the first embodiment. This figure shows the configuration of the video / audio output timing correction unit 10 shown in FIG. 1, which selects one of two input signals or data and outputs them, selectors 130 to 133, and a V_PTS_REG_A register (video data). PTS value register) 121, V_PTS_REG_B register (video data PTS value register) 122, subtractor 123, multiplier 124, V_δPTS_ALL register 125, adder 126, PCM_correct_time register 127, adder 128, comparator 129, A_PTS_REG_A register (audio data) PTS value register) 134, A_PTS_REG_B register (audio data PTS value register) 135, subtractor 136, multiplier 137, adder 138, comparator 139, flip-flops 140 and 141 including SR flip-flop circuits, and a D flip-flop circuit It is comprised by the flip-flop 142 which consists of.

  FIG. 13 is a timing chart showing the operation of the video / audio output timing correction unit of the digital broadcast receiver according to the first embodiment. FIG. 13A is a timing chart of signals and data related to video data, and FIG. 13B is a timing chart of signals and data related to audio data. The flip-flop 142 shown in FIG. 12 is composed of a D flip-flop circuit as described above, and receives the count enable signal cnt_en output from the PCR comparator 5 as the D input and is output from the oscillator 4 as the clk input. Input the clock signal clk. Based on these inputs, the flip-flop 142 generates and outputs a count enable signal cnt_en2 as shown in FIGS. Specifically, as shown in FIG. 8, when the count enable signal cnt_en becomes active, the count enable signal cnt_en2 indicating active is output in synchronization with the rising edge of the next clock signal clk.

  The selector 130 shown in FIG. 12 inputs the data pcr <41..9> output from the PCR comparison unit 5 to the A input and the data pts_v output from the video decoder 6 to the B input. Is switched to output to the V_PTS_REG_A register 121 as data pts_v_s. The selector 131 inputs the signal pcr_det output from the PCR comparison unit 5 to the A input and the PTS enable signal pts_v_w_en output from the video decoder 6 to the B input, and either signal is set as the PTS enable signal pts_v_w_en ′. The output is switched to the V_PTS_REG_A register 121 and the V_PTS_REG_B register 122.

  The selector 132 inputs the data pcr <41..9> to the A input, the data pts_a output from the audio decoder 7 to the B input, and outputs one of the data to the A_PTS_REG_A register 134 as the data pts_a_s. Switch. The selector 133 inputs the signal pcr_det to the A input and the audio enable signal pts_a_w_en output from the audio decoder 7 to the B input, and inputs one of the signals as the PTS enable signal pts_a_en ′ to the A_PTS_REG_A register 134 and the A_PTS_REG_B register 135. Switch to output. The selectors 130 to 133 select the B input when the count enable signal cnt_en2 output from the flip-flop 142 becomes active as shown in FIGS. 8 and 13, and select the A input otherwise. And output.

  The V_PTS_REG_A register 121 storing “0” as an initial value stores the data pts_v_s input from the selector 130 when the PTS enable signal pts_v_w_en ′ input from the selector 131 falls. Similarly, the V_PTS_REG_B register 122 storing “0” as an initial value shifts and inputs the data stored in the V_PTS_REG_A register 121 when the PTS enable signal pts_v_w_en ′ falls. Thereafter, the subtractor 123 calculates a difference value δpts_v between the values stored in the V_PTS_REG_A register 121 and the V_PTS_REG_B register 122 and outputs the difference value δpts_v to the adder 126. At the same time, the multiplier 124 inputs the difference value δpts_v output from the subtractor 123. The multiplier 124 obtains a difference value δpts_v ′ obtained by multiplying the difference value δpts_v by the frequency error data δf acquired from the PCR comparison unit 5, and the difference value δpts_v ′ when the signal pulse of the input PTS enable signal pts_v_w_en falls. Is output or updated and sent to the adder 126. Such an operation of updating / outputting the difference value δpts_v ′ is performed while the video / audio output timing correction unit 10 is operating.

  The adder 126 adds the difference value δpts_v input from the subtractor 123, the difference value δpts_v ′ input from the multiplier 124, and the data stored in the V_δPTS_ALL register 125 to generate and output data v_δpts_all. This data v_δpts_all is not only output to the adder 128, but at the same time, the data stored in the V_δPTS_ALL register 125 is updated to the value of this data v_δpts_all. The adder 128 inputs the data stored in the PCM_correct_time register 127 together with the data v_δpts_all, and adds these data. The PCM_correct_time register 127 stores data representing the time required for the correction processing of the PCM data correction unit 9 shown in FIG. 1, that is, data representing the offset time. Since the processing time of the PCM data correction unit 9 is constant, the data representing this offset time is represented by a fixed value and is handled in the initial setting. The offset time indicates the processing time from when PCM data is input to the PCM data correction unit 9 until the corrected PCM data is output.

  Thereafter, the comparator 129 shown in FIG. 12 compares the data pts'_v output from the adder 128 with the data local_cnt <41..9>, and 'pts'_v = local_cnt <41..9>. When the relationship 'is established, an output enable signal v_en having a pulse for one clock of the clock signal clk is generated and output. Although not shown in FIG. 12, the video / audio output timing correction unit 10 is configured such that the comparator 129 is in a reset state until an edge when the PTS enable signal pts_v_w_en first rises is input. Is done.

  In the data processing on the audio side, the PTS enable signal pts_a_w_en ′ is input from the selector 133 to the A_PTS_REG_A register 134 as shown in FIG. The A_PTS_REG_A register 134 stores the data pts_a_s at the falling timing of the input PTS enable signal pts_a_w_en ′, and at the same time, the data previously stored in the A_PTS_REG_A register 134 is shifted to the A_PTS_REG_B register 135. Thereafter, the subtracter 136 obtains a difference value δpts_a between values stored in the A_PTS_REG_A register 134 and the A_PTS_REG_B register 135 and outputs the difference value δpts_a to the adder 138. At the same time, the multiplier 137 receives the difference value δpts_a output from the subtractor 136. The multiplier 137 obtains a difference value δpts_a ′ obtained by multiplying the difference value δpts_a by the frequency error data δf acquired from the PCR comparison unit 5, and the difference value δpts_a ′ at the falling edge of the signal pulse of the input PTS enable signal pts_a_w_en. Is output / updated and sent to the adder 138. In the video / audio output timing correction unit 10, the processing so far is performed in the same manner as the data processing on the video side.

  The adder 138 adds the difference value δpts_a input from the subtractor 136 and the difference value δpts_a ′ input from the multiplier 137 to generate data pts′_a, and outputs the data pts′_a to the comparator 139. The comparator 139 compares the data local_cnt <41..9> with the data pts'_a output from the adder 138, and if 'pts'_a = local_cnt <41..9>' A signal a_set indicating active is generated by a pulse signal of one clock of the signal clk.

  The flip-flop 140 receives the signal a_set output from the comparator 138 as an S input, and receives a reset signal reset as an R input, and generates an enable signal a_en according to these SR inputs. The flip-flop 140 receives the signal a_set indicating active, and generates and outputs an output enable signal a_en indicating active if the reset signal reset does not indicate active.

  In the operation of the video / audio output timing correction unit 10, the output data control unit 11 is controlled to always perform timing correction on video data, whereas the output data control unit 11 is controlled to control audio data. The reason why the timing correction is only performed first is that the number of video frames is not limited to 30 frames, for example, and the number of video frames to be decoded is variable. On the other hand, the number of audio frames is fixed, and the number of audio frames to be decoded is also constant. Therefore, the decoding of the audio frame does not cause a failure even if the output timing set first is continuously used. Accordingly, in the invention according to the first embodiment, the timing control on the video data side is frequently performed, and the timing control on the audio data side is only performed first, and the operation control relating to the timing correction of the video data and the audio data is simplified. .

  Further, the flip-flop 141 shown in FIG. 12 receives the count enable signal cnt_en2 at the S input and the reset signal reset at the R input, and receives the PES enable signal pes_en for controlling the operation of the transport decoder 3 described above. Generate. When the reset signal reset does not indicate active and the count enable signal cnt_en2 indicates active, the flip-flop 141 outputs the PES enable signal pes_en indicating active.

  FIG. 14 is a block diagram showing the configuration of the PCM data correction unit of the digital broadcast receiver according to the first embodiment. This figure shows a configuration of the PCM data correction unit 9 shown in FIG. 1, and an upsampling unit (upsampling) that inputs audio data adata as PCM data from the audio decoder 7 and performs U-times upsampling. (Means) 151, a low-pass filter 152 that performs filtering of PCM data output from the upsampling unit 151, an interpolation data temporary buffer (data buffer) 153 that holds PCM data output from the low-pass filter 152, and an output from the PCR comparison unit 5 From the interpolation data temporary buffer 153 and the interpolation data temporary buffer 153 which input the frequency error data δf thus inputted and control the operation of the interpolation data temporary buffer 153 and the interpolation data temporary buffer 153. A data storage memory 155 and outputs the accumulated force has been PCM data as appropriate audio correction data adata '. In addition, as described above, the PCM data correction unit 9 includes a clock generation unit (not shown) that receives the clock signal clk and generates the reproduction sampling clock clk2 based on the clock signal clk. The reproduction sampling clock clk2 has a sampling frequency used when generating PCM data in the transmission side system. Specifically, the reproduction is performed on the receiver side so as to correspond to the sampling clock of the AAC encoder provided on the transmission system side. Note that the sampling frequency on the transmission system side is described in an AAC-encoded ES (Elementary Stream) included in the PES packet output from the transport decoder 3 described above, and the clock generation unit converts this description content. Acquire and generate a reproduction sampling clock clk2.

  FIG. 15 is an explanatory diagram showing PCM data processed by the upsampling unit of the digital broadcast receiver according to the first embodiment. This figure shows an image when the upsampling unit 151 interpolates the AC component zero value data AC0 into each PCM data. For example, the insertion state of the data AC0 when the upsampling factor U is tripled. Is shown. The upsampling unit 151 performs an operation process as follows while synchronizing with the reproduction sampling clock clk2. When PCM data adata is input from the audio decoder 7 and this PCM data adata is expressed as, for example, data PCM_N-1, data PCM_N, data PCM_N + 1, or when upsampling is performed with an upsampling factor U of U = 3 Inserts U-1 pieces of data AC0 after data PCM_N-1, data PCM_N and data PCM_N + 1, respectively.

  FIG. 15A shows data PCM_N−1, data PCM_N, and data PCM_N + 1 of PCM data sequentially input to the upsampling unit 151, which is before being processed by the PCM data correction unit 9. PCM data. As shown in the figure, the upsampling unit 151 inserts two data AC0 after the data PCM_N-1, further inserts two data AC0 after the subsequent data PCM_N, and further follows the data PCM_N + 1. Two data AC0 are inserted after. As shown in FIG. 15B, before the data AC0 is inserted, that is, before the interpolation, the signal waveforms that smoothly transition are represented by the data PCM_N-1, PCM_N, and PCM_N + 1. As described above, when the zero value data AC0 of the AC component is inserted between the PCM data, the signal corresponding to the position where the data AC0 is interpolated becomes a zero value. The waveform represented by the data PCM_N-1, AC0, AC0, PCM_N, AC0, AC0, PCM_N + 1, AC0, AC0 has a higher frequency component than the signal waveform originally represented by the audio data adata. The upsampling unit 151 outputs PCM data indicating such a waveform to the low-pass filter 152.

  FIG. 16 is an explanatory diagram showing PCM data processed by the low pass filter of the digital broadcast receiver according to the first embodiment. In this figure, PCM data in which the number of samplings is increased by complementing data AC0 indicating a zero value of the AC component is input to the low-pass filter 152, and the low-pass filter 152 has the interpolated PCM data in the original frequency band. The processing operation for limiting the band of the frequency component included in the PCM data is shown.

  FIG. 16A shows PCM data input to the low-pass filter 152 and PCM data filtered by the low-pass filter 152. As shown in the figure, the PCM data before passing through the low-pass filter 152, that is, the PCM data up-sampled by the up-sampling unit 151 as U = 3, for example, is data PCM_N-1, data AC0, data AC0 as described above. , Data PCM_N, data AC0, data AC0, data PCM_N + 1, data AC0, and data AC0 are sequentially input to the low-pass filter 152. As shown in FIG. 16A, the low-pass filter 152 to which the PCM data is input in this way converts the data PCM_N-1 before passing through the filter into the data PCM_N-1_0 after passing through the filter, and the data AC0 before passing through the next filter. Data PCM_N-1_1 after passing the filter, data AC0 before passing the next filter to data PCM_N-1_2 after passing the filter, data PCM_N before passing the next filter to data PCM_N_0 after passing the filter, The previous data AC0 is converted to data PCM_N_1, the next filtered data AC0 is converted to data PCM_N_2, and the next filtered data PCM_N + 1 is converted to filtered data PCM_N + 1_0. Filter the data AC0 before passing the next filter to the data PCM_N + 1_1 after passing the filter, data AC0 before passing the next filter to the data PCM_N + 1_2 after passing the filter, etc. The In this filtering, as shown in FIG. 16-2, the waveforms indicated by the data PCM_N-1, AC0, AC0, PCM_N, AC0, AC0, PCM_N + 1, AC0, AC0 before passing through the filter are shown as after passing through the filter. The high frequency component included in the zero value data AC0 is removed so as to obtain a smooth transition waveform. The PCM data that has passed through the low-pass filter 152 thus becomes data indicating the waveform of the audio signal.

  PCM data output from the low-pass filter 152, that is, data PCM_N-1_0, PCM_N-1_1, PCM_N-1_2, PCM_N_0, PCM_N_1, PCM_N_2, PCM_N + 1_0, PCM_N + 1_1, after passing through the filter shown in FIG. PCM_N + 1_2 is stored and accumulated in the successive interpolation data temporary buffer 153. Note that the number appended to the last end of each data name indicates a phase value corresponding to the data described later.

  For example, the interpolation data temporary buffer 153 composed of a 2-port RAM temporarily stores all the PCM data that has passed through the low-pass filter 152, that is, the interpolated PCM data. The interpolation data temporary buffer read control unit 154 reads the PCM data interpolated from the interpolation data temporary buffer 153 based on the frequency error data δf acquired from the PCR comparison unit 5 as will be described later, and stores the PCM data in the data storage memory 155. To write. The data storage memory 155 sequentially outputs the PCM correction data adata ′ in synchronization with the reproduction sampling clock clk2. This output operation is performed while incrementing a read address of the data storage memory 155, that is, an address for reading the PCM correction data adata 'in synchronization with the reproduction sampling clock clk2.

  FIG. 17 is a flowchart showing the operation of the interpolation data temporary buffer read control unit of the digital broadcast receiver according to the first embodiment. The flowcharts of FIGS. 17A and 17B show the control operation of the interpolation data temporary buffer read control unit 154 shown in FIG. The interpolation data temporary buffer read control unit 154 calculates the phase shift value using the frequency error data δf input from the PCR comparison unit 5 as described above (step ST101). This phase shift value is a phase value shifted by a single correction process. Further, this phase value is a value representing a phase in a range from −2π to + 2π using radians as a unit. The interpolation data temporary buffer read control unit 154 obtains the phase shift value by the calculation of 2π × δf.

Thereafter, it is determined whether or not the phase shift value is 0 or more (step ST102). If the phase value is 0 or more, the process proceeds to step ST103. If not, the process proceeds to step ST111. If it is determined that the phase shift value is greater than or equal to 0, the current phase value given with an initial value of 0 is read (step ST103). The phase value read here is data held in a register provided in the interpolation data temporary buffer read control unit 153, and is added to the phase shift value in step ST109 described later. Here, the phase value is a value indicating a phase shift with respect to sampling timing of actual transmission sampling data, that is, audio data transmitted from the transmission side system. Next, it is determined whether or not this phase value is smaller than 2π (step ST104). When it is determined that the phase value is smaller than 2π, the process proceeds to step ST107. If it is determined that the phase value is not smaller than 2π, the process proceeds to step ST105. If it is determined in step ST104 that the phase value is smaller than 2π, the read address of the interpolation data temporary buffer 153 is corrected based on the phase value (step ST107). The correction address is calculated using the following formula (4).
Correction address = reference address + (phase value / 2π) × U (4)
(U is the magnification when up-sampling is performed)
Note that the reference address in equation (4) indicates the address where the reference data before upsampling of PCM data, that is, before interpolation, is stored, and the data PCM_N-1_0, PCM_N_0, This indicates the address where the data to be read when the phase value is 0, such as PCM_N + 1_0 and PCM_N + 2_0. Further, the reference data indicates a data value read with a phase value = 0. This reference address is stored and saved in the interpolation data temporary buffer read control unit 154 shown in FIG. 14, and every time the reference address is used as a correction address, reference address = reference address + U (U is up) The content is updated as the magnification when sampling).

  After correcting the read address in step ST107, the data stored in the correction address is read from the interpolation data temporary buffer 153, and this data is written in the data storage memory 155 (step ST108). Next, the phase shift value is added to the phase value (step ST109). Further, the address of the interpolation data temporary buffer 153 is skipped to the next reference address (step ST110). Then, it returns to step ST101 again and repeats the same sequence. If it is determined in step STS104 that the phase value is 2π or more, the process proceeds to step ST105, where 2π is subtracted from the phase value (step ST105), and the address of the interpolation data temporary buffer 153 is set to step ST110. Similarly, the reference address is skipped (step ST106). After skipping to the reference address, the process returns to step ST103 and the same sequence is performed. On the other hand, if it is determined in step ST102 that the phase shift value is not 0 or more, the process proceeds to step ST111. Thereafter, the phase value is read out similarly to step ST103 (step ST111), and then the read address is corrected similarly to step ST107 (step ST112). Thereafter, in the same manner as in step ST108, data is read from the correction address of the interpolation data temporary buffer 153, and then this data is written in the data storage memory 155 (step ST113). Thereafter, the phase shift value is added to the phase value as in step ST109 (step ST114). Next, it is determined whether or not the phase value is −2π or more (step ST115). If the phase value is −2π or more, the process proceeds to step ST117. If the phase value is less than −2π, the process proceeds to step ST116. Transition. In step ST117, the address of the interpolation data temporary buffer 153 is skipped, and the process proceeds to step ST101 again. In step ST116, 2π is added to the phase value to update the phase value, and the process proceeds to step ST111 again, and the subsequent processes are repeated.

  In this way, the interpolation data temporary buffer read control unit 154 controls the data read from the interpolation data temporary buffer 153, and stores / accumulates this data in the data accumulation memory 155. The PCM data correction unit 9 processes the input audio data adata and outputs the data stored in the data storage memory 155 to the output data control unit 11 as the audio correction data adata 'as described above.

  Thereafter, the output data control unit 11 outputs the audio correction data adata ′ to the D / A converter 13 based on the output enable signal a_en output from the video / audio output timing correction unit 10 as described above.

  As described above, according to the invention of the first embodiment, the frequency error data δf is obtained from the PCR sequentially acquired by the PCR comparison unit 5, and the video / audio output timing correction unit 10 determines the video buffer based on the frequency error data δf. The output data control unit 3 and the output data control unit 11 of the audio buffer are controlled so that the synchronization timing of the video signal output from the D / A converter 12 and the audio signal output from the D / A converter 13 is corrected. Therefore, the video signal and the audio signal can be synchronized without providing a PLL circuit, and the AV decoder 14 and the like can be made into one chip, so that the receiver can be reduced in size and price. There is an effect that can be.

  In addition, since the PCM data correction unit 9 corrects the audio data adata which is PCM data based on the frequency error data δf, the sampling data on the transmission system side is data sampled with the reproduction sampling clock on the receiver side. As a result, an overflow or underflow of the audio output buffer is prevented, and an abnormal sound can be prevented.

Embodiment 2. FIG.
The second embodiment of the present invention will be described below.
The digital broadcast receiver according to the second embodiment is configured in the same manner as the digital broadcast receiver according to the first embodiment except for the PCM data correction unit, and operates similarly. Here, description of parts other than the PCM data correction unit configured similarly to the digital broadcast receiver according to Embodiment 1 shown in FIG. 1 and the like is omitted.

  FIG. 18 is a block diagram showing the configuration of the PCM data correction unit of the digital broadcast receiver according to Embodiment 2 of the present invention. 18 corresponds to the PCM data correction unit 9 shown in FIG. 1. Like the PCM data correction unit 9 described with reference to FIG. 14 in the first embodiment, the frequency error data from the PCR comparison unit 5 is shown. δf is input, audio data adata is input from the audio decoder 7, and audio correction data adata ′ is output to the output data control unit 11, and more appropriate data correction is performed. The PCM data correction unit shown in FIG. 18 includes a data storage unit 181 that stores input audio data adata, and an FFT operation unit (FFT operation) that performs an FFT (Fast Fourier Transform) operation on the data stored in the data storage unit 181. Means) 182, phase correction and IDFT (Inverse Discrete-time Fourier Transform) calculation by inputting data fft_result output from FFT calculation unit 182, phase correction / IDFT calculation unit (phase correction calculation means) 183, PCR comparison unit 5 shows the calculation results of the phase correction control unit (phase correction control means) 185 and the phase correction / IDFT calculation unit 183 that input the frequency error data δf from 5 and output the data θ and the signal P_INT to the phase correction / IDFT calculation unit 183. A data storage unit 184 that stores data and outputs the data as audio correction data adata ′ is provided. The PCM data correction unit 9 according to the second embodiment also includes a clock generation unit (not shown) that generates the reproduction sampling clock clk2 in the same manner as the PCM data correction unit 9 described in the first embodiment.

  The data storage unit 181 temporarily stores the PCM data of the audio data adata output from the audio decoder 7 as described above, and outputs the stored data to the FFT operation unit 182 every 1024 samples. The FFT calculation unit 182 multiplies sampling data obtained by cutting out 1024 samples as one frame by a window function such as a Hamming window for one frame as preprocessing of the FFT calculation. Thereafter, the occurrence of aliasing distortion is prevented by performing an FFT operation.

In general, in the periodic function g (t) where g (t + ΔT) = g (t) holds, an approximate expression such as the following expression (5) holds in the period ΔT.
g (t) ≈ (1 / N) × Σ {ak × exp (j × k × ω × t)} (5)
(N = number of sampling during ΔT period, 0 ≦ k ≦ N (k is an integer), ω = 2π × f, 1 / f = ΔT, j ^ 2 = −1)
The coefficient ak (k is an integer of 0 or more) of each frequency component shown in the equation (5) can be calculated by FFT calculation.

Here, for example, when processing sampling data of 1024 samples, assuming that the sampling frequency on the transmission system side is f0 and the frequency of the reproduction sampling clock on the receiver side is f0 × (1-δf) (where -1 <δf) <1) The original voice signal on the transmission system side is expressed by the following equation (6). In the following equations, AK is a coefficient of each frequency component on the transmission system side, and BK is a coefficient of each frequency component on the receiver side.
G (t) ≈A0 + 1/1024 × Σ {Ak × exp (j × k × 2π × f0 × t)} (6)
Further, PCM data reproduced on the receiver side is expressed by the following equation (7).
G ′ (t) = A0 + 1/1024 × Σ {Bk × exp (j × k × 2π × f0 × (1−δf) × t)}
... (7)
Expression (7) can be expressed as the following expression (8).
G ′ (t) = A0 + 1/1024 × Σ {Bk × exp (j × k × 2π × f × t)
× exp (j × k × 2π × f0 × (−δf) × t)} (8)
Here, when equation (8) is replaced with θ = 2π × f0 × (−δf) × t, the following equation (9) is obtained.
G ′ (t) = A0 + 1/1024 × Σ {Bk × exp (j × k × θ) × exp (j × k × 2π × f × t)}
... (9)
Here, when equation (9) is replaced with Bk × exp (j × k × θ) = Ak, the following equation (10) is obtained.
G ′ (t) = A0 + 1/1024 × Σ {Ak × exp (j × k × 2π × f × t)} ≈G (t) (10)
Thus, Expression (10) is the same as Expression (6).

  This is because, when processing the PCM data sampled on the transmission system side on the receiver side, the sampling frequency error between the transmission system and the receiver side is obtained, and sampling is performed after performing the FFT operation from the frequency error. By correcting the data, it means that it can be converted as if it were PCM data sampled at the reproduction sampling frequency on the receiver side. In fact, the sampling data after performing the FFT operation, that is, the above-mentioned data fft_result is a symmetric value centering on half of all the samples, and the value is used as a sine function. And can be expressed using sin (k × ω × t). From this, the data fft_result can be expressed as sin (k × (ω × t + θ)) = sin (k × ω × t) cos θ + cos (k × ω × t) sin θ, and the sine value and cosine value are expressed as The PCM data can be corrected by calculation using these. However, when θ is 2π or more, it is necessary to interpolate the sampling data by one data. Conversely, if θ is −2π or less, it is necessary to thin out the sampling data by one data. The phase correction control unit 185 calculates θ = 2π × f0 × (−δf) × t by the time for each sampling point, and when θ ≧ 2π and θ ≦ −2π that further requires interpolation or thinning of the sampling data. To generate a signal P_INT and notify the phase correction / IDFT calculation unit 183 of the signal.

  The phase correction / IDFT calculator 183 creates a corrected phase sine / cosine value lookup table 202, and uses this corrected phase sine / cosine value lookup table 202 and the sending-side IDFT lookup table 203 to look up an IDFT calculation. A table 205 is created. Further, an IDFT calculation result of each frequency component is obtained using the data fft_result calculated by the FFT calculation unit 182 and the IDFT calculation lookup table 206, and a data sum of these calculation results is obtained to store data. This is written as PCM correction data in the unit 184. The data storage unit 184 outputs the PCM correction data stored in synchronization with the reproduction sampling clock clk2, for example, as audio correction data adata '.

  FIG. 19 is a flowchart showing the operation of the phase correction control unit of the digital broadcast receiver according to the second embodiment. The flowcharts of FIGS. 19A and 19B illustrate the operation of the phase correction control unit 185 illustrated in FIG. The phase correction control unit 185 includes an N register used in arithmetic processing described later, a correction phase value register that stores a correction phase value, and a phase initial value register that stores a phase initial value. The phase correction control unit 185 receives the frequency error data δf from the PCR comparison unit 5 shown in FIG. 1, and performs a calculation using the frequency error data δf in the same manner as the PCM data correction unit 9 described in the first embodiment. To calculate the phase shift value (step ST201). Here, the phase shift value is a phase value shifted by one correction, and is synonymous with the phase shift value defined in the first embodiment. Next, the phase initial value stored in the phase initial value register is written in the correction phase value register (step ST202). In this phase initial value register, 0 is set as an initial value, and the stored phase initial value is updated each time phase correction is performed.

  Next, it is determined whether or not the phase shift value is 0 or more (step ST203). If the value is 0 or more, the process proceeds to step ST204, and if not, the process proceeds to step ST214. In step ST204, the correction phase value stored in the correction phase value register is read. Here, the correction phase value is a value indicating a phase shift of the sampling point, that is, a phase difference. Next, it is determined whether or not the correction phase value is smaller than 2π (step ST205). If the correction phase value is smaller than 2π, the process proceeds to step ST209, and otherwise, the process proceeds to step ST206.

  Next, phase correction control section 185 determines whether or not the READY signal input from phase correction / IDFT calculation section 183 indicates active (step ST209). When the READY signal indicates active, the process proceeds to step ST210, and when the READY signal does not indicate active, step ST209 is repeated.

  In step ST210, the phase correction control unit 185 notifies the phase correction / IDFT calculation unit 183 of the correction phase value being processed at this time. Thereafter, the phase shift value is added to the notified corrected phase value, and the content stored in the corrected phase value register is updated with the calculated value (step ST211). Next, it is determined whether or not the value of the N register is less than a phase initial value number described later (step ST212). If the value of the N register is less than the phase initial value number, the process proceeds to step ST213, where N <phase. If the initial value number is not established, the process proceeds to step ST224. In step ST213, +1 is added to the value of the N register, the value of the N register is incremented, the process returns to step ST204, and the subsequent processes are repeated.

  In Step ST205, when it is determined that the correction phase value is 2π or more, the phase correction control unit 185 subtracts 2π from the correction phase value for which the determination has been performed, and uses the subtraction value as the phase correction value. (Step ST206), a P_INIT signal indicating active is output to the phase correction / IDFT calculation unit 183, and an interrupt process is notified (step ST207). Thereafter, 1 is subtracted from the phase initial value number, the phase initial value number is updated with this calculated value (step ST208), and the process proceeds to step ST209. Note that the initial value of the phase initial value number is 1023 which is the sampling number -1.

  On the other hand, if it is determined in step ST203 that the phase shift value is not 0 or more, the process proceeds to step ST214. In step ST214, the correction phase value stored in the correction phase value register is read. Next, it is determined whether or not the read correction phase value is larger than −2π (step ST215). If the correction phase value is greater than −2π, the process proceeds to step ST219, and if the correction phase value is −2π or less, the process proceeds to step ST216.

  In step ST219, it is determined whether or not the READY signal input from the phase correction / IDFT calculation unit 183 indicates active, and only when the signal indicates active, the process proceeds to step ST220. Until the READY signal indicates active, step ST219 Repeat the process. After the READY signal becomes active, the correction phase value is notified to the phase correction / IDFT calculation unit 183 (step ST220), the phase shift value is added to the correction phase value, and the calculated value is stored in the correction phase value register. The updated contents are updated (step ST221).

  Next, it is determined whether or not the value of the N register is less than the phase initial value number (step ST222). When the value of the N register is less than the initial value number, the process proceeds to step ST223, and when the value of the N register is not less than the initial value number, the process proceeds to step ST224. In step ST223, 1 is added to the value of the N register to increment the value of the N register, and the process returns to step ST214 to repeat the subsequent processes.

  If it is determined in step ST215 that the correction phase value is −2π or less, the process proceeds to step ST216. In step ST216, 2π is added to the correction phase value to be determined in step ST215, and this value is used as the correction phase value. Next, the phase correction control unit 185 outputs a P_INT signal indicating active to the phase correction / IDFT correction unit 183, and notifies an interrupt process (step ST217). Thereafter, 1 is added to the phase initial value number, the phase initial value number is updated with the calculated value (step ST218), and the process proceeds to step ST219.

  Further, when the process proceeds from step ST212 or step ST222 to step ST224, the correction phase value is read again. Thereafter, it is determined whether or not the correction phase value read in step ST224 is larger than −2π (step ST225). If it is determined that the correction phase value is greater than −2π, the process proceeds to step ST226, and if it is not, the process proceeds to step ST216.

  In step ST226, the corrected phase value is written in the phase initial value register, and then the process proceeds to step ST227. In step ST227, the correction phase value is cleared, then the value of the N register is cleared (step ST228), 1023 is set to the phase initial value number (step ST229), the process returns to step ST201 and the subsequent processes are repeated.

Next, the phase correction / IDFT calculation unit will be described.
FIG. 20 is a block diagram showing the configuration of the phase correction / IDFT calculation unit of the digital broadcast receiver according to the second embodiment. This figure shows the configuration of the phase correction / IDFT correction unit 183 shown in FIG. The phase correction / IDFT correction unit 183 calculates a correction phase sine / cosine value lookup table calculation unit 201, a correction phase sine / cosine value lookup table 202, a transmission-side IDFT lookup table 203, and an IDFT calculation lookup table calculation. Section 204, FFT calculation result storage section 205, IDFT calculation lookup table 206, and IDFT calculation processing section 207.

  The corrected phase sine / cosine value look-up table calculation unit 201 calculates the corrected phase sine / cosine value based on the corrected phase data θ that is notified from the phase correction control unit 185 and indicates the corrected phase value, and the calculated value Is written into the corrected phase sine / cosine value lookup table 202. FIG. 21 is an explanatory diagram illustrating a corrected phase sine / cosine value lookup table created by the corrected phase sine / cosine value lookup table calculation unit of the digital broadcast receiver according to the second embodiment. This figure exemplifies an image of a table created for the sine value in the correction phase sine / cosine value lookup table. This correction phase sine / cosine value lookup table 202 is updated for every 1024 samples of PCM data before correction, and is usually a table having values of 1024 × 1024. However, when the P_INT signal indicating active is output from the phase correction control unit 185, a table having each value of 1024 × 1023 is created when the correction phase value is positive, and 1024 × when the correction phase value is negative. A table having each value of 1025 is created.

  The correction phase sine / cosine value lookup table calculation unit 201 outputs a Phase_OK signal to the IDFT calculation lookup table calculation unit 204 every time the correction phase sine / cosine value lookup table 202 is created. When the Phase_OK signal is input, the IDFT calculation lookup table calculation unit 204 creates an IDFT calculation lookup table 206 using the corrected phase sine / cosine value lookup table 202 and the transmission side IDFT lookup table 203. The transmission side IDFT lookup table 203 used at this time is a lookup table used for the IDFT calculation when the correction phase value = 0, and each value described in this table is a fixed value.

  When the A_INT signal is input from the corrected phase sine / cosine value lookup table calculation unit 201, the IDFT calculation lookup table calculation unit 204 creates an IDFT calculation lookup table 206 having a number of samples of 1024 × 1025 and corrects the correction phase. When the M_INT signal is input from the sine / cosine value lookup table calculation unit 201, the IDFT calculation lookup table 206 having a number of samples of 1024 × 1023 is created.

  Further, when the A_INT signal or the M_INT signal is input from the correction phase sine / cosine value lookup table calculation unit 201 to the IDFT calculation lookup table calculation unit 204, the correction phase sine / cosine value lookup table calculation unit 204 Data SEND_IDFT_ADR is input from 201. The IDFT calculation lookup table calculation unit 204 changes the reference order of the transmission side IDFT lookup table 203 based on the data SEND_IDFT_ADR and creates the IDFT calculation lookup table 206.

  Further, the IDFT calculation lookup table calculation unit 204 outputs an IDFT_OK signal to the IDFT calculation processing unit 207 after the IDFT calculation lookup table 206 is completed. The IDFT calculation processing unit 207 that has received the IDFT_OK signal acquires the FFT calculation result data fft_result from the FFT calculation result storage unit 205, and uses this data fft_result and the contents described in the IDFT calculation lookup table 206 to perform the IDFT calculation. And the calculation result of 1024 samples is obtained and output to the data storage unit 184. Further, when the IDFT calculation lookup table calculation unit 204 creates the IDFT calculation lookup table 206 with the number of samples 1023, the IDFT calculation lookup table 206 outputs the I_INT0 signal to the IDFT calculation processing unit 207, and the IDFT calculation lookup table 206 with the number of samples 1025 is output. If created, the I_INT1 signal is output to the IDFT arithmetic processing unit 207. When the IDFT lookup table 206 having 1024 samples is created, neither the I_INT0 signal nor the I_INT1 signal is output.

Next, the operation of the correction phase sine / cosine value lookup table calculation unit 201 will be described in detail.
FIG. 22 is a flowchart illustrating the operation of the correction phase sine / cosine value lookup table calculation unit of the digital broadcast receiver according to the second embodiment. The flowcharts shown in FIGS. 22-1 and 22-2 show the operation of the correction phase sine / cosine value lookup table calculation unit 201 shown in FIG. The correction phase sine / cosine value lookup table calculation unit 201 receives the correction phase data θ indicating the correction phase value from the phase correction control unit 185, and sets the correction phase data θ as the phase value α (step ST301). Next, the address of the correction phase sine / cosine value lookup table to be set, that is, the initial value of the data LUT_ADR is set as the LUT address (step ST302). Here, the initial value of the LUT address refers to the address to which the value of the data LUT (0,0) is written, and the LUT address of the data LUT (M, N) is LUT address = LUT address initial value + 1024 × (M− 1) + N-1.

  Next, it is determined whether or not a P_INT signal indicating active is input from the phase correction control unit 185 (step ST303). When the P_INT signal indicating active is input, the process proceeds to step ST304, and when not input, the process proceeds to step ST308. In step ST304, the current LUT address is stored in the SEND_IDFT_ADR register as data SEND_IDFT_ADR. Next, it is determined whether or not the phase value indicated by the correction phase data θ is positive (step ST305). When the phase value indicated by the correction phase data θ is positive, the process proceeds to step ST307, and when the phase value of the correction phase data θ is not positive, the process proceeds to step ST306. In step ST306, the A_INT signal is notified to the IDFT calculation lookup table calculation unit 204. At this time, the data SEND_IDFT_ADR stored in the SEND_IDFT_ADR register, that is, the LUT address is notified, and the process proceeds to step ST308.

  In step ST305, when it is determined that the correction phase data θ is not a positive value, the M_INT signal is output to the IDFT calculation lookup table calculation unit 204, and at that time, the LUT address stored in the SEND_IDFT_ADR register is also used. Notification is made (step ST307), and then the process proceeds to step ST308. Next, each value of sine sin α and cosine cos α is calculated from phase value α (step ST308), and sine sin α, cosine as data LUT (M, N) is stored in correction phase sine / cosine value lookup table 202. Each value of cos α is written (step ST309). Next, the value of the correction phase data θ is added to the phase value α, and the phase value α is updated with this value (step ST310). Next, it is determined whether or not the value of the M register is less than 1023 (step ST311). When the value of the M register is less than 1023, the process proceeds to step ST316, and when the value of the M register is not less than 1023, the process proceeds to step ST312.

  In step ST316, 1 is added to the value of the M register, the value of the M register is updated with this value, and then the process returns to step ST302 to repeat the subsequent processes. In step ST312, the value of the M register is cleared. Next, a READY signal indicating active is set (step ST313), and the READY signal is output to the phase correction control unit 185. The READY signal is set to indicate active in the initial state, and is automatically canceled when the correction phase data θ indicating the interpolation phase value is set to the phase value α.

  Next, it is determined whether or not the value of the N register is 1025 (step ST314). When the value of the N register is 1025, the process proceeds to step ST317, and when the value of the N register is not 1025, the process proceeds to step ST315. In step ST315, 1 is added to the value of the N register, this value is updated as the value of the N register, the process returns to step ST301 and the subsequent steps are repeated. In Step ST317, the Phase_OK signal is output to the IDFT calculation lookup table calculation unit 204, and the process proceeds to Step ST318. Next, the value of the N register is cleared (step ST318), the process returns to step ST301 and the subsequent processes are repeated.

Next, the operation of the IDFT calculation lookup table calculation unit 204 will be described in detail.
FIG. 23 is a flowchart showing the operation of the IDFT calculation lookup table calculation unit of the digital broadcast receiver according to the second embodiment. What is shown in the flowcharts of FIGS. 23-1, 23-2, and 23-3 is the operation of the IDFT calculation lookup table calculation unit 204 shown in FIG. If the Phase_OK signal output from the corrected phase sine / cosine value lookup table calculation unit 201 is input, the IDFT calculation lookup table calculation unit 204 proceeds to step ST402. If the Phase_OK signal is not input, step ST401 is repeated and the process waits until the Phase_OK signal is input.

  In step ST402, it is determined whether or not the M_INT signal is input from the corrected phase sine / cosine value lookup table calculation unit 201. When the M_INT signal is input, the process proceeds to step ST403, and when the M_INT signal is not input, the process proceeds to step ST422. In step ST422, it is determined whether or not the A_INT signal is input from the corrected phase sine / cosine value lookup table calculation unit 201. When the A_INT signal is input, the process proceeds to step ST423, and when the A_INT signal is not input, the process proceeds to step ST442.

  In step ST403, an I_INT0 signal is output to IDFT arithmetic processing section 207. Next, it is determined whether or not the value indicated by the data SEND_IDFT_ADR notified from the corrected phase sine / cosine value lookup table calculation unit 201 is equal to or greater than the value of the N register (step ST404). When the value indicated by the data SEND_IDFT_ADR is less than the value of the N register, the process proceeds to step ST405, and when the value of the N register is equal to or greater than the value of the data SEND_IDFT_ADR, the process proceeds to step ST413. In step ST405, the data LUT (M, N) is read from the corrected phase sine / cosine value lookup table 202. Next, the transmission side IDFT data (M, N) is read from the transmission side IDFT lookup table 203. Next, a value described in the IDFT calculation lookup table 206 is calculated from the data value read from each table (step ST407). Next, the calculated value is written as data (M, N) in the IDFT calculation lookup table 206 (step ST408). Thereafter, it is determined whether the value of the M register is 1023 (step ST410). When the value of the M register is 1023, the process proceeds to step ST411, and when the value of the M register is not 1023, the process proceeds to step ST409. In step ST409, 1 is added to the value of the M register, this value is updated as the value of the M register, the process returns to step ST404 and the subsequent processes are repeated. In step ST411, the value of the M register is cleared. Next, 1 is added to the value of the N register, this value is incremented as the value of the N register, the value of the N register is updated (step ST412), the process returns to step ST404 and the subsequent processes are repeated.

  If it is determined in step ST404 that the value of the N register is equal to or greater than the value of the data SEND_IDFT_ADR, the correction phase value is considered to exceed 2π, and the data is obtained from the correction phase sine / cosine value lookup table 202. LUT (M, N) is read (step ST413), and the sending side IDFT data (M, N + 1) is read from the sending side IDFT lookup table 203 to thin out one sampling number in this process (step ST414). Thereafter, in step ST415, a value described in the IDFT calculation lookup table 206 is calculated, and in step ST416, the calculated value is written as data (M, N) in the IDFT calculation lookup table 206. Thereafter, it is determined whether or not the value of the M register is 1023 (step ST417). If the value of the M register is 1023, the process proceeds to step ST419. If the value of the M register is not 1023, the process proceeds to step ST418. Migrate to

  In step ST418, 1 is added to the value of the M register, the value of the M register is incremented and updated, and the process returns to step ST404 to repeat the subsequent processes. In step ST419, the value of the M register is cleared. Next, it is determined whether or not the value of the N register is 1022 (step ST420). When the value of the N register is 1022, the process proceeds to step ST451, and when the value of the N register is not 1022, the process proceeds to step ST421. In step ST421, 1 is added to the value of the N register to increment and update the value of the N register, and the process returns to step ST404 to repeat the subsequent processes.

  As described above, when it is determined in step ST422 that the A_INT signal is input from the corrected phase sine / cosine value lookup table calculation unit 201, the I_INT1 signal is output to the IDFT arithmetic processing unit 207 (step ST423), and then Similarly to step ST404 described above, it is determined whether or not the value indicated by the data SEND_IDFT_ADR notified from the corrected phase sine / cosine value lookup table calculation unit 201 is equal to or greater than the value of the N register (step ST424). When the value indicated by the data SEND_IDFT_ADR is less than the value of the N register, the process proceeds to step ST425, and when the value of the N register is equal to or greater than the value of the data SEND_IDFT_ADR, the process proceeds to step ST433. The process of step ST425 to step ST432 shown in FIG. 23-2 is processed in the same manner as the process of step ST405 to step ST412 shown in FIG. 23-1, and the process returns to step ST424. Here, description of the processing operation performed in the process of step ST425 to step ST432 is omitted.

  If it is determined in step ST423 that the value of the N register is equal to or greater than the value of the data SEND_IDFT_ADR, the correction phase value is considered to be −2π or less, and the data LUT ( M, N) is read out (step ST433), and the sending side IDFT data (M, N−1) is read from the sending side IDFT lookup table 203 to interpolate one sampling number in this process (step ST434). Thereafter, a value described in the IDFT calculation lookup table 206 is calculated (step ST435), and the calculated value is written as data (M, N) in the IDFT calculation lookup table 206 (step ST436). Thereafter, it is determined whether or not the value of the M register is 1023 (step ST437). If the value of the M register is 1023, the process proceeds to step ST439. If the value of the M register is not 1023, the process proceeds to step ST438. Transition.

  In step ST438, 1 is added to the value of the M register, the value of the M register is incremented and updated, and the process returns to step ST424 to repeat the subsequent processes. In step ST439, the value of the M register is cleared. Next, it is determined whether or not the value of the N register is 1024 (step ST440). When the value of the N register is 1024, the process proceeds to step ST451, and when the value of the N register is not 1024, the process proceeds to step ST441. In step ST441, 1 is added to the value of the N register to increment and update the value of the N register, and the process returns to step ST424 to repeat the subsequent processes.

  If it is determined in step ST422 that the A_INT signal is not input, the data LUT (M, N) is read from the correction phase sine / cosine value lookup table 202 (step ST442). Next, the transmission side IDFT data (M, N) is read from the transmission side IDFT lookup table 203 (step ST443). Next, the value described in the IDFT calculation lookup table is calculated in the same manner as in step ST407 described above (step ST444). Next, the calculated value is written in the IDFT calculation lookup table 206 as data (M, N) (step ST445). Thereafter, it is determined whether or not the value of the M register is 1023 (step ST446). When the value of the M register is 1023, the process proceeds to step ST448, and when the value of the M register is not 1023, the process proceeds to step ST447. In step ST447, 1 is added to the value of the M register, this value is updated as the value of the M register, the process returns to step ST442 and the subsequent processes are repeated. In step ST448, the value of the M register is cleared.

  Next, it is determined whether or not the value of the N register is 1023 (step ST449). If it is determined that the value of the N register is not 1023, 1 is added to the value of the N register, this value is incremented as the value of the N register, the value of the N register is updated (step ST450), and step ST442 Return to and repeat the subsequent steps. If it is determined that the value of the N register is 1023, the value of the N register is cleared (step ST451), and the IDFT_OK signal is output to the IDFT arithmetic processing unit 207. Then, it returns to step ST401 and repeats the subsequent processes.

  In step ST452, when the IDFT_OK signal is output from the IDFT calculation lookup table 204, the IDFT calculation processing unit 207 causes the IDFT lookup table for one frame of data fft_result stored in the FFT calculation result storage unit 205. Referring to 206, the IDFT operation is started, and the corrected PCM data is 1023 samples when the I_INT0 signal is input, 11025 samples when the I_INT1 signal is input, and 1024 samples when neither signal is input. Is output to the data storage unit 184 shown in FIG. Thereafter, the sampling data stored in the data storage unit 184 is output from the PCM data correction unit 9 as the audio correction data adata ′ as described above. The subsequent operation is the same as that of the digital broadcast receiver described in the first embodiment.

  As described above, according to the second embodiment, the PCM data correction unit 9 obtains the correction phase data θ based on the FFT calculation unit 182 that performs the FFT calculation of the PCM data and the frequency error data δf, and performs phase correction / Phase correction control unit 185 that controls the phase correction operation of the IDFT calculation unit 183, the number of samples to be corrected based on the correction phase data θ, and phase correction / Since it includes the IDFT calculation unit 183, the sampling data (PCM data) on the transmission system side can be corrected to sampling data as if it were sampled with the sampling clock on the receiver side, and an overflow of the audio buffer or Underflow is prevented, and audio data is not There is an effect that it is possible to prevent the occurrence.

It is a block diagram which shows the structure of the digital broadcast receiver by Embodiment 1 of this invention. 3 is a block diagram showing a configuration of a transport decoder of the digital broadcast receiver according to Embodiment 1. FIG. 3 is a block diagram illustrating a configuration of a PID filter unit of the digital broadcast receiver according to Embodiment 1. FIG. It is explanatory drawing which shows the structure of TS header and PES header. It is explanatory drawing which shows the structure of PCR. 4 is a timing chart of PCR output from the transport decoder of the digital broadcast receiver according to the first embodiment. 3 is a block diagram illustrating a configuration of a PCR comparison unit of the digital broadcast receiver according to Embodiment 1. FIG. 3 is a timing chart illustrating an operation of a PCR comparison unit of the digital broadcast receiver according to the first embodiment. 6 is an explanatory diagram showing bit assignment of data stored in a register of the digital broadcast receiver according to Embodiment 1. FIG. 3 is a block diagram illustrating a configuration of a counter of the digital broadcast receiver according to Embodiment 1. FIG. 3 is a block diagram illustrating a configuration of a counter error detection unit of the digital broadcast receiver according to Embodiment 1. FIG. 3 is a block diagram illustrating a configuration of a video / audio output timing correction unit of the digital broadcast receiver according to Embodiment 1. FIG. 4 is a timing chart showing the operation of the video / audio output timing correction unit of the digital broadcast receiver according to the first embodiment. 4 is a timing chart showing the operation of the video / audio output timing correction unit of the digital broadcast receiver according to the first embodiment. 3 is a block diagram illustrating a configuration of a PCM data correction unit of the digital broadcast receiver according to Embodiment 1. FIG. 6 is an explanatory diagram showing PCM data processed by an upsampling unit of the digital broadcast receiver according to Embodiment 1. FIG. 6 is an explanatory diagram showing PCM data processed by an upsampling unit of the digital broadcast receiver according to Embodiment 1. FIG. 6 is an explanatory diagram showing PCM data processed by a low-pass filter of the digital broadcast receiver according to Embodiment 1. FIG. 6 is an explanatory diagram showing PCM data processed by a low-pass filter of the digital broadcast receiver according to Embodiment 1. FIG. 6 is a flowchart illustrating an operation of an interpolation data temporary buffer read control unit of the digital broadcast receiver according to the first embodiment. 6 is a flowchart illustrating an operation of an interpolation data temporary buffer read control unit of the digital broadcast receiver according to the first embodiment. It is a block diagram which shows the structure of the PCM data correction | amendment part of the digital broadcast receiver by Embodiment 2 of this invention. 6 is a flowchart illustrating an operation of a phase correction control unit of the digital broadcast receiver according to the second embodiment. 6 is a flowchart illustrating an operation of a phase correction control unit of the digital broadcast receiver according to the second embodiment. 6 is a block diagram illustrating a configuration of a phase correction / IDFT calculation unit of a digital broadcast receiver according to Embodiment 2. FIG. 10 is an explanatory diagram showing a corrected phase sine / cosine value lookup table created by a corrected phase sine / cosine value lookup table calculation unit of the digital broadcast receiver according to Embodiment 2. FIG. 10 is a flowchart illustrating an operation of a correction phase sine / cosine value lookup table calculation unit of the digital broadcast receiver according to the second embodiment. 10 is a flowchart illustrating an operation of a correction phase sine / cosine value lookup table calculation unit of the digital broadcast receiver according to the second embodiment. 6 is a flowchart illustrating an operation of an IDFT calculation lookup table calculation unit of the digital broadcast receiver according to the second embodiment. 6 is a flowchart illustrating an operation of an IDFT calculation lookup table calculation unit of the digital broadcast receiver according to the second embodiment. 6 is a flowchart illustrating an operation of an IDFT calculation lookup table calculation unit of the digital broadcast receiver according to the second embodiment.

Explanation of symbols

  1 tuner, 2 OFDM demodulator, 3 transport decoder, 4 oscillator, 5 PCR comparator (PCR comparator), 6 video decoder, 7 audio decoder, 8 output data controller (video buffer), 9 PCM data corrector ( PCM data correction means), 10 video / audio output timing correction section (output timing correction means), 11 output data control section (audio buffer), 12, 13 D / A converter, 14 AV decoder, 15 antenna, 21 PID filter section 22 PSI analysis unit, 23 content data buffer, 31 TS header analysis / decoding unit, 32-34 PES packet extraction unit, 71 Local_CNT counter, 72 Local_REG_A register (count value register), 73 Local_REG_B register (count value register), 74 PCR_REG_A register (PCR value register), 75 PCR_REG_B register (PCR value register), 76 counter error detector (error detector), 77 shift register, 78 averaging processor, 79 δf calculator (frequency error data calculator) , 80 shift register, 81 averaging processing unit, 91 300 counter, 92 Local_base counter, 93 flip-flop, 101-106 subtractor, 121 V_PTS_REG_A register (video data PTS value register), 122 V_PTS_REG_B register (video data PTS value register) , 123 subtractor, 124 multiplier, 125 V_δPTS_ALL register, 126 adder, 127 PCM_correct_time register, 128 adder, 129 comparator, 130 to 133 selector, 134 A_PTS_REG_A register (audio data PTS value register) 135 A_PTS_REG_B register (audio data PTS value register), 136 subtractor, 137 multiplier, 138 adder, 139 comparator, 140 to 142 flip-flop, 151 upsampling unit (upsampling means), 152 low-pass filter, 153 interpolation data Temporary buffer (data buffer), 154 Interpolation data temporary buffer read control section (data buffer read control means), 155 data storage memory, 181 data storage section, 182 FFT operation section (FFT operation means), 183 Phase correction / IDFT operation section (Phase correction calculation means), 184 data storage section, 185 phase correction control section (phase correction control means), 201 corrected phase sine / cosine value lookup table calculation section, 202 corrected phase sine / cosine value level Click-up table, 203 sender IDFT lookup table, 204 IDFT computation lookup table calculating unit, 205 FFT computation result storage unit, 206 IDFT lookup table, 207 IDFT processing unit.

Claims (7)

A transport decoder that separates PCR and PES from the received TS packet; an AV decoder that obtains PCR and PES from the transport decoder, converts the PES using the PCR, and outputs a video signal and an audio signal; In a digital broadcast receiver equipped with
The AV decoder comprises a PCR comparison means for comparing the sequentially input PCR and a clock signal generated by the receiver to obtain frequency error data indicating an error of the clock signal by calculation;
PTSs for synchronizing the video data decoded from the PES by the video decoder and the audio data decoded from the PES by the audio decoder are respectively obtained from the video decoder and the audio decoder, and these PTSs are obtained based on the frequency error data. And an output timing correction means for controlling the operation timing of the video buffer that outputs the video data by generating an enable signal based on the corrected PTS and the audio buffer that outputs the audio data. Digital broadcast receiver. A transport decoder that separates PCR and PES from the received TS packet; an AV decoder that obtains PCR and PES from the transport decoder, converts the PES using the PCR, and outputs a video signal and an audio signal; In a digital broadcast receiver equipped with
The AV decoder
PCR comparison means for calculating frequency error data indicating an error of the clock signal by comparing the sequentially input PCR and the clock signal generated by the receiver;
PTSs for synchronizing the video data decoded from the PES by the video decoder and the audio data decoded from the PES by the audio decoder are respectively obtained from the video decoder and the audio decoder, and these PTSs are obtained based on the frequency error data. Output timing correction means for controlling the operation timing of the video buffer that outputs the video data by generating an enable signal based on the corrected PTS and the audio buffer that outputs the audio data;
An audio data correction means for correcting the number of samplings of audio data output from the audio decoder based on the frequency error data.   The PCR comparison means includes a counter for counting clock signals generated by the receiver, a plurality of PCR value registers for sequentially storing PCR values sequentially input, and a plurality of counts for sequentially storing the count values of the counters. A value register, error detection means for obtaining a difference value between the PCR values stored in the plurality of PCR value registers and obtaining a difference value between the count values stored in the plurality of count value registers, and the error 3. The frequency error data calculating means for calculating frequency error data using the difference value of the PCR value and the difference value of the count value obtained by the detecting means. Digital broadcast receiver. The output timing correction means includes a plurality of video data PTS value registers for sequentially storing PTSs relating to video data sequentially input from the video decoder,
Video data PTS for obtaining a difference value of each value stored in the plurality of video data PTS value registers and correcting the PTS related to the video data using the difference value and the frequency error data output from the PCR comparison means Correction means;
A plurality of audio data PTS value registers for sequentially storing PTS relating to audio data sequentially input from an audio decoder;
Audio data PTS correction means for calculating a difference value between the values stored in the plurality of audio data PTS value registers and correcting the PTS related to the audio data using the difference value and the frequency error data. The digital broadcast receiver according to claim 1. The output timing correction means includes a plurality of video data PTS value registers for sequentially storing PTSs relating to video data sequentially input from the video decoder,
The difference value of each value stored in the plurality of video data PTS value registers is obtained, and the difference value, the frequency error data output from the PCR comparison means, and the data indicating the audio data processing time by the audio correction means are obtained. Video data PTS correction means for correcting the PTS for the video data using,
A plurality of audio data PTS value registers for sequentially storing PTS relating to audio data sequentially input from an audio decoder;
Audio data PTS correction means for calculating a difference value of each value stored in the plurality of audio data PTS value registers and correcting the PTS related to the audio data by an operation using the difference value and the frequency error data; The digital broadcast receiver according to claim 2, further comprising:   The audio data correction means includes an upsampling means for upsampling PCM data output as audio data from the audio decoder, a data buffer for storing the upsampled PCM data, and frequency error data output from the PCR comparison means. A data buffer read control means for obtaining a value indicating the phase of the PCM data from the data buffer so that the PCM data is thinned out or interpolated based on the value indicating the phase. The digital broadcast receiver according to claim 2, wherein:   The audio data correction means includes an FFT calculation means for performing an FFT calculation on PCM data output as audio data from an audio decoder, and a phase correction for obtaining a correction phase by applying frequency error data output from a PCR comparison means to a periodic function. Control means; phase correction calculation means for determining a sampling number of the calculation result output from the FFT calculation means based on the correction phase, and performing IDFT calculation on the calculation result output from the FFT calculation means of the sampling number; The digital broadcast receiver according to claim 2, further comprising:

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