JP2005311243A - Semiconductor device, and rear-surface analyzing system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a rear-surface analyzing system and method wherein positioning of observing positions for performing a fault analysis from the rear-surface of a substrate can be performed easily and accurately. <P>SOLUTION: The rear-surface analyzing system has an infrared-ray transmitting substrate 10. With respect to the substrate 10, there is provided in the observing field of the rear-surface analyzing system three or more semiconductor elements or the portions of semiconductor elements separated from each other which function as position aligning portions 12a-12d where the mutual intervals among them become not larger than the half range of the minimum observing field of the rear-surface analyzing system. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device inspection, and more particularly to a semiconductor device, a back surface analysis system, and a back surface analysis method capable of accurately aligning the inspection of a semiconductor device.

  Semiconductor devices are being highly integrated, such as multilayered and flip-chip mounted. As the integration of semiconductor devices increases, it is difficult to analyze the signal wirings in the lower layer where failure analysis of the semiconductor device is desired from the surface of the semiconductor device. Therefore, “back surface analysis technology” for performing failure analysis from the back surface of a semiconductor device using infrared light transmitted through a silicon (Si) substrate, which is the back surface of the semiconductor device, has become widespread (for example, see Patent Document 1). .)

  However, the image that can be observed through the Si by the back surface analysis technique is an image that is mainly reflected by a gate electrode or a contact made of polysilicon or the like located closest to the Si substrate. Wiring layers other than the lowest layer that can be observed are limited to gaps without gate electrodes or contacts. Therefore, with the backside analysis technology, only the image of the gate electrode and the contact can actually be observed in reality. Since the gate electrode and the contact have a poor feature, it is very difficult to specify the observation location.

  Even if there is a feature in the shape of the gate electrode and contact, the optical resolution when observing from the back via Si is too large compared to the wiring currently used, so it can be observed with sufficient resolution. Can not. Therefore, it is very difficult to specify the observation place.

In addition, semiconductor devices such as gate arrays may all have the same shape for the gate electrode, and unless a pattern such as a characteristic element other than the gate array is visible nearby, the position from the observation image It is almost impossible to specify.
JP 7-35697 A

  It is an object of the present invention to provide a semiconductor device, a back surface analysis system, and a back surface analysis method capable of easily and accurately aligning an observation position when performing failure analysis from the back surface.

  The first feature of the present invention is that (a) a substrate having infrared transparency and (b) a set of semiconductor elements functioning as an alignment portion, or a part of the semiconductor elements are formed on the substrate, and the distance between them is the back surface. The gist of the invention is that the semiconductor device is arranged at least three in the observation field of view of the back surface analysis system so as to be ½ or less of the range of the minimum observation field of view of the analysis system.

  The second feature of the present invention is that (a) a set of semiconductor elements functioning as an alignment unit or a part of the semiconductor elements is a substrate, and the distance between them is 1/2 or less of the range of the minimum observation visual field of the detector. An observation unit for obtaining observation image data including an optical image of the alignment unit of the semiconductor device arranged at least three in the observation field of view of the detector, and (b) alignment of the observation image data Coordinate value collating means for collating the coordinate value of the portion with the coordinate value of the alignment portion of the CAD layout data, and (c) the coordinate value of the alignment portion of the observation image data corresponding to the coordinate value corresponding to the CAD layout data (D) position correction data calculating means for correcting the position of the semiconductor device by calculating position correction data for correcting the position shift of the semiconductor device. And summarized in that a backside analysis system comprising a.

  The third feature of the present invention is that (a) a set of semiconductor elements functioning as an alignment section or a part of the semiconductor elements is a substrate, and the distance between them is 1/2 or less of the range of the minimum observation visual field of the detector. A step of acquiring observation image data including an optical image of an alignment unit of a semiconductor device arranged at least three in the observation field of view of the detector, and (b) an alignment unit of the observation image data And (c) the coordinate value of the alignment part of the observation image data is misaligned with the corresponding coordinate value of the CAD layout data. And (d) calculating the position correction data for correcting the positional deviation of the semiconductor device and correcting the position of the semiconductor device. The gist.

  According to the present invention, it is possible to provide a semiconductor device, a back surface analysis system, and a back surface analysis method capable of easily and accurately aligning observation positions when performing failure analysis from the back surface.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in light of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

(First embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes a substrate 10 having infrared transparency and a set of semiconductor elements functioning as an alignment portion, or a part of the semiconductor elements. Three or more substrates are arranged in the observation field of the back surface analysis system so as to be spaced apart from each other by half or less of the range of the minimum observation field of view F of the back surface analysis system. As an alignment unit of the semiconductor device according to the first embodiment,
A set of semiconductor elements constitutes the inverters 12a to 12d, and the light emission by the operation of the inverters 12a to 12d is used for alignment.

  The inverters 12a to 12d are arranged at unused locations where functional units (cells) of basic units constituting circuits such as inverters and NAND elements necessary for the operation of the semiconductor device are not arranged. As the substrate 10, an Si substrate that transmits infrared rays or the like can be used. The range of the minimum observation visual field F of the back surface analysis system is a range on the substrate 10 that can be observed when the magnification of the detector of the back surface analysis system is maximized, and the specific size differs depending on the system. For example, in the case of a system for observing with a 100 × objective lens, the range is a rectangular shape with one side of about 150 nm. The inverters 12a to 12d are arranged in half or less of the range of the minimum observation visual field F of the back surface analysis system, so that three or more inverters exist in the observation visual field.

  The plurality of inverters 12 a to 12 d are connected in an even number in a chain in series to form an inverter chain 13. A NAND element 20 is disposed at the end of the inverter chain 13. The input side of the NAND element 20 is connected to the external terminal 30 and the final stage inverter 12 d of the inverter chain 13. The output side of the NAND element 20 is connected to the first stage inverter 12 a of the inverter chain 13. Since an even number of inverters 12a to 12d are arranged in the inverter chain 13, when a low (L) level is input to the external terminal 30 during normal operation, the output of the NAND element 20 is fixed at a high (H) level. It becomes. The input / output levels of the inverters 12a to 12d are also fixed values.

  The semiconductor device according to the first embodiment is observed by the back surface analysis system 4 shown in FIG. The back surface analysis system 4 images extremely weak light caused by hot carriers generated when an electric field is concentrated on an abnormal portion of the semiconductor device, and extremely weak light in the infrared region due to recombination such as latch-up. Further, the back surface analysis system 4 images extremely weak light obtained by reflecting the irradiated infrared light by a gate electrode or contact such as polysilicon located closest to the Si substrate. The back surface analysis system 4 includes an observation unit 5 and a control unit 6. An emission microscope or the like is used for the back surface analysis system 4.

  The observation unit 5 includes a sample stage 50, a drive unit 52, an irradiation unit 54, a detection unit 56, and a dark box 58. The sample stage 50, the drive unit 52, the irradiation unit 54, and the detection unit 56 are arranged in a dark box 58 that blocks the incidence of light from the outside. However, the drive unit 52 may be disposed outside the dark box 58.

  The sample stage 50 is a stage on which the semiconductor device shown in FIG. The drive unit 52 is a pulse motor or the like that moves the sample stage 50 to a desired position. The irradiation unit 54 is an illumination optical system having a light source that irradiates a semiconductor device placed on the sample stage 50 with infrared light. The detection unit 56 is an imaging device such as a CCD camera that performs analog / digital (A / D) conversion of an observation image of the semiconductor device. The detection unit 56 outputs the observation image data that has been digitally converted to the control unit 6.

  The control unit 6 includes a central processing unit (CPU) 60, a main storage device 70, an observation image storage device 71, a CAD layout storage device 72, an output device 80, and an input device 82. The CPU 60 includes a data storage unit 601, a coordinate value matching unit 602, a positional deviation presence / absence determination unit 603, and a position correction data calculation unit 604. Further, the CPU 60 includes storage device management means (not shown).

  The data storage unit 601 acquires observation image data from the detection unit 56 and stores it in the observation image storage device 71. The data storage unit 601 stores the CAD layout data used for designing the semiconductor device in the CAD layout storage device 72.

The coordinate value matching unit 602 acquires observation image data from the observation image storage device 71, and
CAD layout data is acquired from the CAD layout storage device 72. Further, the coordinate value matching unit 602 displays observation image data and CAD layout data on the output device 80. For the image displayed on the output device 80, the coordinate value collating means 602 converts three or more coordinate values of the observation image data alignment units 12a to 12d and the coordinate values of the CAD layout data alignment units 12a to 12d, respectively. Matched.

  As a result of collation of the image displayed on the output device 80, the positional deviation presence / absence determination means 603 is positioned at coordinate values corresponding to three or more coordinate values of the alignment units 12a to 12d of the observation image data and corresponding to CAD layout data. Determine if there is a gap.

  The position correction data calculation means 604 calculates position correction data for correcting the position shift of the semiconductor device when there is a position shift by collating coordinate values. Then, the position correction data calculation unit 604 outputs the calculated position correction data to the drive unit 52 and corrects the position of the sample stage 50.

  The back surface analysis system 4 includes an input / output control device (interface) (not shown) that connects the output device 80, the input device 82, and the like to the CPU 60. The main storage device 70 incorporates a ROM and a RAM. The RAM sequentially stores information used during program execution in the CPU 60, and functions as an information memory used as a work area. The observation image storage device 71 and the CAD layout storage device 72 are recording units using a known magnetic tape, magnetic drum, magnetic disk, optical disk, magneto-optical disk, or semiconductor memory such as ROM or RAM. The observation image storage device 71 stores observation image data of the semiconductor device to be inspected. The CAD layout storage device 72 stores CAD layout data used for designing the semiconductor device. As the output device 80, a liquid crystal display (LCD), a CRT display, or the like can be used. The input device 82 includes a keyboard, a mouse, a voice device, a light pen, or the like.

  The back surface analysis method using the semiconductor device according to the first embodiment will be described below with reference to FIGS.

  (A) First, in step S101 of FIG. 3, the semiconductor device shown in FIG. 1 is placed on the sample stage 50 shown in FIG. 2 so that the substrate 10, the irradiation unit 54, and the detection unit 56 face each other. At this time, the L level is input to the external terminal 30 of the semiconductor device shown in FIG.

  (B) Next, in step S102, the H level is input to the external terminal 30. When the H level is input to the external terminal 30, the NAND element 20 operates in the same manner as the inverter. That is, a loop connected to the inverter chain 13 having an even number of inverters 12a to 12d is formed and operates as a ring oscillator. When the inverter chain 13 operates as a ring oscillator, the inverters 12a to 12d repeatedly turn on and off at a fast frequency and continuously emit light.

  (C) Next, in step S103, the continuously emitting light is received by the detection unit 56 shown in FIG. 2 and A / D converted. The observation image data converted from the digitally converted observation image is stored in the observation image storage device 71 by the data storage unit 601 shown in FIG. Further, the CAD layout data used for designing the semiconductor device is stored in the CAD layout storage device 72 by the data storage means 601.

  (D) Next, in step S <b> 104, the observation image data is read from the observation image storage device 71 by the coordinate value matching unit 602. Also, the CAD layout data is read from the CAD layout storage device 72 by the coordinate value matching means 602. The read observation image data and CAD layout data are output to the output device 8 as shown in FIG. In FIG. 4, the dotted line of the cell frame of the observation image is shown for reference, but only light emission is displayed in the normal observation image. And the light emission position of the alignment parts 12a-12d of the observation image data displayed on the output device 8 and the coordinate value of the alignment parts 12a-12d of CAD layout data are collated, respectively.

  (E) Next, in step S105, the image collated by the output device 80 by the misalignment presence / absence determination unit 603 is the coordinate value corresponding to the coordinate value of the alignment unit 12a to 12d of the observation image data in the CAD layout data. It is determined whether or not there is a position shift. If there is no displacement, the process proceeds to step S107 and failure analysis is performed. On the other hand, if there is a positional shift, the process proceeds to step S106.

  (F) Next, in step S106, the position correction data calculation means 604 calculates position correction data for correcting the positional deviation of the semiconductor device. Then, the position correction data calculation unit 604 outputs the calculated position correction data to the drive unit 52 and corrects the position of the sample stage 50.

  (G) After confirming the desired inspection position, in step S107, the semiconductor device is irradiated with infrared light from the irradiation unit 54, and failure analysis is performed based on the infrared light reflected by the semiconductor device.

  As described above, according to the semiconductor device according to the first embodiment, since there are three or more alignment portions in the observation visual field of the back surface analysis system 4, observation is performed by comparing three or more points. It is possible to specify the position of the location. Therefore, the semiconductor device according to the first embodiment can easily and accurately align the observation position when performing failure analysis from the back surface. In addition, since the alignment unit of the semiconductor device according to the first embodiment uses the inverters 12a to 12d, alignment is possible without inputting a clock from the outside.

(Second Embodiment)
As shown in FIG. 5, the semiconductor device according to the second embodiment of the present invention uses flip-flops 14a to 14d as alignment units instead of the inverters 12a to 12d of the semiconductor device shown in FIG. Different. As the flip-flops 14 a to 14 d are used, the semiconductor device is provided with a shift clock input terminal 32. The other parts are substantially the same as those of the semiconductor device shown in FIG.

  When the flip-flops 14a to 14d receive a clock having a high frequency from the shift clock input terminal 32, the transistors in the clock input portions of the flip-flops 14a to 14d emit light. When the flip-flops 14a to 14d are caused to emit light, it is not necessary to input data. The number of flip-flops 14a to 14d is not limited to an even number, and may be an odd number.

  Description of the back surface analysis method using the semiconductor device according to the second embodiment is omitted because only the method of causing the alignment unit to emit light is different.

  As described above, according to the semiconductor device according to the second embodiment, since there are three or more alignment portions in the observation visual field of the back surface analysis system 4, observation is performed by comparing three or more points. It is possible to specify the position of the location. Therefore, the semiconductor device according to the second embodiment can easily and accurately align the observation position when performing failure analysis from the back surface. Further, since the alignment unit of the semiconductor device according to the second embodiment uses the flip-flops 14a to 14d, the alignment can be performed without inputting data. Since flip-flops are usually arranged in the design of a semiconductor device, there is no need to provide them for alignment if the arranged flip-flops are used.

(Third embodiment)
As shown in FIG. 6, the semiconductor device according to the third embodiment of the present invention is an unused gate electrode which is a part of a semiconductor element instead of the inverters 12a to 12d of the semiconductor device shown in FIG. The contact pattern is a “cross” mark, and this is different in that the alignment portions 16a to 16d are used. The other parts are substantially the same as those of the semiconductor device shown in FIG.

  The alignment units 16a to 16d are larger than the optical resolution of the back surface analysis system 4 shown in FIG. The alignment units 16 a to 16 d can be detected by infrared rays such as a lowermost contact and a gate electrode that are in direct contact with the substrate 10 so as to be easily detected by the back surface analysis system 4.

  Hereinafter, a back surface analysis method using the semiconductor device according to the third embodiment will be described with reference to FIGS. 2, 6, and 7.

  (A) First, in step S301 of FIG. 7, the semiconductor device shown in FIG. 6 is placed on the sample stage 50 shown in FIG. 2 so that the substrate 10, the irradiation unit 54, and the detection unit 56 face each other.

  (B) Next, in step S302, the semiconductor device is irradiated with infrared light from the irradiation unit 54. Then, an observation image including an optical image (“cross” mark) reflected by the alignment units 16a to 16d is received by the detection unit 56 and A / D converted. The observation image data is stored in the observation image storage device 71 by the data storage means 601 shown in FIG. Further, the CAD layout data used for designing the semiconductor device is stored in the CAD layout storage device 72 by the data storage means 601.

  (C) Next, in step S303, the observation value storage unit 71 reads the observation image data by the coordinate value matching unit 602. Also, the CAD layout data is read from the CAD layout storage device 72 by the coordinate value matching means 602. The read observation image data and CAD layout data are output to the output device 8 by the coordinate value matching unit 602. Then, the coordinate values of the “cross” mark display positions of the alignment units 16a to 16d of the observation image data displayed on the output device 8 are collated with the coordinate values of the alignment units 16a to 16d of the CAD layout data.

  (D) Next, in step S304, the image collated by the output device 80 by the misregistration presence / absence determining unit 603 is the coordinate value corresponding to the coordinate value of the alignment unit 16a to 16d of the observation image data by the CAD layout data. It is determined whether or not there is a position shift. If there is no position shift, the process proceeds to step S306 to perform failure analysis. On the other hand, if there is a positional shift, the process proceeds to step S305.

  (E) Next, in step S305, the position correction data calculating unit 604 calculates position correction data for correcting the positional deviation of the semiconductor device. Then, the position correction data calculation unit 604 outputs the calculated position correction data to the drive unit 52 and corrects the position of the sample stage 50.

  (F) After confirming the desired inspection position, in step S306, the semiconductor device is irradiated with infrared light from the irradiation unit 54, and failure analysis is performed based on the infrared light reflected by the semiconductor device.

  As described above, according to the semiconductor device according to the third embodiment, three or more alignment portions are present in the observation field of view of the back surface analysis system 4, so that the observation is performed by comparing three or more points. It is possible to specify the position of the location. Therefore, the semiconductor device according to the third embodiment can easily and accurately align the observation position when analyzing the semiconductor device from the back surface. Further, since the alignment portions 16a to 16d of the semiconductor device according to the third embodiment have a “cross” shape, the center of the alignment portion is easy to understand even if the resolution is somewhat poor, and thus alignment is easy. .

(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques should be apparent to those skilled in the art.

  For example, in the first embodiment, the output device 80 is described as displaying the observation image and the CAD layout image side by side on one monitor as shown in FIG. 4, but two monitors are prepared separately. May be displayed.

  In the third embodiment, the alignment portions 16a to 16d are described as contacts, gate electrodes, and the like that are in direct contact with the substrate 10, but an obstacle does not enter between the alignment portions 16a to 16d and the substrate 10. In this case, the member need not be in direct contact with the substrate 10.

  Furthermore, in the third embodiment, the alignment units 16a to 16d are “cross” marks, but the shapes such as “#” and “∞” are easy to understand the centers of the alignment units 16a to 16d even if the resolution is poor. It doesn't matter.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is a schematic block diagram of the back surface analysis system which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the back surface analysis method which concerns on the 1st Embodiment of this invention. It is a schematic diagram displayed on the output device of the back surface analysis system which concerns on the 1st Embodiment of this invention. FIG. 6 is a plan view of a semiconductor device according to a second embodiment of the present invention. It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. It is a flowchart which shows the back surface analysis method which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 4 ... Back surface analysis system 5 ... Observation part 6 ... Control part 8 ... Output device 10 ... Board | substrate 12a-12d ... Inverter 13 ... Inverter chain 14a-14d ... Flip-flop 16a-16d ... Positioning part 20 ... NAND element 30 ... External terminal 32 ... Shift clock input terminal 50 ... Sample stage 52 ... Drive unit 54 ... Irradiation unit 56 ... Detection unit 58 ... Dark box 60 ... CPU
DESCRIPTION OF SYMBOLS 70 ... Main memory device 71 ... Observation image memory device 72 ... CAD layout memory device 80 ... Output device 82 ... Input device 601 ... Observation image data storage means 602 ... Coordinate value collation means 603 ... Presence judgment means 604 ... Position correction data calculation means

Claims (5)

A substrate having infrared transparency;
A set of semiconductor elements that function as an alignment unit, or a part of the semiconductor elements, are separated from the substrate such that the distance between them is less than or equal to half the range of the minimum observation field of view of the back surface analysis system. A semiconductor device characterized in that three or more are arranged in the observation field of view of the analysis system.   The semiconductor device according to claim 1, wherein the set of semiconductor elements constitutes a logic element, and light emission by operation of the logic element is used for alignment.   The semiconductor device according to claim 1, wherein a part of the semiconductor element is a gate electrode of the semiconductor element or a contact to the semiconductor element. A set of semiconductor elements functioning as an alignment unit or a part of the semiconductor elements are separated from the substrate so that the distance between them is 1/2 or less of the range of the minimum observation visual field of the detector. An observation unit that acquires observation image data including an optical image of the alignment unit of the semiconductor device that is arranged three or more in the observation visual field;
Coordinate value collating means for collating the coordinate value of the alignment portion of the observation image data with the coordinate value of the alignment portion of the CAD layout data;
Misalignment presence / absence judging means for judging whether or not the coordinate value of the alignment portion of the observation image data is misaligned with respect to the corresponding coordinate value in the CAD layout data;
A backside analysis system comprising: position correction data calculating means for calculating position correction data for correcting a position shift of the semiconductor device and correcting the position of the semiconductor device. A set of semiconductor elements functioning as an alignment unit or a part of the semiconductor elements are separated from the substrate so that the distance between them is 1/2 or less of the range of the minimum observation visual field of the detector. Obtaining observation image data including an optical image of the alignment unit of the semiconductor device arranged at least three in the observation visual field;
Collating the coordinate value of the alignment portion of the observation image data with the coordinate value of the alignment portion of the CAD layout data;
Determining whether the coordinate value of the alignment portion of the observation image data is misaligned with the corresponding coordinate value in the CAD layout data;
Calculating a position correction data for correcting a position shift of the semiconductor device and correcting the position of the semiconductor device.

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