JP2005311000A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving the characteristics of a p-type MOS transistor without affecting the characteristics of other elements formed in an SOI layer, and to provide the method of manufacturing the same. <P>SOLUTION: A groove 12 which does not reach a BOX layer 3 is formed by dry etching in the periphery of a portion for the p-type well 4a and the n-type well 4b of an SOI layer 4. Then, a groove 13, the width of which is narrower than that of the groove 12, is formed such that the groove reaches the BOX layer 3 in a region in the n-type well 4b side of the bottom of the groove 12 parallel with the direction of the extension of an electrode 8. Then, a bird's beak (an oxide layer) 14 is formed between the BOX layer 3 and the SOI layer 4 in the vicinity of the groove 13 by oxidizing the insides of the groove 12 and the groove 13. Then, an STI region 19 is formed by embedding an insulator in the groove 12 and the groove 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a substrate provided with an SOI (Silicon On Insulator) layer and a method for manufacturing the same, and more particularly to a complementary metal oxide semiconductor (CMOS) or the like on the same substrate. The present invention relates to a semiconductor device in which a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an n-channel MOSFET are formed, and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, a semiconductor device in which a BOX (Buried Oxide: buried oxide) layer is formed on a silicon substrate, an SOI layer is formed on the BOX layer, and a semiconductor integrated circuit including an element such as a MOSFET is formed on the SOI layer. Has been developed.

In such a semiconductor device, an STI (Shallow Trench Isolation) region is formed in the SOI layer in order to electrically isolate elements such as a p-channel MOSFET and an n-channel MOSFET from each other. . 13A to 13C and FIGS. 14A to 14C are cross-sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps. First, as shown in FIG. 13A, an SOI wafer 101 in which a BOX layer 103 is formed on a silicon substrate 102 and an SOI layer 104 is formed on the BOX layer 103 is prepared. Then, as shown in FIG. 13B, the SOI wafer 101 is thermally oxidized to form a silicon oxide film (SiO ₂ film) 105 on the surface of the SOI layer 104. Thereafter, as shown in FIG. 13C, a silicon nitride film (Si ₃ N ₄ film) 106 is formed on the silicon oxide film 105.

  Next, as shown in FIG. 14A, a photoresist (not shown) is formed on the silicon nitride film 106 by photolithography. The photoresist is provided with an opening in a region where an STI region is to be formed in a later step. Then, using this photoresist as a mask, the silicon nitride film 106 is etched and removed selectively by dry etching, and then the photoresist is peeled off. Next, using the silicon nitride film 106 as a mask, the silicon oxide film 105 and the SOI layer 104 are selectively removed by etching to form a groove 107. At this time, the groove 107 is formed so as to reach the BOX layer 103.

  Next, as shown in FIG. 14B, the SOI wafer 101 is subjected to a thermal oxidation process, and a silicon oxide film 109 is formed in a region where the BOX layer 103 is exposed on the inner surface of the groove 107. This process is called rounding oxidation. At this time, oxygen flows from the bottom of the groove 107 to the interface between the BOX layer 103 and the SOI layer 104, and an oxide layer 113 is formed between the BOX layer 103 and the SOI layer 104 in the vicinity of the groove 107.

  Next, as shown in FIG. 14C, a silicon oxide film is formed on the entire surface by an HDP (High Density Plasma) oxide film or the like. Then, the silicon oxide film formed in a region other than the inside of the groove 107 is removed by CMP (Chemical Mechanical Polishing), and an STI region 112 made of a silicon oxide film is formed inside the groove 107. Then, an element such as a MOSFET is formed in a region partitioned by the STI region 112 in the SOI layer 104 to form a semiconductor device.

  FIG. 15 is a sectional view showing a conventional semiconductor device in which a p-channel MOSFET and an n-channel MOSFET are formed adjacent to each other. As shown in FIG. 15, the p-channel MOSFET 120 and the n-channel MOSFET 121 are provided with a gate electrode 114 on the SOI layer 104 partitioned by the STI region 112 via a gate insulating film 116, and further on both sides of the gate electrode 11. A side wall 115 is provided on the surface. Since both the p-channel MOSFET 120 and the n-channel MOSFET 121 have the oxide layer 113 formed between the BOX layer 103 and the SOI layer 104 in the vicinity of the STI region 112, compressive stress is generated in the SOI layer 104. .

  However, when compressive stress is applied to the channel region formed in the SOI layer 104, the carrier mobility in the n-channel MOSFET is lowered, and the transistor characteristics are lowered. Therefore, when the STI region is formed, the semiconductor integrated circuit prevents the oxide layer from being formed between the BOX layer and the SOI layer in the vicinity of the groove by forming the groove in two stages. Has been proposed (see, for example, Patent Document 1). FIG. 16 is a cross-sectional view showing a semiconductor integrated circuit described in Patent Document 1. In FIG. As shown in FIG. 16, the semiconductor integrated circuit described in Patent Document 1 forms a groove 107 a so as not to reach the BOX layer 103, and forms a groove 107 b that reaches the BOX layer 103 after rounding oxidation. The STI region 112 made of a silicon oxide film is formed inside the trench 107a and the trench 107b.

  On the other hand, if the direction of the stress applied to the channel region is optimized, the transistor characteristics can be improved. FIG. 17A is a plan view schematically showing a stress direction in which the characteristics of the n-channel MOSFET are improved, and FIG. 17B is a plan view schematically showing a stress direction in which the characteristics of the p-channel MOSFET are improved. is there. As shown in FIG. 17A, in the case of an n-channel MOSFET, the direction parallel to and perpendicular to the direction in which the gate electrode 131 formed on the channel region between the pair of adjacent diffusion layers 130a and 130b extends. When tensile stress is applied in any direction, the characteristics are improved. As shown in FIG. 17B, in the case of a p-channel MOSFET, a direction parallel to the direction in which the gate electrode 133 formed on the channel region between the pair of adjacent diffusion layers 132a and 132b extends. When tensile stress is applied to the film and compressive stress is applied in the vertical direction, the characteristics are improved (see Non-Patent Document 1).

  In view of this, there has been proposed a semiconductor device in which characteristics are improved by utilizing compressive stress and tensile stress applied to the channel region (see, for example, Patent Documents 2 and 3). In the method of manufacturing a semiconductor device described in Patent Document 2, an n-channel MOSFET gate electrode is formed of a silicon film, a metal film, or a laminated film that generates tensile stress in the channel region, and compressive stress is generated in the channel region. The gate electrode of the p-channel MOSFET is formed by the silicon film, the metal film, or the laminated film thereof. FIG. 18A is a cross-sectional view showing a p-channel MOSFET described in Patent Document 3, and FIG. 18B is a cross-sectional view showing an n-channel MOSFET. As shown in FIGS. 18A and 18B, in Patent Document 3, a diffusion layer 142 serving as a source / drain region is formed on a p well 141a and an n well 141b formed on a silicon substrate 141. The diffusion layer 142 between the elements is separated by the STI region 143, and the gate electrode 144 is formed on the channel region between the diffusion layers 142 on each well, and is formed on both side surfaces of the gate electrode 144. A sidewall 145 is formed. In the p-channel MOSFET, the length of the source / drain region in the channel direction is set to 1 μm or less and the gate electrode length is set to 0.2 μm or less so that compressive stress is applied in the channel direction. Further, in the n-channel MOSFET, a tensile stress is applied in the channel direction by inserting a silicon nitride film 146 between the surface of the source / drain region parallel to the gate electrode length direction and the STI region 143. .

JP 2003-332416 A JP 2002-93921 A JP 2003-179157 A C. H. Ge, 17 others, “Process-Strained Si (PSS) CMOS Technology Featuring 3D strain Engineering”, IEDM papers, 2003, p. 3.7.1-3.7.4

  However, the conventional techniques described above have the following problems. The semiconductor circuit described in Patent Document 1 can suppress the generation of an oxide layer and prevent deterioration of transistor characteristics, but has no effect of positively improving transistor characteristics. In addition, since it is difficult for the methods described in Patent Documents 2 and 3 to apply stress only to specific elements and directions, a p-channel MOSFET and an n-channel MOSFET are formed on the same substrate as in a CMOS. When it is applied to a semiconductor device, there is a problem that one characteristic is deteriorated. As described above, when a p-type MOS transistor and other elements are mixedly formed on the same substrate, if stress is applied to improve the characteristics of the p-type MOS transistor, the characteristics of the other elements deteriorate. There is a problem that.

  The present invention has been made in view of such problems, and a semiconductor device capable of improving the characteristics of a p-type MOS transistor without affecting the characteristics of other elements formed in the SOI layer. It aims at providing the manufacturing method.

  A semiconductor device according to a first invention of the present application includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a semiconductor layer formed on the insulating film, a p-type MOS transistor formed on the semiconductor layer, And a first element isolation film that electrically isolates the p-type MOS transistor, the source and drain of the p-type MOS transistor in the first element isolation film are positioned in the opposing channel direction The portion is formed between the first groove formed on the surface side of the semiconductor layer, and between the first groove and the insulating film, and has a width shorter than that of the first groove. A second groove formed at a position closer to the p-type MOS transistor than the center, and an isolation insulating film filling the first and second grooves, and the semiconductor layer and the insulating film In the middle Wherein the first oxide layer extending from the side surface of the second groove to the midway toward the center of the p-type MOS transistor in the channel direction is formed.

  In the present invention, since the second groove is formed in the portion where the source and drain of the p-type MOS transistor are located in the opposite channel direction, the p-type MOS transistor in the channel direction from the side surface of the p-type MOS transistor. An oxide layer is formed halfway toward the center. Thereby, no compressive stress is applied in the direction in which the gate electrode in which the transistor characteristics are degraded extends, that is, in the direction perpendicular to the channel direction, and in the direction in which the gate electrode in which characteristics are improved extends in the direction in which the gate electrode extends. Only compressive stress can be applied. As a result, the characteristics of the p-type MOS transistor can be improved without affecting other elements formed in the SOI layer.

  For example, the first oxide layer may have a shape in which the thickness is reduced as the distance from the side surface of the second groove increases and the tip is pointed. Further, the first groove may be further formed in a portion of the first element isolation film located in a direction orthogonal to the channel direction. At this time, the second groove can be formed at a position farther from the p-type MOS transistor than the center of the first groove formed in a portion located in a direction perpendicular to the channel direction. Alternatively, a third groove can be formed between the first groove formed in a portion located in a direction orthogonal to the channel direction and the insulating film, and in this case, the third groove is It is preferable that the oxide film is filled with the isolation insulating film, and the oxide layer does not extend from the side surface of the third groove. Thereby, the element isolation performance can be improved without degrading the characteristics of the p-type MOS transistor.

  Furthermore, an n-type MOS transistor formed in the semiconductor layer and a second element isolation film that electrically isolates the n-type MOS transistor may be included. In this case, the second element The separation film can be constituted by a fourth groove formed on the surface side of the semiconductor layer and an isolation insulating film filling the fourth groove. Thereby, since an oxide layer is not formed around the n-type MOS transistor, even when n-type MOS transistors and p-type MOS transistors are mixed, the characteristics of the n-type MOS transistor are not degraded. The characteristics of the p-type MOS transistor can be improved.

  Furthermore, the second element isolation film is formed between the fourth groove and the insulating film and has a width shorter than that of the fourth groove, and is smaller than the center of the fourth groove. A fifth groove may be formed at a position distant from the MOS transistor, and the fifth groove may be filled with the isolation insulating film. In this case, for example, between the semiconductor layer and the insulating film In part, a second oxide layer extending from the side surface of the fifth groove toward the center of the n-type MOS transistor is formed. Alternatively, a sixth groove may be formed between the fourth groove and the insulating film in the second element isolation film, and in this case, the sixth groove is formed by the isolation insulating film. Preferably, the oxide layer is buried and does not extend from the side surface of the sixth groove. Thereby, the element isolation performance can be improved without degrading the characteristics of the n-type MOS transistor.

  For example, the second oxide layer may have a shape in which the thickness decreases as the distance from the side surface of the fifth groove increases and the tip is pointed. The semiconductor substrate and the semiconductor layer are made of, for example, silicon.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming an insulating film on a semiconductor substrate; forming a semiconductor layer on the insulating film; and forming a p-type MOS transistor in the semiconductor layer. Forming a first groove on a surface side of a portion of the p-type MOS transistor that is located in a channel direction facing the source and drain of the p-type MOS transistor around the portion; and the first groove between the first groove and the insulating film. Forming a second groove having a width smaller than that of the first groove at a position closer to the p-type MOS transistor than the center of the first groove; and oxidizing the inside of the first and second grooves; And embedding an insulator in the first and second grooves.

  In the present invention, since the second groove is formed in the portion located in the channel direction of the p-type MOS transistor, an oxide layer is formed along the side surface of the element isolation region parallel to the direction in which the gate electrode extends. The For this reason, compressive stress is applied only in the direction perpendicular to the direction in which the gate electrode in which the characteristics of the p-type MOS transistor are extended, that is, in the channel direction. As a result, the characteristics of the p-type MOS transistor can be improved efficiently without affecting the characteristics of other elements.

  The first groove can be formed also in a portion located in a direction orthogonal to the channel direction around the portion where the p-type MOS transistor is formed. At this time, the second groove may be formed at a position farther from the p-type MOS transistor than the center of the first groove in a portion located in a direction orthogonal to the channel direction. Alternatively, after oxidizing the inside of the first trench, the portion between the first trench and the insulating film at a portion located in a direction orthogonal to the channel direction around the portion where the p-type MOS transistor is formed A third groove may be formed therebetween, and an insulator may be embedded in the third groove. Thereby, the element isolation performance can be improved without degrading the characteristics of the p-type MOS transistor.

  In addition, a fourth groove is formed on the surface side of at least a part of the semiconductor layer around the portion where the n-type MOS transistor is formed, and after oxidizing the inside of the fourth groove, an insulator is provided in the fourth groove. It can also be buried. As a result, the formation of an oxide layer around the n-type MOS transistor can be prevented, and the characteristics of the p-type MOS transistor can be improved without degrading the characteristics of the n-type MOS transistor. .

  At this time, a fifth groove having a width smaller than that of the fourth groove is located farther from the n-type MOS transistor than the center of the fourth groove between the fourth groove and the insulating film. After forming and oxidizing the inside of the fifth groove, an insulator may be embedded in the fifth groove. Alternatively, after oxidizing the inside of the first and fourth grooves, a sixth groove is formed between the fourth groove and the insulating film, and an insulator is buried in the sixth groove. Good. Thereby, the element isolation performance can be improved without degrading the characteristics of the n-type MOS transistor.

  Further, the first groove and the fourth groove are formed simultaneously, and the second groove and the fifth groove are formed simultaneously, and the inside of the second groove and the fifth groove is oxidized simultaneously. You can also Furthermore, the first groove and the fourth groove are formed at the same time, and the inside of the first groove and the fourth groove is oxidized simultaneously, and then the third groove and the sixth groove are simultaneously formed. It may be formed. Furthermore, in the step of oxidizing the inside of the second trench, the side of the second trench on the side where the p-type MOS transistor is formed is formed in a part between the semiconductor layer and the insulating film. An oxide layer extending halfway toward the center of the p-type MOS transistor can be formed.

  According to the present invention, the element isolation region located in the channel direction where the source and drain of the p-type MOS transistor are opposed to each other includes the first groove formed on the surface side of the semiconductor layer and the first groove and the insulating film. An insulating material is embedded in the second groove formed between the two, and the second groove is formed at a position closer to the p-type MOS transistor than the center of the first groove. Forming an oxide layer between the layer and the insulating film from the side surface of the second groove toward the center of the p-type MOS transistor in the channel direction, and compressing stress only in the channel direction of the p-type MOS transistor Therefore, the characteristics of the p-type MOS transistor can be improved without degrading the characteristics of other elements formed adjacent to each other.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, the semiconductor device according to the first embodiment of the present invention will be described. The semiconductor device of the present embodiment is a semiconductor device including a CMOS device formed by mixing a p-channel MOSFET and an n-channel MOSFET. FIG. 1A is a plan view showing the semiconductor device of this embodiment, and FIG. 1B is a cross-sectional view thereof. As shown in FIGS. 1A and 1B, in the semiconductor device 1 of this embodiment, a BOX layer 3 is formed on a silicon substrate 2, and p wells 4a and n are formed on the BOX layer 3. An SOI layer 4 to be the well 4b is formed. A p-type diffusion layer 5 and an n-type diffusion layer 6 are formed on the p-well 4a and the n-well 4b as source / drain regions, respectively. Further, a gate electrode 8 is formed on the channel regions formed between the p-type diffusion layers 5 and the n-type diffusion layer 6 via a gate insulating film 7, and sidewalls are formed on both sides of the gate electrode 8. 9 is formed. The p-channel MOSFET 10 composed of the n-well 4b, the p-type diffusion layer 5 and the gate electrode 8 and the n-channel MOSFET 11 composed of the p-well 4a, the n-type diffusion layer 6, the gate electrode 8 and the like are STI. It is partitioned by a region 19.

  In the semiconductor device 1 of the present embodiment, the STI region 19 is composed of a groove 12 that does not reach the BOX layer 3 and a groove 13 that is formed at the bottom of the groove 12 and reaches the BOX layer 3. Specifically, a groove 12 is formed around the p-channel MOSFET 10 and the n-channel MOSFET 11, and the groove 13 is parallel to the direction in which the gate electrode 8 extends at the bottom of the groove 12 and along the side on the p-channel MOSFET 10 side. Is formed. That is, the STI region 19 in the semiconductor device 1 of the present embodiment reaches the BOX layer 3 only in a portion parallel to the direction in which the gate electrode 8 extends and near the p-channel MOSFET 10, and the other portions reach the BOX layer 3. Not reached.

  Further, in the semiconductor device 1 of the present embodiment, the oxide has a shape between the BOX layer 3 and the SOI layer 4 in the vicinity of the groove 13 that becomes thinner as the distance from the side surface of the groove 13 increases and the tip is pointed. A layer (hereinafter referred to as a bird's beak) 14 is formed. During the rounding oxidation, the bird's beak 14 enters oxygen from the boundary between the BOX layer 3 constituting the bottom of the groove 13 and the SOI layer 4 constituting the side surface, and at the interface between the BOX layer 3 and the SOI layer 4. The SOI layer 4 is oxidized. When the SOI layer 4 is oxidized, volume expansion occurs, so that compressive stress is applied to the element. Usually, since bird's beaks are formed on both sides of the groove, compressive stress is applied to the elements on both sides. However, in the semiconductor device 1 of this embodiment, the gate electrode 8 at the bottom of the groove 12 is parallel to the extending direction. Since the groove 13 is formed along the side on the p-channel MOSFET 10 side, the bird's beak 14 on the p-channel MOSFET 10 side is formed below the diffusion layer, and the bird's beak 14 on the n-channel MOSFET 11 side is formed below the groove 12. The For this reason, a compressive stress in a direction perpendicular to the direction in which the gate electrode 8 extends is applied to the channel region of the p-channel MOSFET 10, but the compressive stress hardly affects the channel region of the n-channel MOSFET 11.

  As shown in FIGS. 17A and 17B, in the case of an n-channel MOSFET, the characteristics are improved when a tensile stress is applied in a direction parallel to and perpendicular to the direction in which the gate electrode extends, and the p-channel MOSFET is improved. In this case, when tensile stress is applied in a direction parallel to the direction in which the gate electrode extends and compressive stress is applied in the perpendicular direction, the characteristics are improved. Therefore, in the semiconductor device 1 of the present embodiment, the compressive stress is applied to the p-channel MOSFET 10 in the direction perpendicular to the direction in which the gate electrode 8 extends and the compressive stress is suppressed from being applied to the n-channel MOSFET 11. The characteristics of the p-channel MOSFET 10 can be improved without degrading the channel MOSFET 11.

  Furthermore, in the semiconductor device 1 of this embodiment, since the groove 12 does not reach the BOX layer 3, no bird's beak 14 is formed in the vicinity of the groove 12. For this reason, compressive stress in the direction parallel to the direction in which the gate electrode 8 extends in the p-channel MOSFET 10 that degrades the transistor characteristics, and compressive stress in the direction parallel to and perpendicular to the direction in which the gate electrode 8 in the n-channel MOSFET 11 extends Can be prevented.

Next, a method for manufacturing the semiconductor device 1 of this embodiment will be described. 2A to 2C and FIGS. 3A to 3C are cross-sectional views showing the method of manufacturing the semiconductor device 1 of this embodiment in the order of the steps. First, as shown in FIG. 2A, an SOI wafer in which a BOX layer 3 and an SOI layer 4 are formed on a silicon substrate 2 is thermally oxidized, and a silicon oxide film (SiO ₂ film) is formed on the surface of the SOI layer 4. 15 is formed, and then a silicon nitride film (Si ₃ N ₄ film) 16 is formed by CVD. In the semiconductor device 1 of the present embodiment, the thickness of the SOI layer 4 is, for example, 400 to 10,000 mm, the thickness of the silicon oxide film 15 is, for example, 50 to 150 mm, and the thickness of the silicon nitride film 16 Is 1000 to 2000 mm.

Next, a photoresist is applied on the silicon nitride film 16, and a resist pattern in which an area for forming the STI region 19 is an opening is formed by photolithography. Then, the silicon nitride film 16 is selectively removed by dry etching using this photoresist as a mask, and then the photoresist is peeled off. Subsequently, as shown in FIG. 2B, using the silicon nitride film 16 as a mask, the silicon oxide film 15 and the SOI layer 4 are selectively removed by dry etching to form the groove 12. At this time, when the silicon oxide film 15 and the silicon nitride film 16 are dry-etched, for example, CF ₄ is used as an etching gas, and the gas pressure is set to 0.7 to 6.7 Pa, for example. When the SOI layer 4 is dry-etched, for example, a mixed gas of Cl ₂ and O ₂ is used as the etching gas, and the gas pressure is set to 1 to 10 Pa, for example. This dry etching is stopped in the middle of the SOI layer 4 so that the groove 12 does not reach the BOX layer 3.

  The depth of the groove 12 is preferably about (1/2) to (4/5) of the thickness of the SOI layer 4, for example. If the trench 12 is shallower than ½ of the thickness of the SOI layer 4, element isolation may not be possible. Further, when the groove 12 is formed deeper than 4/5 of the thickness of the SOI layer 4, bird's beaks may also be formed on the side surfaces of the groove 12.

  Next, as shown in FIG. 2C, a photoresist 18 is formed on the silicon nitride film 16. Then, an opening 18a is formed in the photoresist 18 along the side on the p-channel MOSFET 10 side at the bottom of the portion extending in parallel with the direction in which the gate electrode of the groove 12 is formed by photolithography. That is, the opening 18 a is formed so as to be positioned on the p-channel MOSFET 10 side inside the groove 12 when viewed from the direction perpendicular to the surface of the BOX layer 3.

Next, as shown in FIG. 3A, using the photoresist 18 as a mask, the SOI layer 4 located at the bottom of the groove 12 is selectively removed by etching to form the groove 13 reaching the BOX layer 3. To do. In this dry etching, for example, HBrO ₂ is used as an etching gas, and the gas pressure is, for example, 0.5 to 3.0 Pa. Thereafter, the photoresist is removed.

Next, as shown in FIG. 3B, the SOI wafer is subjected to a thermal oxidation process to perform rounding oxidation. This oxidation treatment is performed, for example, by holding in an atmosphere having a gas composition of H ₂ —O ₂ , a pressure of normal pressure, and a temperature of 900 to 1200 ° C. for 10 to 1000 seconds. Thereby, regions corresponding to the bottom and side surfaces of the trench 12 and the trench 13 in the SOI layer 4 are oxidized, and a silicon oxide film 19 a is formed in this region, and bird's beaks 14 a and 14 b are formed on both sides of the trench 13. The size and length of the bird's beaks 14a and 14b can be adjusted by changing the temperature and time of the thermal oxidation treatment.

  Next, a silicon oxide film is formed on the entire surface of the SOI wafer with an HDP oxide film or the like, and the silicon oxide film is embedded in the trenches 12 and 13. Then, as shown in FIG. 3C, the silicon oxide film formed outside the trenches 12 and 13 is removed by CMP, and an STI region 19 made of a silicon oxide film is formed in the trenches 12 and 13. Form.

  Thereafter, a p-well 4a and an n-well 4b are formed in the SOI layer 4, and then a gate electrode 8 is formed on the p-well 4a and the n-well 4b via a gate insulating film 7, respectively. Sidewalls 9 are formed. Then, by using the gate electrode 8 and the sidewall 9 as a mask, the p-type diffusion layer 5 and the n-type diffusion layer 6 to be the source / drain regions are formed, respectively, and the semiconductor device shown in FIGS. Set to 1. Although omitted in FIGS. 1A and 1B, an interlayer insulating film, a wiring layer, and the like are formed on the semiconductor device 1.

  In the manufacturing method of the semiconductor device 1 of the present embodiment, since the formation of bird's beaks that generate compressive stress is controlled by changing the height of the STI region 19, the direction and presence / absence of compressive stress applied to the channel region are determined. Can be easily adjusted. For this reason, even when the p-channel MOSFET 10 and the n-channel MOSFET 11 are mixed as in CMOS, only the channel region of the p-channel MOSFET 10 is subjected to compressive stress in the direction perpendicular to the direction in which the gate electrode 8 extends. Can do.

  Further, in the method for manufacturing the semiconductor device 1 of the present embodiment, since the grooves in the STI region 19 are in two stages of forming the grooves 12 and forming the grooves 13, patterning is easy even when the gate interval is short. The groove 13 can be formed with high accuracy.

  FIG. 4A is a plan view showing a semiconductor device according to a modification of the first embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along line BB shown in FIG. In the semiconductor device 1 according to the first embodiment described above, since the second groove reaching the BOX layer is formed only in a part of the STI region, the SOI layer is continuous between adjacent elements. There is a part. For this reason, when it is necessary to completely separate adjacent elements, for example, when the thickness of the SOI layer is thin or when the voltage applied to the transistor is large, FIGS. As shown in b), after the trench 13a is formed and rounding oxidation is performed, the BOX layer 4 is selectively reached at a portion other than the portion parallel to the direction in which the gate electrode 8 extends at the bottom of the trench 12. It is also possible to form the third trench 13b and fill the silicon oxide film in the first to third trenches to form the STI region 19a.

  In the semiconductor device 1a of this modification, a groove 12 is formed around the p-channel MOSFET 10 and the n-channel MOSFET 11. Further, a groove 13a is formed along the side on the p-channel MOSFET 10 side in parallel with the direction in which the gate electrode 8 extends at the bottom of the groove 12, and a third groove 13b is formed in the other part. . In the semiconductor device 1a, since the third groove 13b is formed after rounding and oxidation, the bird's beaks 14 are formed only on both sides of the groove 13a and are formed on both sides of the third groove 13b. Absent. Thereby, the characteristics of the p-channel MOSFET 10 can be improved without degrading the n-channel MOSFET 11, and adjacent elements can be completely separated.

  Next, a semiconductor device according to a second embodiment of the present invention will be described. FIG. 5A is a plan view showing the semiconductor device of the embodiment, and FIG. 5B is a cross-sectional view taken along the line CC shown in FIG. As shown in FIGS. 5A and 5B, in the semiconductor device 21 of the present embodiment, a groove 22 is formed around the p-channel MOSFET 10 and the n-channel MOSFET 11, and the groove 22 is formed at the bottom of the groove 22. Also, a groove 23 having a narrow width and reaching the BOX layer 3 is provided. That is, in the semiconductor device 21, adjacent elements are completely separated by the groove 23.

  In this case, the trench 23 is formed along the side on the p-channel MOSFET 10 side of the region corresponding to the bottom of the trench 22 in a portion parallel to the direction in which the gate electrode 8 extends, and the p-channel is formed in other portions. It is formed in a region opposite to the MOSFET 10 and the n-channel MOSFET 11, that is, at a position away from the p-channel MOSFET 10 and the n-channel MOSFET 11 by a predetermined distance. For this reason, in the p-channel MOSFET 10, the bird's beak 24 is formed below the p-type diffusion layer 5 along the side surface parallel to the direction in which the gate electrode 8 of the groove 23 extends. Formed. As a result, compressive stress in the direction perpendicular to the direction in which the gate electrode 8 extends can be applied to the channel region of the p-channel MOSFET 10, and the compressive stress generated by the bird's beak 24 formed below the groove 22 is p The influence on the channel regions of the channel MOSFET 10 and the n-channel MOSFET 11 can be suppressed. Note that the configuration and effects of the semiconductor device 21 of the present embodiment other than those described above are the same as those of the semiconductor device 1 of the first embodiment described above.

  Next, a method for manufacturing the semiconductor device 21 of this embodiment will be described. 6A to 6C and FIGS. 7A to 7C are cross-sectional views showing the method of manufacturing the semiconductor device 1 of this embodiment in the order of the steps. First, as shown in FIG. 6A, a silicon oxide film 15 and a silicon nitride film 16 are formed on the SOI layer 4 of the SOI wafer by the same method as the method for manufacturing the semiconductor device 1 of the first embodiment. Form. Next, a photoresist is applied on the silicon nitride film 16, and a resist pattern in which an area for forming the STI region 29 is an opening is formed by photolithography. Then, the silicon nitride film 16 is selectively removed by dry etching using this photoresist as a mask, and then the photoresist is peeled off. Subsequently, as shown in FIG. 5B, using the silicon nitride film 16 as a mask, the silicon oxide film 15 and the SOI layer 4 are selectively removed to form a trench 22. At this time, dry etching is stopped in the middle of the SOI layer 4 so that the groove 22 does not reach the BOX layer 3.

  Next, as shown in FIG. 6C, a photoresist 28 is formed on the silicon nitride film 16. Then, by photolithography, a portion of the photoresist 28 parallel to the direction in which the gate electrode 8 extends is along the side on the p-channel MOSFET 10 side of the region corresponding to the bottom of the trench 22 and the other portions are The opening 28 a is formed at a position away from the p-channel MOSFET 10 and the n-channel MOSFET 11 by a predetermined distance so that the distance between the p-channel MOSFET 10 and the n-channel MOSFET 11 and the groove 23 is longer than the length of the bird's beak 24.

  Next, as shown in FIG. 7A, using the photoresist 28 as a mask, the SOI layer 4 located at the bottom of the groove 12 is selectively removed by etching to form the groove 23 reaching the BOX layer 3. To do. Next, as shown in FIG. 7B, the SOI wafer is subjected to a thermal oxidation process to perform rounding oxidation. Thereby, regions corresponding to the bottom and side surfaces of the trench 22 and the trench 23 in the SOI layer 4 are oxidized, and a silicon oxide film 29 a is formed in this region, and bird's beaks 24 are formed on both sides of the trench 23.

  Next, a silicon oxide film is formed on the entire surface of the SOI wafer with an HDP oxide film or the like, and the silicon oxide film is also embedded in the grooves 22 and 23. Then, as shown in FIG. 7C, the silicon oxide film formed outside the trenches 22 and 23 is removed by CMP, and an STI region 29 made of a silicon oxide film is formed inside the trenches 22 and 23. Form.

  Thereafter, a p-well 4a and an n-well 4b are formed in the SOI layer 4 in the same manner as in a normal CMOS, and then a gate electrode 8 is formed on the p-well 4a and the n-well 4b via a gate insulating film 7, respectively. Further, sidewalls 9 are formed on the side surfaces of the gate electrode 8. Then, by using the gate electrode 8 and the sidewall 9 as a mask, the p-type diffusion layer 5 and the n-type diffusion layer 6 to be the source / drain regions are formed, respectively, and the semiconductor device shown in FIGS. 21. Although omitted in FIGS. 5A and 5B, an interlayer insulating film, a wiring layer, and the like are formed on the semiconductor device 21.

  In the manufacturing method of the semiconductor device 21 of the present embodiment, since the position of the bird's beak that generates the compressive stress is controlled by changing the position where the groove 23 is formed, the compressive stress applied to the channel region can be easily adjusted. Can do. For this reason, even when the p-channel MOSFET 10 and the n-channel MOSFET 11 are mixed as in the CMOS, a compressive stress in a direction perpendicular to the direction in which the gate electrode 8 extends is applied only to the channel region of the p-channel MOSFET 10. it can.

  Next, a semiconductor device according to a third embodiment of the present invention will be described. 8 is a plan view showing the semiconductor device of the present embodiment, FIG. 9A is a cross-sectional view taken along the line DD shown in FIG. 8, and FIG. 9B is a line EE shown in FIG. It is sectional drawing by. In the semiconductor devices of the first and second embodiments described above, the case where the p-channel MOSFET and the n-channel MOSFET are formed adjacent to each other in the direction perpendicular to the direction in which the gate electrode extends has been described. However, the present invention is not limited to this, and as shown in FIG. 8, the p-channel MOSFET 40 and the n-channel MOSFET 41 may be formed adjacent to each other in a direction parallel to the direction in which the gate electrode 38 extends.

  The semiconductor device 31 of this embodiment includes a p-channel MOSFET portion in which a plurality of p-channel MOSFETs 40 are arranged in a direction perpendicular to the direction in which the gate electrode 38 extends, and a plurality in a direction perpendicular to the direction in which the gate electrode 38 extends. The n-channel MOSFET portions in which the n-channel MOSFETs 41 are arranged are alternately arranged in a direction parallel to the direction in which the gate electrode 38 extends. A p-channel MOSFET 40 and an n-channel MOSFET 41 adjacent in the direction in which the gate electrode 38 extends are connected to one gate electrode 38.

  9A and 9B, in the semiconductor device 31, a groove 42 that does not reach the BOX layer 3 is formed around the p-channel MOSFET 40 and the n-channel MOSFET 41. A groove 43 extending in parallel with the direction in which the gate electrode 38 extends and reaching the BOX layer 3 is formed at the bottom of the portion of the groove 42 formed around the gate electrode 38 that extends in parallel with the direction in which the gate electrode 38 extends. . That is, the STI region 49 in the semiconductor device 31 reaches the BOX layer 3 only in a part extending in parallel with the direction in which the gate electrode 38 around the p-channel MOSFET 40 extends, and the other part reaches the BOX layer 3. Absent. In the semiconductor device 31, a bird's beak 44 is formed between the BOX layer 3 and the SOI layer 4 in the vicinity of the groove 43 along a side surface parallel to the direction in which the gate electrode 38 of the groove 43 extends.

  As described above, in the semiconductor device 31 of the present embodiment, the bird's beak 44 is formed only below the p-type diffusion layer 35 of the p-channel MOSFET 40 in parallel with the direction in which the gate electrode 38 extends. The bird's beak 44 is not formed. Therefore, compressive stress is applied only to the p-channel MOSFET 40 in the direction perpendicular to the direction in which the gate electrode 8 extends. As a result, even in a semiconductor device in which the p-channel MOSFET 40 and the n-channel MOSFET 41 are formed adjacent to each other in a direction parallel to the direction in which the gate electrode 38 extends, the characteristics of the n-channel MOSFET 41 are not degraded. Characteristics can be improved.

  Next, a method for manufacturing the semiconductor device 31 of this embodiment will be described. The semiconductor device 31 of the present embodiment is configured so that the groove 42 does not reach the BOX layer 3 around the p-channel MOSFET 40 and the n-channel MOSFET 41 in the same manner as the semiconductor devices of the first and second embodiments described above. To form. Thereafter, a groove 43 selectively extending in parallel with the direction in which the gate electrode 38 extends is formed at the bottom of a portion of the groove 42 formed around the p-channel MOSFET 40 and extending in parallel with the direction in which the gate electrode 38 extends. It is formed so as to reach the BOX layer 3. Next, a thermal oxidation process is performed on the SOI wafer to perform rounding oxidation. As a result, the regions corresponding to the bottom and side surfaces of the trench 42 and the trench 43 in the SOI layer 4 are oxidized, a silicon oxide film is formed in this region, and between the BOX layer 3 and the SOI layer 4 in the vicinity of the trench 43. A bird's beak 44 is formed along the side surface of the trench 13 parallel to the direction in which the gate electrode 38 extends.

  Next, an HDP oxide film or the like is formed on the entire surface of the SOI wafer, and a silicon oxide film is embedded in the grooves 42 and 43. Then, the silicon oxide film formed outside the groove 42 and the groove 43 is removed by CMP, and an STI region 49 made of a silicon oxide film is formed inside the groove 42 and the groove 43. Thereafter, a p-well 34a and an n-well 34b are formed in the SOI layer 4 by a method similar to that for a normal CMOS, and then a gate electrode 38 is formed on the p-well 34a and the n-well 34b via a gate insulating film 37, respectively. Further, a sidewall 39 is formed on the side surface of the gate electrode 38. Then, by using the gate electrode 38 and the sidewall 39 as a mask, a p-type diffusion layer 35 and an n-type diffusion layer 36 to be a source / drain region are formed, respectively, and the semiconductor device shown in FIGS. 31. Although omitted in FIGS. 9A and 9B, an interlayer insulating film, a wiring layer, and the like are formed on the semiconductor device 31.

  Further, in the semiconductor device 31 of this embodiment, the groove 43 extending in parallel with the direction in which the gate electrode 38 extends is formed only in the p-channel MOSFET portion, but it is necessary to completely separate adjacent elements. In some cases, after forming the second trench and performing rounding oxidation, the bottom of the portion of the trench 42 formed around the p-channel MOSFET 40 that extends perpendicular to the direction in which the gate electrode 38 extends, and n A third groove that selectively reaches the BOX layer 4 is selectively formed at the bottom of the groove 42 formed around the channel MOSFET, and a silicon oxide film is embedded in the first to third grooves to form an STI region. You can also Thereby, the characteristics of the p-channel MOSFET 40 can be improved without degrading the n-channel MOSFET 41, and adjacent elements can be completely separated.

  Hereinafter, the effect of the Example of this invention is demonstrated compared with the comparative example which remove | deviates from the scope of the present invention. As Example 1 of the present invention, a CMOS device including a p-channel MOSFET and an n-channel MOSFET having the structure shown in FIGS. 5A and 5B was manufactured. At this time, the ratio of the height of the first groove to the height of the second groove (first groove / second groove) was set to (5/5) to (7/3). Further, as Comparative Example 1 of the present invention, a CMOS device including a p-channel MOSFET and an n-channel MOSFET having a structure without bird's beak shown in FIG. 16 was produced. In the CMOS device of Comparative Example 1, as in the CMOS device of Example 1, the ratio of the height of the first groove to the height of the second groove (first groove / second groove) is ( 5/5) to (7/3). Further, as Comparative Example 2 of the present invention, a CMOS device including a p-channel MOSFET and an n-channel MOSFET having the structure shown in FIGS. 18A and 18B was manufactured.

  The transistor characteristics of the CMOS devices of Example 1 and Comparative Examples 1 and 2 were evaluated. FIG. 10 is a schematic diagram showing a method for evaluating transistor characteristics. As shown in FIG. 10, in this embodiment, the distance between the channel region formed below the gate electrode 51, that is, between the diffusion layer 52a and the diffusion layer 52b, and the STI region 50 (hereinafter referred to as source / drain). The on-current Ion was measured by changing Lsd (referred to as “length”). FIG. 11A is a graph showing the characteristics of the p-channel MOSFET in the CMOS devices of Example 1 and Comparative Example 1, with the source / drain length (Lsd) on the horizontal axis and the on-current (Ion) on the vertical axis. FIG. 11B is a graph showing the characteristics of the n-channel MOSFET. FIG. 12A is a graph showing the characteristics of the p-channel MOSFET in the CMOS devices of Example 1 and Comparative Example 2, with the horizontal axis representing the source / drain length (Lsd) and the vertical axis representing the Ion ratio. FIG. 12B is a graph showing the characteristics of the n-channel MOSFET. Note that the on-current Ion values shown in FIGS. 11A and 11B and FIGS. 12A and 12B are standardized with the on-current Ion being 1 when the source / drain length Lsd is 5.00 μm. Value.

  As shown in FIG. 11A and FIG. 12A, the p-channel MOSFET in the CMOS device of Example 1 is significantly larger than the n-channel MOSFET in the conventional CMOS device of Comparative Example 1 and Comparative Example 2. The on-current Ion could be improved. Further, as shown in FIGS. 11B and 12B, the n-channel MOSFET in the CMOS device of Example 1 is equivalent to the n-channel MOSFET in the CMOS devices of Comparative Example 1 and Comparative Example 2. Ion was obtained. As a result, the CMOS device of Example 1 was able to improve the characteristics of the p-channel MOSFET without degrading the characteristics of the n-channel MOSFET.

(A) is a top view which shows the semiconductor device of the 1st Embodiment of this invention, (b) is sectional drawing by the AA line shown to (a). (A) thru | or (c) are sectional drawings which show the manufacturing method of the semiconductor device 1 of the 1st Embodiment of this invention in the order of the process. (A) thru | or (c) are sectional drawings which show the manufacturing method of the semiconductor device 1 of the 1st Embodiment of this invention in order of the process, and show the process following FIG.2 (c). (A) is a top view which shows the semiconductor device of the modification of the 1st Embodiment of this invention, (b) is sectional drawing by the BB line shown to (a). (A) is a top view which shows the semiconductor device of the 2nd Embodiment of this invention, (b) is sectional drawing by CC line shown to (a). (A) thru | or (c) are sectional drawings which show the manufacturing method of the semiconductor device 21 of the 2nd Embodiment of this invention in the order of the process. (A) thru | or (c) are sectional drawings which show the manufacturing method of the semiconductor device 21 of the 2nd Embodiment of this invention in order of the process, and show the process following FIG.6 (c). It is a top view which shows the semiconductor device of the 3rd Embodiment of this invention. (A) And (b) is sectional drawing which shows the semiconductor device of the 3rd Embodiment of this invention, (a) is sectional drawing by the DD line | wire shown in FIG. 8, (b) is FIG. It is sectional drawing by the EE line shown in FIG. It is a schematic diagram which shows the evaluation method of transistor characteristics. (A) is a graph showing the characteristics of the p-channel MOSFET in the CMOS devices of Example 1 and Comparative Example 1, with the source / drain length (Lsd) on the horizontal axis and the Ion ratio on the vertical axis. b) is a graph showing the characteristics of an n-channel MOSFET. (A) is a graph showing the characteristics of the p-channel MOSFET in the CMOS devices of Example 1 and Comparative Example 2, with the source / drain length (Lsd) on the horizontal axis and the Ion ratio on the vertical axis. b) is a graph showing the characteristics of an n-channel MOSFET. (A) thru | or (c) are sectional drawings which show the manufacturing method of the conventional semiconductor device in the order of the process. (A) thru | or (c) are sectional drawings which show the manufacturing method of the conventional semiconductor device in the order of the process, and show the process following FIG.13 (c). It is sectional drawing which shows the conventional semiconductor device in which p channel MOSFET and n channel MOSFET were formed adjacently. 10 is a cross-sectional view showing a semiconductor integrated circuit described in Patent Document 1. FIG. (A) is a top view which shows typically the stress direction which the characteristic of n channel MOSFET improves, (b) is a top view which shows typically the stress direction where the characteristic of p channel MOSFET improves. (A) is sectional drawing which shows p channel MOSFET of patent document 3, (b) is sectional drawing which shows n channel MOSFET.

Explanation of symbols

Semiconductor device 2, 101; Silicon substrate 3, 103; BOX layer 4, 104; SOI layer 4a, 34a, 141a; p-well 4b, 34b, 141b; n-well 5, 35; 6, 36; n-type diffusion layers 7, 37, 116; gate insulating films 8, 38, 51, 114, 131, 133, 144; gate electrodes 9, 39, 115, 145; sidewalls 10, 40;
11, 41; n-channel MOSFET
12, 13, 22, 23, 42, 43, 107, 107a, 107b; groove 14, 24, 44, 113; bird's beak (oxide layer)
15, 19a, 29a, 105; silicon oxide films 16, 106, 146; silicon nitride films 18, 28; photoresists 18a, 28a; openings 19, 29, 49, 50, 112, 143; STI regions 43b; Groove 52a, 52b, 130a, 130b, 132a, 132b, 142; diffusion layer

Claims (21)

Electrically connecting a semiconductor substrate, an insulating film formed on the semiconductor substrate, a semiconductor layer formed on the insulating film, a p-type MOS transistor formed on the semiconductor layer, and the p-type MOS transistor In the semiconductor device having the first element isolation film to be isolated, a portion of the first element isolation film located in the channel direction facing the source and drain of the p-type MOS transistor is on the surface side of the semiconductor layer. The first groove formed, and formed between the first groove and the insulating film, is shorter in width than the first groove and closer to the p-type MOS transistor than the center of the first groove. A second groove formed at a position, and an isolation insulating film filling the first and second grooves, and the second groove is formed between the semiconductor layer and the insulating film. From the side of the groove Wherein a first oxide layer extending to the middle toward the center of the p-type MOS transistor in the Le direction is formed. 2. The semiconductor device according to claim 1, wherein the first oxide layer has a shape in which the thickness decreases as the distance from the side surface of the second groove increases and the tip is pointed. 3. The semiconductor device according to claim 1, wherein the first groove is further formed in a portion of the first element isolation film located in a direction orthogonal to the channel direction. In the portion of the first element isolation film located in the direction orthogonal to the channel direction, the second groove is formed at a position farther from the p-type MOS transistor than the center of the first groove. The semiconductor device according to claim 3. A third groove is formed between the first groove and the insulating film in a portion of the first element isolation film located in a direction orthogonal to the channel direction. This third groove 4. The semiconductor device according to claim 3, wherein the semiconductor device is filled with the isolation insulating film, and an oxide layer does not extend from a side surface of the third groove. An n-type MOS transistor formed in the semiconductor layer; and a second element isolation film that electrically isolates the n-type MOS transistor, wherein the second element isolation film is a surface of the semiconductor layer. 6. The semiconductor device according to claim 1, comprising a fourth groove formed on a side and an isolation insulating film filling the fourth groove. 6. The second element isolation film is formed between the fourth groove and the insulating film and has a width shorter than that of the fourth groove and the n-type MOS transistor than the center of the fourth groove. A fifth groove is formed at a position away from the fifth groove, and the fifth groove is filled with the isolation insulating film, and the fifth groove is formed in a part between the semiconductor layer and the insulating film. The semiconductor device according to claim 6, wherein a second oxide layer is formed extending from a side surface of the groove toward the center of the n-type MOS transistor. In the second element isolation film, a sixth groove is formed between the fourth groove and the insulating film, and the sixth groove is filled with the isolation insulating film, The semiconductor device according to claim 6, wherein the oxide layer does not extend from a side surface of the sixth groove. 9. The semiconductor device according to claim 7, wherein the second oxide layer has a shape in which a thickness is reduced and a tip is sharpened as the distance from the side surface of the fifth groove is increased. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon. The semiconductor device according to claim 1, wherein the semiconductor layer is made of silicon. A step of forming an insulating film on the semiconductor substrate; a step of forming a semiconductor layer on the insulating film; and a source / drain of the p-type MOS transistor around a portion of the semiconductor layer where the p-type MOS transistor is formed. Forming a first groove on the surface side of the portion located in the opposing channel direction, and closer to the p-type MOS transistor than the center of the first groove between the first groove and the insulating film Forming a second groove having a width shorter than that of the first groove at the position, oxidizing the inside of the first and second grooves, and applying an insulator to the first and second grooves And a step of embedding the semiconductor device. 13. The semiconductor device according to claim 12, wherein the first groove is also formed in a portion located in a direction orthogonal to the channel direction around a portion where the p-type MOS transistor is formed. Production method. Around the portion where the p-type MOS transistor is formed, the second groove is located farther from the p-type MOS transistor than the center of the first groove in the portion located in the direction orthogonal to the channel direction. The method of manufacturing a semiconductor device according to claim 13, wherein: After oxidizing the inside of the first trench, the portion around the portion where the p-type MOS transistor is formed is between the first trench and the insulating film at a portion located in a direction orthogonal to the channel direction. 14. The method of manufacturing a semiconductor device according to claim 13, further comprising a step of forming a third groove and a step of burying an insulator in the third groove. forming a fourth groove on the surface side of at least a part of the semiconductor layer around the portion where the n-type MOS transistor is formed, oxidizing the fourth groove, and forming the fourth groove The method for manufacturing a semiconductor device according to claim 12, further comprising a step of burying an insulator. Forming a fifth groove having a width shorter than that of the fourth groove at a position farther from the n-type MOS transistor than a center of the fourth groove between the fourth groove and the insulating film; The method of manufacturing a semiconductor device according to claim 16, further comprising: oxidizing the inside of the fifth groove; and embedding an insulator in the fifth groove. Forming a sixth groove between the fourth groove and the insulating film after oxidizing the first and fourth grooves, and embedding an insulator in the sixth groove; The method of manufacturing a semiconductor device according to claim 16, further comprising: Forming the first groove and the fourth groove simultaneously, simultaneously forming the second groove and the fifth groove, and simultaneously oxidizing the inside of the second groove and the fifth groove; The method of manufacturing a semiconductor device according to claim 17. Forming the first groove and the fourth groove at the same time; simultaneously oxidizing the inside of the first groove and the fourth groove; and simultaneously forming the third groove and the sixth groove. The method of manufacturing a semiconductor device according to claim 18. In the step of oxidizing the inside of the second trench, the p-type MOS is formed from a side surface of the second trench on the side where the p-type MOS transistor is formed in a part between the semiconductor layer and the insulating film. 21. The method for manufacturing a semiconductor device according to claim 12, wherein an oxide layer extending partway is formed toward a center of the transistor.

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