JP2005310366A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To satisfy a specification and to reduce test time of an substandard special test by singly setting a multi-bit mode standardized by JEDEC (Joint Electron Device Engineering Council) so as to simultaneously set a special test mode whicn is not standardized by JEDEC and this multi-bit test mode. <P>SOLUTION: The semiconductor device is provided with: a state detection circuit 1610 which receives control signals /RAS, /CAS, /WE, address signals /A<SB>0</SB>, A<SB>1</SB>, and row address signals /RA<SB>0</SB>, /RA<SB>1</SB>and outputs timing detection signals /TDA, TDB, TDC and test group detection signals /TGA, /TGB; and a test mode setting signal generation circuit 1620 which receives the row address signals /RA<SB>0</SB>, /RA<SB>1</SB>, the timing detection signals /TDA, TDB, TDC and the test group detection signals /TGA, /TGB and outputs a multi-bit test mode setting signal TE and test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST 5, TEST6N, TEST6S and TEST7, according to this. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a test mode for performing a predetermined test.

  Currently, various semiconductor devices such as a microcomputer, a memory, and a gate array are mounted on various electric products including personal computers and workstations. Many of these semiconductor devices are constituted by MOS (Metal Oxide Silicon) transistors suitable for high integration and low power consumption. Among the memories including these MOS transistors and having increased in capacity in recent years, there is a DRAM (Dynamic Random Access Memory) used as a main memory of a personal computer or a workstation. In this DRAM, further cost reduction and high performance are required, but various characteristic tests become complicated in order to provide a high-performance and highly reliable product. As a result, the problem of increasing the product cost has emerged.

  In order to solve this problem, logic test devices such as microcomputers and gate arrays have been introduced early in the design stage so that tests can be performed easily, but this problem also applies to semiconductor memories. To solve this problem, design for testability has become necessary. As one of these, JEDEC (Joint Electron Device Engineering Council) reduces test time by reducing the number of accesses to reduce DRAM test time, that is, multiple memory cells that require multiple accesses in normal mode. In the test mode, the same data is written in one access, and the data written in the plurality of memory cells is read out in the chip, and a signal indicating whether or not they match is output in one access. Multi-bit test is standardized. Further, for example, the internal potential monitor described in JP-A-6-194424, which is not standardized by JEDEC, or the number of inverters in a delay chain by a plurality of inverters described in JP-A-5-2442698 is reduced. DRAMs with special test modes such as a test mode in which a certain access path is shorted to realize a high temperature condition at room temperature and a test mode in which a substrate bias is changed to accelerate defects are also proposed.

  FIG. 29 is a circuit diagram including a conventional test mode setting circuit mounted on a DRAM disclosed in Japanese Patent Application Laid-Open No. H5-242698. In this test mode setting circuit, a write enable signal / WE and a column address strobe signal / CAS WCBR (/ WE, / CASBefore / RAS) timing when the row address strobe signal / RAS is lowered to L level after the voltage is first lowered to L level and a potential higher than the power supply potential to a specific input pin In combination with the super voltage input, the output of NA becomes L level, and one of NO10, NO11, NO12, NO13 based on A1 and A2 outputs H level, and flip-flop circuits 5, 6, 7, 8 are each NO10 , NO11, NO12, NO13, NO10, NO1 except when the reset signal RST is H level and the super voltage is not applied to a specific input pin, that is, when the output of NO1 is L level The flip-flop circuit that receives the output at H level among the outputs from 1, NO12, NO13 sets the test mode setting signals OPT1, OPT2, OPT3, OPT4 corresponding to the H level and holds them (then corresponding NO10, Even if the output from NO11, NO12, NO13 becomes L level, it continues to output H level). When the reset signal RST is at H level and no super voltage is applied to a specific input pin, that is, when the output of NO1 is at H level, OPT1, OPT2, OPT3, and OPT4 are reset to L level.

  As described above, the conventional test mode setting circuit sets the OPT1, OPT2, OPT3, and OPT4 to the H level once until the reset signal RST is set to the H level and the super voltage is not applied to the specific input pin. Therefore, a plurality of test modes can be simultaneously activated by setting the plurality of OPT1, OPT2, OPT3, and OPT4 to the H level by changing the address signals A1 and A2.

In addition to this, JP-A-62-222948 discloses a semiconductor integrated circuit that realizes reliable setting of a special test mode.
JP-A-6-194424 JP-A-5-242698 Japanese Patent Laid-Open No. 6-222948

  In the conventional test mode setting generation circuit shown in FIG. 29, the multi-bit test is not performed only by the WCBR timing standardized by JEDEC, and the multi-bit test mode and the special test mode are not used. Cannot be activated at the same time, so there is a problem that the test time cannot be shortened using the multi-bit test mode.

  Also, wiring for transmitting the test mode setting signals OPT1, OPT2, OPT3, OPT4 to each internal circuit (not shown) that is set to the test mode by receiving the test mode setting signals OPT1, OPT2, OPT3, OPT4, respectively. Therefore, there is a problem that the number of test modes cannot be increased from four when there is only an area where only four wires are extended.

  Furthermore, in a region where a power supply line such as a power supply potential line to which a power supply potential is applied or a ground potential line to which a ground potential is applied is provided as a shield line so that the signal line does not receive noise, these wirings are provided. There is also a problem that the area occupied by is increased and it is difficult to extend the wiring for transmitting the test mode setting signal.

  The present invention has been made in view of the above points, and when the input signal enters a standardized predetermined state, the multi-bit test mode is set, and the input signal is different from the standardized predetermined state. A first object is to obtain a semiconductor device in which a special test mode is set when a predetermined state is reached and the multi-bit test mode can be set even when the special test mode is set.

  A second object is to reduce the number of wirings for transmitting a test mode setting signal to be smaller than the number of test modes.

  Furthermore, the third object is to shield the signal line without providing the power line on the shield line.

According to a first aspect of the present invention, there is provided a semiconductor device provided in a semiconductor chip, and provided in the semiconductor chip, an encode signal generating circuit for outputting a plurality of test mode encode signals corresponding to a state of an input signal input to the semiconductor chip. A plurality of encode signal wirings, each of which transmits each test mode encode signal from the encode signal generation circuit and at least partially extending in the first direction, and more than the encode signal generation circuit of the semiconductor chip. A test mode that is provided on one direction side, receives a test mode encode signal from a plurality of encode signal wirings, and outputs a plurality of test mode setting signals corresponding to the test mode encode signal more than the number of the test mode clock signals A test mode setting circuit having a decoding circuit, and a semiconductor chip Provided in the first direction side with respect to the encode signal generating circuit, and having a plurality of internal circuits for receiving each test mode setting signal from the test mode decoding circuit and performing a predetermined test operation in accordance with the test mode setting signal It is.

  According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein the semiconductor device according to the first aspect is located at the center of one side of the semiconductor chip and extends to the other side of the chip adjacent to the one side. A plurality of pads arranged along the side direction are further provided, and an encode signal wiring is provided in the chip central band.

The semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the input signal includes a first input signal and a second input signal,
A test mode setting circuit receives a first input signal, outputs a state detection signal corresponding to the state of the first input signal, receives the state detection signal, and the first input signal is the first input signal. When this state detection signal indicates that the current state is a multi-bit test mode setting signal which is set to an activation level, the first input signal is in a second state different from the first state. When the detection signal indicates, an input decode signal corresponding to the second input signal is supplied to the encode signal generation circuit, so that at least one of the test mode setting signals output from the test mode decode circuit is set to the activation level, The state detection signal indicates that the first input signal is in the second state. If the second input signal is in the third state, the multi-bit test mode setting signal is set to the activation level and And an input decoder for providing at least one of the test mode setting signals output from the test mode decode circuit to an activation level by applying an input decode signal corresponding to the input signal to the encode signal generating circuit. It is what.

  According to a fourth aspect of the present invention, there is provided a semiconductor device according to the first or second aspect, wherein the test mode setting circuit outputs a first test mode setting signal and an input decode signal corresponding to the input signal. The input decode signal is supplied to the encode signal generating circuit, and at least one of the first test mode setting signal and the test mode setting signal output from the test mode decode circuit when the input signal is in a predetermined state. It further includes an input decoder for setting the activation level.

  According to a fifth aspect of the present invention, there is provided a semiconductor device according to the first or second aspect, wherein the test mode decode circuit receives a test mode encode signal from a plurality of encode signal wirings and receives the test mode encode signal. A first local test mode decoding circuit that outputs a test mode setting signal according to the number of the test signal, and a test mode encode signal received from the plurality of encode signal lines, and a smaller number than the encode signal line in accordance with the test mode encode signal And a second local test mode decode circuit provided by the first local test mode decode circuit rather than an internal circuit corresponding to the test mode set signal. is there.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the test mode decode circuit receives a test mode encode signal from a plurality of encode signal wirings, and the test mode encode signal is A first local test mode decoding circuit for outputting a corresponding test mode setting signal and a test mode encoding signal from a plurality of encoding signal wirings, and a test mode setting signal equal to or higher than the encoding signal wiring is received according to the test mode encoding signal. It has a second local test mode decode circuit provided by an internal circuit corresponding to the test mode setting signal rather than the first local test mode decode circuit.

  In the invention according to claim 1, since the test mode setting signal is reduced to a test mode encoding signal smaller than the test mode setting signal and transmitted to the internal circuit with a small number of encode signal wirings, the test mode setting signal is transmitted with a small wiring area. Can communicate.

  In the invention according to claim 2, in addition to the operation of the invention according to claim 1, since the test mode setting signal can be transmitted with a small wiring area, a plurality of pads are arranged and the wiring is passed through the central band of the chip. Even in a semiconductor device having a narrow area, a large number of test modes can be set by transmitting a test mode setting signal with less encode signal wiring than the test mode setting signal.

  In the invention according to claim 3, in addition to the operation of the invention according to claim 1 or claim 2, the test mode setting circuit includes not only the first input signal in the first state but also the second state. Even in this case, the multi-bit test mode setting signal can be activated by the second input signal, and both the multi-bit test mode setting signal and other test mode setting signals can be activated. By setting both the mode and another test mode, the test time required for the second test mode can be shortened.

  In the invention according to claim 4, in addition to the operation of the invention according to claim 1 or 2, the first test mode setting signal activated together with another test mode setting signal is not given to the encode signal generating circuit. Therefore, it is not necessary to provide a combination of encode signals for activating both the first test mode setting signal and other test mode setting signals, and more test mode setting signals can be obtained with a limited encode signal wiring. Can be transmitted.

  In the invention according to claim 5, in addition to the operation of the invention according to claim 1 or 2, the test mode encode signal is decoded by the first local test mode decode circuit, and several test mode setting signals are output. When the number of test mode setting signals output from the second local test mode decode circuit is smaller than that of the test mode encode signal, the second local test mode decode circuit is replaced with the first local test mode decode circuit. Since the test mode setting signal is decoded and transmitted to the internal circuit, the number of encode signal wirings that are larger than the test mode setting signal output from the second local test mode decoding circuit is provided in this test mode. Less distribution than extending to the internal circuit corresponding to the setting signal In capable of transmitting the test mode setting signal.

  In the invention according to claim 6, in addition to the operation of the invention according to claim 1 or 2, the test mode encode signal is decoded by the first local test mode decode circuit, and several test mode setting signals are output. Even when the number of test mode setting signals output from the second local test mode decode circuit is greater than or equal to the number of test mode encode signals, the second local test mode decode circuit is provided from the corresponding internal circuit. Since the encode signal is transmitted to the internal circuit as it is, the number of encode signal wirings less than the test mode setting signal output from the second local test mode decoding circuit is close to the internal circuit corresponding to the test mode setting signal. The test mode setting signal can be transmitted with less wiring.

  The invention according to claim 1 has an effect that the test mode setting signal can be transmitted with a small wiring area.

  In the invention according to claim 2, in addition to the effect of the invention according to claim 1, a plurality of test modes can be set even in a semiconductor device in which a plurality of pads are arranged and a region through which wiring is passed in the chip central band is narrow. effective.

  In the invention according to claim 3, in addition to the effect of the invention according to claim 1 or 2, there is an effect that the test time required for the second test mode can be shortened.

  In the invention according to claim 4, in addition to the effect of the invention according to claim 1 or 2, there is an effect that more test mode setting signals can be transmitted by a limited encode signal wiring.

  In the invention according to claim 5, in addition to the effect of the invention according to claim 1 or 2, the test mode encode signal is decoded by the first local decode circuit, and several test mode setting signals are output, When the number of test mode setting signals output from the second local decode circuit is smaller than that of the test mode encoding signal, an increase in the wiring area for transmitting the test mode setting signal can be suppressed.

  In the invention according to claim 6, in addition to the effect of the invention according to claim 1 or 2, the test mode encode signal is decoded by the first local decode circuit and several test mode setting signals are output. However, when the number of test mode setting signals output from the second local decoding circuit is greater than or equal to the number of test mode encode signals, an increase in the wiring area for transmitting the test mode setting signals can be suppressed.

(Example 1.)
A DRAM according to a first embodiment of the present invention will be described below with reference to FIGS. Figure 1 is a simplified block diagram showing the whole of the DRAM, 100 receives the external power supply potential EXTV _CC from the power supply potential node 100a applied external power supply potential EXTV _CC in figure, the external power supply potential EXTV _CC an internal power supply potential generation circuit 110 supplies a low internal power supply potential intVcc than the power supply potential node 100c, and driven by the internal power supply potential intVcc, outputs a high step-up potential V _PP than the internal power supply potential intV _CC boosted potential and generating circuit 120, a cell plate potential generation circuit 130 for outputting a cell plate potential V _CP of receiving internal power supply potential intV _CC (1/2) intV _CC, receives the internal power supply potential intV _CC (1/2) an internal potential generation circuit group and a bit line precharge potential generation circuit 140 for outputting a bit line precharge potential V _BL of intV _CC.

200 receives an external row address strobe signal ext / RAS given from the outside and outputs a row address strobe signal / RAS for the internal circuit / RAS buffer, 300 is an address signal A _i (i = 0,1, ... ., 10) and / RAS buffer 200 receives row address strobe signal / RAS, and when this row address strobe signal / RAS changes from H level to L level, address signal A _i is latched as a row address signal, and the internal circuit The row address buffer 400 outputs the row address signal RA _i (the same logic as the address signal A _i ) and / RA _i (the opposite logic to the address signal A _i ) for the row address 400, and 400 is the row address signal RA _i from the row address buffer 300. , / RA _i, and one of the row predecode signals X _{0 to} X ₃ , RA ₂ , / RA ₂ , RA ₃ , /, one of which becomes H level according to RA ₀ , / RA ₀ , RA ₁ , / RA ₁ one depending on RA ₃ but row predecode at H level No. _{X 4 ~X 7, RA 4,} / RA 4, RA 5, / RA 1 one in response to ₅ but row predecode signal X ₈ to X ₁₁ at H _{level, RA 6, / RA 6,} RA 7, / The block selection signal BS _j in which eight selected based on the row predecode signals X _{12 to} X ₁₅ , RA ₈ , / RA _{8 to} RA ₁₀ , / RA ₁₀ that become H level according to RA ₇ become H level. This is a row predecoder that outputs (j = 0, 1,..., 63).

Reference numeral 500 denotes a memory cell array having four memory mats each having 4 × 2 ²⁰ memory cells 511a arranged in a plurality of rows and columns, and each memory mat has 256 × 2 ¹⁰ memory cells. is divided into 16 memory cell blocks having 511a, each memory cell blocks are arranged in a plurality of rows, 256 word lines 511b, each being connected to a 2 ¹⁰ memory cells arranged in rows corresponding and are arranged in a plurality of rows, each has a pair of bit lines 511c of 2 ¹⁰ which is connected to 256 memory cells arranged in rows corresponding. Each memory cell block is divided into 8 column blocks each having 128 bit line pairs.

600 is divided corresponding to the memory cell blocks 64 of the row decoder block, the block selection signal BS by each row decoder block corresponding to the row predecode signal X ₀ to X ₁₅ and row decoder block from the row predecoder 400 a row decoder 700 that receives one of _j and sets one of 256 word lines corresponding to the selected row decoder block according to the row predecode signals X _{0 to} X ₁₅ to the boosted potential V _PP level; The external column address strobe signal ext / RAS given from the outside is received and the column address strobe signal / CAS for the internal circuit is output / CAS buffer, 800 is the address signal A _i (i = 0,1, ..., 10) and / CAS receives the column address strobe signal / CAS from the buffer 700, Kola address signal a _i When the column address strobe signal / CAS is changed from H level to L level Latched as an address signal, a column address buffer for outputting the column address signal CA _i (address signal A _i and the logic) and / CA _i (address signal A _i and inverse logic) for the internal circuit.

900 receives column address signals CA _i , / CA _i from the column address buffer 800, and one of the column predecode signals Y ₀ -Y becomes one in accordance with CA ₀ , / CA ₀ , CA ₁ , / CA _{1. 3, CA 2, / CA 2} , CA 3, / CA 3 1 one in response to but a column predecode signal Y ₄ to Y ₇ becomes H _{level, CA 4, / CA 4,} CA 5, in accordance with / CA ₅ Column block selection signal CBS _k (k = 0), one of which is selected based on column predecode signals Y _{8 to} Y ₁₁ , CA ₆ , / CA _{6 to} CA ₁₀ , / CA _{10 in} which one becomes H level , 1,..., 31).

1000 is provided in common to 16 memory cell blocks included in the same memory mat, and has 32 column decoder blocks divided corresponding to column blocks having 128 bit line pairs. receiving the column predecode signal Y ₀ to Y ₁₁ and column block select signal CBS _k from 900, the column selection signal CSL _{m (m} = 0 one which becomes H level in response to the column predecode signal Y ₀ to Y _11, 1,..., 63) are output and two pairs of bit lines are selected in each memory cell block based on the column selection signal CSL _m and selected by the block selection signal BS _j according to the column block selection signal CBS _k 4 bits are selected from 128-bit data read from a total of 128 pairs of bit lines output from two pairs of bit lines selected by the column selection signal CSL _{m in} each column block of the eight memory cell blocks Shita The data selection signal _{DS n (n = 0,1, ···} , 127) is a column decoder for outputting.

  1100 is divided into 68 sense amplifier blocks each including 512 sense amplifiers corresponding to the memory cell blocks, and 60 sense amplifier blocks among the 68 sense amplifier blocks are between two memory cell blocks. The sense amplifier group and the bit line corresponding to the two sense amplifier blocks are shared by the two adjacent memory cell blocks and shared between the two sense amplifier blocks. A memory having a circuit such as an I / O circuit including a local I / O line and a global I / O line for outputting data of a memory cell output via the memory cell and transmitting data written to the memory cell to a bit line It is a cell array peripheral circuit group.

1200 receives an external write enable signal ext / WE given from the outside, outputs a write enable signal / WE for the internal circuit / WE buffer, 1300 receives an external output enable signal ext / OE given from the outside, Write enable signal / OE for internal circuit / OE buffer, 1400 receives row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE and output enable signal / OE A write / read control circuit that outputs a write / read control signal WO indicating whether it is read, 1500 receives a write / read control signal WO from the write / read control circuit 1400, and when this signal WO indicates writing, it is externally Contact data corresponding to 4-bit data D _{r (r} = 0,1,2,3) given to the memory cell array peripheral circuit group 1100 Given to that I / O circuit, when the signal WO indicates a read is a output buffer for outputting data D _r in accordance with the data output from the I / O circuit in the memory cell array peripheral circuit group 1100 to the outside.

1600 receives a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a address signal A _0, A ₁ and a row address signal / RA _0, ···, a / RA _6, these inputs This is a test mode setting circuit that outputs test mode setting signals TE, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6N, TEST6S, and TEST7 according to the signal.

Next, a normal read operation of the DRAM shown in FIG. 1 will be described with reference to FIG. First, during the read operation, the external write enable signal ext / WE is at the H level and the external output enable signal ext / OE is at the L level, so the write enable output from the / WE buffer 1200 and the / OE buffer 1300, respectively. Signal / WE and output enable signal / OE are also at H level and L level, respectively. Then, before the row address strobe signal / RAS falls to the L level at time t ₀ as shown in FIG. 2A, the potentials WL _p of all the word lines 511b are as shown in FIG. And the potentials BL _q and / BL _{q of} all the bit line pairs 511c are precharged to the bit line precharge potential V _BL as shown in FIG. 2E, and all the column selection signals CSL _m Is set to the L level as shown in FIG. _2F , and the output data _Dr is in a high impedance (Hi-Z) state as shown in FIG.

When the address signal A _i is changed to a row address as shown in FIG. 2C and the row address strobe signal / RAS falls to the L level at time t _{0 as} shown in FIG. In response to this, the row address buffer 300 latches the address signal A _i as the row address signal RA _i and supplies it to the row predecoder 400, and also supplies the row address signal / RA _{i of the} inverted logic to the row predecoder 400. Row predecoder 400 provides row decoder 600 with row predecode signals X ₀ ,..., X ₁₅ and block selection signal BS _j corresponding to row address signals RA _i , / RA _i . The row decoder 600 shows one word line corresponding to the row predecode signals X ₀ ,..., X ₁₅ among the word lines corresponding to the row decoder block selected by the block selection signal BS _j as shown in FIG. Thus, the voltage is raised to the boosted potential V _PP level at time t ₁ .

Then, charge is transferred between the capacitor and the bit line in the memory cell 511a. When L level data is stored in the capacitor, the potential of the bit line is changed to the bit as shown in FIG. Although it is not shown when the H level data is stored slightly lower than the line precharge potential _VBL , the bit line potential slightly rises from the bit line precharge potential _VBL and the bit line precharge potential _VBL is stored. A minute potential difference is generated between the bit line and the bit line pair that remains at the charge potential _VBL . Then, the sense amplifier in the memory cell array peripheral circuit group 1100 detects and amplifies a minute potential difference generated in the bit line pair, and the potential of the bit line having the lower potential is set to the L level as shown in FIG. The potential of the higher bit line is set to H level.

When the address signal A _i is set to the column address as shown in FIG. 2C, and the column address strobe signal / CAS falls to the L level at time t _{2 as} shown in FIG. 2B, In response to this, the column address buffer 800 latches the address signal A _i as the column address signal CA _i and supplies it to the column pre-decoder 900, and also supplies the column address signal / CA _{i of the} inverted logic to the column pre-decoder 900. Column predecoder 900 _supplies column decoder 1000 with column predecode signals Y ₀ ,..., Y ₁₁ and column block selection signal CBS _k corresponding to column address signals CA _i , / CA _i . The column decoder 1000 selects one of the column selection signals CSL _m corresponding to each column block according to the column predecode signals Y ₀ ,..., Y ₁₁ at time t _{3 as} shown in FIG. Launch to H level.

Then, the data is read from a total of 128 pairs of bit lines output from the two pairs of bit lines selected by the column selection signal CSL _{m in} each column block of the eight memory cell blocks selected by the block selection signal BS _j . 128 bits of data is outputted to the I / O circuit (not shown) in the memory cell array peripheral circuit group 1100, output buffer 4 bits corresponding to the data selection signal DS _n of the I / O circuit 128-bit data 1500, the input / output buffer 1500 outputs data _Dr corresponding to the 4-bit data at time t _{4 as} shown in FIG.

Figure 3 is a circuit diagram showing an internal power supply potential generation circuit 110, 111 receives an external power supply potential EXTV _CC in figure, the reference potential generating circuit for outputting a reference voltage V _ref which does not depend on the external power supply potential EXTV _CC, p channel MOS transistor 111a, n channel MOS transistor 111b, resistor element 111c, p channel MOS transistor 111d, n channel MOS transistor 111e, p channel MOS transistor 111f, and resistor element 111g. 112 driven by the EXTV _CC, the reference receives the reference potential V _ref from the potential generating circuit 111, an external power supply potential EXTV lower than _CC, the reference potential V _ref internal power supply potential node internal power supply potential intV _CC corresponding to A regulator for supplying to 100c, which is arranged on one side of the long side of the semiconductor chip (hereinafter referred to as N (North) side), has a differential amplifier circuit 112a and a p-channel MOS transistor 112b, and is located on the N side The internal power supply potential intV _CC is supplied to the circuit. 113 is connected between external power supply potential node 100a and external power supply potential node 100c, receives test mode setting signal TEST6N, and when this test mode setting signal TEST6N becomes H level, external power supply potential node 100a and internal power supply potential node 100c Are stressed to increase the internal power supply potential intV _CC and apply stress to the circuit driven by the internal power supply potential intV _CC, and have a p-channel MOS transistor 113a and an inverter 113b.

114 driven by the EXTV _CC, the reference receives the reference potential V _ref from the potential generating circuit 111, an external power supply potential EXTV lower than _CC, the reference potential V _ref internal power supply potential node internal power supply potential intV _CC corresponding to A regulator for supplying to 100c, which is disposed on the other side in the long side direction of the chip (hereinafter referred to as S (South) side), has a differential amplifier circuit 114a and a p-channel MOS transistor 114b, and is located on the S side Is supplied with the internal power supply potential intV _CC . 115 is connected between external power supply potential node 100a and external power supply potential node 100c, receives test mode setting signal TEST6S, and when this test mode setting signal TEST6S becomes H level, external power supply potential node 100a and internal power supply potential node 100c short the preparative stress mode circuit stress the circuit being driven by the internal power supply potential intV _CC and has a p-channel MOS transistors 115a and inverter 115b.

FIG. 4 is a block diagram showing the configuration of the test mode setting circuit 1600. In FIG. 4, reference numeral 1610 denotes a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, address signals A ₀ and A ₁ and a row address. In response to signals / RA ₀ and / RA ₁ , row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE both set column address strobe signal / CAS and write enable signal / WE to L level. Is input at the WCBR timing when the row address strobe signal / RAS is set to L level, the address signal A ₀ is at a super H level higher than the normally used H level, and the address signal A ₁ is at the normally used H level. Test group detection signal / TGA, low address strobe signal / RAS, column address strobe The test group detection signal //, which is input at the WCBR timing, becomes the L level when the address signal A ₀ is normally used and the address signal A ₁ is at the super H level. It is a state detection circuit that outputs TGB.

  This state detection circuit 1610 is set to L level when the row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at the WCBR timing, and the write enable signal / WE is set to H level. The column address strobe signal / CAS is set to L level and then the row address strobe signal / RAS is set to L level. After the CBR (/ CASBefore / RAS) refresh timing is input, or the column address strobe signal / CAS and write enable signal are input. After being input at the ROR (/ RASOnlyRefresh) timing to set the row address strobe signal / RAS to the L level with both / WE held at the H level, the row address strobe signal / RAS is reset to the H level based on the rise to the H level. Timing detection signal / TDA and row address strobe signal / RAS When the column address strobe signal / CAS and the write enable signal / WE are input at the WCBR timing, the timing detection signal TDB which is H level for a predetermined period after a predetermined time, the row address strobe signal / RAS, the column address strobe signal After / CAS and write enable signal / WE are input at WCBR timing, when row address strobe signal / RAS rises to H level, it is set to H level, row address strobe signal / RAS, column address strobe signal / CAS and write After the enable signal / WE is input at the CBR refresh timing or ROR timing, when the row address strobe signal / RAS rises to the H level, the timing detection signal TDC that is reset to the L level is output.

  The state detection circuit 1610 receives three control signals of a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable signal / WE, and receives timing detection signals / TDA, TDB corresponding to the timing of the control signals. And a timing detection circuit 1611 (FIG. 5) for outputting TDC.

Further, the state detection circuit 1610 receives the timing detection signals / TDA, TDB, TDC, the address signals A ₀ , A ₁ and the row address signals / RA ₀ , / RA _1, and receives the row address strobe signal / RAS, the column address strobe signal. When / CAS and write enable signal / WE are input at WCBR timing, and address signal A ₀ is set to a super H level higher than normal H level and address signal A ₁ is set to normal H level, timing detection signal A test group detection signal / TGA that is set to L level in response to the rise of TDC to H level, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE are input at WCBR timing, and When the address signal A ₀ is set to the normal H level and the address signal A ₁ is set to the super H level, the H level of the timing detection signal TDC is set. And a test group detection circuit 1612 (FIG. 6) for outputting a test group detection signal / TGB which is set to L level in response to the rise to the signal level.

1620 row address signal / RA ₂ from the timing detection signal / TDA, TDB, test group detection signal / TGA, / TGB and the row address buffer 300 from the state detection circuit 1610 receives ..., and / RA _6, waxes When address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at the WCBR timing, _one of address signals A ₀ and A ₁ is at the super H level and the other is at the normal H level. If not, the multi-bit test mode setting signal TE which is set to H level in response to the rise of the timing detection signal TDC, the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are WCBR timing. in is input, when one of the address signals a _0, a ₁ and the other is a normal H-level super H level, the row address signals _{/ RA 2, ···, / RA} 6 that according to become H-level special test mode setting signal TEST1, TEST2, TEST3, TEST4, TEST5, TEST6N, outputs and TEST6S, TEST7, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at WCBR timing, _one of address signals A ₀ and A ₁ is set to the super H level and the other is set to the normal H level, and row address signal / When RA ₆ is set to the L level, the multi-bit test mode setting signal TE is set to the H level and the row address signal / RA among the special test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST5, TEST6N, TEST6S, and TEST7. ₂ ,..., / RA ₅ is a test mode setting signal generation circuit (FIG. 7) for setting the level to H level.

  FIG. 5 is a specific circuit diagram of the timing detection circuit 1611 in the state detection circuit 1610. 1611a is a delay circuit that outputs the delay signal D / RAS of the row address strobe signal / RAS, 1611b is the L address of the row address strobe signal / RAS. Output the clocked inverter control signal CLC and the inverted signal / CLC which are L level until the delay signal D / RAS rises to the H level with a delay from the row address strobe signal / RAS. / RAS and a clocked inverter control circuit having a NAND circuit 1611ba and inverters 1611bb and 1611bc that make the output L level when both of these delay signals D / RAS become H level, 1611c is a write enable signal / WE, clocked inverter control signal In response to CLC and / CLC, the write enable signal / WE first becomes L level, and the row address strobe signal / RAS Is a WBR detection circuit that outputs a WBR (/ WEBefore / RAS) detection signal / WBR that becomes L level when the signal becomes L level, and has a clocked inverter 1611ca, an inverter 1611cb, and a clocked inverter 1611cc, and a clocked inverter control signal CLC When / CLC is at H level and L level, respectively, the WBR detection signal / WBR has the same logic as the write enable signal / WE, and when the clocked inverter control signals CLC and / CLC are at L level and H level, respectively, Holds the current WBR detection signal / WBR.

  1611d receives column address strobe signal / CAS and clocked inverter control signals CLC and / CLC. When column address strobe signal / CAS first goes to L level and row address strobe signal / RAS goes to L level, CBR detection circuit that outputs CBR (/ CASBefore / RAS) detection signal / CBR, which has clocked inverter 1611da, inverter 1611db and clocked inverter 1611dc, and clocked inverter control signals CLC and / CLC are H level and At the L level, the CBR detection signal / CBR has the same logic as the write enable signal / WE, and when the clocked inverter control signals CLC and / CLC are at the L level and the H level, respectively, the CBR detection signal / CBR at that time Hold.

  1611e receives row address strobe signal / RAS, delay signal D / RAS, WBR detection signal / WBR and CBR detection signal / CBR, and WBR detection signal / WBR and CBR detection signal / CBR are at L level, that is, row address strobe signal When / RAS, column address strobe signal / CAS and write enable signal / WE are input at the WCBR timing, delay signal D / RAS becomes H level in response to L address following row address strobe signal / RAS. WCBR timing detection circuit that outputs a WCBR timing detection signal WCBR that is reset to L level when the row address strobe signal / RAS rises to H level. The row address strobe signal / RAS and this delay signal D / RAS are The circuit includes a NOR circuit 1611ea, an inverter 1611eb, a NAND circuit 1611ec, and a NOR circuit 1611ed that set the output to the H level when both are at the L level.

  1611f receives row address strobe signal / RAS, delay signal D / RAS, column address strobe signal / CAS, WBR detection signal / WBR and CBR detection signal / CBR, and receives row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at CBR refresh timing and WBR detection signal / WBR is at H level and CBR detection signal / CBR is at L level, or row address strobe signal / RAS and column address strobe signal / CAS Is input at the ROR timing, the reset timing detection circuit outputs a reset timing detection signal / RST that becomes L level for a predetermined period after the row address strobe signal / RAS rises to H level.

  This reset timing detection circuit 1611f receives row address strobe signal / RAS, delay signal D / RAS, WBR detection signal / WBR and CBR detection signal / CBR, and receives row address strobe signal / RAS, column address strobe signal / CAS and When the write enable signal / WE is input at the CBR refresh timing and the WBR detection signal / WBR becomes H level and the CBR detection signal / CBR becomes L level, the row address strobe signal / RAS rises to H level for a predetermined period. The CBR refresh timing detection signal CBRR is output, and the inverter 1611ga, NOR circuit 1611gb, inverter 1611gc, NOR circuit 1611gd, NOR circuit 1611ge, and NOR circuit 1611ge have a NOR circuit 1611gf and a NOR circuit 1611gg A CBR refresh timing detection circuit 1611g is included.

  Further, the reset timing detection circuit 1611f receives the row address strobe signal / RAS, the delay signal D / RAS and the column address strobe signal / CAS, and inputs the row address strobe signal / RAS and the column address strobe signal / CAS at the ROR timing. Then, the ROR timing detection signal ROR that becomes H level for a predetermined period after the row address strobe signal / RAS rises to H level is output, and the inverter 1611ha, NAND circuit 1611hb, NOR circuit 1611hc, NOR circuit 1611hd, NOR circuit 1611hd And the ROR refresh timing detection circuit 1611h having the NOR circuit 1611he, the inverter 1611hf and the NOR circuit 1611hg, and the reset timing detection signal / RST in response to the CBR refresh timing detection signal CBRR and the ROR timing detection signal ROR. Output CBR refresh timing detection signal CB When at least one of RR and ROR timing detection signal ROR is at H level, it has a NOR circuit 1611fa that sets reset timing detection signal / RST to L level.

  1611i receives WCBR timing detection signal WCBR and reset timing detection signal / RST, and outputs timing detection signal TDA. Row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at WCBR timing. When the WCBR timing detection signal WCBR is at H level and the reset timing detection signal / RST is at H level, the timing detection signal TDA is set to H level, the row address strobe signal / RAS, the column address strobe signal / CAS, and the write enable signal When / WE is input at CBR refresh timing or ROR timing and the WCBR timing detection signal WCBR is at L level and the reset timing detection signal / RST is at L level at the rise of the row address strobe signal / RAS to H level, timing detection Reset signal TDA to L level Collected by inverter 1611Ia, a set / reset circuit with a NAND circuit 1611ic constituting the flip-flop circuit by the NAND circuit 1611Ib and NAND circuit 1611Ib.

  The 1611j receives the timing detection signal TDA and the clocked inverter control signals CLC and / CLC and outputs the timing detection latch signal LTDA. When the clocked inverter control signals CLC and / CLC are at the H level and the L level, respectively, the timing detection When the latch signal LTDA has the same logic as the timing detection signal TDA, and the clocked inverter control signals CLC and / CLC become L level and H level, respectively, the timing detection signal latch circuit holds the timing detection latch signal LTDA at that time. A clocked inverter 1611ja, an inverter 1611jb, and a clocked inverter 1611jc.

  1611k is a pulse generation circuit that receives a row address strobe signal / RAS and outputs a pulse signal PLS that falls to L level for a predetermined period after a predetermined time has elapsed since the row address strobe signal / RAS fell to L level. The circuit includes a delay circuit 1611ka, an inverter 1611kb, a delay circuit 1611kc, and a NAND circuit 1611kd.

  1611m receives the timing detection signal TDA timing detection latch signal LTDA and the pulse signal PLS, the timing detection signal TDA obtained by inverting the timing detection signal TDA, the timing detection signal TDA is H level, the pulse signal PLS is L level, the timing detection latch This is a timing detection signal generation circuit that outputs a timing detection signal TDB that becomes H level when the signal LTDA is at L level, and a timing detection signal TDC having the same logic as the timing detection latch signal LTDA. Inverters 1611ma, 1611mb, NAND circuit 1611mc And inverters 1611md, 1611me and 1611mf.

  Therefore, the timing detection signal / TDA is set to L level when the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are input at the WCBR timing, and is input at the CBR refresh timing or ROR timing. Then, the row address strobe signal / RAS is reset to the H level in response to the rising to the H level, the timing detection signal TDB is set to the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are set to WCBR. When input is performed at a timing, the row detection strobe signal / RAS becomes the H level only for a predetermined period after the lapse of a predetermined time from the fall of the row address strobe signal / RAS, and the timing detection signal TDC is the row address strobe signal / RAS, the column address strobe signal / CAS. And write enable signal / W When E is input at the WCBR timing, it becomes H level based on the rise of the row address strobe signal / RAS to the H level, and when E is input at the CBR refresh timing or ROR timing, the row address strobe signal / RAS is at the H level. It becomes L level based on the rising edge.

Figure 6 is a specific circuit diagram of a test group detection circuit 1612 in the state detection circuit 1610, 1612a in the super H level detection circuit, address pins 1612aa and super H level detection signal SD ₀ for receiving an address signal A ₀ is output Connected between super high level detection signal output node 1612ab, each having threshold voltage _Vth , gate and drain connected, and serially connected between address pin 1612aa and super high level detection signal output node 1612ab. three n-channel MOS transistor 1612ac connected to have 1612ad and 1612Ae, super when the address signal a ₀ is the external power supply potential extV higher than _CC Super H level (intV _CC + 3V _th higher level than) a pull-up circuit 1612af give (a ₀ -3 V _th is the internal power supply potential intV _CC more potential) H level detection signal output node 1612Ab H-level potential to, Sue A load circuit 1612ah which is connected between H-level detection signal output node 1612ab and ground potential node 100b and which has an n-channel MOS transistor 1612ag whose gate is connected to internal power supply potential node 100c and which is always on; When the address signal A ₀ is at the super H level, the super H level detection signal SD ₀ is set at the H level.

The n-channel MOS transistor 1612ag starts from the address pin 1612aa so that the super H level detection signal SD ₀ becomes intV _CC (internal H level) when the address signal A ₀ is intV _CC + 3V _th (included in the super H level). Compared with the current supplied to the super H level detection signal output node 1612ab via the pull-up circuit 1612af, the current flowing from the super H level detection signal output node 1612ab to the ground potential node 100b via the load circuit 1612ah can be ignored. In order to reduce the ratio, the ratio W / L of the channel width W to the channel length L is made sufficiently smaller than the ratio of the channel width to the channel length of the n-channel MOS transistors 1612ac, 1612ad and 1612ae in the pull-up circuit 1612af. Since n channel MOS transistor 1612ag is always in a conductive state, super H level detection circuit 1612a consumes power by flowing current from address pin 1612aa to ground potential node 100b when address signal A ₀ exceeds 3V _th. To do.

1612b is configured in the same manner as the super H level detection circuit 1612a, and outputs a super H level detection signal SD ₁ which becomes H level when the address signal A ₁ applied to the address pin 1612ba is at the super H level. Thus, a pull-up circuit 1612bf having n-channel MOS transistors 1612bc, 1612bd and 1612be and a load circuit 1612bh having an n-channel MOS transistor 1612bg are provided.

1612c receives timing detection signals / TDA, TDB, TDC, super H level detection signals SD ₀ and SD ₁ and row address signals RA ₀ and RA ₁ , and address signal A ₀ is super H level (hereinafter referred to as S level). A ₁ is set to the normal H level, S level detection signals SD ₀ , SD ₁ row address signals / RA ₀ and / RA ₁ become H level, L level, L level and L level, respectively, and row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at the WCBR timing, timing detection signal TDB becomes H level for a predetermined period, / TDA becomes L level, and TDC becomes L level when TDC becomes H level. Test group detection signal / TGA and address signal A ₀ are set to H level, A ₁ is set to S level, and S level detection signals SD ₀ and SD ₁ row address signals / RA ₀ and / RA ₁ are set to L level and H, respectively. Level, L level and L level, row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at WCBR timing, timing detection signal TDB is at H level for a predetermined period, and / TDA is This is a test group detection signal generation circuit that outputs a test group detection signal / TGB that becomes L level and becomes L level when TDC becomes H level.

The test group detection signal generation circuit 1612c receives the super H level detection signals SD ₀ and SD ₁ and the row address signals / RA ₀ and / RA ₁ and receives the test group detection auxiliary signal SV ₀ corresponding to the address signals A ₀ and A _1. , HV ₀ , SV ₁ , HV ₁ output test group detection auxiliary circuit 1612ca, test group detection auxiliary signal SV ₀ , HV ₀ , SV ₁ , HV ₁ and timing detection signal TDC And a test group detection signal control circuit 1612cb for outputting / TGB. The test group detection auxiliary circuit 1612ca is an inverter 1612cc, a clocked inverter 1612cd, a NOR circuit 1612ce, an inverter 1612cf, a NOR circuit 1612cg, a clocked inverter 1612ch, a NOR circuit 1612ci, an inverter 1612cj, a clocked inverter 1612ck, a NOR circuit 1612cm, an inverter 1612Cn, NOR circuit 1612Cp, clocked inverter 1612Cq, has a NOR circuit 1612cr and inverter 1612Cs, address signals a ₀ and a ₁ are the S and H levels, respectively, a row address strobe signal / RAS, a column address strobe signal / When CAS and write enable signal / WE are input at WCBR timing, test group detection auxiliary signals SV ₀ , HV ₀ , SV ₁ and HV ₁ are set to H level, L level, L level and H level, respectively, and address signal A test glue when ₀ and a ₁ is at H level and S levels, respectively Detection assisting signals SV _0, HV _0, SV ₁ and HV ₁ respectively L level, the H level, H level and L level.

Further, the test group detection signal control circuit 1612cb includes NAND circuits 1612ct and 1612cu, the test group detection auxiliary signals SV ₀ , HV ₀ , SV ₁ and HV ₁ are address signals A ₀ and A ₁ are S level and H level, H level, L level, L level and H level indicating that row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at WCBR timing, and When the timing detection signal TDC is at the H level, the test group detection signals / TGA and / TGB are set to the address signals A ₀ and A ₁ respectively to the S level and the H level, and the row address strobe signal / RAS, the column address strobe signal / CAS and write enable signal / WE are set to L level and H level to indicate that they are input at WCBR timing. Preparative group detection assisting signals SV _0, HV _0, SV ₁ and HV ₁ is, the address signals A ₀ and A ₁ are the H level and S level, the row address strobe signal / RAS, a column address strobe signal / CAS and write When the enable signal / WE becomes L level, H level, H level and L level indicating that it is input at WCBR timing, and the timing detection signal TDC is at H level, the test group detection signals / TGA and / TGB are Address signals A ₀ and A ₁ are set to H level and L level, respectively, and H address indicating that row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at WCBR timing, and Set to L level.

Figure 7 is a block diagram illustrating a test mode setting signal generating circuit 1620 shown in FIG. 4, 7 1621 timing detection signal / TDA, TDB and the row address signal _{/ RA 2, ···, / RA} 6 In response, the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are input at the WCBR timing, the timing detection signal / TDA becomes L level, and the timing detection signal TDB becomes H level for a predetermined period. row address signal / RA ₂ during which, ..., / RA ₆ takes in the row address signal _{/ RA 2, ···, / RA} 6 and address key signal AK ₂ logic is inverted, ... , AK ₆ and address key signal / AK ₂ ,..., / AK ₆ of the same logic are output, and when the timing detection signal TDB becomes L level, the row address strobe signal / RAS, the column address strobe signal / CAS and the write enable The address key signals AK ₂ ,..., AK ₆ , / AK ₂ ,... Until the signal / WE is input at the reset timing of CBR refresh timing or ROR timing and the timing detection signal / TDA rises to H level. , / AK ₆ is an address key latch circuit (FIG. 8).

1622 receives address key signals AK ₂ ,..., AK ₆ , / AK ₂ ,..., / AK ₆ , and the address key predecode signals AK ₂ AK ₃ , AK _{2. AK 3, / AK 2 · AK} 3, / AK 2 · / AK 3, AK 4 · AK 5, AK 4 · / AK 5, / AK 4 · AK 5, an address key for outputting / AK ₄ · / AK ₅ predecoder (Fig. 9), 1623 address key predecoded signals _{AK 2 · AK 3, AK 2} · / AK 3, / AK 2 · AK 3, / AK 2 · / AK 3, AK 4 · AK 5, AK 4 _{· / AK 5, / AK 4} · AK 5, / AK 4 · / AK 5, address key signal AK _6, receiving the test group detection signal / TGA, / TGB and timing detection signal TDC, the address corresponding to these signals key decode signal AKD _0, · · ·, address key main decoder for outputting AKD ₇ (FIG. 10), 1624 address key decoded signal AKD _0, · · ·, undergo AKD _7, the address key decoded signal AKD _0, ... Test mode setting signals TE, TEST1, TEST2, TEST3, TEST4, TEST5, T according to AKD ₇ This is a buffer (FIG. 11) for outputting EST6N, TEST6S, and TEST7.

  FIG. 8 is a specific circuit diagram showing the address key latch circuit 1621. The address key latch circuit 1621 includes an inverter 1621a, an inverter 1621bc that constitutes a latch circuit with a clocked inverter 1621ba, a NOR circuit 1621bb, a NOR circuit 1621bb, and an inverter. Partial latch circuit 1621b having 1621bd, clocked inverter 1621ca, NOR circuit 1621cb, NOR circuit 1621cb constitutes a latch circuit, inverter 1621cc, partial latch circuit 1621c having inverter 1621cd, clocked inverter 1621da, NOR circuit 1621db , An inverter 1621dc that forms a latch circuit with the NOR circuit 1621db, and a partial latch circuit 1621d that has an inverter 1621dd, an inverter 1621ec that forms a latch circuit with the clocked inverter 1621ea, the NOR circuit 1621eb, and the NOR circuit 1621eb, and an inverter 1621ed A partial latch circuit 1621e having a clocked inverter 1 621fa, a NOR circuit 1621fb, and an NOR circuit 1621fb constitute an inverter 1621fc that constitutes a latch circuit, and a partial latch circuit 1621f having an inverter 1621fd.

FIG. 9 is a specific circuit diagram showing the address key predecoder 1622. The address key predecoder 1622 includes NOR circuits 1622a, 1622b, 1622c, 1622d, 1622e, 1622f, 1622g, and 1622h. By latching the two-phase address key signals AK _i and / AK _i in this way, only one NOR circuit can output one address key predecode signal. Figure 10 is a specific circuit diagram showing an address key main decoder 1623, the address key main decoder 1623 timing detection signal TDC, the test group detection signal / TGA, / TGB and receives the address key signal AK _6, address key decoded signal Partial decoder 1623a that outputs AKD ₀ , address key predecode signals AK ₂・ AK ₃ , / AK ₂・ AK ₃ , AK ₄・ / AK ₅ , AK ₂・ / AK ₃ , / AK ₄・ AK ₅ and test Address group pre-decode signals AK ₂・ AK ₃ , / AK ₂・ AK ₃ , AK ₄・ / AK ₅ , AK ₂・ / AK ₃ , / AK ₄・ AK ₅ Address key decode signals AKD ₆ , AKD ₄ , AKD ₇ , AKD ₃ , AKD ₅ , partial decoder 1623b and address key predecode signals AK ₂ AK ₃ , AK ₂ ./AK ₃ , / AK ₂ AK ₃ and organic and partial decoder 1623c which receives the test group detection signal / TGB outputs address key decoded signals AKD _1, AKD ₂ That.

A portion decoder 1623a inverter 1623Aa, NAND circuit 1623Ab, NOR circuit 1623Ac, inverter 1623Ad, NAND circuit 1623Ae, has a NAND circuit 1623af and NAND circuit 1623Ag, one of the address signals A ₀ and A ₁ is the other is S level The row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are input at the WCBR timing (JEDEC standard multi-bit test mode set timing) except when the signal is at the H level. When both TGA and / TGB are set to H level and timing detection signal TDC is set to H level, or one of address signals A ₀ and A ₁ is set to S level and the other is set to H level, row address strobe signal / RAS Column address strobe signal / CAS and write enable signal / WE are WCBR timing (special test mode set type Entered in ring), this time H level is applied as an address signal A _6, the one of the test group detection signal / TGA, / TGB is the L level, the timing address key signal AK ₆ is the H level when the detection signal TDC is the H level, the address key decoded signal AKD ₀ H level.

Partial decoder 1623b inverter 1623ba, 1623bb, 1623bc, 1623bd, 1623be and NOR circuit 1623bf, 1623bg, 1623bh, 1623bi, have 1623Bj, the address signals A ₀ and A ₁ is the S and H levels, respectively, a row address strobe When signal / RAS, column address strobe signal / CAS and write enable signal / WE are input at the WCBR timing (special test mode set timing) and test group detection signal / TGA is set to L level, address key decode signal AKD ₆ , AKD ₄ , AKD ₇ , AKD ₃ , AKD ₅ out of 5 address key predecode signals AK ₂・ AK ₃ , / AK ₂・ AK ₃ , AK ₄・ / AK ₅ , AK ₂・ / AK ₃ , The signal corresponding to the address key predecode signal which has become H level according to the address signals A ₂ ,..., A ₅ in / AK ₄ and AK ₅ is set to H level.

Partial decoder 1623c is NOR circuit 1623ca, 1623cb, 1623cc, have 1623Cd, address signals A ₀ and A ₁ is the H level and S levels respectively row address strobe signal / RAS, a column address strobe signal / CAS and write enable When the signal / WE is input at the timing of WCBR (special test mode set timing) and the test group detection signal / TGB is set to L level, the address signals A ₂ and A ₃ supplied at this time are both H level. in address key predecoded signals _{AK 2 · AK 3, AK 2} · / AK 3, / AK 2 · AK 3 is H level, L level, when at the L level address key decoded signals AKD ₁ and AKD ₂ together H Address signal A ₂ and A ₃ are H level and L level, respectively, and address key predecode signals AK ₂ , AK ₃ , AK ₂ , / AK ₃ , / AK ₂ , AK ₃ are respectively L level and H level. Le, if it is L level address key decoded signals AKD ₁ and AKD ₂ and H level and L level, respectively, the address signal A ₂ and A ₃ address key is L level and H level, respectively predecode signals AK ₂ · AK ₃ , AK ₂ ./AK ₃ , / AK ₂ .AK ₃ are at L level, L level, and H level, respectively, the address key decode signals AKD ₁ and AKD ₂ are set to L level and H level, respectively, and the address signal A ₂ and If both A ₃ are L level and address key predecode signals AK ₂ AK ₃ , AK ₂ ./AK ₃ , / AK ₂ AK ₃ are both L level, both address key decode signals AKD ₁ and AKD ₂ are L. Level.

  FIG. 11 is a specific circuit diagram showing the buffer 1624. The buffer 1624 has an inverter 1624a, an inverter 1624b having a larger current driving capability than the inverter 1624a, an inverter 1624c, and a larger current driving capability than the inverter 1624c. Inverter 1624d, Inverter 1624e, Inverter 1624f with greater current drive capability than this inverter 1624e, Inverter 1624g, Inverter 1624h with greater current drive capability than this inverter 1624g, Inverter 1624i, Current greater than this inverter 1624i Inverter 1624j having a large driving capability, inverter 1624k, inverter 1624m having a larger current driving capability than this inverter 1624k, inverter 1624n, inverters 1624p and 1624q having a larger current driving capability than this inverter 1624n, and inverter 1624r, Current drive than this inverter 1624r And a force large inverter 1624s. In this way, by increasing the current drive capability in the subsequent inverter, the wiring for transmitting the test mode setting signals TE, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6N, TEST6S, and TEST7 can be quickly charged and discharged.

FIG. 12 is a simplified plan view showing the layout of the DRAM on the semiconductor chip. In the figure, 10 is the semiconductor chip, 11 is located at the center of the short side of the semiconductor chip 10 and extends in the long side direction. The control signal such as the address signal A _i and the row address strobe signal ext / RAS is input to the semiconductor chip 10 through the pad 11 with 24 pads arranged in the long side direction on the chip central band 12 to be processed. , exchange data D _r is also performed via the pad 11. 13a is a test mode setting signal wiring that transmits the multi-bit test mode setting signal TE output from the test mode setting circuit 1600, and 13b is a test mode setting signal that transmits the test mode setting signal TEST1 output from the test mode setting circuit 1600. Wiring, 13c is a test mode setting signal wiring that transmits a test mode setting signal TEST2 output from the test mode setting circuit 1600, and 13d is a test mode setting signal that transmits a test mode setting signal TEST3 output from the test mode setting circuit 1600 Wiring, 13e is a test mode setting signal wiring that transmits a test mode setting signal TEST4 output from the test mode setting circuit 1600, and 13f is a test mode setting signal that transmits a test mode setting signal TEST5 output from the test mode setting circuit 1600 Wiring, 13g is test mode setting output from test mode setting circuit 1600 Test mode setting signal wiring that transmits signal TEST6N, 13h is a test mode setting signal wiring that transmits test mode setting signal TEST6S output from test mode setting circuit 1600, and 13i is a test mode setting that is output from test mode setting circuit 1600 This is a test mode setting signal wiring for transmitting the signal TEST7.

14 includes the reference potential generation circuit 111, the regulator 114, and the stress mode circuit 115 shown in FIG. 3, and the reference potential V _ref output from the internal circuit 117 disposed on the S (South) side of the semiconductor chip 10 is obtained. A reference potential wiring for transmitting to the internal circuit 116 disposed on the N (North) side of the semiconductor chip 10, having a regulator 112 and a stress mode circuit 113, and this reference on the S side of the test mode setting circuit 1600 The potential wiring 14 is provided adjacent to and in parallel with the test mode setting signal wiring 13f and the test mode setting signal wiring 13h. On the N side of the test mode setting circuit 1600, the test mode setting signal wiring 13g and the test mode setting signal are provided. It is provided adjacent to and parallel to the wiring 13i. As described above, by making the test mode setting signal wiring whose potential is fixed at the L level in normal use adjacent to the reference potential wiring 14, it is difficult for noise to be applied to the reference potential wiring 14, and the stable reference potential V in normal use. _Ref can be transmitted. Needless to say, the same is possible even when the test mode setting signal wiring is fixed at the H level during normal use.

The boosted potential generation circuit 120 is provided on the N side of the semiconductor chip 10 and receives the test mode setting signal TEST7 from the test mode setting circuit 1600 via the test mode setting signal wiring 13i, and is output when the test mode setting signal TEST7 becomes H level. (If, for example typically a V _PP = intV _CC + 2BST, the intV _CC + BST when TEST = H) was as boost level is lowered to the internal power supply potential intV _CC boosted potential V _PP to have been. The cell plate potential generation circuit 130 is provided on the S side of the semiconductor chip 10 and receives the test mode setting signal TEST5 from the test mode setting circuit 1600 via the test mode setting signal wiring 13f, and when the test mode setting signal TEST5 becomes H level. The cell plate potential V _CP is increased from the normal (1/2) intV _CC to intV _CC .

The internal circuit 410 included in the row predecoder 400 receives the test mode setting signal TEST4 via the test mode setting signal wiring 13e, and when the test mode setting signal TEST4 becomes H level, more BS _j than usual is received. At a high level, more memory cell blocks 511 than normal are selected so that a word line rises (disturb test mode). Besides receiving the test mode setting signal TEST4 through the test mode setting signal line 13e, when the test mode setting signal TEST4 becomes H level, 4 bits of data from the 128-bit by the data selection signal DS _n from column decoder 1000 Multi-bit test circuit 1120 for performing a multi-bit test mode in which the same data is simultaneously written to 128 bits before is selected, or whether the 128-bit data is the same data and the determination result is output to the pad 11, Each receives test mode setting signals TEST1, TEST2, and TEST3 via test mode setting signal wirings 13b, 13c, and 13d, and when the test mode setting signals TEST1, TEST2, and TEST3 are at H level, each predetermined test operation is performed. Circuits 1130, 1140 and 1150 are provided.

  Reference numeral 510 denotes a memory mat, which is provided in a total of four, two across the chip central band 12, and each is divided into 16 memory cell blocks 511 by 17 sense amplifier blocks 1110. The row decoder 600 is provided on the chip center band 12 side of each memory mat 510 and has a row decoder block 610 provided corresponding to each memory cell block 511. A column decoder 1000 is provided for each memory mat 510 and has one column decoder block 1010 provided corresponding to a column block including 128 pairs of bit lines (not shown).

  FIG. 13 is a simplified cross-sectional view of a portion where the test mode setting signal wirings 13f and 13h and the reference potential wiring 14 are arranged in parallel. In the figure, 10a is a semiconductor substrate, 10b is an insulating film, 10c is a wiring formed of a first metal layer (for example, an aluminum layer or a tungsten layer) on the insulating film 10b, and 10d is an interlayer insulating film formed on the wiring 10c. In the film, the test mode setting signal wirings 13f and 13h and the reference potential wiring 14 are formed of a second metal layer (for example, an aluminum layer or a tungsten layer) on the insulating film 10d. Reference numeral 10e denotes an insulating film formed on the test mode setting signal wirings 13f and 13h and the reference potential wiring 14.

Next, the operation of the test mode setting circuit 1600 will be described based on the timing charts of FIGS. FIG. 14 is a timing diagram showing the operation when the timing detection circuit 1611 shown in FIG. 5 is set to the test mode at the WCBR timing and reset to the test mode at the CBR refresh timing. First, the timing detection signal before time t ₀ / TDA, TDB, and TDC are reset to H level, L level, and L level, respectively, as shown in (p), (q), and (r) of FIG. When the write enable signal / WE is set to the L level at time t ₀ as shown in FIG. 14C, the WBR detection signal / WBR output from the WBR detection circuit 1611c in the timing detection circuit 1611 is as shown in FIG. of the L level as shown in (d), the column address strobe signal / CAS is the L level at time t ₁ as shown in (b) of FIG. 14, the CBR detection circuit 1611d in the timing detection circuit 1611 CBR detection signal / CBR output becomes L level as shown in (e) of FIG. 14, when the row address strobe signal / RAS is at the L level at time t ₂ as shown in FIG. 14 (a) The WBR detection signal / WBR and the CBR detection signal / CBR are both latched and held at the L level.

  On the other hand, at this time, the WCBR timing detection signal WCBR output from the WCBR timing detection circuit 1611e is at the L level as shown in FIG. 14 (g), and is output from the set / reset circuit 1611i that receives this WCBR timing detection signal WCBR. The timing detection signal TDA to be output is also in the state reset to the L level as shown in FIG. 14 (k), and the timing detection latch signal LTDA output from the timing detection signal latch circuit 1611j is (n) in FIG. ) And is held at the L level. Therefore, the timing detection signal TDC output from the timing detection signal generation circuit 1611m remains at the L level as shown in (r) of FIG.

When the delay signal D / RAS of the row address strobe signal / RAS falls to L level at time t ₃ as shown in (f) of FIG. 14, WCBR timing detection signal WCBR output from WCBR timing detection circuit 1611e is As shown in FIG. 14 (g), it becomes H level, and the timing detection signal TDA output from the set / reset circuit 1611i is set to H level as shown in FIG. 14 (k). The timing detection signal / TDA inverted by the timing detection signal generation circuit 1611m becomes L level as shown in FIG. 14 (p). Then, the pulse signal PLS is a row address strobe signal / RAS is at the L level as shown in (m) in FIG. 14 at time t ₄ when a predetermined time has elapsed from the time t ₂ which is changed to the L level output from the pulse generating circuit 1611k When it becomes L level for a predetermined period until time t ₅ , the timing detection signal TDB output from the timing detection signal generation circuit 1611m becomes H level as shown in (q) of FIG. 14 during this predetermined period.

Then, the write enable signal / RAS is at time t _6, as shown in FIG. 14 (c) to the H level, the column address strobe signal / CAS is at H level at time t ₇ as shown in (b) of FIG. 14 is a, the row address strobe signal / RAS is set to H level at time t ₈ as shown in (c) of FIG. 14, WCBR timing detection signal WCBR output from WCBR timing detection circuit 1611e is 14 ( It becomes L level as shown in g). However, the timing detection signal TDA output from the set / reset circuit 1611i that receives the WCBR timing detection signal WCBR has the reset timing detection signal / RST output from the reset timing detection circuit 1611f as shown in FIG. Since it remains at the H level, it remains latched at the H level as shown in (k) of FIG. 14, and therefore the timing detection signal / TDA also remains at the L level as shown in (p) of FIG.

When the delay signal D / RAS of the row address strobe signal / RAS is at the H level at time t _9, as shown in (f) of FIG. 14, WBR detection signal / WBR output from WBR detection circuit 1611c Figure 14 As shown in (d) of FIG. 14, the latch is released and changes to the H level, and the CBR detection signal / CBR output from the CBR detection circuit 1611d is released from the latch as shown in (e) of FIG. To change. The timing detection latch signal LTDA output from the timing detection signal latch circuit 1611j is released from the latch and changes to the H level as shown in (n) of FIG. 14, and the timing detection signal receiving the timing detection latch signal LTDA. The timing detection signal TDC output from the generation circuit 1611m changes to the H level as shown in (r) of FIG. In this way, the test mode is set at the WCBR timing.

Next, when the column address strobe signal / CAS is the L level at time t ₁₀ as shown in (b) of FIG. 14, the CBR detection signal / CBR Figure 14 outputted from the CBR detection circuit 1611d (e the L level as shown in), when the row address strobe signal / RAS is at the L level at time t ₁₁ as shown in (a) of FIG. 14, WBR detection signal / WBR and CBR detection signal / CBR both Latched to hold H level and L level, respectively. On the other hand, the timing detection signal TDA output from the set / reset circuit 1611i is latched at the H level as shown in (k) of FIG. 14, and is output from the timing detection signal latch circuit 1611j. The timing detection latch signal LTDA is latched as shown in (n) of FIG. 14, and holds the H level. Accordingly, the timing detection signal TDC output from the timing detection signal generation circuit 1611m remains at the H level as shown in (r) of FIG.

The delay signal D / RAS of the row address strobe signal / RAS falls to an L level at time t ₁₂ as shown in (f) of FIG. 14, the pulse signal PLS is from time t ₁₃ as shown in (m) in FIG. 14 It becomes L level during the period of time of time t _14. Then, a column address strobe signal / CAS is set to the H level at time t ₁₅ as shown in (b) of FIG. 14, H row address strobe signal / RAS is at time t ₁₆ as shown in FIG. 14 (a) When the level is reached, the CBR refresh timing detection signal CBRR output from the CBR refresh timing detection circuit 1611g in the reset timing detection circuit 1611f changes to the H level as shown in FIG. 14 (h), and the reset timing detection circuit 1611f The reset timing detection signal / RST output from is changed to L level as shown in (j) of FIG.

The timing detection signal TDA output from the set / reset circuit 1611i that receives the reset timing detection signal / RST is reset to the L level and output from the timing detection signal generation circuit 1611m as shown in (k) of FIG. The timing detection signal / TDA changes to the H level as shown in FIG. When the delay signal D / RAS of the row address strobe signal / RAS is changed to the H level at time t ₁₇ as shown in (f) of FIG. 14, CBR refresh timing detection signal output from the CBR refresh timing detecting circuit 1611g As shown in FIG. 14 (h), CBRR changes to L level, and the reset timing detection signal / RST output from the reset timing detection circuit 1611f changes to H level.

  Further, the CBR detection signal / CBR output from the CBR detection circuit 1611d is released from the latch and changes to the H level as shown in FIG. 14 (e). Further, the timing detection latch signal LTDA output from the timing detection signal latch circuit 1611j is unlatched and changed to the L level as shown in (n) of FIG. 14, and generates a timing detection signal that receives this timing detection latch signal LTDA. The timing detection signal TDC output from the circuit 1611m changes to the L level as shown in (r) of FIG. In this way, the test mode is reset at the CBR refresh timing.

FIG. 15 is a timing chart showing the operation when the test mode is set at the WCBR timing and the test mode is reset at the ROR timing. The timing chart until the time t ₉ when the test mode is set at the WCBR timing is the same as the timing chart of FIG. is there. Time t ₉ differs from the timing chart of FIG. 14 or later, column address strobe signal / CAS Sarezu is the L level, that CBR detection signal / CBR does not become L level, and at time t ₁₆ the row address strobe signal / When RAS is set to the H level, the CBR refresh timing detection signal CBRR output from the CBR refresh timing detection circuit 1611g does not become the H level, and the ROR timing detection signal ROR output from the ROR timing detection circuit 1611h is shown in FIG. As shown in (i), the reset timing detection signal / RST output from the reset timing detection circuit 1611f changes to the L level as shown in (j) of FIG. In this way, the test mode can be similarly reset at the CBR refresh timing or the ROR timing.

FIG. 16 is a timing diagram showing the operation when setting the multi-bit test mode standardized by JEDEC. First, the address signals A ₀ and A ₁ are converted to normal H as shown in (g) and (h) of FIG. Set to level or L level, and input row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE at WCBR timing as shown in (a), (b) and (c) of FIG. Then, as described based on FIG. 13, the timing detection signals / TDA, TDB, and TDC change as shown in (d), (e), and (f) of FIG.

Also, the test group detection signals / TGA and / TGB output from the test group detection signal generation circuit 1612c in the test group detection circuit 1612 are both at the H level as shown in (j) and (k) of FIG. When the timing detection signal TDC becomes H level at time t _9, as shown in (f) of FIG. 16, both output from the partial decoder 1623a in the address key main decoder 1623 for receiving a test group detection signals / TGA and / TGB the H level addressed key decoded signal AKD ₀ is becomes H level, the multi-bit test mode setting signal TE output from the buffer 1624 is activated to H level as shown in (m) in FIG. 16. The multi-bit test mode setting signal TE is reset to the L level by inputting a CBR refresh timing or an ROR timing, which is not shown here.

FIG. 17 is a timing diagram showing the operation when both the special test mode (here stress test mode) not standardized by JEDEC and the multi-bit test mode are set. First, the address signals A ₀ and A ₁ are set as shown in FIG. As shown in (g) and (h), the address signals A ₂ ,..., A ₆ are respectively at the H level, H level, and L level as shown in (i) of FIG. The row address strobe signal / RAS, the column address strobe signal / CAS and the write enable signal / WE are set to the WCBR timing as shown in FIGS. 17 (a), (b) and (c). As described with reference to FIG. 14, the timing detection signals / TDA, TDB, and TDC change as shown in (d), (e), and (f) of FIG. 17, respectively.

Then, when the timing detection signal TDC is changed to H level at time t _9, as shown in (f) of FIG. 17, the test group detection signal / TGA outputted from the test group detection signal generation circuit 1612c in the test group detection circuit 1612 Is at the L level as shown in (j) of FIG. 17, and the address signals A ₂ ,..., A ₆ are changed to H level, H level, L level, L level, respectively, as shown in (i) of FIG. since the H level, the level address key signal AK ₆ is H, address key predecoded signals AK ₂ · AK ₃ output from the address key predecoder _{1622, / AK 2 · AK 3} , AK 4 · / AK 5, AK ₂ · / AK ₃ , / AK ₄ · AK ₅ are H level, L level, L level, L level, and L level, respectively, so that the address key decode output from the partial decoder 1623a in the address key main decoder 1623 signal AKD ₀ becomes H level Will address key decoded signals AKD ₆ outputted from the partial decoder 1623b is the H level, setting a multi-bit test mode is outputted from the buffer 1624 signal TE and stress test mode TEST6N, TEST6S is, respectively, in FIG 17 (m) and (n) As shown in FIG.

Thus, not only it can be set in the multi-bit test mode JEDEC standard, so that it is set in the multi-bit test mode with that in the special test mode to keep the address signal A ₆ to H level. In addition, when setting the special test mode, _one of the address signals A ₀ and A ₁ must be set to the S level and the other must be set to the H level. It is not set to. The test mode is reset by inputting a CBR refresh timing or an ROR timing although not shown here.

FIG. 18 shows an address key indicating which test mode setting signal is activated to H level according to the state (address key) of the address signals A ₀ ,..., A ₆ when the WCBR timing is input. In the correspondence table with the test mode, S in the figure indicates an S level, H indicates an H level, L indicates an L level, and * indicates an H level or an L level. The reason why the test mode setting signals TEST1 and TEST2 are set to the H level by the independent setting key is that the special test mode setting signals other than the test mode setting signals TEST1 and TEST2 are simultaneously set to the H level. Of course, the present invention is not limited to this combination of address keys, and a circuit may be formed by freely determining combinations of address keys.

  As described above, in the first embodiment, not only can the multi-bit test mode standardized by JEDEC be set, but also the multi-bit test mode can be set together with the special test mode, so that the test time required for the special test can be shortened. it can.

In order to set the special test mode, _one of the address signals A ₀ and A ₁ must be set to the S level and the other must be set to the H level. Is not set incorrectly.

The load circuit 1612ah to be kept connected, super H level detection circuit 1612a having 1612Bh, simply by providing 1612b to the address signals A _0, A _1, each address signal A _2, · · ·, to A ₆ However, since the special test mode can be set with the address keys A ₂ ,..., A ₆ after that, power consumption is reduced, and an increase in circuit area is also suppressed.

Also, after the test group detection auxiliary signals SV ₀ , HV ₀ , SV ₁ , HV ₁ are determined, the timing detection signal TDC becomes H level and the test group detection signals / TGA, / TGB change to L level. Therefore, misconfiguration is suppressed.

  Furthermore, since the test mode setting signal is held by latching the address key signal and is not latched by the subsequent buffer 1624 or the like, a latch circuit can be configured with a small logic gate having a small current driving capability. Thus, the area of the test mode setting circuit 1600 can be reduced.

(Example 2)
Next, a DRAM according to a second embodiment of the present invention will be described with reference to FIGS. The difference between the DRAM of the second embodiment and the DRAM of the first embodiment is the difference in the layout of the test mode setting signal generation circuit 1620 in the test mode setting circuit 1600 and the layout. This difference will be described below.

FIG. 19 is a block diagram showing a test mode setting signal generation circuit 1620 in the DRAM test mode setting circuit 1600 of the second embodiment. This test mode setting signal generation circuit 1620 is the test of the first embodiment shown in FIG. The difference from mode setting signal generator circuit 1620 is that the configuration of buffer 1624 (Fig. 20) is different. It receives six address key decode signals AKD ₁ , AKD ₂ , AKD ₃ , AKD ₄ , AKD ₆ and AKD ₇ Encoding signal generation circuit for outputting three test mode encode signals TEN ₀ , TEN ₁ and TEN ₂ corresponding to the address key decode signals AKD ₁ , AKD ₂ , AKD ₃ , AKD ₄ , AKD ₆ and AKD ₇ 1625 (Fig. 21) is newly provided, and seven test mode setting signals TEST1, TEST2, TEST3, TEST4, and TEST6N are received in response to the three test mode encode signals TEN ₀ , TEN ₁ and TEN ₂ , TEST7 and TEST6S output test Mode decode circuit group 1626 is that newly provided (Figure 22).

FIG. 20 is a circuit diagram showing a buffer 1624 in the DRAM test mode setting circuit 1600 of the second embodiment. The buffer 1624 is different from the buffer 1624 in the first embodiment shown in FIG. Inverters 1624a and 1624b that receive AKD ₀ and output multi-bit test mode setting signal TE, and inverters 1624k and 1624m that receive address key decode signal AKD ₅ and output test mode setting signal TEST5, leave other inverters Excluded points.

FIG. 21 is a circuit diagram showing an encode signal generating circuit 1625 in the DRAM test mode setting circuit 1600 of the second embodiment. The encode signal generating circuit 1625 is an address key decode signal AKD ₆ , AKD ₃ , AKD ₁ , AKD. ₂ when the address key decode signal AKD ₆ is at H level, the address key decode signal AKD ₃ is at H level, or the address key decode signals AKD ₁ and AKD ₂ are at H level and L level, respectively. a partial encoding circuit 1625a which outputs a test mode encoded signals TEN ₀ consisting receives an address key decoded signals _{AKD 6, AKD 4, AKD 2} , AKD 1, when the address key decoded signal AKD ₆ is H level, the address key decoded signal when AKD ₄ is at the H level, or the address key decoded signals AKD ₂ and AKD ₁ is H level when the H-level and L level, respectively A partial encoding circuit 1625b which outputs a strike mode encoded signal TEN _1, address key decoded signals _{AKD 6, AKD 7, AKD 3} , receives the _{AKD 4, AKD 1, AKD 2} , address key decoded signals AKD ₆ and AKD _7, respectively A test mode encode signal that becomes H level when at least one of address key decode signals AKD ₃ and AKD ₄ is at H level when H level and L level, or when both of address key decode signals AKD ₁ and AKD ₂ are at H level A partial encoding circuit 1625c for outputting TEN ₂ .

  The partial encoding circuit 1625a includes inverters 1625aa, 1625ab, 1625ac, a NAND circuit 1625ad, a NAND circuit 1625ae, and inverters 1625af and 1625ag. The partial encoding circuit 1625b includes inverters 1625ba, 1625bb, 1625bc, a NAND circuit 1625bd, a NAND circuit 1625be, and inverters 1625bf and 1625bg. Further, the partial encoding circuit 1625b includes an inverter 1625ca, a NAND circuit 1625cb, a NOR circuit 1625cc, a NAND circuit 1625cd, a NAND circuit 1625ce, and inverters 1625cf and 1625cg.

FIG. 22 is a circuit diagram showing a test mode decode circuit group 1626 in the test mode setting circuit 1600 of the DRAM of the second embodiment. The test mode decode circuit group 1626 includes three test mode encode signals TEN ₀ , TEN ₁ , TEN. ₂ and 6 test mode setting signals TEST3, TEST4, TEST1, TEST2 that are larger than the test mode encode signals TEN ₀ , TEN ₁ , TEN ₂ according to the test mode encode signals TEN ₀ , TEN ₁ , TEN ₂ , TEST6N, TEST7 are output, and this test mode encode is received by receiving the test mode decode circuit 1626a arranged on the N side of the semiconductor chip from the encode signal generating circuit 1625 and the test mode encode signals TEN ₀ , TEN ₁ , TEN ₂ When the signals TEN ₀ , TEN ₁ , and TEN ₂ are both at the H level, the test mode setting signal TEST6S that becomes the H level is output, and the test mode decoding circuit 16 having the NAND circuit 1626ba and the inverter 1626bb is output. 26b.

Test mode decode circuit 1626a the test mode encoded signals TEN _0, TEN _1, TEN ₂ receiving, comprising the test mode encoded signals TEN _0, TEN ₁ and TEN ₂ is H level, respectively, if it is L level and H level and H level Test mode setting signal TEST3, test mode encoding signals TEN ₀ , TEN ₁ and TEN ₂ are at L level, H level and H level, respectively, test mode setting signal TEST4 and test mode encoding signals TEN ₀ , TEN ₁ And TEN ₂ are H level, L level and L level, respectively, and H level and L level, respectively, and test mode encode signals TEN ₀ , TEN ₁ and TEN ₂ are respectively L level, H level and L level, respectively. the L level and H level, the test mode encoded signals TEN _0, TEN ₁ and TEN ₂ is L level, respectively A local test mode decode circuit 1626c which outputs a test mode setting signal TEST1 and TEST2 at H level as well as a L-level and H-level, the test mode encoded signals TEN _0, TEN _1, TEN ₂ receiving the test mode encoded signals TEN ₀ , TEN ₁ and TEN ₂ are both H level, the test mode setting signal TEST6N which becomes H level, and the test mode encoding signals TEN ₀ , TEN ₁ and TEN ₂ are H level, H level and L level, respectively And a local test mode decode circuit 1626d for outputting a test mode setting signal TEST7 which becomes H level.

The local test mode decode circuit 1626c includes an inverter 1626ca, a NAND circuit 1626ab, an inverter 1626cc, an inverter 1626cd, a NAND circuit 1626ce, an inverter 1626cf, an inverter 1626cg, 1626ch, 1626ci, 1626cj, 1626ck, 1626cm, 1626cn, 1626cp, 1626cq, NAND Circuits 1626cr, 1626cs, 1626ct and NAND circuits 1626cu, 1626cv are provided. The local test mode decode circuit 1626d includes a NAND circuit 1626da, inverters 1626db and 1626dc, a NAND circuit 1626dd, and an inverter 1626de. Here, inverters 1626cg and 1626ch constitute delay circuit 1626cw, inverters 1626cm and 1626cn constitute delay circuit 1626cx, and inverters 1626cp and 1626cq constitute delay circuit 1626cy. The test mode encode signals TEN ₀ , TEN ₁ , TEN ₂ are not input directly, but are input via the delay circuits 1626cw, 1626cx, 1626cy because the clock skew of the test mode encode signals TEN ₀ , TEN ₁ , TEN ₂ is NAND This is to prevent whisker-like pulses from the circuits 1626cr, 1626cs, 1626ct.

FIG. 23 is a simplified plan view showing the layout on the semiconductor chip of the DRAM of the second embodiment. In FIG. 23, reference numeral 15 denotes a state detection circuit 1610 in the test mode setting circuit 1600 and a test mode setting signal generation circuit 1620. Address key latch circuit 1621, address key predecoder 1622, address key main decoder 1623, buffer 1624 and encode signal generation circuit 1625, and test mode in test mode decoding circuit group 1626 of test mode setting signal generation circuit 1620 This is a test circuit having a decode circuit 1626b. The three encode signal wires 13j, 13k and 13m for transmitting the test mode encode signals TEN ₀ , TEN ₁ and TEN ₂ output from the encode signal generation circuit 1625 in the test circuit 15 are connected to the semiconductor from the test circuit 15. The chip 10 is arranged extending to the N side.

The local test mode decode circuits 1626c and 1626d constituting the test mode decode circuit 1626a are provided on the N side of the semiconductor chip 10 relative to the test circuit 15 having the encode signal generation circuit 1625, respectively, and encode signal wirings 13j, 13k, The test mode encode signals TEN ₀ , TEN ₁ , TEN ₂ are received from 13m, and the test mode setting signals TEST1, TEST2, TEST3, TEST4 and the test mode setting signals TEST6N, TEST7 corresponding to the test mode encode signal are generated as an encode signal generation circuit. Output to the internal circuits 1130, 1140, 1150, 410 and the internal circuits 116, 120 provided on the N side of the semiconductor chip 10 relative to the test circuit 15 having 1625. Although the encode signal wirings 13j, 13k, and 13m do not extend from the test circuit 15 to the S side of the semiconductor chip 10, the test mode setting signal TEST6S output to the internal circuit 117 is bothered as shown in FIG. ₀ , TEN ₁ , TEN ₂ are decoded by the test mode decode circuit 1626b and generated by setting the test mode setting signals TEST6N and TEST6S to the H level at the same timing, and the internal circuit 116 on the N side and the internal circuit on the S side This is because the circuit 117 performs the stress test mode operation at the same timing.

The reference potential line 14 for transmitting the reference potential V _ref output from the internal circuit 117 provided on the S side of the semiconductor chip 10 to the internal circuit 116 provided on the N side of the semiconductor chip 10 is a test circuit. On the S side of 15, the test circuit 15 is sandwiched between and adjacent to test mode setting signal wirings 13 f and 13 h formed of the same second metal layer as the reference potential line 14 (for example, an aluminum layer or a tungsten layer) In the center part of the chip where various signal wirings (not shown) such as a row address signal and a column address signal between the local test mode decode circuit 1626d are arranged, the same second metal layer as the reference potential line 14 (for example, It is sandwiched between and parallel to the encode signal wirings 13k and 13m formed of an aluminum layer or a tungsten layer, and is the same as the reference potential line 14 on the N side of the local test mode decode circuit 1626d. The test mode setting signal wirings 13g and 13i formed of a second metal layer (for example, an aluminum layer or a tungsten layer) are adjacent to and parallel to each other. As a result, the reference potential line 14 is shielded by the test mode clock wiring (test mode setting signal wiring and encode signal wiring) fixed at the L level during normal operation, so that it is difficult for the reference potential line 14 to receive noise. Needless to say, the same is possible even when the test mode clock wiring is fixed at the H level during abnormal use.

  In addition, the test mode setting signal is transmitted in an encoded form with three encode signal wires 13j, 13k, and 13m, which is smaller than the number of test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7. In the DRAM of the first embodiment shown in FIG. 12, the test mode setting signal wirings 13a, 13b, 13c, 13d, 13e, 13g, and 13i are extended from the test mode setting circuit 1600 to the N side of the semiconductor chip 10. On the other hand, in the DRAM of the second embodiment shown in FIG. 23, the wiring extending from the test circuit 15 to the N side of the semiconductor chip 10 is encoded signal wiring 13j, 13k, 13m and test mode setting signal wiring 13a. Since a book is sufficient, the area required to extend the wiring is reduced. In particular, in the configuration in which the pads 11 are arranged on the chip central band 12 of the semiconductor chip 10 as in the second embodiment, a large area of the chip central band 12 is used for the pads 11 and wiring for transmitting output data to the pads 11. In addition, various wirings such as wiring for transmitting the address signal received from the pad 11 occupy, and it is effective to reduce the wiring by transmitting the test mode setting signal in an encoded form.

  In addition, not only in the position of the pad 11 but generally in the DRAM, the vicinity of the center of the semiconductor chip 10 is an intersection of a row address predecode signal extending in the vertical and horizontal directions of the semiconductor chip 10 and a wiring for transmitting the column address predecode signal. For this reason, an area for extending the wiring excessively is small. Therefore, even when the test mode setting signal is transmitted through the vicinity of the center of the chip, it is effective to reduce the wiring by transmitting the test mode setting signal in an encoded form.

Also, by transmitting the test mode setting signal in an encoded form, the wiring extending from the test circuit 15 to the N side of the semiconductor chip 10 is reduced, so that the external power supply potential line that transmits the external power supply potential extV _CC and the internal power supply potential intV _By increasing the thickness of the power supply line 16, such as the internal power supply potential line that transmits _CC and the ground potential line that transmits the ground potential GND, the resistance value of the power supply line 16 becomes smaller and the voltage drop becomes smaller. (Including ground potential) can be transmitted to various parts of the semiconductor chip 10. Further, when the test mode setting signals TEST1, TEST2, TEST3, and TEST4 are decoded near the center of the semiconductor chip 10 by the local test mode decode circuit 1626c, the remaining two test mode setting signals TEST6N and TEST7 are transferred to the N side of the semiconductor chip 10. Since it is not a good idea to transmit to the three encode signal wirings 13j, 13k, and 13m, the local test mode decode circuit 1626d is more locally tested than the internal circuits 116 and 120 corresponding to the test mode setting signals TEST6N and TEST7. A mode decode circuit 1626c is provided.

FIG. 24 is a decoding table showing which of the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 is activated to H level depending on the state of the test mode encode signals TEN ₀ , TEN ₁ , and TEN ₂ When the test mode encode signals TEN ₀ , TEN ₁ and TEN ₂ are at the L level, L level and L level, respectively, no test mode is activated, and the test mode encode signals TEN ₀ , TEN ₁ and TEN ₂ are at the L level, L level and H level. Test mode setting signals TEST1 and TEST2 are set to H level, and when L level, H level and L level, test mode setting signal TEST2 is set to H level, and when L level, H level and H level, test mode setting signal Test mode setting signal TEST1 is set to H level when TEST4 is at H level, H level, L level, and L level, and test is performed to be at H level, L level and H level. Mode setting signal TEST3 is set to H level, test mode setting signal TEST7 is set to H level when it is at H level, H level and L level, and test mode setting signal TEST6N is set to H level when it is at H level, H level and H level. To the level.

As described above, in general, n n test mode encode signals can specify 2 ⁿ −1 combinations of activated test mode setting signals except for one combination in which no test mode setting signal is activated. . Also, the test mode setting signal that is activated together with various test mode setting signals, such as the multi-bit test mode setting signal TE, is not encoded and is made independent so that the encode signal generating circuit 1625 and the test mode decoding circuit The complexity of the group 1626 can be avoided.

In the first embodiment, as shown in FIG. 18, the address signals A ₀ , A ₁ , A ₂ , A ₃ , A ₄ , A ₅ are S level, H level, L level, H level, H level, L level, respectively. , Both test mode setting signals TEST4 and TEST7 are activated to H level, and address signals A ₀ , A ₁ , A ₂ , A ₃ , A ₄ , A ₅ are respectively S level, H level, H level, L The test mode setting signals TEST3 and TEST7 are both activated to H level when the level, H level, and L level, and the address signals A ₀ , A ₁ , A ₂ , A ₃ , A ₄ , and A ₅ are S level, There are modes in which the test mode setting signals TEST6N and TEST7 are both activated to H level when they are at H level, H level, H level, H level, and L level, but these modes are not used, so they are degenerated and three It is possible to set the test mode used in the encode signal wiring 13j, 13k, 13m It is. However, since only the signals that are transmitted through the vicinity of the center of the semiconductor chip 10 where other signal wirings are concentrated are degenerated, the combinations of test mode setting signals that are simultaneously activated are not extremely limited. .

As described above, the DRAM of the second embodiment also has the same effect as the DRAM of the first embodiment. Further, the six test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 are converted into the test mode setting signals. Three test mode encoding signals less than TEN ₀ , TEN ₁ , TEN ₂ and less encode signal wiring 13j, 13k, 13m are transmitted to the internal circuits 1130, 1140, 1150, 410, 116, 120, so test mode setting with less wiring area Signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 can be transmitted.

  In addition, since the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 can be transmitted with a small wiring area by encoding, the area through which wiring is passed is narrow in the chip central band 12 where a plurality of pads 11 are arranged. Many test modes can be set even in the semiconductor chip 10.

  In addition, because the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 can be transmitted with a small wiring area by encoding, the test mode passes through the vicinity of the center of the semiconductor chip 10 where various signal wirings are crowded together. Setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, TEST7 can be transmitted.

  In addition, the wiring to transmit the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 has been reduced by encoding. The power supply line 16 can be strengthened by increasing the number of wires or increasing the number of wires. (Including ground potential) can be supplied to various parts of the semiconductor chip 10.

  Also, since only the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 are transmitted through the vicinity of the center of the semiconductor chip 10 where various signal wirings are concentrated, the encode signal wiring is transmitted simultaneously. The combination of the test mode setting signals to be activated is not extremely limited.

  Further, since the multi-bit test mode setting signal activated together with other test mode setting signals is not encoded, a combination of encode signals for activating both the multi-bit test mode setting signal and other test mode setting signals is given. This eliminates the need for transmitting more test mode setting signals with limited encode signal wiring.

  Also, the encode signal wirings 13j, 13k, 13m are not directly input to the internal circuits 1130, 1140, 1150, 410, 116, 120, and the test mode setting signal TEST1 corresponding to each internal circuit 1130, 1140, 1150, 410, 116, 120 is provided by the test mode decode circuit 1626a , TEST2, TEST3, TEST4, TEST6N, TEST7 and decoding and inputting to each internal circuit 1130, 1140, 1150, 410, 116, 120 will increase the wiring area around each internal circuit 1130, 1140, 1150, 410, 116, 120 As a result, the internal circuits 1130, 1140, 1150, 410, 116, and 120 themselves do not require a decoding circuit, and an increase in area is suppressed.

  When the test mode setting signals TEST1, TEST2, TEST3, and TEST4 are decoded near the center of the semiconductor chip 10 by the local test mode decoding circuit 1626c, the remaining two test mode setting signals TEST6N and TEST7 are transferred to the N side of the semiconductor chip 10. The local test mode decode circuit 1626d is transmitted from the local test mode decode circuit 1626c rather than the internal circuits 116 and 120 corresponding to the test mode setting signals TEST6N and TEST7, without being transmitted through the three encode signal wirings 13j, 13k, and 13m. Since it is transmitted by the two test mode setting signal wirings 13g and 13i, an increase in the wiring area can be suppressed.

(Example 3.)
Next, a DRAM according to a third embodiment of the present invention will be described with reference to FIGS. The DRAM of the third embodiment is different from the DRAM of the second embodiment in that the layout of the test mode decoding circuit group 1626 in the test mode setting signal generation circuit 1620 of the test mode setting circuit 1600 is different from the layout. The layout position of the internal circuit 410 that receives the test mode setting signal TEST4 has moved. This difference will be described below.

  FIG. 25 is a circuit diagram showing a test mode decode circuit group 1626 in the test mode setting signal generation circuit 1620 of the DRAM test mode setting circuit 1600 of the third embodiment. This test mode decode circuit group 1626 is shown in FIG. The difference from the test mode decode circuit group 1626 of the second embodiment is that the inverter 1626cd, the NAND circuit 1626ce, and the inverter 1626cf that generated the test mode setting signal TEST4 in the local test mode decode circuit 1626c of the test mode decode circuit 1626a are eliminated. In addition, an inverter 1626df, a NAND circuit 1626dg, and an inverter 1626dh that generate the test mode setting signal TEST4 are newly provided in the local test mode decode circuit 1626d of the test mode decode circuit 1626a.

FIG. 26 is a simplified plan view showing the layout of the DRAM of the third embodiment on the semiconductor chip. FIG. 26 is different from the plan view of the DRAM of the second embodiment shown in FIG. The internal circuit 410 that receives the setting signal TEST4 has moved to the N side of the semiconductor chip 10, and the local test mode decode circuit 1626c whose circuit configuration has changed accordingly does not output the test mode setting signal TEST4. The changed local test mode decode circuit 1626d outputs the test mode setting signal TEST4, and the local test mode decode circuit 1626d has three test mode encode signals TEN ₀ , TEN ₁ , near the center of the semiconductor chip 10. TEN ₂ the local test mode decode circuit 1626c by three test mode setting signal TEST1, TEST2, be TEST3 and decodes the output, still N semiconductor chip 10 The three test mode setting signals TEST4, TEST6N, and TEST7 must be transmitted to the internal circuits 410, 116, and 120, and are equal to or greater than the number of the three encode signal wirings 13j, 13k, and 13m (this In the embodiment, it is the same), and the remaining test mode setting signals TEST4, TEST6N, and TEST7 are encoded as they are through the encode signal wirings 13j, 13k, and 13m, and transmitted to the vicinity of the internal circuit 410, 116, and 120 on the N side of the semiconductor chip 10, and the local test mode The decoding circuit 1626d is different from the local test mode decoding circuit 1626c in that the internal circuits 410, 116, and 120 are provided.

As described above, the DRAM of the third embodiment also has the same effect as the DRAM of the first embodiment, and, similarly to the DRAM of the second embodiment, six test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, Since TEST7 is transmitted to the internal circuits 1130, 1140, 1150, 410, 116, and 120 by using the three test mode encode signals TEN ₀ , TEN ₁ , and TEN ₂ that are smaller than the test mode setting signal and the less encode signal wirings 13j, 13k, and 13m. Test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 can be transmitted with a small wiring area.

  As with the DRAM of the second embodiment, the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 can be transmitted with a small wiring area by encoding, so that the chip central band in which a plurality of pads 11 are arranged. Even in the semiconductor chip 10 where the wiring area is narrow in 12, it is possible to set many test modes, and the test mode setting signals TEST1, TEST2, TEST3, TEST4 pass through the vicinity of the center of the semiconductor chip 10 where various signal wirings are crowded. , TEST6N, TEST7 can also be transmitted.

  Similarly to the DRAM of the second embodiment, the number of wires for transmitting the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 is reduced by encoding, so that the power supply line 16 is made thicker or the number is increased. And a stable power supply potential (including a ground potential) can be supplied to various portions of the semiconductor chip 10. Also, since only the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 are transmitted through the vicinity of the center of the semiconductor chip 10 where various signal wirings are concentrated, the encode signal wiring is transmitted simultaneously. The combination of the test mode setting signals to be activated is not extremely limited.

  Also, since the multi-bit test mode setting signal activated together with other test mode setting signals is not encoded as in the DRAM of the second embodiment, both the multi-bit test mode setting signal and other test mode setting signals are activated. There is no need to provide a combination of encode signals, and more test mode setting signals can be transmitted with limited encode signal wiring.

  Similarly to the second embodiment, the encode signal wirings 13j, 13k, 13m are not directly input to the internal circuits 1130, 1140, 1150, 410, 116, 120, and the test mode decode circuit 1626a supports each internal circuit 1130, 1140, 1150, 410, 116, 120. By decoding into the test mode setting signals TEST1, TEST2, TEST3, TEST4, TEST6N, and TEST7 and inputting them to the internal circuits 1130, 1140, 1150, 410, 116, 120, extra in the vicinity of each internal circuit 1130, 1140, 1150, 410, 116, 120 The increase in the wiring area is suppressed, and the internal circuits 1130, 1140, 1150, 410, 116, 120 themselves do not require a circuit for decoding, and the area increase is suppressed.

  Further, in the DRAM of the third embodiment, even if the test mode setting signals TEST1, TEST2, TEST3, and TEST4 are decoded near the center of the semiconductor chip 10 by the local test mode decoding circuit 1626c, the remaining three test mode setting signals TEST4 and TEST6N , TEST7 is transmitted to the N side of the semiconductor chip 10 through three encode signal wirings 13j, 13k, 13m, and the local test mode decode circuit 1626d is set to the test mode setting signal TEST4, than the local test mode decode circuit 1626c. By providing the internal circuits 410, 116, and 120 corresponding to TEST6N and TEST7, an increase in wiring area can be suppressed.

(Example 4.)
Next, a DRAM according to a fourth embodiment of the present invention will be described with reference to FIGS. The DRAM of the fourth embodiment is different from the DRAM of the third embodiment in that the layout of the test mode decoding circuit group 1626 in the test mode setting signal generation circuit 1620 of the test mode setting circuit 1600 is different from the layout. The layout position of the internal circuit 1150 that receives the test mode setting signal TEST3 has moved. This difference will be described below.

  FIG. 27 is a circuit diagram showing a test mode decoding circuit group 1626 in the test mode setting signal generation circuit 1620 of the DRAM test mode setting circuit 1600 of the fourth embodiment. This test mode decoding circuit group 1626 is shown in FIG. The difference from the test mode decode circuit group 1626 of the third embodiment is that the inverter 1626ca, the NAND circuit 1626cb and the inverter 1626cc which have generated the test mode setting signal TEST3 in the local test mode decode circuit 1626c of the test mode decode circuit 1626a are eliminated. In addition, an inverter 1626bc, a NAND circuit 1626bd, and an inverter 1626be, which generate a test mode setting signal TEST3 in the test mode decode circuit 1626b, are newly provided.

FIG. 28 is a simplified plan view showing the layout of the DRAM of the fourth embodiment on the semiconductor chip. FIG. 28 is different from the plan view of the DRAM of the third embodiment shown in FIG. The test mode decode circuit 1626b is not included in the test circuit 15 and the test mode decode circuit 1626b having a different circuit configuration is provided separately from the test circuit 15, the test mode setting signal The internal circuit 1150 that receives TEST3 has moved to the S side of the semiconductor chip 10, and the local test mode decode circuit 1626c whose circuit configuration has changed accordingly does not output the test mode setting signal TEST3. Instead, the circuit configuration has changed. At the same time, the local test mode 1626b, which is separate from the test circuit 15, outputs the test mode setting signal TEST3, and the reference potential wiring 14 for transmitting the reference potential V _ref On the S side of the decode circuit 1626b, as shown in FIG. 26, the test mode setting signal wiring 13d and the internal power supply potential intV _CC or the ground are not sandwiched between and in parallel by the test mode setting signal wirings 13f and 13h. It differs in that it is shielded by being sandwiched between and parallel to the power line 17 that transmits the potential GND.

  Then, in order to transmit the two test mode setting signals TEST3 and TEST6S to the internal circuits 1150 and 117 arranged on the S side of the semiconductor chip 10, three encoded signal wirings 13j, 13k, and 13m are used in an encoded form. Since the wiring area increases, the test mode decode circuit 1626b is provided in the test circuit 15 including the encode signal generation circuit 1625 rather than the internal circuits 1150 and 117, and decoding is performed earlier to set two test modes. Test mode setting signals TEST3 and TEST6S are transmitted by signal wirings 13d and 13h.

  As described above, the DRAM of the fourth embodiment has the same effects as the DRAM of the third embodiment, and the test mode decode circuit 1626b is provided in the test circuit 15 rather than the internal circuits 1150 and 117. An increase in wiring area for transmitting the mode setting signals TEST3 and TEST6S can be suppressed. In the first to fourth embodiments, the row decoder is arranged in the central band. However, the object of the present invention can be achieved even if the row decoder is arranged on the opposite side of the central band. Further, although an example in which the test mode setting circuit is arranged beside the pads is shown, it may be arranged between the pads.

It is a block diagram of DRAM of Example 1 of this invention. FIG. 5 is a timing chart showing the operation of the DRAM of Embodiment 1 of the invention. 1 is a circuit diagram of an internal power supply potential generation circuit of a DRAM according to Embodiment 1 of the present invention. FIG. 1 is a circuit diagram of a DRAM test mode setting circuit according to Embodiment 1 of the present invention; FIG. 1 is a circuit diagram of a timing detection circuit in a DRAM test mode setting circuit according to Embodiment 1 of the present invention; FIG. 1 is a circuit diagram of a test group detection circuit in a DRAM test mode setting circuit according to Embodiment 1 of the present invention; FIG. FIG. 3 is a block diagram of a test mode setting signal generation circuit in the DRAM test mode setting circuit according to the first embodiment of the present invention. 1 is a circuit diagram of an address key latch circuit in a DRAM test mode setting signal generation circuit according to Embodiment 1 of the present invention; FIG. FIG. 3 is a circuit diagram of an address key predecoder in the DRAM test mode setting signal generation circuit according to the first embodiment of the present invention; 1 is a circuit diagram of an address key main decoder in a DRAM test mode setting signal generation circuit according to Embodiment 1 of the present invention; FIG. FIG. 3 is a circuit diagram of a buffer in the test mode setting signal generation circuit of the DRAM according to the first embodiment of the present invention. It is the simplified top view of the semiconductor chip with which DRAM of Example 1 of this invention was formed. 1 is a simplified cross-sectional view including a test mode setting signal wiring of a DRAM according to Embodiment 1 of the present invention; FIG. 5 is a timing chart showing an operation of the DRAM test mode setting circuit according to the first embodiment of the present invention; FIG. 5 is a timing chart showing an operation of the DRAM test mode setting circuit according to the first embodiment of the present invention; FIG. 5 is a timing chart showing an operation of the DRAM test mode setting circuit according to the first embodiment of the present invention; FIG. 5 is a timing chart showing an operation of the DRAM test mode setting circuit according to the first embodiment of the present invention; It is a figure which shows the relationship between the address key of DRAM of Example 1 of this invention, and a test mode. FIG. 10 is a block diagram of a test mode setting signal generation circuit in a DRAM test mode setting circuit according to a second embodiment of the present invention. It is a circuit diagram of the buffer in the test mode setting signal generation circuit of DRAM of Example 2 of this invention. FIG. 7 is a circuit diagram of an encode signal generation circuit in a DRAM test mode setting signal generation circuit according to Embodiment 2 of the present invention; FIG. 6 is a circuit diagram of a test mode decoding circuit group in a DRAM test mode setting signal generation circuit according to Embodiment 2 of the present invention; It is the simplified top view of the semiconductor chip with which DRAM of Example 2 of this invention was formed. It is a circuit diagram which shows the relationship between the test mode encoding signal and test mode of DRAM of Example 2 of this invention. FIG. 10 is a circuit diagram of a test mode decoding circuit group in a DRAM test mode setting signal generating circuit according to Embodiment 3 of the present invention; It is the simplified top view of the semiconductor chip with which DRAM of Example 3 of this invention was formed. FIG. 10 is a circuit diagram of a test mode decoding circuit group in a DRAM test mode setting signal generating circuit according to Embodiment 4 of the present invention; It is the simplified top view of the semiconductor chip with which DRAM of Example 4 of this invention was formed. It is a circuit diagram of a conventional test mode setting circuit.

Explanation of symbols

  10 semiconductor chip, 11 pads, 12 chip center band, 13d, 13f, 13g, 13h, 13i test mode setting signal wiring, 13j, 13k, 13m encoding signal wiring, 14 reference potential lines, 116, 120, 410, 1130, 1140, 1150 internal circuit , 1600 test mode setting circuit, 1610 status detection circuit, 1612a super high level detection circuit, 1612af pull up circuit, 1612ah load circuit, 1612b super high level detection circuit, 1612bf pull up circuit, 1612bh load circuit, 1612c test group detection signal generation Circuit, 1612ca test group detection auxiliary circuit, 1612cb test group detection signal control circuit, 1620 test mode setting signal generation circuit, 1623 address key main decoder, 1625 encode signal generation circuit, 1626a test mode decode circuit, 1626c, 1626d local test mode decode circuit.

Claims (6)

An encode signal generating circuit that is provided in the semiconductor chip and outputs a plurality of test mode encode signals in accordance with a state of an input signal input to the semiconductor chip; and provided in the semiconductor chip, each of which is provided from the encode signal generating circuit. A plurality of encode signal wirings that transmit at least part of the test mode encode signals, and are provided closer to the first direction than the encode signal generation circuit of the semiconductor chip. A test mode decode circuit that receives a test mode encode signal from the plurality of encode signal wirings and outputs a plurality of test mode set signals corresponding to the test mode encode signal, the number being greater than the number of the test mode encode signals. A test mode setting circuit having the semiconductor chip A plurality of internal circuits that are provided on the first direction side relative to the encode signal generation circuit, receive each test mode setting signal from the test mode decode circuit, and perform a predetermined test operation in accordance with the test mode setting signal A semiconductor device comprising: The semiconductor chip further includes a plurality of pads disposed along the other side direction in a chip central band located in the center of one side and extending in the other side direction adjacent to the one side.
The semiconductor device according to claim 1, wherein the encode signal wiring is provided in the center band of the chip. The input signal includes a first input signal and a second input signal,
The test mode setting circuit receives the first input signal and outputs a state detection signal corresponding to the state of the first input signal. The test mode setting circuit receives the state detection signal and receives the first input signal. When this state detection signal indicates that the first state is the first state, a multi-bit test mode setting signal which is at an activation level is output, and the second state is different from the first state. When the state detection signal indicates that the input signal is an input decode signal corresponding to the second input signal to the encode signal generation circuit, at least one of the test mode setting signals output from the test mode decode circuit is provided. To the activation level, the state detection signal indicates that the first input signal is in the second state, and the multi-bit when the second input signal is in the third state. At least one of the test mode setting signals output from the test mode decoding circuit is obtained by setting the strike mode setting signal to the activation level and applying an input decode signal corresponding to the second input signal to the encode signal generation circuit. The semiconductor device according to claim 1, further comprising an input decoder for setting the activation level.   The test mode setting circuit outputs a first test mode setting signal and an input decode signal corresponding to the input signal, applies the input decode signal to the encode signal generation circuit, and outputs the first decode signal when the input signal is in a predetermined state. 3. The semiconductor device according to claim 1, further comprising an input decoder for causing at least one of one test mode setting signal and a test mode setting signal output from the test mode decoding circuit to be at an activation level.   The test mode decode circuit receives a test mode encode signal from a plurality of encode signal lines and outputs a test mode setting signal corresponding to the test mode encode signal, and the plurality of encode signal lines. In response to the test mode encode signal, a smaller number of test mode setting signals than the encode signal wiring are output according to the test mode encode signal, and the first local test is performed by the internal circuit corresponding to the test mode set signal. 3. The semiconductor device according to claim 1, further comprising a second local test mode decode circuit provided by the mode decode circuit.   The test mode decode circuit receives a test mode encode signal from a plurality of encode signal lines and outputs a test mode setting signal corresponding to the test mode encode signal, and the plurality of encode signal lines. An internal circuit corresponding to the test mode setting signal than the first local test mode decoding circuit receives a test mode encode signal, outputs a test mode setting signal higher than the encode signal wiring in accordance with the test mode encode signal. The semiconductor device according to claim 1, further comprising a second local test mode decode circuit provided.

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