JP2005308917A - Plasma display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a wrong light-on in order to display an image accurately by solving the problem that regarding sustaining discharge of a plasma display apparatus, although sustain discharge is performed by discriminating a light-on cell and a light-off cell using discharging phenomena when a reverse voltage is applied by providing a wall charge with addressing discharge, the cell to be light-on is not on and the cell to be light-off is on, since discharge characteristics changes due to change of temperature and internal gas pressure or the like. <P>SOLUTION: The number of pixels which address to a panel 5 is counted by a pulse count circuit 7 and a pulse voltage is converted to a direct current voltage by an integrator comprising 11, 13 and 14 and a voltage which is proportional to a current pulse of the sustain discharge is generated in a current detector 10 and subtracted in the integrator. The voltage which is applied to the sustain discharge is controlled according to the subtraction result. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a plasma display device using a plasma display panel for displaying television images and the like.

  As a thin display device capable of displaying a television image or the like, there is a plasma display device using an AC plasma display panel. The plasma display device can realize a thin flat display with a large screen, and the demand for both business use and home use is increasing.

  A conventional plasma display device is composed of a front substrate and a rear substrate made of glass substrates disposed to face each other, and forms a pair of common electrodes (also referred to as “sustain discharge electrodes”) disposed substantially parallel to the front substrate side. ) And scanning electrodes are provided for the number of display lines, and are arranged substantially orthogonal to the electrode pairs on the back substrate side, and address electrodes for scanning discharge with the scanning electrodes are provided for the number of display dots. (Hereinafter abbreviated as “PDP”), a common electrode for applying a drive pulse voltage to each electrode, each drive circuit for scan electrodes and address electrodes, and a power supply circuit for supplying power to each drive circuit. . Discharge cells (hereinafter sometimes simply referred to as “cells”) serving as pixels of the PDP are formed by the number of display lines × the number of display dots at the intersections of the common electrode, scan electrode pair, and address electrode. A phosphor is applied to the inner wall on the back plate side. In the following description, “pixel” = “discharge cell” is described.

As a driving method thereof, a subfield driving method in which gradation display is controlled by the number of discharges is generally used. That is, consider a case where black to white are expressed in, for example, 256 levels (8 bits). In this case, one field is divided into eight subfields, and the LSB discharges for 1 (= 2 ⁰ ) cycles... MSB discharges for 128 (= 2 ⁷ ) cycles. Therefore, in order to express brightness, it is necessary to perform eight address operations.

  Each subfield is composed of a reset period, an address period, and a sustain discharge period, and each generally performs the following operation.

  In the reset period, prior to lighting, a reset pulse voltage is applied between the scan electrode and the common electrode to discharge all the pixels, and the wall charges in the immediately preceding subfield are erased, so that each pixel is in an initial state. . For this purpose, a high voltage (reset pulse voltage) of about twice the normal lighting voltage is applied between the scan electrode and the common electrode. This discharges whether or not there is a charge on each electrode (on the dielectric). Due to this discharge, a large amount of wall charges adhere to the scanning electrode and the common electrode. Thereafter, when the voltage of both electrodes is set to 0, dielectric breakdown occurs due to the electric field due to the wall charges described above, the charges are neutralized, and the wall charges disappear.

  In the next address period, a scan pulse is sequentially applied to each scan electrode, and at the same time, an address is addressed to an address electrode of a pixel corresponding to the image display content (hereinafter, such a pixel to be lit is referred to as a “write pixel”). Apply pulse voltage. That is, a positive voltage is applied to the address electrode of the writing pixel, and a negative voltage is applied to the scanning electrode of the display line in which the pixel is present (for convenience, “select the writing pixel and apply the voltage” hereinafter). Is written as “addressing”). As a result, a discharge is generated between the scan electrode and the address electrode of the pixel (hereinafter, this discharge is referred to as “address discharge”), and negative charges are deposited on the address electrodes and positive charges are deposited on the scan electrodes as wall charges. To do. Thereafter, the voltage of each electrode is set to 0, but the electric field due to the wall charge is set to a charge that does not cause dielectric breakdown. Thus, the address is completed and the next sustain discharge period starts.

  In the sustain discharge period, a negative voltage is first applied to the common electrode. As a result, an electric field is generated between the scanning electrode and the writing pixel. However, in the writing pixel, an electric field due to wall charges formed in the address period is added to the electric field. Discharge)) occurs. Visible light is generated by irradiating the phosphor with vacuum ultraviolet rays generated by the sustain discharge, and the pixel is turned on. When discharged, the wall charge adhesion polarity is reversed.

  Next, the voltage of the common electrode is returned to 0, and a negative voltage is applied to the scan electrode. In this way, the same thing as described above occurs on the scanning electrode and the common electrode, and the wall charges are inverted again. This cycle is repeated 128 times for the MSB and once for the LSB.

  The background art as described above is described in Patent Document 1, for example.

  By the way, the applied voltage for the sustain discharge (hereinafter referred to as “sustain discharge voltage”) is very important, and the pixel (written pixel) selected (written) in the address period is discharged, It is necessary to set a voltage that does not discharge a pixel that is not selected (not written) in the address period. A voltage range that satisfies both of these conditions is called a margin. At present, the power supply voltage (that is, the sustain discharge voltage) of the sustain discharge drive circuit is adjusted at the time of shipment from the factory so as to be in the middle of the margin.

  However, the discharge start voltage that causes discharge decreases with time, and there is a concern that an erroneous discharge may occur in which a non-addressed pixel discharges during a sustain discharge. Therefore, for example, Patent Document 2 discloses a technique for controlling the sustain discharge voltage based on a decrease curve with respect to the cumulative time of the discharge start voltage. Further, for example, Patent Document 3 discloses a technique for automatically detecting a light emitting cell and a non-light emitting cell with a discharge current using a test video signal of an all black signal or an all white signal and automatically adjusting a sustain discharge voltage. ing.

JP 2001-13916 A JP 2002-366088 A JP 2000-284743 A

  In Patent Document 1, the sustain discharge voltage is controlled on the basis of a decrease curve with respect to the cumulative time of the discharge start voltage. However, this discharge start voltage reduction curve is an average characteristic of many PDPs, and individual PDPs may deviate from this reduction curve. In that case, there is a concern that erroneous discharge may occur due to a change with time, and there is a circumstance that reliability is poor.

Further, in Patent Document 2, the maintenance discharge voltage adjustment is based on the premise of a maintenance service by a service person with respect to changes over time, and there is a circumstance that the user cannot use this function. In addition, this function is inconvenient because it cannot be performed during normal viewing.
The present invention has been made in view of the above circumstances, and an object of the present invention is to perform automatic adjustment of the sustain discharge voltage that is performed with the passage of time according to the discharge characteristics of each PDP and during normal viewing. An object of the present invention is to provide a plasma display device that can be used.

  In order to achieve the above object, the power supply voltage of the sustain discharge drive circuit is adjusted based on the relationship between the number of pixels to be lit and the amount of mobile charge due to the sustain discharge at a certain time. That is, a common electrode driving circuit that generates a voltage proportional to the number of cells to be lit, subtracts a voltage proportional to the number of cells that are actually lit, and applies a sustain discharge voltage to the PDP by the subtraction output. In addition, the output voltage (that is, the sustain discharge voltage) of the power supply circuit that supplies the power supply voltage to the scan electrode driving circuit is controlled (automatically adjusted). As a result, even if the ease of discharge of each cell changes due to changes over time, the same number of cells as the number of cells to be lit can be lit. This adjustment has the advantage that it can be performed while viewing.

  According to the present invention, display quality can be maintained while viewing.

  Hereinafter, the best mode of the present invention will be described in detail with reference to the drawings. In each figure, elements having the same function are denoted by the same reference numerals.

  FIG. 1 is a block diagram of a plasma display apparatus according to a first embodiment of the present invention, and FIG. 2 is a timing chart showing an outline of the operation of the plasma display apparatus.

  In FIG. 1, 1 is a television signal source that outputs a video signal S, 2 is an A / D converter that converts an analog video signal S into digital data, 3 is a frame memory, and 4 is a serial writing from the frame memory 3. An address driving circuit that converts the embedded pixel bit data into parallel data and addresses the writing pixel, 5 is a PDP, 8 is a common electrode driving circuit, and 9 is a scanning electrode driving circuit. The scan electrode drive circuit 9 has a switch 9a for each scan line output.

  7 is a pulse number counting circuit for generating a negative voltage pulse having a predetermined pulse width corresponding to a write pixel bit from serial write pixel bit data output from the frame memory 3 to the address drive circuit 4. This is a current detection circuit that detects the output current (sustain discharge current) of the sustain discharge output from the common electrode drive circuit 8 and generates a positive voltage pulse proportional to the output current.

  An adder / subtracter circuit 19 includes an operational amplifier 14, resistors 11 and 12 connected to the negative phase input terminal of the operational amplifier 14, and an integrating capacitor connected between the negative phase input terminal and the output terminal of the operational amplifier 14. 13 and a reset switch 15. The reset switch 15 initializes the operation of the addition / subtraction circuit 19. One end of the resistor 11 and the resistor 12 is connected to the negative phase input terminal of the operational amplifier 14, and the other end is connected to the outputs of the pulse number counting circuit 7 and the current detection circuit 10, respectively. The positive phase input terminal of the operational amplifier 14 is grounded.

  20 is a switch for controlling the output of the addition / subtraction circuit 19, 25 is an integration circuit comprising a resistor 22, an integration capacitor 24 and an operational amplifier 23, and 18 is a power supply for supplying power to the common electrode drive circuit 8 and the scan electrode drive circuit 9. Circuit.

  The power supply circuit 18 includes a reference voltage generator 181, a comparator 180, and an amplifier 182, and if there is no voltage Vg input through the resistor 26 (if 0 V), a general reference voltage generator 181 and a comparator This is a feedback type power supply circuit that outputs a predetermined power supply voltage Vs composed of 180 and an amplifier 182. If there is the voltage Vg, the input voltage Vg is compared with the reference voltage Vr of the reference voltage generator 181 by the comparator 180, the comparison error is inverted and amplified by the amplifier 182, and the predetermined power supply voltage Vs is compared with the input voltage Vg. Is changed in the reverse polarity direction (for example, the direction of increasing the power supply voltage if the input voltage Vg is negative) and supplied to the common electrode drive circuit 8 and the scan electrode drive circuit 9. That is, a voltage change corresponding to the input voltage Vg and having a polarity opposite to the input voltage Vg is superimposed on the power supply voltage Vs and supplied to the common electrode drive circuit 8 and the scan electrode drive circuit 9.

  A timing generator 6 supplies a timing signal for controlling operations of the frame memory 3, the scan electrode driving circuit 9, the reset switch 15 and the switch 20.

  Hereinafter, the operation of the plasma display apparatus of the present embodiment will be described with reference to FIGS.

  The video signal from the television signal source 1 is converted into digital data by the A / D converter 2, and the data is stored in the frame memory 3. Then, in the address period of an arbitrary subfield period, bit data (write pixel bit data) to be displayed at that time out of the data of the scanning line to be addressed at that time in response to an instruction from the frame memory 3 from the frame generator 3. ) Is transferred to the address drive circuit 4 as serial data. FIG. 2A shows an input waveform of the address driving circuit 4 in an address period in an arbitrary subfield. In FIG. 2A, each pulse is a write pixel bit. In FIG. 2 (a), for the convenience of explanation, it is assumed that the write pixel bits exist continuously, but it goes without saying that there may be no write pixel bits depending on the video signal to be displayed. Absent.

  This serial data is converted into parallel data for one scanning line by the address driving circuit 4. The timing generator 6 issues a command to the scan electrode drive circuit 9 and the address drive circuit 4, and an address discharge (also referred to as “write discharge”) between the scan electrode of the PDP 5 selected by the switch 9a and the address electrode. ) To cause wall charges to adhere. The above-described operation is performed for all scanning lines, wall charges are attached to all pixels to be illuminated, and then sustain discharge is repeated for the number of cycles linked to the subfield between the common electrode and the scanning electrode to obtain a desired gradation. Get.

  In the plasma display device having such a basic configuration, the pulse number counting circuit 7 includes a negative voltage pulse having a predetermined pulse width corresponding to each write pixel bit of the serial data transmitted from the frame memory 3 to the address driving circuit 4. Is generated. That is, as apparent from the output waveform of the pulse number counting circuit 7 in FIG. 2B, negative voltage pulses having the same number as the number of write pixel bits are generated.

  On the other hand, the current detection circuit 10 that detects the output current of the sustain discharge of the common electrode driving circuit 8 generates a positive voltage pulse proportional to the output current (see the output waveform of the current detection circuit 10 in FIG. 2C). .

  The output of the pulse number count circuit 7 is input to the adder / subtractor circuit 19 via the resistor 11 and the output of the current detection circuit 10 is input to the adder / subtractor circuit 19 via the resistor 12. In the address period, a negative voltage pulse is input from the pulse number counting circuit 7 to the addition / subtraction circuit 19. This pulse voltage is converted into a current by the resistor 11, and the integration capacitor 13 is charged by the current. Therefore, the output voltage of the adder / subtractor circuit 19 increases by a voltage proportional to the number of pulses. Therefore, as apparent from the output waveform of the addition / subtraction circuit 19 in FIG. 2 (e), the output voltage of the addition / subtraction circuit 19 gradually increases due to the input of the negative voltage pulse generated corresponding to the write pixel bit. When a transition is made from the address period to the sustain discharge period, the common electrode drive circuit 8 operates for light emission, a voltage is applied to all the pixels, and the first sustain discharge occurs only in the addressed pixels. Accordingly, a positive voltage pulse proportional to the sustain discharge current indicated by the output waveform of the current detection circuit 10 in FIG. 2C is generated by the current detection circuit 10 and input to the addition / subtraction circuit 19. This positive voltage pulse is converted into a current by the resistor 12, and this current decreases the charge of the integrating capacitor 13, and the output voltage of the adder / subtractor circuit 19 decreases as shown in FIG.

  At this time, the resistors 11 and 12 of the adder / subtractor circuit 19 cause the output voltage of the adder / subtractor circuit 19 to return to 0 as shown by the waveform 190 in FIG. 2E when all the addressed pixels are discharged without excess or deficiency. It has been adjusted.

  However, let us assume a case where the number of discharged pixels is smaller than the addressed number of pixels due to the temporal change of the PDP 5 (when lighting is insufficient). In this case, since the sustain discharge current is lower than the expected value, the output voltage of the addition / subtraction circuit 19 becomes a positive value as shown by the waveform 191 in FIG. Hereinafter, the output voltage of the addition / subtraction circuit 19 is referred to as an error voltage for convenience of explanation.

  The switch 20 is closed under the control of the timing generator 6 for a predetermined time after the first sustain discharge until the next sustain discharge (hereinafter referred to as “ON”) as in the switch state of FIG. Therefore, this positive voltage (error voltage) is supplied to the integration circuit 25 via the switch 20, and the output voltage of the integration circuit 25 is held at a negative (voltage having a polarity opposite to that of the error voltage) (switch 20). Even after the opening of).

  By applying this negative voltage (voltage having the opposite polarity to the error voltage) to the amplifier of the power supply circuit 18, the power supply voltage that is the output voltage of the power supply circuit 18 starts to rise. Since it is supplied to the scan electrode driving circuit 9, it becomes easy to perform sustain discharge, and the addressed pixel is discharged.

  On the contrary, in the case of excessive lighting in which a pixel that has not been addressed is discharged due to a change over time, the reverse action described above occurs, and the output voltage of the power supply circuit 18 starts to decrease, and only the addressed pixel is controlled to be discharged sustainly. . Note that a waveform 192 in FIG. 2E is an output characteristic of the addition / subtraction circuit 19 in the case of excessive lighting.

  The switch 20 is opened after a predetermined time, and then the reset switch 15 connected in parallel to the integrating capacitor 13 of the adder / subtractor circuit 19 is in the state of the switch 15 in FIG. Then, it is closed (turned on) and the adder / subtracter circuit 19 is initialized, and waits for the start of the address period of the next subfield. The reset switch 15 is opened before the write pixel bit data is transmitted from the frame memory 3 to the address drive circuit.

  The above-described operation is performed for each subfield, and the common electrode driving circuit 8 and the scanning electrode driving circuit for applying the sustain discharge voltage to the PDP 5 so that the number of addressed write pixels and the number of sustain discharge pixels are the same. By controlling the power supply voltage 9, the sustain discharge voltage is set so that the addressed write pixel is appropriately sustain-discharged according to the discharge characteristics of each PDP even if the discharge start voltage decreases with time. Can be adjusted automatically. Moreover, this adjustment has the advantage that it can be performed while viewing.

  Next, a second embodiment will be described.

  The output of the adder / subtractor circuit 19 includes a noise component and cannot be attenuated even after passing through the integrating circuit 25. In the first embodiment, there is a concern that the power supply voltage of the power supply circuit 18 may slightly fluctuate due to noise.

  Therefore, in this embodiment, in order to eliminate the influence of noise, a common band drive circuit that provides a predetermined range of dead band at the output of the adder / subtractor circuit and applies a sustain discharge voltage to the PDP 5 by an error output exceeding the range of the dead band. 8. It is characterized in that the power supply voltage of the scan electrode drive circuit 9 is controlled.

  FIG. 3 is a block diagram of a plasma display apparatus according to a second embodiment of the present invention, FIG. 4 is an input / output characteristic of a window circuit for setting a dead zone, FIG. 5 is an input / output characteristic of a logic circuit, and FIG. It is a timing chart which shows the outline | summary of operation | movement of a display apparatus. 3 and 6, elements having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted.

In FIG. 3, the difference from the first embodiment is after the switch 21 connected to the output of the integrating circuit 25. In the figure, reference numeral 16 has a dead band characteristic (threshold characteristic) shown in FIG. 4, and when the output from the integrating circuit 25 exceeds the positive threshold V _TH , a high (hereinafter referred to as “H”) level is output. This is a window circuit that outputs a low (hereinafter referred to as “L”) level when a negative threshold −V _TH is exceeded, and outputs a 0 level within the threshold range. A logic circuit 17 receives the output H, 0, L level of the window circuit 16 and outputs a DC voltage having a predetermined value as shown in FIG. The power supply circuit 18 is the same as that shown in FIG. 1 and receives a DC voltage having a predetermined value from the logic circuit 17 and changes the power supply voltage in a direction opposite to the DC voltage by a predetermined value corresponding to the DC voltage. Let

  Hereinafter, the operation of the plasma display apparatus according to the present embodiment will be described with reference to FIGS.

When the error voltage of each field is output to the output of the adder / subtractor circuit 19, the switches 20 and 21 are closed, as shown in the switch state of FIG. Input to the circuit 16. The window circuit 16 has a dead zone (threshold) characteristic as shown in FIG. 4, and even if a small error voltage within the threshold (within ± _VTH ) is input, the output is 0, but when the error voltage exceeds the threshold, the output is performed. Swings to H or L. This output is input to the logic circuit 17 at the next stage. The logic circuit 17 has logic characteristics as shown in FIG. 5, and the power output of the power supply circuit 18 is changed by the logic output.

  For example, if the output of the addition / subtraction circuit 19 is negative, that is, the output of the integration circuit 25 is positive, due to excessive lighting, the output of the window circuit 16 becomes H level and the output of the logic circuit 17 becomes a positive voltage of a predetermined value with this positive voltage. The circuit 18 changes by a predetermined value corresponding to the positive voltage value in the direction opposite to the inputted positive voltage, that is, in the direction of decreasing the power supply voltage.

  By doing so, when there are more discharge pixels than planned (when lighting is excessive), the power supply voltage of the power supply circuit 18 is reduced, and this reduced power supply voltage is applied to the common electrode drive circuit 8 and the scan electrode drive circuit 9. In the next subfield, the sustain discharge voltage applied to the PDP 5 is lowered and it becomes difficult to discharge. On the other hand, when the number of discharge icons is less than expected (when the discharge is insufficient), the power supply voltage of the power supply circuit 18 rises, and it becomes easy to discharge in the next subfield. By repeating such an operation over a plurality of subfields, the power supply voltage of the power supply circuit 18 eventually converges to an appropriate power supply voltage.

  According to the present embodiment, it is possible to eliminate the influence of noise included in the error voltage by providing a dead band for detection of the error voltage.

  In the second embodiment, the output of the logic circuit is generated based on the window output of the current subfield. However, for example, it may be generated in consideration of the window output of the previous subfield. For example, if the previous window output is 0 and this time is H, the reduction change of the power supply voltage is reduced (this change is referred to as “first change”). The reduction change of the power supply voltage may be set as a larger second change.

  In this way, not only the current window output but also the window output of multiple subfields prior to the current subfield can be referred to so that the change in the power supply voltage of the power supply circuit can be set to multiple levels. The convergence to can be accelerated.

1 is a block configuration diagram of a plasma display device according to a first embodiment of the present invention. The timing chart which shows the outline | summary of operation | movement of the plasma display apparatus which shows a 1st Example. The block block diagram of the plasma display apparatus which shows the 2nd Example by this invention. The input / output characteristics of the window circuit used in the second embodiment. Input / output characteristics of the logic circuit used in the second embodiment. The timing chart which shows the outline | summary of operation | movement of the plasma display apparatus which shows a 2nd Example.

Explanation of symbols

1 signal source, 2 A / D converter, 3 frame memory, 4 address drive circuit, 5 PDP, 6 timing generator, 7 pulse count circuit, 8 common electrode drive circuit, 9 operation electrode drive circuit, 10 current detection circuit, 11 resistors, 12 resistors, 13 integrating capacitors, 14 operational amplifiers, 15 reset switches, 16 window circuits, 17 logic circuits, 18 power supply circuits, 19 addition / subtraction circuits, 20 switches, 21 switches, 22 resistors, 23 operations Amplifier, 24 Integration capacitor, 25 Integration circuit, 26 Resistor, 180 Comparator, 181 Reference voltage generator, 182 Amplifier

Claims (8)

A plasma display panel having address electrodes and scan electrodes;
Address discharge driving means for driving the address electrodes to perform address discharge;
Sustain discharge driving means for applying a voltage to the scan electrode to drive the discharge so as to perform a sustain discharge;
Control means for controlling a voltage for driving the scan electrodes in the sustain discharge driving means based on a signal input to the address driving means and a signal detected from the sustain discharge driving means by sustain discharge;
A plasma display device comprising: A plasma display panel having address electrodes and scan electrodes;
Address discharge driving means for driving the address electrodes to perform address discharge;
Sustain discharge driving means for applying a voltage to the scan electrode to drive the discharge so as to perform a sustain discharge;
Control means for feedback-controlling the voltage applied to the scan electrode in the sustain discharge driving means when there is a pixel in which sustain discharge is not performed even if address discharge is performed at the address electrode;
A plasma display device comprising: Pulse detection means for counting the number of pulses for address discharge input to the address discharge drive means from a signal input to the address drive means;
Current detection means for detecting a current of the sustain discharge output from the sustain discharge driving means,
3. The plasma according to claim 1, wherein the control unit controls a voltage in the sustain discharge driving unit by comparing an output of the pulse detection unit and an output of the current detection unit. 4. Display device.   The control unit increases the voltage applied to the scan electrode in the sustain discharge driving unit when there is a pixel in which the sustain discharge is not performed even if the address discharge is performed on the address electrode. The plasma display device according to claim 2.   The control means reduces the voltage applied to the scan electrode in the sustain discharge driving means when there is a pixel in which the address discharge is not performed at the address electrode but the sustain discharge is performed. Item 5. The plasma display device according to Item 4. The control means includes
Voltage control means for generating an output voltage to control the voltage applied to the scan electrode in the sustain discharge driving means based on the input voltage;
3. The input voltage is determined by comparing a signal input to the address driving unit with a signal detected by the sustain discharge of the sustain discharge driving unit. The plasma display device described.   7. The plasma display apparatus according to claim 6, wherein the voltage control unit has a dead zone that does not change with respect to the input voltage within a predetermined range in relation to the input voltage with respect to the output voltage. 8. The plasma according to claim 7, wherein the voltage control means changes the range of the output voltage when an input voltage in a predetermined range is input a plurality of times in relation to the relationship with the input voltage. Display device.

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