JP2005304004A - Pll modulation circuit and polar modulation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL modulation circuit and a polar modulation device for improving accuracy in modulation. <P>SOLUTION: First and second calibration signals 308, 309 are fed to a discrimination circuit unit 102 of a PLL unit 100A and to an adder 116 and demodulated at a demodulator 111 and then fed to a modulation signal control circuit 115 after being passed through a low pass filter 113 and a high pass filter 114. In the modulation signal control circuit 115, the phase and amplitude of the first and second calibration signals 308, 309 are compared to generate control information 318, which is fed to a modulation signal adjustment unit 106. The modulation signal adjustment unit 106 holds the control information 318 and controls the value of the first modulation input signal or the second modulation input signal given to the discrimination circuit 102 and to the adder 116 based on the control information 318 held at the operation of modulation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL modulation circuit and a polar modulation device in a wireless communication device.

  Generally, a PLL (Phase Locked Loop) modulation circuit is required to have low cost, low power consumption, low noise characteristics, and high modulation accuracy. In order to increase the modulation accuracy of the PLL modulation circuit, it is desirable that the PLL frequency bandwidth (PLL bandwidth) is wider than the frequency bandwidth (modulation bandwidth) of the modulation signal.

  However, when the bandwidth of the PLL modulation circuit is increased, noise characteristics are degraded. Therefore, as a technique for realizing a wide-band PLL modulation circuit, the bandwidth of the PLL modulation circuit is set to be narrower than the bandwidth of the modulation signal, and the modulation within the band of the PLL modulation circuit is different from the modulation outside the band of the PLL modulation circuit. Two-point modulation performed at a location has been proposed (see, for example, Patent Document 1).

  FIG. 12 is a block diagram showing a configuration of a conventional broadband PLL modulation circuit. As shown in FIG. 12, the conventional PLL modulation circuit is output from a VCO (Voltage Controlled Oscillator) 1 whose oscillation frequency changes according to a voltage applied to a control voltage terminal (Vt), and a VCO 1. A frequency divider 2 that divides the frequency of the RF modulation signal (high frequency modulation signal), and a phase comparator 4 that compares the phase of the output signal of the frequency divider 2 with the reference signal and outputs a signal corresponding to the phase difference. And a loop filter 3 that averages the output signal of the phase comparator.

  Further, the conventional PLL modulation circuit modulates the modulation sensitivity table 7 that outputs a signal corresponding to the characteristic of the modulation sensitivity based on the modulation signal, and adjusts the gain of the output signal according to the gain control signal from the control unit 6. A D / A converter 10 that converts the output signal of the sensitivity table 7 into an analog voltage, and a signal obtained by adding channel selection information to the output signal from the modulation sensitivity table 7 are delta-sigma modulated to the frequency divider 2 as a division ratio. A delta-sigma modulator 9 for output and an A / D converter 11 for converting the voltage value of the control voltage terminal (Vt) into a digital signal and outputting the digital signal to the control unit 6 are provided.

  Here, factors affecting the modulation accuracy of the two-point modulation will be described. The main factors that affect the modulation accuracy include the degree of modulation and the time difference between the two points. First, the modulation degree will be described.

  Two-point modulation is a method in which modulation is performed at two different locations as described above. FIG. 2 shows frequency characteristics of a PLL modulation circuit using two-point modulation. Here, the transfer function of the PLL modulation circuit is assumed to be H (s) (where s = jω). H (s) has a low-pass characteristic as shown in FIG. The modulation signal added to the frequency division ratio set in the frequency divider 2 is cut off from the high frequency component by the low pass filter of the transfer function H (s) and passes only the low frequency component. On the other hand, the modulation signal applied to the control voltage terminal of the VCO 1 has its low-frequency component blocked by a high-pass filter having a transfer function 1-H (s) as shown in FIG. 2, and passes only the high-frequency component. Let

  Since these two modulation components are added at the control voltage terminal of the VCO 1, the modulation signal is equivalently given a flat characteristic indicated by a broken line in FIG. 2 and given to the VCO 1. As a result, it is possible to output a broadband RF modulation signal 307 extending from the VCO 1 to the outside of the band of the PLL modulation circuit.

  Here, a case where flat characteristics cannot be applied to the modulation signal will be described. The inability to maintain flat characteristics leads to a decrease in modulation accuracy.

  The characteristic is not flat when the amplitude of the modulation signal input to the control voltage terminal of the VCO 1 is not matched with the modulation sensitivity of the VCO 1. The modulation sensitivity refers to a conversion gain obtained by converting the amplitude of the modulation signal input to the control voltage terminal of the VCO 1 into the frequency shift of the RF modulation signal 307 output from the VCO 1. The unit is [Hz / V]. Further, the ratio between the frequency of the modulation signal and the maximum frequency deviation at this time is referred to as a modulation degree.

  If the modulation sensitivity is not matched, the transfer function 1-H (s) will fluctuate as shown in FIG. FIG. 3 shows a transfer function obtained by multiplying the transfer function 1-H (s) by a shift amount of a. In this case, as indicated by a broken line in FIG. 3, the gain is high at a high frequency, and the synthesis characteristic with H (s) is not flat. This is a factor that degrades the modulation accuracy.

  FIG. 4 shows an example of characteristics representing changes in output frequency with respect to a general VCO control voltage. The modulation sensitivity is represented by the slope of this voltage-frequency characteristic. FIG. 4 shows that the modulation sensitivity of the VCO varies depending on the oscillation frequency.

  FIG. 5 is a graph showing the characteristics of modulation sensitivity with respect to the oscillation frequency of a general VCO. FIG. 5 shows that the modulation sensitivity changes depending on the oscillation frequency.

  Here, an example will be described in which the control voltage (amplitude of the modulation signal) needs to be changed due to the characteristic that the modulation sensitivity of the VCO varies depending on the oscillation frequency. Assume that the modulation sensitivity of the VCO 1 at a frequency of 2 GHz is 100 MHz / V and the maximum frequency shift of the modulation signal is 5 MHz. In this case, it is necessary to input a signal having a maximum amplitude of 50 mV to the control voltage terminal. However, it is assumed that the modulation sensitivity is 80 MHz / V when the frequency of VCO 1 is 2.1 GHz. In this case, it is necessary to input a signal having a maximum amplitude of 62.5 mV to the control voltage terminal. That is, in order to obtain an RF modulation signal having the same frequency shift at different oscillation frequencies, it is necessary to adjust the modulation degree by changing the amplitude of the modulation signal input to the control voltage terminal of the VCO according to the oscillation frequency of the VCO. There is.

  The modulation sensitivity for the modulation component included in the frequency division ratio set in the frequency divider 2 is the frequency of the reference signal and does not change with respect to the frequency of the VCO 1. For example, a case where the frequency of VCO 1 is 2 GHz, the frequency of the reference signal is 1 MHz, and the maximum frequency shift of the modulation signal is assumed to be 5 MHz will be described as an example. In this case, the maximum change ratio of the frequency division ratio is 5. Therefore, the frequency of VCO 1 is irrelevant for this calculation.

  In the conventional PLL modulation circuit of FIG. 12, the modulation sensitivity characteristic with respect to the oscillation frequency of the VCO 1 is held as the modulation sensitivity table 7, and the variation of the control voltage is calculated when the channel frequency changes, thereby correcting the modulation factor. To adjust the gain of the D / A converter.

  The characteristics of the modulation sensitivity vary from LSI to LSI because the values of elements constituting the VCO change due to individual differences (variations) in manufacturing. In the conventional PLL modulation circuit, it is necessary to measure the modulation sensitivity with respect to the frequency for each LSI and hold it in the modulation sensitivity table 7 in order to deal with the fluctuation of the modulation sensitivity characteristic for each LSI caused by these variations.

  In order to prepare the modulation sensitivity table 7, it is necessary to measure the modulation sensitivity with respect to the frequencies of all the channels to be used, and this involves switching the frequency of the PLL modulation circuit by the number of measurement points. Therefore, preparation of the modulation sensitivity table 7 takes a lot of time, which may increase the manufacturing cost.

  Next, the time difference between two points will be described. In the two-point modulation, after modulation is performed at two locations, the values of the respective modulation signals are added and input to the control voltage terminal of the VCO. At this time, if there is a time difference between the modulated signals, the modulation accuracy decreases.

In the conventional PLL modulation circuit, there is no description regarding a method for adjusting a time difference between two points, and therefore it is difficult to set an appropriate timing.
US Pat. No. 6,211,747

  However, the conventional PLL modulation circuit has a problem that it is difficult to improve the modulation accuracy because the modulation degree is lowered and the time difference between the two points is generated as described above.

  The present invention has been made in view of such a point, and an object thereof is to provide a PLL modulation circuit and a polar modulation device capable of improving modulation accuracy.

  A PLL modulation circuit according to a first aspect of the present invention includes a voltage controlled oscillator, a frequency divider that divides the output signal of the voltage controlled oscillator, and a phase comparator that compares the output signal of the frequency divider and a reference signal. A PLL unit that includes: a loop filter that averages the output of the phase comparator; an adder that adds the output of the loop filter and a second modulation input signal and supplies the second modulation input signal to the voltage controlled oscillator; Based on the first modulation signal generation unit that generates the first modulation signal to be input to the frequency divider of the PLL unit, and the second input to the adder of the PLL unit based on the modulation signal A second modulation signal generation unit that generates the first modulation signal, and a first calibration signal generation unit that generates a first calibration signal that is a signal in the PLL band that is input to the frequency divider of the PLL unit. When, A second calibration signal generation unit that generates a second calibration signal that is a signal outside the PLL band that is input to the adder of the PLL unit, the first calibration signal, and the second calibration. A demodulator that demodulates the output signal of the voltage-controlled oscillator when adjusting the modulation degree and time difference of the signal, a low-pass filter that blocks high-frequency from the demodulated signal demodulated by the demodulator, and the demodulated signal Based on the control information, a high-pass filter that cuts off the low-frequency of the signal, a modulation signal control circuit that generates control information by comparing the amplitude and phase of the outputs of the low-pass filter and the high-pass filter, and And a modulation signal adjustment unit that adjusts the first modulation input signal or the second modulation input signal.

  According to this configuration, the first calibration signal and the second calibration signal are demodulated, and the modulation signal adjustment is performed by comparing the amplitude and time difference of the output after passing through the low-pass filter and the high-pass filter. A PLL modulation circuit with improved modulation accuracy can be provided by generating control information for each unit and adjusting the first modulation input signal or the second modulation input signal based on the control information.

  A PLL modulation circuit according to a second aspect of the present invention employs a configuration in which, in the first aspect of the present invention, the first calibration signal and the second calibration signal are sinusoidal signals.

  According to this configuration, the first calibration signal and the second calibration signal have the effects of the first aspect of the present invention, and the first calibration signal and the second calibration signal are sine wave signals. When the two calibration signals are demodulated and the amplitude and phase of the output after passing through the low-pass filter and the high-pass filter are compared, the difference in amplitude and phase can be accurately detected.

  A PLL modulation circuit according to a third aspect of the present invention is the PLL circuit according to the first aspect of the present invention, wherein one of the frequencies of the first calibration signal and the second calibration signal is an integral multiple of the other. The structure which is is taken.

  According to this configuration, the effect of the first aspect of the present invention is obtained, and one of the frequencies of the first calibration signal and the second calibration signal is an integral multiple of the other. The time required for adjustment can be shortened.

  A polar modulation device according to a fourth aspect of the present invention receives an amplitude modulation signal generation unit that generates an amplitude modulation signal, a PLL modulation circuit, and a high-frequency modulation signal output from the PLL modulation circuit as a phase modulation signal. A polar modulation device comprising: a non-linear power amplifier that modulates the phase modulation signal according to a voltage value of the amplitude modulation signal to generate a transmission output signal, wherein the PLL modulation circuit includes: a voltage controlled oscillator; A frequency divider that divides the output signal of the voltage controlled oscillator, a phase comparator that compares the output signal of the divider and a reference signal, a loop filter that averages the output of the phase comparator, and an output of the loop filter And an adder that adds the second modulation input signal to the voltage-controlled oscillator, and inputs to the frequency divider of the PLL unit based on the input modulation signal A first modulation signal generation unit that generates one modulation signal; a second modulation signal generation unit that generates the second modulation signal to be input to the adder of the PLL unit based on the modulation signal; A first calibration signal generation unit that generates a first calibration signal that is a signal within a PLL band that is input to the frequency divider of the PLL unit, and an out-of-PLL band that is input to the adder of the PLL unit A second calibration signal generating unit that generates a second calibration signal that is a signal of the first calibration signal, and the voltage-controlled oscillator during adjustment of a modulation factor and a time difference between the first calibration signal and the second calibration signal A demodulator that demodulates the output signal, a low-pass filter that blocks high-frequency from the demodulated signal demodulated by the demodulator, and A high-pass filter that cuts off a frequency band, a modulation signal control circuit that generates control information by comparing amplitudes and phases of outputs of the low-pass filter and the high-pass filter, and the control signal based on the control information And a modulation signal adjustment unit that adjusts the first modulation input signal or the second modulation input signal.

  According to this configuration, the first calibration signal and the second calibration signal are demodulated, and the modulation signal adjustment is performed by comparing the amplitude and time difference of the output after passing through the low-pass filter and the high-pass filter. A polar modulation device with improved modulation accuracy can be provided by generating control information for each unit and adjusting the first modulation input signal or the second modulation input signal based on the control information.

  A wireless communication device according to a fifth aspect of the present invention includes a polar modulation device according to the fourth aspect of the present invention, a reception processing unit that demodulates a received signal, an antenna, and the polar modulation device to the antenna. A transmission / reception switching unit that switches between transmission signal supply and reception signal supply from the antenna to the reception processing unit is employed.

  According to this configuration, since the wireless communication device is equipped with a PLL modulation circuit and a polar modulation device that can improve the modulation accuracy, it is possible to make a call with a high-accuracy and high-quality transmission signal.

  According to the present invention, it is possible to provide a PLL modulation circuit and a polar modulation device that can improve modulation accuracy.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a PLL modulation circuit according to Embodiment 1 of the present invention. As shown in FIG. 1, a PLL modulation circuit 100 according to Embodiment 1 of the present invention includes a PLL unit 100A. The PLL unit 100A includes a voltage controlled oscillator (hereinafter referred to as VCO) 101, a frequency divider 102, a phase comparator 104, a loop filter 103, and an adder 116.

The VCO 101 changes the oscillation frequency according to the voltage input to the control voltage terminal. The frequency divider 102 divides the frequency of the RF modulation signal 307 output from the VCO 101. The phase comparator 104 compares the phases of the output signal 304 of the frequency divider 102 and the reference signal 306 and outputs a signal 301 corresponding to the phase difference. The loop filter 103 outputs a signal 302 obtained by averaging the output signal 301 of the phase comparator 104. The adder 116 adds the value of the signal 302 from the loop filter 103 and the value of the modulation signal 305 to generate an input signal 303 to the VCO 101.

  The PLL modulation circuit 100 according to the first embodiment of the present invention includes a calibration signal generation unit 109, selectors 107 and 108, a frequency division ratio generation unit 105, a modulation signal adjustment unit 106, and an operation switching control unit 1100. ing.

  The modulation signal generation unit 110 generates a modulation signal. The calibration signal generation unit 109 generates calibration signals 308 and 309. The selectors 107 and 108 select one of the calibration signals 308 and 309 and the modulation signal 310 according to the selection instruction signal 1101 from the operation switching control unit 1100. The frequency division ratio generator 105 combines the output signal 311 of the selector 107 and the carrier frequency data 319 to generate the frequency division ratio 313. The modulation signal adjustment unit 106 outputs the modulation signal 305 having the modulation degree and the time difference adjusted based on the output signal 312 of the selector 108 and the control information 318.

  The operation switching control unit 1100 alternately generates a selection instruction signal 1101 for instructing the selection of the calibration signals 308 and 309 and a selection instruction signal 1101 for instructing the selection of the modulation signal 310 and supplies them to the selectors 107 and 108. The selectors 107 and 108 select the calibration signals 308 and 309 according to the selection instruction signal 1101 for instructing the selection of the calibration signals 308 and 309, and provide them to the frequency division ratio generation unit 105 and the modulation signal adjustment unit 106. Further, the selectors 107 and 108 select the modulation signal 310 according to the selection instruction signal 1101 for instructing the selection of the modulation signal 310, and provide it to the frequency division ratio generation unit 105 and the modulation signal adjustment unit 106.

  When the operation switching control unit 1100 generates the selection instruction signal 1101 for instructing the selection of the calibration signals 308 and 309, it is an adjustment operation for executing the adjustment operation of the modulation signal 305. Further, when the operation switching control unit 1100 generates the selection instruction signal 1101 for instructing the selection of the modulation signal 310, it is during the modulation operation for executing the modulation operation.

  Furthermore, the PLL modulation circuit 100 according to the first embodiment of the present invention includes a demodulator 111, an A / D converter 112, a low-pass filter 113, a high-pass filter 114, and a modulation signal control circuit 115. .

  The demodulator 111, the A / D converter 112, the low-pass filter 113, the high-pass filter 114, and the modulation signal control circuit 115 are a selection instruction signal that instructs the operation switching control unit 1100 to select the calibration signals 308 and 309. The operation is executed only when 1101 is generated, that is, only during the adjustment operation.

  The demodulator 111 demodulates the RF modulation signal 307 output from the VCO 101. The A / D converter 112 converts the output signal 314 of the demodulator 111 into a digital signal. The low-pass filter 113 generates a signal 316 in which a high-frequency component outside the band of the PLL modulation circuit 100 is cut off from the output signal 315 of the A / D converter 112. The high-pass filter 114 generates a signal 317 that blocks a low-frequency component in the band of the PLL modulation circuit 100 in the output signal 315 of the A / D converter 112. The modulation signal control circuit 115 compares the phase and amplitude of the output signal 316 of the low-pass filter 113 and the output signal 317 of the high-pass filter 114 and transmits control information 318 to the modulation signal adjustment unit 106.

  The calibration signal generation unit 109 outputs two types of calibration signals 308 and 309. In FIG. 1, the calibration signal 308 is input to the selector 107, and the calibration signal 309 is input to the selector 108.

  Next, the modulation operation of the PLL modulation circuit 100 according to the first embodiment will be described. During the modulation operation, the selectors 107 and 108 select and output the modulation signal 310 output from the modulation signal generation unit 110. The output signal (modulation signal) 311 output from the selector 107 generates a frequency division ratio for the frequency divider 102 by the frequency division ratio generation unit 105 and modulates the PLL unit 100A.

  Also, the output signal (modulation signal) 312 output from the selector 108 is input to the adder 116 as the modulation signal 305 whose modulation degree and time difference are adjusted with respect to the signal 302 in the modulation signal adjustment unit 106, and the input signal of the VCO 101. 303 can be modulated. The modulation signal adjustment unit 106 has a control information holding unit, and initially sets a predetermined value in the control information holding unit, and receives control information 318 from the modulation signal control circuit 115 and holds it in the control information holding unit. Update control information. Then, the modulation signal adjustment unit 106 delays the modulation signal 312 based on the control information held in the control information holding unit, and adjusts the gain of the modulation signal 312 to thereby adjust the time difference and the modulation with respect to the signal 302. A modulation signal 305 adjusted in degree is generated and supplied to the adder 116.

  In this way, modulation is performed by controlling the frequency division ratio of the frequency divider 102 and the control voltage of the VCO 101. That is, wideband modulation is possible by applying modulation at two different locations.

  Next, the adjustment operation in the PLL modulation circuit 100 according to the first embodiment, that is, the modulation degree adjustment operation will be described.

  The calibration signal 308 used in the adjustment operation is a sine wave signal having a frequency component within the band of the PLL modulation circuit 100 generated by the calibration signal generation unit 109. The other calibration signal 309 is a sine wave signal having a frequency component outside the band of the PLL modulation circuit 100 generated by the calibration signal generation unit 109. Further, the calibration signals 308 and 309 are output simultaneously.

  Here, FIG. 2 is a diagram illustrating a transfer function of the PLL modulation circuit 100. The high frequency component of the modulated signal applied to the frequency divider 102 is blocked by the low pass filter 113 having a frequency characteristic as shown by the transfer function H (s) in FIG. 2, and only the low frequency component is allowed to pass. Further, as shown by the transfer function 1-H (s) in FIG. 2, the low-frequency component is blocked by the high-pass filter 114, and only the high-frequency component is allowed to pass through the modulated signal applied to the VCO 101.

Therefore, the calibration signals 308 and 309 are preferably at frequencies that do not affect the gain of the PLL modulation circuit for these inputs. For example, as in f _c1 and f _c2 shown in FIG. 2, the calibration signal 308 has a frequency at which the gain of the out-of-band modulation of the PLL modulation circuit 100 is sufficiently low, and the calibration signal 309 is the frequency of the PLL modulation circuit 100. The frequency is such that the gain due to in-band modulation is sufficiently low.

Here, the calibration signal generation unit 109 sets the calibration signal so that the maximum frequency deviations of f _c1 and f _c2 are the same. As described above, the product of the maximum change ratio of the frequency division ratio and the comparison frequency of the reference signal is the maximum frequency deviation of the output signal. Therefore, even if the modulation sensitivity to the control voltage of the VCO 101 varies, the output of the VCO 101 The amplitude does not vary.

  During the adjustment operation, as described above, the selector 107 selects and outputs the calibration signal 308, and the selector 108 selects and outputs the calibration signal 309.

  An output signal (calibration signal) 311 output via the selector 107 is output as an output signal 302 from the loop filter 103 via the frequency divider 102 and the phase comparator 104. First, the frequency division ratio generation unit 105 generates a frequency division ratio according to the carrier frequency data 319, and locks the PLL unit 100A to a frequency according to the carrier frequency data 319. When the PLL unit 100A locks to a frequency corresponding to the carrier frequency data 319, the calibration signal generation unit 109 outputs a calibration signal 308 having a frequency within the band of the PLL modulation circuit 100.

  Next, the calibration signal 308 output from the calibration signal generation unit 109 is input to the frequency division ratio generation unit 105 via the selector 107, and the frequency division ratio generation unit 105 generates and divides the frequency division ratio. Modulate the frequency divider 102.

  At the same time, a signal (calibration signal) 312 output via the selector 108 is output as a modulation signal 305 by the modulation signal adjustment unit 106. The adder 116 outputs an output signal 303 obtained by adding the value of the output signal 302 of the loop filter 103 and the value of the modulation signal 305 of the modulation signal adjustment unit 106.

  The output signal 303 of the adder 116 is input to the VCO 101. The VCO 101 outputs an RF modulation signal 307 modulated at the frequency of the signal 303 obtained by adding the modulation signal within the band of the PLL modulation circuit 100 and the modulation signal outside the band of the PLL modulation circuit 100. The demodulator 111 demodulates the RF modulation signal 307 and outputs a modulation signal 314. The A / D converter 112 converts the modulated signal 314 from the demodulator into a digital signal and outputs a signal 315. The low pass filter 113 blocks the high frequency of the output signal 315 from the A / D converter 112 and outputs a signal 316. The high pass filter 114 cuts off the low frequency of the output signal 315 from the A / D converter 112 and outputs a signal 317.

  The modulation signal control circuit 115 compares the value of the output signal 316 from the low-pass filter 113 with the value of the output signal 317 from the high-pass filter 114, and adjusts the modulation signal when there is a time difference between the signals. The control information 318 for correcting the time difference is generated by the unit 106, and if there is an amplitude difference between the signals, the control information 318 for correcting the amplitude difference is generated by the modulation signal adjusting unit 106.

  The control information 318 generated by the modulation signal control circuit 115 is sent to the modulation signal adjustment unit 106, and the modulation signal adjustment unit 106 updates the control information in the control information holding unit. In FIG. 1, the modulation signal control circuit 115 adjusts only the calibration signal 309 and the output signal 312 of the selector 108 through which the modulation signal 310 passes. You may adjust.

Here, the operation and principle of adjusting the modulation factor and the time difference in the modulation signal control circuit 115 will be described. A signal 314 output as a result of demodulating the RF modulation signal 307 by the demodulator 111 is equivalent to the output 303 of the adder 116. By comparing the calibration signals f _c1 and f _c2 included in the signal 314 and calculating the amplitude difference and the time difference, the modulation degree and the time difference between the two points can be adjusted.

Further, in order to facilitate the comparison of the calibration signals, the calibration signals f _c1 and f _c are converted using the low-pass filter 113 and the high-pass filter 114 after being converted into digital signals using the A / D converter 112. _c2 is separated and taken out. By converting to a digital signal, it is possible to calculate an amplitude difference and a time difference between two points from the amplitude information and phase information of the output signal 316 and the output signal 317 without being affected by variations. A specific method for comparing signals will be described later.

At this time, the frequencies of the calibration signals f _c1 and f _c2 are adjusted without any special relationship except that f _c1 is a frequency within the PLL band and f _c2 is a frequency outside the PLL band. It is possible to adjust that the frequencies of f _c1 and f _c2 have a relationship in which one frequency is N (N is an integer) times the other, or N times the same specific frequency. It is more preferable because the time required can be shortened.

Next, operation examples of the amplitude difference detection method and the time difference detection method for the modulation signal control circuit 115 will be described. In the calibration signals f _c1 and f _c2 used here, as described above, f _c1 is a frequency at which the gain of out-of-band modulation of the PLL modulation circuit 100 is sufficiently low, and f _c2 is within the band of the PLL modulation circuit 100. The frequency is such that the gain due to modulation is sufficiently low. 6 and 7 show the signal f _c1 and the signal f _c2 .

FIG. 8 shows a signal demodulated by the demodulator 111, which is equivalent to the signal 307 output by adding the calibration signals f _c1 and f _c2 by the adder 116. The signal 314 is A / D converted at a sampling frequency that allows the original signal to be extracted with sufficient accuracy, and input to the low-pass filter 113 and the high-pass filter 114. This operation signal 316 is able to extract the signal having the same frequency as the calibration signal f _c1, the signal 317 can extract the signal of the same frequency as the calibration signal f _c2.

Output signals 317 and 318 from the low-pass filter 113 and the high-pass filter 114 are input to the modulation signal control circuit 115. FIG. 9A shows a comparison operation in the modulation signal control circuit 115 when the frequency between the calibration signals f _c1 and f _c2 is N times. The amplitude difference between the signals input to the modulation signal control circuit 115 can be calculated by comparing the amplitudes of the signal peaks. Further, the time difference can be calculated from the fact that there is no time difference if the phases are regularly matched by comparing the phases at the time when the signals are input. In the case of FIG. 9 (a), the phase of the signal matches every cycle of the calibration signal _fc1 .

As shown in FIG. 9B, when there is no N-fold frequency relationship between the calibration signals f _c1 and f _c2 and there is a delay in one of the signals, the delay is applied to either one of the signals. and controlling a modulation signal adjustment unit 106 via the modulation signal control circuit 115 to provide, as the phase of the calibration signals f _c1 and f _c2 matches for each cycle of the least common multiple of the frequency of the calibration signal f _c1 and f _c2 You can do it.

  In the PLL modulation circuit 100 according to the first embodiment of the present invention, signals are input to two different places in the PLL unit 100A to detect amplitude differences and time differences, and modulation is performed based on these amplitude differences and time differences. The modulation signal adjustment unit 106 adjusts the modulation signal 312 so as to correct the signal 312, so that the modulation accuracy can be improved. Such a PLL modulation circuit 100 is applicable to, for example, a modulation system such as a polar modulation system, a wireless communication device such as a mobile communication terminal device and a radio base station, and the like. A communication device or the like can be provided.

  Note that the demodulator 111, the A / D converter 112, the low-pass filter 113, the high-pass filter 114, and the modulation signal control circuit 115 are not integrated in the same IC, but a demodulator and an adjustment device are separately provided. May be provided. Further, the calibration signals 308 and 309 are not limited to sine wave signals.

(Embodiment 2)
FIG. 10 is a block diagram showing a configuration of a polar modulation device according to Embodiment 2 of the present invention. In the second embodiment of the present invention, the same components as those in the first embodiment of the present invention are designated by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 10, a polar modulation apparatus 200 according to Embodiment 2 of the present invention includes a nonlinear power amplifier 201 and an amplitude modulation signal generation unit 202 in addition to the PLL modulation circuit 100 according to Embodiment 1 of the present invention. Prepare.

  The RF modulation signal 307 from the VCO 101 of the PLL modulation circuit 100 is input to the nonlinear power amplifier 201 as a phase modulation signal. The amplitude modulation signal generation unit 202 generates the amplitude modulation signal 2021 and supplies it to the nonlinear power amplifier 201 as a control signal. The nonlinear power amplifier 201 modulates the RF modulation signal 307 according to the voltage value of the amplitude modulation signal 2021 to generate and output a transmission output signal 3071. With the above configuration, a polar modulation device with improved modulation accuracy can be provided.

  In the second embodiment of the present invention, the demodulator 111 demodulates the transmission output signal 3071 output from the nonlinear power amplifier 201 to demodulate the A / D converter 112, the low-pass filter 113, and the high-pass filter 114. The modulation signal control circuit 115 may be provided via In this case, it is necessary for the demodulator 111 to demodulate the transmission output signal 3071 output from the nonlinear power amplifier 201 in a state where the amplitude modulation signal generation unit 202 does not supply the amplitude modulated signal 2021 to the nonlinear power amplifier 201.

(Embodiment 3)
FIG. 11 is a block diagram showing a configuration of a wireless communication device according to Embodiment 3 of the present invention. In the third embodiment of the present invention, the same components as those in the second embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 11, radio communication apparatus 400 according to Embodiment 3 of the present invention includes PLL modulation circuit 100, nonlinear power amplifier 201, and amplitude modulation signal generation of polar modulation apparatus 200 according to Embodiment 2 of the present invention. In addition to the unit 202, the transmission / reception switch 401, the antenna 402, and the reception device 403 are provided. The transmission / reception switch 401 supplies the transmission signal from the PLL modulation circuit 100 of the polar modulation device 200 to the antenna 402, and the antenna 402. To supply the reception signal to the reception device 403.

  The non-linear power amplifier 201 provides a transmission output signal 3071 to the transmission / reception switch 401. The transmission / reception switch 401 receives the transmission output signal 3071 from the nonlinear power amplifier 201 and provides it to the antenna 402. The antenna 402 receives the transmission output signal 3071 from the transmission / reception switch 401 and generates and transmits a wireless transmission signal.

  In addition, the antenna 402 receives a transmission signal from the counterpart wireless communication device, generates a reception signal, and supplies the reception signal to the transmission / reception switch 401. The transmission / reception switch 401 receives a reception signal from the antenna 402 and gives it to the reception device 403.

  According to the above configuration, a wireless communication device equipped with a PLL modulation circuit and a polar modulation device that can improve modulation accuracy can be used to make a call with a high-accuracy and high-quality transmission signal.

  The present invention is useful for radio communication apparatuses such as mobile radios and radio base station apparatuses.

1 is a block diagram showing a configuration of a PLL modulation circuit according to Embodiment 1 of the present invention. The figure which shows the frequency characteristic for operation | movement description of a PLL modulation circuit The figure which shows the frequency characteristic for operation | movement description of a PLL modulation circuit The figure which shows an example of the characteristic showing the change of the output signal frequency with respect to the control voltage of a general VCO The figure which showed the characteristic of the modulation sensitivity with respect to the oscillation frequency of the general VCO The figure which shows the in-band input signal of the PLL modulation circuit for operation | movement description of modulation degree adjustment The figure which shows the out-of-band input signal of the PLL modulation circuit for operation | movement description of modulation degree adjustment The figure which shows the added signal for operation | movement description of a modulation degree adjustment (A) Diagram for explaining calculation of amplitude difference and phase difference for explaining operation of modulation degree adjustment and time difference adjustment, (b) Amplitude difference and phase difference for explaining operation of modulation degree adjustment and phase difference adjustment Another diagram to explain the calculation of The block diagram which shows the structure of the polar modulation apparatus which concerns on Embodiment 2 of this invention. Block diagram showing a configuration of a wireless communication device according to a third embodiment of the present invention The block diagram which shows the structure of the conventional PLL modulation circuit

Explanation of symbols

101 Voltage controlled oscillator (VCO)
102 Frequency Divider 103 Loop Filter 104 Phase Comparator 105 Frequency Division Ratio Generation Unit 116 Adder 106 Modulation Signal Adjustment Unit 107, 108 Selector 109 Calibration Signal Generation Unit 110 Modulation Signal Generation Unit 1100 Operation Switching Control Unit 111 Demodulator 112 A / D converter 113 Low-pass filter 114 High-pass filter 115 Modulation signal control circuit 200 Polar modulator 201 Nonlinear power amplifier 202 Amplitude modulation signal generator 400 Wireless communication device 401 Transmission / reception switch 402 Antenna 403 Receiver

Claims (5)

A voltage controlled oscillator, a frequency divider for dividing the output signal of the voltage controlled oscillator, a phase comparator for comparing the output signal of the frequency divider with a reference signal, and an output of the phase comparator are averaged A PLL unit comprising: a loop filter; and an adder that adds the output of the loop filter and a second modulation input signal to give to the voltage controlled oscillator;
A first modulation signal generation unit that generates a first modulation signal to be input to the frequency divider of the PLL unit based on an input modulation signal;
A second modulation signal generation unit that generates the second modulation signal to be input to the adder of the PLL unit based on the modulation signal;
A first calibration signal generation unit that generates a first calibration signal that is a signal in a PLL band that is input to the frequency divider of the PLL unit;
A second calibration signal generation unit that generates a second calibration signal that is a signal outside the PLL band to be input to the adder of the PLL unit;
A demodulator that demodulates the output signal of the voltage-controlled oscillator when adjusting the modulation degree and time difference between the first calibration signal and the second calibration signal;
A low-pass filter that blocks high-frequency from the demodulated signal demodulated by the demodulator;
A high-pass filter that blocks low-frequency from the demodulated signal;
A modulation signal control circuit that generates control information by comparing amplitudes and phases of outputs of the low-pass filter and the high-pass filter;
A modulation signal adjusting unit that adjusts the first modulation input signal or the second modulation input signal based on the control information;
A PLL modulation circuit comprising:   The PLL modulation circuit according to claim 1, wherein the first calibration signal and the second calibration signal are sinusoidal signals.   2. The PLL modulation circuit according to claim 1, wherein one of the frequencies of the first calibration signal and the second calibration signal is an integral multiple of the other one. An amplitude modulation signal generation unit that generates an amplitude modulation signal, a PLL modulation circuit, and a high frequency modulation signal output from the PLL modulation circuit are input as a phase modulation signal, and the phase modulation signal is output according to a voltage value of the amplitude modulation signal. A polar modulation device comprising: a non-linear power amplifier that modulates a signal to generate a transmission output signal;
The PLL modulation circuit includes:
A voltage controlled oscillator, a frequency divider for dividing the output signal of the voltage controlled oscillator, a phase comparator for comparing the output signal of the frequency divider with a reference signal, and an output of the phase comparator are averaged A PLL unit comprising: a loop filter; and an adder that adds the output of the loop filter and a second modulation input signal to give to the voltage controlled oscillator;
A first modulation signal generation unit that generates a first modulation signal to be input to the frequency divider of the PLL unit based on an input modulation signal;
A second modulation signal generation unit that generates the second modulation signal to be input to the adder of the PLL unit based on the modulation signal;
A first calibration signal generation unit that generates a first calibration signal that is a signal in a PLL band that is input to the frequency divider of the PLL unit;
A second calibration signal generation unit that generates a second calibration signal that is a signal outside the PLL band to be input to the adder of the PLL unit;
A demodulator that demodulates the output signal of the voltage-controlled oscillator when adjusting the modulation degree and time difference between the first calibration signal and the second calibration signal;
A low-pass filter that blocks high-frequency from the demodulated signal demodulated by the demodulator;
A high-pass filter that blocks low-frequency from the demodulated signal;
A modulation signal control circuit that generates control information by comparing amplitudes and phases of outputs of the low-pass filter and the high-pass filter;
A modulation signal adjusting unit that adjusts the first modulation input signal or the second modulation input signal based on the control information;
A polar modulation device comprising: A polar modulation device according to claim 4;
A reception processing unit for demodulating the received signal;
An antenna,
A transmission / reception switching unit that switches between supply of a transmission signal from the polar modulation device to the antenna and supply of a reception signal from the antenna to the reception processing unit;
A wireless communication device comprising:

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