JP2005303191A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which suppresses a progression of a corrosion of a wiring including a copper. <P>SOLUTION: The method for manufacturing the semiconductor device comprises steps of: forming a lower wiring 3 having a top face 3a and including the copper; forming a diffusion preventing film 4 so as to cover the top face 3a; forming a contact hole 8 reaching the top face 3a in the diffusion preventing film 4 by etching processing a part of the diffusion preventing film 4 with the use of an etchant including a fluorocarbon system gas; and plasma processing the lower wiring 3 exposing from the contact hole 8 with the use of a gas including at least one type selected from a group comprising nitrogen, argon, and hydrogen after the step of forming the contact hole 8. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a copper wiring is formed using a damascene method.

With the miniaturization and speeding up of semiconductor devices, copper having a low electrical resistance has recently been used as a wiring material. When copper wiring is manufactured using the damascene method, for example, a copper wiring film, a diffusion prevention film, an organic low dielectric constant film, and a SiO ₂ film are sequentially deposited on the substrate. Forming a resist film having an opening in a predetermined position on the SiO ₂ film, using the resist film as a mask, to etch the SiO ₂ film and the organic low dielectric constant film. After removing the resist film, the diffusion preventing film is further etched using the SiO ₂ film as a mask to form a contact hole reaching the copper wiring film. The contact hole is filled with a conductive film to form a contact plug connected to the copper wiring film.

  In addition, Japanese Patent Laid-Open No. 2003-303811 discloses a mixture containing a chlorine component or bromine component gas, an oxygen gas, and a reducing gas at the time of etching the barrier film provided as the diffusion preventing film. A plasma etching method using a gas as an etching gas is disclosed (Patent Document 1). Japanese Laid-Open Patent Publication No. 11-297678 discloses a method for manufacturing a semiconductor device for preventing re-deposition of unnecessary products when etching a barrier metal film and a tungsten film containing titanium. (Patent Document 2). According to the method for manufacturing a semiconductor device disclosed in Patent Document 2, after etching a barrier metal film and a tungsten film formed on an interlayer insulating film, an inert gas such as argon is introduced into the etching apparatus, and the semiconductor Expose the substrate to plasma.

Furthermore, Japanese Patent Laid-Open No. 4-273442 discloses a wiring formation method for preventing oxidation of a formed pattern after dry etching of a Cu-based material layer (Patent Document 3). According to the wiring forming method disclosed in Patent Document 3, after a Cu electrode pattern is produced by dry etching using NO ₂ gas, an oxygen-containing layer formed on the side wall portion of the Cu electrode pattern is replaced with NH ₃ gas or the like. Reduced and removed by plasma treatment using
JP 2003-303811 A JP 11-297678 A JP-A-4-273442

  When etching the diffusion barrier film formed on the copper wiring film, the copper wiring film exposed by the etching is exposed to the etchant. At this time, since corrosion of copper constituting the copper wiring film proceeds, there arises a problem that the resistance of the copper wiring increases or the contact resistance between the copper wiring and the contact plug increases.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems and to provide a semiconductor device manufacturing method that suppresses the progress of corrosion of wiring containing copper.

  A method of manufacturing a semiconductor device according to the present invention uses a step of forming a wiring having a surface and containing copper, a step of forming a diffusion prevention film so as to cover the surface, and an etchant containing a fluorocarbon-based gas. And etching at least part of the diffusion prevention film to form a hole reaching the surface of the wiring in the diffusion prevention film, and after forming the hole, at least one selected from the group consisting of nitrogen, argon and hydrogen And a step of plasma-treating the wiring exposed from the hole by using a gas containing gas.

  According to this invention, it is possible to provide a method for manufacturing a semiconductor device that suppresses the progress of corrosion of wiring containing copper.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a semiconductor device manufactured by using the method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, a semiconductor device includes an interlayer insulating film 1 having a top surface 1a, a lower wiring 3 formed on the interlayer insulating film 1, a diffusion prevention film 4 and an interlayer deposited sequentially on the top surface 1a. An insulating film 5 and a contact plug 10 formed in the interlayer insulating film 5 and connected to the lower wiring 3 are provided.

  A groove 12 extending in the depth direction of the paper surface shown in FIG. 1 is formed in the interlayer insulating film 1. A diffusion preventing film 2 is formed in the groove 12 so as to cover the inner wall thereof. The diffusion prevention film 2 is formed of a laminated body of tantalum (Ta) and tantalum nitride (TaN), for example. A lower wiring 3 is formed on the diffusion prevention film 2 so as to fill the inside of the groove 12. The lower wiring 3 is made of copper (Cu) and has a top surface 3 a that is continuous with the top surface 1 a of the interlayer insulating film 1 on the same plane.

  A diffusion prevention film 4 is formed on the top surfaces 1 a and 3 a, and an interlayer insulating film 5 is further formed on the diffusion prevention film 4. The diffusion prevention film 4 is made of, for example, SiC, SiCN, SiN, or the like. The interlayer insulating films 1 and 5 are made of, for example, a silicon oxide film, TEOS (tetra etyle orthosilicate), SiOF, SOG (spin on glass), or the like. Further, it may be made of a low dielectric constant material (Low-k material).

  In the interlayer insulating film 5 and the diffusion preventing film 4, a contact hole 8 is formed which opens to the top surface 5 a side of the interlayer insulating film 5 and reaches the top surface 3 a of the lower wiring 3. A diffusion barrier film 6 is formed in the contact hole 8 so as to cover the inner wall thereof. The diffusion preventing film 6 is formed from, for example, a laminate of tantalum and tantalum nitride. A contact plug 10 is formed on the diffusion prevention film 6 so as to fill the inside of the contact hole 8. The contact plug 10 is made of copper. A trench may be formed in place of the contact hole 8.

  Next, a process for manufacturing the semiconductor device in FIG. 1 by the method for manufacturing the semiconductor device in the present embodiment will be described. 2 and 3 are cross-sectional views showing respective steps of the method of manufacturing the semiconductor device in FIG.

  Referring to FIG. 2, a lower wiring layer including diffusion prevention film 2 and lower wiring 3 is formed in interlayer insulating film 1 by a normal damascene method. Next, the diffusion preventing film 4 and the interlayer insulating film 5 are sequentially formed on the top surface 1 a of the interlayer insulating film 1.

Referring to FIG. 3, a resist film (not shown) is formed on top surface 5 a of interlayer insulating film 5. The interlayer insulating film 5 is etched using the resist film (not shown) as a mask, and then the resist film is removed. Subsequently, the semiconductor device is placed in a predetermined processing chamber, and the diffusion preventing film 4 is etched using the etched interlayer insulating film 5 as a mask. Thereby, a contact hole 8 reaching the top surface 3 a of the lower wiring 3 is formed in the interlayer insulating film 5 and the diffusion preventing film 4. At this time, CF ₄ gas, which is a fluorocarbon-based gas, is used as an etchant for etching the diffusion prevention film 4. In addition to CF ₄ gas, CHF ₃ gas, CH ₂ F ₂ gas, CH ₃ F gas, or a mixed gas thereof can also be used. When these gases are used for etching the diffusion prevention film 4 formed of SiC, SiCN, SiN, or the like, the etching rate and the shape controllability of etching can be improved.

After the above etching process is completed, a plasma process using nitrogen (N ₂ ) gas is performed in the same process chamber as the process chamber in which the etching process is performed. At this time, the plasma treatment conditions are as follows: nitrogen gas flow rate: 200 sccm to 800 sccm, treatment atmosphere pressure: 3 Pa to 10 Pa, ion energy: 50 eV to 500 eV. The unit sccm represents the gas flow rate (cm ³ / min) in the standard state (1013 hPa, 273 K).

Fluorine (F) remains on the top surface 3a of the lower wiring 3 exposed from the contact hole 8 by etching using a fluorocarbon-based gas. Therefore, by performing a plasma treatment using nitrogen gas, the concentration of fluorine remaining on the top surface 3a can be reduced and the top surface 3a can be cleaned. Thereby, it is possible to prevent CuF _{2 and the} like from being formed by the reaction between copper and fluorine constituting the lower wiring 3. The fluorine concentration on the top surface 3a is preferably 10 atomic% or less.

Furthermore, in this embodiment mode, since the plasma processing step is performed in the same processing chamber as the etching processing step, the semiconductor device is not exposed to the atmosphere between the etching processing step and the plasma processing step. Thereby, the reaction product of copper or copper and fluorine constituting the lower wiring 3 reacts with oxygen (O ₂ ) or water vapor (H ₂ O) present in the atmosphere to form Cu ₂ O or the like. Can be prevented. Further, when the plasma treatment step and the etching treatment step are performed in the same treatment chamber, it is not necessary to move the semiconductor device between these steps, so that the production efficiency of the semiconductor device can be improved.

  Referring to FIG. 1, next, a diffusion prevention film 6 is formed so as to cover a range from the inner wall of the contact hole 8 to the top surface 5 a of the interlayer insulating film 5. Further, a copper film is formed on the diffusion prevention film 6 so as to fill the inside of the contact hole 8. The copper film and the diffusion preventing film on the top surface 5 a are removed by CMP (chemical mechanical polishing), and a contact plug 10 is formed inside the contact hole 8. Through the above steps, the semiconductor device shown in FIG. 1 is completed.

In the above-described manufacturing process, nitrogen gas is used at the time of plasma treatment. However, the present invention is not limited to this, and argon (Ar) gas or hydrogen (H ₂ ) gas may be used.

  In addition, there is a method in which the semiconductor device can be kept in a state where the semiconductor device is not exposed to the atmosphere between these steps even when the processing chamber for etching and the processing chamber for plasma processing are not the same. FIG. 4 is a plan view showing a semiconductor manufacturing apparatus for manufacturing the semiconductor device in FIG. Referring to FIG. 4, the semiconductor manufacturing apparatus includes a load port 23 for setting a cassette in which semiconductor wafers are accommodated, a processing chamber 21 for performing an etching process, and a processing chamber 22 for performing a plasma process. And a buffer chamber 24 provided between these rooms. A transfer robot is arranged in the buffer chamber 24, and the chamber is kept in a vacuum state. With the semiconductor manufacturing apparatus provided with such a buffer chamber 24, the semiconductor device that has been subjected to the etching process in the processing chamber 21 can be transferred to the processing chamber 22 where plasma processing is performed without being exposed to the atmosphere. .

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a lower wiring 3 having a top surface 3a as a surface and a copper-containing wiring, and forming a diffusion prevention film 4 so as to cover the top surface 3a. A step of etching part of the diffusion preventing film 4 using an etchant containing a fluorocarbon-based gas to form a contact hole 8 as a hole reaching the top surface 3a in the diffusion preventing film 4, and a contact hole 8 And a step of plasma-treating the lower wiring 3 exposed from the contact hole 8 using a gas containing at least one selected from the group consisting of nitrogen, argon and hydrogen.

  In addition to the parallel plate type capacitively coupled plasma processing apparatus, the plasma processing performed on the semiconductor device includes other plasma processing apparatuses such as a magnetic field electromagnetic radiation discharge type plasma processing apparatus and an inductively coupled plasma. The present invention can also be applied to a plasma processing apparatus using another discharge method such as a processing apparatus.

  Next, an example of a method for manufacturing a semiconductor device according to the present invention will be described. Note that a parallel plate type capacitively coupled plasma processing apparatus was used for plasma processing of the semiconductor device.

  FIG. 5 is a graph showing the relationship between plasma processing time and fluorine concentration. Plasma treatment using nitrogen gas was performed at a gas flow rate of 400 sccm, a processing atmosphere pressure of 5.3 Pa, ion energy of 500 eV, and the fluorine concentration remaining on the top surface 3 a of the lower wiring 3 was measured. At this time, the relationship between the plasma processing time and the fluorine concentration was determined by changing the processing time. As can be seen with reference to FIG. 5, the fluorine concentration could be reduced to a level of 10 atomic% or less with a short plasma treatment. Further, it was confirmed that the lower wiring 3 was not corroded when the processing time was 10 seconds.

  FIG. 6 is a graph showing the relationship between the magnitude of ion energy and the fluorine concentration. Plasma treatment using nitrogen gas was performed at a gas flow rate of 400 sccm, a treatment atmosphere pressure of 5.3 Pa, a treatment time of 60 seconds, and the fluorine concentration remaining on the top surface 3a of the lower wiring 3 was measured. At this time, the relationship between the magnitude of the ion energy and the fluorine concentration was determined by changing the magnitude of the ion energy. As can be seen with reference to FIG. 6, the higher the ion energy, the more effective the fluorine concentration could be reduced.

  FIG. 7 is a cross-sectional view showing the semiconductor device after plasma processing when ion energy is too high. Referring to FIG. 7, as described above, it is advantageous to increase the ion energy when it comes to reducing the fluorine concentration. However, when the ion energy is too high, the top surface 5a of the interlayer insulating film 5 is used. There is a possibility that the shoulder 8m from the contact hole 8 to the inner wall of the contact hole 8 may be greatly shaved or the bottom surface 8n of the contact hole 8 may be formed deep inside the lower wiring 3. In this case, there arises a problem that a short circuit occurs between adjacent wirings and the reliability of the wirings is lowered. Therefore, it is preferable to perform plasma processing with low ion energy, for example, it is preferable to perform plasma processing with ion energy of less than 500 eV.

  FIG. 8 is a graph showing the residual fluorine concentration when different processing gases are used. Plasma treatment using nitrogen gas was performed at a gas flow rate of 400 sccm, an ion energy of 500 eV, a processing atmosphere pressure of 5.3 Pa, a processing time of 60 seconds, and a fluorine concentration remaining on the top surface 3a of the lower wiring 3 Was measured. At this time, three types of processing gases, nitrogen gas, argon gas, and hydrogen gas, were used, and the residual fluorine concentration when the plasma processing was performed with each processing gas was determined. As can be seen with reference to FIG. 8, the fluorine concentration was most reduced when nitrogen gas was used. Further, when the plasma treatment was not performed, corrosion was observed on the wiring. However, when the plasma treatment was performed, no corrosion was observed in any of the processing gases.

  According to the method of manufacturing a semiconductor device configured as described above, the plasma processing using a predetermined gas is performed after the etching processing step, so that the top surface 3a of the lower wiring 3 exposed by the etching processing is hooked. It is possible to suppress the progress of conversion. Further, by keeping the semiconductor device not exposed to the atmosphere during these steps, it is possible to further suppress the progress of oxidation on the top surface 3a of the lower wiring 3. By suppressing the progress of the fluorination and oxidation, the lower wiring 3 can be prevented from being corroded. As a result, the electrical resistance of the lower wiring 3 can be prevented from increasing, and the contact resistance between the lower wiring 3 and the contact plug 10 can be prevented from increasing.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which shows the semiconductor device produced using the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing which shows the 1st process of the method of manufacturing the semiconductor device in FIG. It is sectional drawing which shows the 2nd process of the method of manufacturing the semiconductor device in FIG. It is a top view which shows the semiconductor manufacturing apparatus for manufacturing the semiconductor device in FIG. It is a graph which shows the relationship between plasma processing time and fluorine concentration. It is a graph which shows the relationship between the magnitude | size of ion energy, and a fluorine concentration. It is sectional drawing which shows the semiconductor device after a plasma process when ion energy is too high. It is a graph which shows the residual fluorine density | concentration at the time of using different process gas.

Explanation of symbols

  1,5 interlayer insulation film, 1a, 3a top surface, 3 lower wiring, 4 diffusion prevention film, 8 contact hole, 10 contact plug.

Claims (4)

Forming a wiring having a surface and including copper;
Forming a diffusion barrier film so as to cover the surface;
Etching a part of the diffusion preventing film using an etchant containing a fluorocarbon-based gas, and forming a hole reaching the surface in the diffusion preventing film;
And a step of plasma-treating the wiring exposed from the hole using a gas containing at least one selected from the group consisting of nitrogen, argon and hydrogen after the step of forming the hole. Method. The diffusion preventing film includes at least one selected from the group consisting of SiC, SiCN, and SiN, and the etchant is at least one selected from the group consisting of CF ₄ , CHF ₃ , CH ₂ F _2, and CH ₃ F. The manufacturing method of the semiconductor device of Claim 1 containing this.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching-processed wiring is maintained in a state of being cut off from an air atmosphere between the step of forming the hole and the step of performing the plasma treatment. The step of forming the hole includes a step of etching in a predetermined processing chamber,
The method of manufacturing a semiconductor device according to claim 3, wherein the plasma processing includes a plasma processing in the predetermined processing chamber.

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