JP2005294707A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2005294707A
JP2005294707A JP2004110411A JP2004110411A JP2005294707A JP 2005294707 A JP2005294707 A JP 2005294707A JP 2004110411 A JP2004110411 A JP 2004110411A JP 2004110411 A JP2004110411 A JP 2004110411A JP 2005294707 A JP2005294707 A JP 2005294707A
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polishing
polishing cloth
semiconductor substrate
processed
acidic
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JP4064943B2 (en
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Masaru Fukushima
大 福島
Fukugaku Minami
学 南幅
Nobuyuki Kurashima
延行 倉嶋
Hiroyuki Yano
博之 矢野
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Toshiba Corp
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Toshiba Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/6723Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one plating chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67219Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one polishing chamber

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which avoids an occurrence of a defect and has a high reliability when forming a damascene wiring. <P>SOLUTION: The method comprises the steps of acidifying the surface to be processed by processing a surface to be processed provided on a semiconductor substrate 22 on a polishing cloth by an acidifying processing solvent 27, and transferring the semiconductor substrate 22 from on the polishing cloth 21 to a cleaning unit with the surface to be processed kept acidic. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置の製造方法に係り、特にシステムLSIや、高速LOGIC−LSIのCuダマシン配線等を形成するCMP(Chemical−Mechanical−Planarization)工程に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a CMP (Chemical-Mechanical-Planarization) process for forming a Cu damascene wiring of a system LSI or a high-speed LOGIC-LSI.

次世代の高性能LSIは、素子の高集積化が必須であり、CMPにより形成されるダマシン配線のデザインルールは、配線幅が0.07〜30μm、膜厚は100nmと厳しい設計となりつつある。   The next-generation high-performance LSI requires high integration of elements, and the design rule of damascene wiring formed by CMP is becoming a strict design with a wiring width of 0.07 to 30 μm and a film thickness of 100 nm.

通常、膜厚が100nmのダマシン配線を形成するには、スラリーを用いたCMPが行なわれる。CMP後の洗浄工程が不充分で配線の仕上がり状態が悪い場合、例えば局所的な異常が存在していると、半導体装置の性能が急激に低下する。また、動作中に断線するおそれもあることから、CMP後のウェハーの洗浄に関して研究が進められている(例えば、特許文献1参照)。   Usually, CMP using slurry is performed to form a damascene wiring having a thickness of 100 nm. If the cleaning process after the CMP is insufficient and the finished state of the wiring is poor, for example, if there is a local abnormality, the performance of the semiconductor device is drastically deteriorated. Further, since there is a possibility of disconnection during operation, research is being conducted on cleaning of a wafer after CMP (see, for example, Patent Document 1).

Cuダマシン配線が形成される場合、洗浄後には、Cu腐食、Cu溶解、スクラッチ、およびダストの再付着(研磨粒子、研磨生成物、研磨布からの汚染など)といった欠陥を極力低減することが必須である。最近では、半導体デバイスの微細化が進んで欠陥の歩留に対する影響が明確になってきたため、欠陥低減の要求はさらに高まってきた。欠陥評価のレベルを高めることによって、特殊なパターン部にのみ発生する腐食や非常に僅かな配線端でのえぐれが生じていることが確認されている。また、ダストやスクラッチも無視できない状況であることも判明してきた。   When Cu damascene wiring is formed, it is essential to reduce defects such as Cu corrosion, Cu dissolution, scratches, and dust reattachment (contamination from abrasive particles, polishing products, polishing cloth, etc.) as much as possible after cleaning. It is. Recently, since the miniaturization of semiconductor devices has progressed and the influence of defect yields has become clear, the demand for defect reduction has further increased. By increasing the level of defect evaluation, it has been confirmed that corrosion that occurs only in a special pattern portion and very slight erosion at the end of the wiring have occurred. It has also been found that dust and scratches cannot be ignored.

こうした欠陥の発生を回避して、信頼性の高い半導体装置を製造する方法は、未だ得られていないのが現状である。
特開2001−358111号公報
At present, a method for manufacturing a highly reliable semiconductor device by avoiding such a defect has not yet been obtained.
JP 2001-358111 A

本発明は、欠陥の発生を回避して高い信頼性を有する半導体装置を製造する方法を提供することを目的とする。   An object of the present invention is to provide a method for manufacturing a semiconductor device having high reliability by avoiding the occurrence of defects.

本発明の一態様にかかる半導体装置の製造方法は、半導体基板に設けられた被処理面を研磨布上で酸性処理液により処理し、前記被処理面を酸性にする工程と、前記被処理面を酸性に保ったまま、前記半導体基板を前記研磨布上から洗浄ユニットに移動させる工程とを具備することを特徴とする。   A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of treating a surface to be processed provided on a semiconductor substrate with an acid treatment liquid on a polishing cloth to make the surface to be treated acidic, and the surface to be processed. A step of moving the semiconductor substrate from the polishing cloth to a cleaning unit while maintaining acidity.

本発明の他の態様にかかる半導体装置の製造方法は、半導体基板に設けられた被処理面を研磨布に当接して、前記研磨布上に液体を供給し、前記研磨布上の酸濃度をモニターしつつ、前記被処理面を処理する工程、および、前記酸濃度が予め設定された所定値未満になったことを検知し、前記半導体基板を前記研磨布上から待避させて、洗浄ユニットに搬送する工程を具備することを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a surface to be processed provided on a semiconductor substrate is brought into contact with a polishing cloth, a liquid is supplied onto the polishing cloth, and an acid concentration on the polishing cloth is set. The step of processing the surface to be processed while monitoring, and detecting that the acid concentration is less than a predetermined value set in advance, and retracting the semiconductor substrate from the polishing cloth, the cleaning unit It has the process to convey, It is characterized by the above-mentioned.

本発明のさらに他の態様にかかる半導体装置の製造方法は、半導体基板に設けられた被処理面を研磨布に当接して、前記研磨布上に液体を供給し、前記研磨布上のpHをモニターしつつ、前記被処理面を処理する工程、および、前記pHが予め設定された所定値を越えたことを検知し、前記半導体基板を前記研磨布上から待避させて、洗浄ユニットに搬送する工程を具備することを特徴とする。   According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a surface to be processed provided on a semiconductor substrate is brought into contact with a polishing cloth, a liquid is supplied onto the polishing cloth, and a pH on the polishing cloth is adjusted. While monitoring, the process of processing the surface to be processed, and detecting that the pH exceeds a predetermined value set in advance, the semiconductor substrate is retracted from the polishing cloth and transported to the cleaning unit It comprises the process.

本発明の態様によれば、欠陥の発生を回避して高い信頼性を有する半導体装置を製造する方法が提供される。   According to an aspect of the present invention, a method for manufacturing a highly reliable semiconductor device by avoiding the occurrence of defects is provided.

以下、本発明の実施形態を説明する。   Embodiments of the present invention will be described below.

本発明者らは、特殊なパターン部にのみ発生する腐食や、非常に僅かな配線端に生じるえぐれについて鋭意検討した結果、こうした欠陥が発生するのは、CMP自体に原因があるのではなく、仕上げ方や洗浄研磨の方法に原因があることを見出した。例えばCu膜の場合、スラリーでの研磨、およびその後の純水による研磨の段階では、Cu膜の表面はスラリー中の錯化剤に保護されて保護膜が形成されているので、腐食や配線端のえぐれは生じない。しかしながら、洗浄液を用いた研磨の後に純水での研磨を行なうと、特殊パターン部の腐食やえぐれが発生する。この原因を追求したところ、洗浄液を用いた研磨によってCu膜表面の保護膜が取り除かれてしまうこと、さらに、保護膜が除去された後には、純水で研磨することによって欠陥が発生することを見出した。   As a result of intensive investigations on corrosion that occurs only in a special pattern portion or on a very small wiring end, the present inventors have not caused the defect in CMP itself. We found that there is a cause in the method of finishing and cleaning and polishing. For example, in the case of a Cu film, the surface of the Cu film is protected by the complexing agent in the slurry at the stage of polishing with slurry and subsequent polishing with pure water. No excitement occurs. However, if polishing with pure water is performed after polishing using a cleaning liquid, corrosion or scooping of the special pattern portion occurs. In pursuit of this cause, it was found that the protective film on the surface of the Cu film was removed by polishing with the cleaning liquid, and that defects were generated by polishing with pure water after the protective film was removed. I found it.

また、ダストやスクラッチについても、その増加に純水が関与していることを見出した。具体的には、洗浄液で研磨している間は、ウェハー上および研磨布上のいずれのダストも洗い流されやすい環境である。しかしながら、純水で研磨をすると、研磨布からの逆汚染を招いて、ウェハーおよび研磨布のいずれの表面もダストが残りやすい環境となる。したがって、最終的な仕上げに純水が用いられることによって研磨布からの逆汚染が発生してダストが増加し、副次的にスクラッチも増加してしまう。純水に起因した逆汚染は、洗浄後の純水研磨の際に研磨布上で発生する。   We also found that pure water is involved in the increase of dust and scratches. Specifically, during polishing with the cleaning liquid, it is an environment in which any dust on the wafer and the polishing cloth is easily washed away. However, polishing with pure water causes back-contamination from the polishing cloth, resulting in an environment in which dust tends to remain on the surfaces of the wafer and the polishing cloth. Therefore, when pure water is used for final finishing, back-contamination from the polishing cloth occurs, dust increases, and scratches also increase secondarily. Back-contamination due to pure water occurs on the polishing cloth during polishing with pure water after cleaning.

こうした知見に基づいて、洗浄液により研磨してピュアなCu面が露出した後には純水での研磨を避けること、具体的には、研磨布上での処理によりCu面が露出した後の被処理面を酸性にすることにより、欠陥の低減を可能とした。本発明の実施形態にかかる方法においては、洗浄液での研磨が終了した後、一般的には洗浄ユニットに搬送される前に、被処理面は純水で洗浄されてはならず、酸性状態であることが必要である。また、洗浄液を用いずにスラリーのみで研磨して洗浄ユニットに搬送する場合には、スラリー研磨の後の被処理面が酸性状態でなければならない。研磨布上での処理後の被処理面のpHあるいは酸濃度を所定の範囲に保つことによって、被処理面を酸性に維持することができる。pHの場合は7未満であり、酸濃度は、用いられる酸に依存するが、例えばクエン酸の場合には0.05wt%以上である。   Based on these findings, avoid polishing with pure water after the pure Cu surface is exposed by polishing with the cleaning liquid. Specifically, the target surface after the Cu surface is exposed by the treatment on the polishing cloth. By making the surface acidic, defects can be reduced. In the method according to the embodiment of the present invention, the surface to be treated must not be cleaned with pure water after the polishing with the cleaning liquid is finished, and generally before being transferred to the cleaning unit. It is necessary to be. Further, in the case of polishing only with the slurry without using the cleaning liquid and transporting it to the cleaning unit, the surface to be processed after the slurry polishing must be in an acidic state. By maintaining the pH or acid concentration of the treated surface after the treatment on the polishing cloth within a predetermined range, the treated surface can be maintained acidic. In the case of pH, it is less than 7, and the acid concentration depends on the acid used, but for example, citric acid is 0.05 wt% or more.

具体的には、酸性処理液を用いて研磨布上で被処理面を処理し、処理後の半導体基板を洗浄ユニットに直接搬送することによって、これを達成することができる。酸性処理液は、スラリーおよび洗浄液のいずれであってもよい。酸性スラリーで研磨を行なった場合には、研磨後の半導体基板を、そのまま直接、洗浄ユニットに移動すればよい。酸性洗浄液が用いられる場合には、中性またはアルカリ性のスラリーを用いることもでき、この場合は、中性またはアルカリ性のスラリーによる研磨の後、純水研磨を行なったうえで酸性洗浄液で洗浄研磨してもよい。   Specifically, this can be achieved by treating the surface to be treated on an abrasive cloth using an acidic treatment liquid and directly transporting the treated semiconductor substrate to a cleaning unit. The acidic treatment liquid may be either a slurry or a cleaning liquid. When polishing with an acidic slurry, the polished semiconductor substrate may be moved directly to the cleaning unit. When an acidic cleaning solution is used, a neutral or alkaline slurry can also be used. In this case, after polishing with a neutral or alkaline slurry, after washing with pure water, washing with an acidic cleaning solution is performed. May be.

(実施形態1)
Cuダマシン配線の形成方法を例に挙げて説明する。図1は、Cu−CMPを示す工程断面図である。
(Embodiment 1)
A method for forming Cu damascene wiring will be described as an example. FIG. 1 is a process cross-sectional view showing Cu-CMP.

まず、図1(a)に示すように、素子(図示せず)が形成された半導体基板10上に、膜厚6000Åの絶縁膜11を堆積し、溝14を形成した。ここでは、TEOS(テトラエトキシシラン)を用いて絶縁膜11を形成した。   First, as shown in FIG. 1A, an insulating film 11 having a thickness of 6000 mm was deposited on a semiconductor substrate 10 on which an element (not shown) was formed, and a groove 14 was formed. Here, the insulating film 11 is formed using TEOS (tetraethoxysilane).

絶縁膜11の全面に、ライナー材12としてのTaN膜(100Å)、および配線材料膜13としてのCu膜(6000Å)を、スパッタリング法およびメッキにより堆積した。   A TaN film (100 Å) as the liner material 12 and a Cu film (6000 Å) as the wiring material film 13 were deposited on the entire surface of the insulating film 11 by sputtering and plating.

Cu膜13およびTaN膜12の不要部分をCMPにより除去することによって、Cuダマシン配線が形成される。具体的には、まず、図2に示すように、研磨布21が貼付されたターンテーブル20を100rpmで回転させつつ、半導体基板22を保持したトップリング23を300gf/cm2の研磨荷重で当接させた。トップリング23の回転数は100rpmとし、研磨布21上には、処理液供給ノズル25から200cc/minの流量で、処理液27としてのスラリーを供給した。ここでは、スラリーとしてCMS7401/CMS7452(JSR社)を用い、研磨布としてはIC1000(RODEL社)を用いて、80秒間の研磨を行なった。なお、図2には、水供給ノズル24およびドレッサー26も併せて示してある。 By removing unnecessary portions of the Cu film 13 and the TaN film 12 by CMP, a Cu damascene wiring is formed. Specifically, as shown in FIG. 2, the top ring 23 holding the semiconductor substrate 22 is applied with a polishing load of 300 gf / cm 2 while rotating the turntable 20 to which the polishing cloth 21 is attached at 100 rpm. Touched. The rotational speed of the top ring 23 was 100 rpm, and the slurry as the processing liquid 27 was supplied onto the polishing cloth 21 from the processing liquid supply nozzle 25 at a flow rate of 200 cc / min. Here, polishing was performed for 80 seconds using CMS7401 / CMS7452 (JSR) as the slurry and IC1000 (RODEL) as the polishing cloth. In FIG. 2, the water supply nozzle 24 and the dresser 26 are also shown.

その後、TaN膜12の不要部分をCMPにより除去して、図1(b)に示すように絶縁膜11の表面を露出した。ここでは、トップリング23およびターンテーブル20の回転数をいずれも50rpmに変更し、研磨荷重を400gf/cm2に変更し、スラリーとしてCMS8301(JSR社)を用いた以外は、前述と同様の条件で60秒間の研磨を行なった。CMS8301は、pH9.5のアルカリ性のスラリーであり、腐食防止剤(防食剤)が配合されている。酸性のスラリーが好ましいものの、防食剤が添加されていればアルカリ性スラリーを用いることもできる。 Thereafter, unnecessary portions of the TaN film 12 were removed by CMP to expose the surface of the insulating film 11 as shown in FIG. Here, the same conditions as described above except that the rotational speeds of the top ring 23 and the turntable 20 are both changed to 50 rpm, the polishing load is changed to 400 gf / cm 2, and CMS8301 (JSR) is used as the slurry. Polishing was performed for 60 seconds. CMS8301 is an alkaline slurry having a pH of 9.5, and a corrosion inhibitor (anticorrosive) is blended therein. Although an acidic slurry is preferable, an alkaline slurry can be used if an anticorrosive agent is added.

この研磨に引き続いて、水供給ノズル24から純水を供給して15秒研磨して酸性側にシフトする準備をし、さらに、洗浄液供給ノズル(図示せず)から、洗浄液としてのクエン酸水溶液0.2wt%を供給して30秒研磨を行なった。ここまでの工程は、図2に示したように1つのターンテーブル20上で連続的に行ない、その後、ロール洗浄などの次工程へ直接引き継ぐ。クエン酸水溶液のpHは3であることから、被処理面は酸性状態のまま、ロール洗浄に供されることになる。洗浄液としては、クエン酸、シュウ酸、マレイン酸、マロン酸等、酸性の水溶液を用いることもできる。   Following this polishing, pure water is supplied from the water supply nozzle 24 to prepare for shifting to the acidic side by polishing for 15 seconds. Further, from the cleaning liquid supply nozzle (not shown), a citric acid aqueous solution 0 as a cleaning liquid is prepared. Polishing was performed for 30 seconds by supplying 2 wt%. The steps so far are continuously performed on one turntable 20 as shown in FIG. 2, and then directly taken over to the next step such as roll cleaning. Since the pH of the citric acid aqueous solution is 3, the surface to be treated is subjected to roll cleaning while being in an acidic state. As the cleaning liquid, an acidic aqueous solution such as citric acid, oxalic acid, maleic acid, malonic acid or the like can be used.

図3には、本発明の実施形態にかかる方法に用いられる研磨装置の構成を模式的に示す。図示する研磨装置は一般的な構成であり、二系統で研磨が行なわれるCMP部30と、それぞれから搬送されたウェハーを洗浄する洗浄部31とを有している。半導体ウェハー33は、CMP部30において、ターンテーブル32上でCMPが行なわれた後、ポリッシングユニット34に保持される。上述した例においては、クエン酸水溶液での研磨が終了した後、表面が酸性のままの状態でウェハー33が搬送される。なお、CMP部30には、ドレッシングユニット35も併せて示してある。   In FIG. 3, the structure of the grinding | polishing apparatus used for the method concerning embodiment of this invention is shown typically. The illustrated polishing apparatus has a general configuration, and includes a CMP unit 30 that performs polishing in two systems, and a cleaning unit 31 that cleans a wafer transferred from each. The semiconductor wafer 33 is held by the polishing unit 34 after CMP is performed on the turntable 32 in the CMP unit 30. In the example described above, after the polishing with the citric acid aqueous solution is completed, the wafer 33 is transported with the surface remaining acidic. The CMP unit 30 also includes a dressing unit 35.

洗浄部31においては、ウェハー搬送ロボット36のウェハーハンガー(図示せず)が、ポリッシングユニット34から半導体ウェハー33を受け取り、両面ロール洗浄機37に搬送する。ウェハーは、両面ロール洗浄機37で水等により両面が洗浄され、さらにウェハー搬送ロボット36により反転機38に搬送される。反転されたウェハーは、ペンシル洗浄機39で洗浄・乾燥が行なわれた後、カセット40に収容される。   In the cleaning unit 31, a wafer hanger (not shown) of the wafer transfer robot 36 receives the semiconductor wafer 33 from the polishing unit 34 and transfers it to the double-sided roll cleaning machine 37. The wafer is cleaned on both sides with water or the like by a double-sided roll cleaning machine 37 and further transferred to a reversing machine 38 by a wafer transfer robot 36. The inverted wafer is cleaned and dried by the pencil cleaner 39 and then accommodated in the cassette 40.

本実施形態においては、被処理面は酸性のままロール洗浄が行なわれる。ロール洗浄前の被処理面の表面には、Cuの腐食やCu配線端のえぐれといった欠陥は存在せず、こうした欠陥は、ロール洗浄後にも確認されなかった。また、Cu膜上のスクラッチは10個/cm2にとどまっており、欠陥評価装置での観察の結果、ダストは60個/cm2であった。 In this embodiment, roll cleaning is performed while the surface to be processed is acidic. There were no defects such as corrosion of Cu or chipping of Cu wiring edges on the surface of the surface to be processed before roll cleaning, and such defects were not confirmed even after roll cleaning. Further, the number of scratches on the Cu film was 10 / cm 2 , and as a result of observation with a defect evaluation apparatus, dust was 60 / cm 2 .

比較のため、従来の手法により研磨を行なった。具体的には、前述と同様にクエン酸水溶液での研磨まで行なった後、さらに、純水で15秒間研磨した。純水研磨後の絶縁膜11には、図4に示すようにCu配線端にえぐれ50が発生しており、その深さは最大で500Åにも及んでいた。また、Cu膜上のスクラッチは98個/cm2、ダストは170個/cm2であり、純水研磨により欠陥が増加することが確認された。 For comparison, polishing was performed by a conventional method. Specifically, after performing the polishing with a citric acid aqueous solution in the same manner as described above, the polishing was further performed with pure water for 15 seconds. In the insulating film 11 after the pure water polishing, as shown in FIG. 4, a gap 50 is generated at the end of the Cu wiring, and the depth reaches a maximum of 500 mm. Further, the number of scratches on the Cu film was 98 / cm 2 and the number of dust was 170 / cm 2 , and it was confirmed that defects were increased by pure water polishing.

(実施形態2)
図5に示すように絶縁膜11を、LKD5109(JSR製)からなる第1の絶縁膜(膜厚3000Å)51とLKD27(JSR製)からなる第2の絶縁膜(膜厚1500Å)52との積層膜に変更し、ライナー12をTa/TaN膜53に変更した以外は、図1(a)と同様の構成で、半導体基板10上に各膜を形成した。第2の絶縁膜52の形成に用いたLKD27は、疎水性の材料である。
(Embodiment 2)
As shown in FIG. 5, the insulating film 11 is composed of a first insulating film (thickness 3000 mm) 51 made of LKD5109 (made by JSR) and a second insulating film (thickness 1500 mm) made of LKD27 (made by JSR). Each film was formed on the semiconductor substrate 10 with the same configuration as in FIG. 1A except that the film was changed to a laminated film and the liner 12 was changed to the Ta / TaN film 53. The LKD 27 used for forming the second insulating film 52 is a hydrophobic material.

さらに、前述と同様の条件でCMPを行なってCu膜13の不要部分を除去し、Ta/TaN膜53表面を露出した後、前述と同様の条件でCMPを行なって、第2の絶縁膜52の表面を露出した。   Further, CMP is performed under the same conditions as described above to remove unnecessary portions of the Cu film 13 and the surface of the Ta / TaN film 53 is exposed. Then, CMP is performed under the same conditions as described above to perform the second insulating film 52. The surface of was exposed.

この研磨に引き続いて、水供給ノズル24から純水を供給して15秒研磨した後、洗浄液供給ノズル(図示せず)から、洗浄液を供給して30秒研磨を行なった。洗浄液としては、CIREX(和光純薬工業)を純水で希釈して、クエン酸濃度が1wt%の水溶液を用いた。Ta/TaN膜53のスラリーによる研磨以降の処理は、研磨布上のクエン酸濃度をモニターしつつ行なった。具体的には、近赤外分光装置を用いて酸度を測定し、研磨布上のクエン酸濃度をモニターした。   Following this polishing, pure water was supplied from the water supply nozzle 24 and polished for 15 seconds, and then a cleaning liquid was supplied from a cleaning liquid supply nozzle (not shown) to perform polishing for 30 seconds. As the cleaning liquid, CIREX (Wako Pure Chemical Industries) was diluted with pure water, and an aqueous solution having a citric acid concentration of 1 wt% was used. The processing after polishing with the slurry of the Ta / TaN film 53 was performed while monitoring the citric acid concentration on the polishing cloth. Specifically, the acidity was measured using a near-infrared spectrometer, and the citric acid concentration on the polishing cloth was monitored.

被処理面に供給していた洗浄液を純水に切り替えたところ、研磨布上のクエン酸濃度は0.1wt%未満になったので、半導体基板を研磨布上から待避させて、直ちに洗浄ユニットに移動させた。   When the cleaning liquid supplied to the surface to be processed was switched to pure water, the citric acid concentration on the polishing cloth became less than 0.1 wt%, so the semiconductor substrate was saved from the polishing cloth and immediately put into the cleaning unit. Moved.

こうした動作は、連動して行なわれるよう制御してもよい。すなわち、センサーが検知したクエン酸の濃度が、予め設定した所定値(例えば0.1wt%)を越えて低下したところで、研磨装置本体にインターロックがかかるように連動させる。研磨布上のクエン酸濃度をセンサーでモニターしつつ洗浄研磨を行ない、そのクエン酸濃度が所定値を越えると、本体装置はセンサーからのインターロックを受ける。トップリングは、直ちに待避位置に誘導され、半導体基板は洗浄ユニットに搬送される。   Such an operation may be controlled to be performed in conjunction with each other. That is, when the concentration of citric acid detected by the sensor falls below a predetermined value (for example, 0.1 wt%) set in advance, the polishing apparatus body is interlocked so as to be interlocked. When cleaning and polishing are performed while monitoring the citric acid concentration on the polishing cloth with a sensor, and the citric acid concentration exceeds a predetermined value, the main body device receives an interlock from the sensor. The top ring is immediately guided to the retracted position, and the semiconductor substrate is transferred to the cleaning unit.

クエン酸濃度が0.1wt%よりも若干低い程度であれば、十分に酸性状態であることから、本実施形態においても、被処理面を酸性状態に維持したままで洗浄ユニットにて洗浄が行なわれる。クエン酸研磨後の表面を観察したところ、実施形態1の場合と同様に欠陥は何等認められず、Cu異常は回避された。   If the citric acid concentration is slightly lower than 0.1 wt%, it is sufficiently acidic, so that in this embodiment as well, cleaning is performed in the cleaning unit while maintaining the surface to be processed in an acidic state. It is. When the surface after citric acid polishing was observed, no defects were observed as in the case of Embodiment 1, and Cu abnormality was avoided.

酸濃度の所定値は、研磨布に当接した被処理面が酸性状態となり得る最小の酸濃度に応じた値であり、用いる酸に応じて適宜決定することができる。一般的には、0.05wt%の酸濃度であれば酸性状態であるといえるが、被処理面を確実に酸性状態に維持するために、所定値は0.1wt%程度に設定することが望まれる。   The predetermined value of the acid concentration is a value corresponding to the minimum acid concentration at which the surface to be treated that is in contact with the polishing cloth can be in an acidic state, and can be determined as appropriate according to the acid used. In general, an acid concentration of 0.05 wt% can be said to be in an acidic state, but the predetermined value may be set to about 0.1 wt% in order to reliably maintain the surface to be processed in an acidic state. desired.

比較のために、洗浄液による洗浄研磨の後、純水で15秒間の研磨を行なった。純水研磨後の被処理面の表面には、図4に示したようなえぐれが発生していた。   For comparison, polishing with a cleaning liquid was followed by polishing with pure water for 15 seconds. On the surface of the surface to be treated after the pure water polishing, the erosion as shown in FIG. 4 occurred.

一般的に、疎水性材料からなる絶縁膜は、純水により逆汚染が加速される傾向がある。LKD27以外にも、Silk(Dow Chemical,Co.製),Coral(Novellus Systems,Inc.製),およびBD(ブラックダイアモンド、アプライド・マテリアルズ社製)等が疎水性の絶縁膜材料として知られている。上述したように、研磨布上の酸濃度を所定の範囲に維持することにより純水の使用は回避され、これによって絶縁膜の逆汚染を低減することができた。   In general, an insulating film made of a hydrophobic material tends to accelerate reverse contamination by pure water. Besides LKD27, Silk (manufactured by Dow Chemical, Co.), Coral (manufactured by Novellus Systems, Inc.), and BD (black diamond, manufactured by Applied Materials) are known as hydrophobic insulating film materials. Yes. As described above, the use of pure water was avoided by maintaining the acid concentration on the polishing cloth within a predetermined range, thereby reducing the back contamination of the insulating film.

(実施形態3)
前述の実施形態2と同様にして、図5に示すようにTa/TaN膜53を露出した。
(Embodiment 3)
In the same manner as in the second embodiment, the Ta / TaN film 53 was exposed as shown in FIG.

Ta/TaN膜53を研磨するためのスラリーは、砥粒としてのコロイダルシリカ5wt%、腐食防止剤としてのBTA(ベンゾトリアゾール)0.1wt%、およびpH調整剤としての硝酸0.1wt%を純水に加えて調製した。得られたスラリーのpHは1.5である。こうしたスラリーを用いた以外は、前述の実施形態1と同様の条件でTa/TaN膜53の不要部分を除去した。本実施形態においては、Ta/TaN膜53の研磨は、pH2.5付近の分解能の高いセンサーにより被処理面のpHをモニターしつつ行なった。具体的には、導電率計を用いてイオン濃度を測定して、研磨布上のpHをモニターした。   The slurry for polishing the Ta / TaN film 53 is pure 5% by weight of colloidal silica as abrasive grains, 0.1% by weight of BTA (benzotriazole) as a corrosion inhibitor, and 0.1% by weight of nitric acid as a pH adjuster. Prepared in addition to water. The resulting slurry has a pH of 1.5. Except for using such a slurry, unnecessary portions of the Ta / TaN film 53 were removed under the same conditions as in the first embodiment. In the present embodiment, the Ta / TaN film 53 is polished while monitoring the pH of the surface to be processed by a high resolution sensor around pH 2.5. Specifically, the ion concentration was measured using a conductivity meter, and the pH on the polishing cloth was monitored.

スラリーでの研磨に引き続いて、水供給ノズル24から純水を供給したところ、被処理面のpHが2.5を越えたので、半導体基板を研磨布上から待避させて、直ちに洗浄ユニットに移動させた。   Following the polishing with the slurry, when pure water was supplied from the water supply nozzle 24, the pH of the surface to be processed exceeded 2.5, so the semiconductor substrate was retracted from the polishing cloth and immediately moved to the cleaning unit. I let you.

こうした動作は、連動して行なわれるよう制御してもよい。すなわち、センサーが検知したpHが予め設定された所定値(例えば2.5)を越えたところで、研磨装置本体にインターロックがかかるように連動させる。研磨布上のpHをセンサーでモニターしつつ純水研磨を行ない、そのpHが所定値を越えると、本体装置はセンサーからのインターロックを受ける。トップリングは、直ちに待避位置に誘導され、半導体基板は洗浄ユニットに搬送される。   Such an operation may be controlled to be performed in conjunction with each other. That is, when the pH detected by the sensor exceeds a predetermined value (for example, 2.5) set in advance, the polishing apparatus body is interlocked so as to be interlocked. When pure water polishing is performed while monitoring the pH on the polishing cloth with a sensor and the pH exceeds a predetermined value, the main unit receives an interlock from the sensor. The top ring is immediately guided to the retracted position, and the semiconductor substrate is transferred to the cleaning unit.

pHが略2.5以下であれば酸性状態であることから、本実施形態においても、被処理面を酸性状態に維持したままで洗浄ユニットにて洗浄が行なわれる。ロール洗浄前の被処理面の表面を観察したところ、実施形態1の場合と同様に欠陥は何等認められず、Cu異常は回避された。   If the pH is approximately 2.5 or lower, the acidic state is obtained. Therefore, also in this embodiment, the cleaning unit is cleaned while the surface to be processed is maintained in the acidic state. When the surface of the surface to be treated before roll cleaning was observed, no defects were observed as in the case of Embodiment 1, and Cu anomaly was avoided.

pHの所定値は、研磨布に当接した被処理面が酸性状態となり得る最大のpHである。pHが7未満であれば酸性ということができるが、被処理面を確実に酸性状態に維持するために、pHの所定値は3以下程度に小さいことが望まれる。   The predetermined value of pH is the maximum pH at which the surface to be treated that is in contact with the polishing cloth can be in an acidic state. If the pH is less than 7, it can be said to be acidic, but in order to reliably maintain the surface to be treated in an acidic state, it is desirable that the predetermined value of pH is as small as 3 or less.

比較のために、被処理面のpHが7.0を越えるまで純水を供給した以外は前述と同様にして、研磨布上で研磨を行なった。純水研磨後の被処理面には、図4に示したようなえぐれが発生していた。酸性スラリーを用いて被処理面を研磨した場合であっても、引き続く工程で、被処理面が中性になるまで純水で研磨を行なうと、欠陥が発生することが確認された。   For comparison, polishing was performed on a polishing cloth in the same manner as described above except that pure water was supplied until the pH of the surface to be processed exceeded 7.0. On the surface to be processed after the pure water polishing, the erosion as shown in FIG. 4 occurred. Even when the surface to be processed was polished using an acidic slurry, it was confirmed that defects were generated when polishing with pure water until the surface to be processed became neutral in the subsequent process.

以上、Cuダマシン配線の形成を例に挙げて説明したが、配線材料はCuに限定されるものではなく、AlやWを用いた場合も同様に、酸性状態で洗浄ユニットに移動することによって、研磨後の異常を回避することができる。   As described above, the formation of Cu damascene wiring has been described as an example. However, the wiring material is not limited to Cu, and when Al or W is used, similarly, by moving to a cleaning unit in an acidic state, Abnormalities after polishing can be avoided.

本発明の一実施形態にかかる半導体装置の製造方法を表わす工程断面図。1 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. CMPの状態を示す概略図。Schematic which shows the state of CMP. 本発明の実施形態にかかる方法に用いられる研磨装置の構成を表わす概略図。Schematic showing the structure of the grinding | polishing apparatus used for the method concerning embodiment of this invention. 従来の方法による研磨後における絶縁膜の状態を示す断面図。Sectional drawing which shows the state of the insulating film after grinding | polishing by the conventional method. 本発明の他の実施形態にかかる半導体装置の製造方法を表わす工程断面図。Sectional drawing showing the manufacturing method of the semiconductor device concerning other embodiment of this invention.

符号の説明Explanation of symbols

10…半導体基板; 11…絶縁膜; 12…ライナー材; 13…配線材料膜
14…溝; 20…ターンテーブル; 21…研磨布; 22…半導体基板
23…トップリング; 24…水供給ノズル; 25…処理液供給ノズル
26…ドレッサー; 27…処理液; 30…CMP部; 31…洗浄部
32…ターンテーブル; 33…半導体ウェハー; 34…ポリッシングユニット
35…ドレッシングユニット; 36…ウェハー搬送ロボット
37…両面ロール洗浄機; 38…反転機; 39…ペンシル洗浄機
40…カセット; 50…えぐれ; 51…第1の絶縁膜; 52…第2の絶縁膜
53…Ta/TaN膜。
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate; 11 ... Insulating film; 12 ... Liner material; 13 ... Wiring material film 14 ... Groove; 20 ... Turntable; 21 ... Polishing cloth; 22 ... Semiconductor substrate 23 ... Top ring; ... Processing liquid supply nozzle 26 ... Dresser; 27 ... Processing liquid; 30 ... CMP unit; 31 ... Cleaning unit 32 ... Turntable; 33 ... Semiconductor wafer; 34 ... Polishing unit 35 ... Dressing unit; 36 ... Wafer transfer robot 37 ... Double-sided Roll cleaning machine; 38 ... reversing machine; 39 ... pencil cleaning machine 40 ... cassette; 50 ... punch; 51 ... first insulating film; 52 ... second insulating film 53 ... Ta / TaN film.

Claims (5)

半導体基板に設けられた被処理面を研磨布上で酸性処理液により処理し、前記被処理面を酸性にする工程と、
前記被処理面を酸性に保ったまま、前記半導体基板を前記研磨布上から洗浄ユニットに移動させる工程とを具備することを特徴とする半導体装置の製造方法。
Treating the surface to be treated provided on the semiconductor substrate with an acidic treatment liquid on a polishing cloth to make the surface to be treated acidic;
And a step of moving the semiconductor substrate from the polishing cloth to a cleaning unit while keeping the surface to be processed acidic.
前記被処理面は、前記半導体基板上に設けられた凹部を有する絶縁膜上に堆積された導電性膜の表面であり、前記酸性処理液はスラリーであり、前記処理は前記導電性膜を研磨して前記凹部内に選択的に残置させることにより前記絶縁膜の表面を露出するものであることを特徴とする請求項1に記載の半導体装置の製造方法。   The surface to be treated is a surface of a conductive film deposited on an insulating film having a recess provided on the semiconductor substrate, the acidic treatment liquid is a slurry, and the treatment polishes the conductive film. The method for manufacturing a semiconductor device according to claim 1, wherein the surface of the insulating film is exposed by being selectively left in the recess. 前記被処理面は、前記半導体基板上に設けられ、凹部に埋め込まれた導電性膜を有する絶縁膜の表面であり、前記酸性処理液は洗浄液であることを特徴とする請求項1に記載の半導体装置の製造方法。   The said to-be-processed surface is a surface of the insulating film which has the electroconductive film embedded in the recessed part provided on the said semiconductor substrate, The said acidic process liquid is a washing | cleaning liquid. A method for manufacturing a semiconductor device. 半導体基板に設けられた被処理面を研磨布に当接して、前記研磨布上に液体を供給し、前記研磨布上の酸濃度をモニターしつつ、前記被処理面を処理する工程、および
前記酸濃度が予め設定された所定値未満になったことを検知し、前記半導体基板を前記研磨布上から待避させて、洗浄ユニットに搬送する工程
を具備することを特徴とする半導体装置の製造方法。
Contacting the surface to be processed provided on the semiconductor substrate with a polishing cloth, supplying a liquid onto the polishing cloth, and monitoring the acid concentration on the polishing cloth, and processing the surface to be processed; and A method for manufacturing a semiconductor device, comprising: detecting that the acid concentration is less than a predetermined value set in advance, retracting the semiconductor substrate from the polishing cloth, and transporting the semiconductor substrate to a cleaning unit. .
半導体基板に設けられた被処理面を研磨布に当接して、前記研磨布上に液体を供給し、前記研磨布上のpHをモニターしつつ、前記被処理面を処理する工程、および
前記pHが予め設定された所定値を越えたことを検知し、前記半導体基板を前記研磨布上から待避させて、洗浄ユニットに搬送する工程
を具備することを特徴とする半導体装置の製造方法。
Contacting the surface to be processed provided on the semiconductor substrate with a polishing cloth, supplying a liquid onto the polishing cloth, and monitoring the pH on the polishing cloth, and processing the surface to be processed; and the pH A method of manufacturing a semiconductor device, comprising: detecting that a predetermined value exceeds a predetermined value, retracting the semiconductor substrate from the polishing cloth, and transporting the semiconductor substrate to a cleaning unit.
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US9902038B2 (en) 2015-02-05 2018-02-27 Toshiba Memory Corporation Polishing apparatus, polishing method, and semiconductor manufacturing method

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