JP2005294441A - Element mounting board and semiconductor device employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small size element mounting board exhibiting high reliability. <P>SOLUTION: The material composing a photosolder resist layer 328 can be shaped into a thin film under such a state as generation of voids or irregularities is suppressed using a base material, i.e. cardo type polymer, and a specific additive. Consequently, a film having a thickness of about 25 μm can be employed as a material composing the photosolder resist layer 328. As compared with a 35 μm thick resin material normally employed to compose the photosolder resist layer 328, the thickness can be reduced to about 2/3. The element mounting board 400 can thereby be reduced in size. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an element mounting substrate and a semiconductor device using the same.

  As portable electronic devices such as mobile phones, PDAs, DVCs, and DSCs are accelerating their functions, miniaturization and weight reduction are essential for their acceptance in the market. There is a need for a system LSI. On the other hand, these electronic devices are required to be easier to use and convenient, and higher functionality and higher performance are required for LSIs used in the devices. For this reason, as the number of I / Os increases with higher integration of LSI chips, there is a strong demand for miniaturization of the package itself. In order to achieve both of these, a semiconductor package suitable for high-density board mounting of semiconductor components Development is strongly demanded. In order to meet such demands, various package technologies called CSP (Chip Size Package) have been developed.

  As an example of such a package, BGA (Ball Grid Array) is known. In the BGA, a semiconductor chip is mounted on a package substrate, resin-molded, and then solder balls are formed in an area as external terminals on the opposite surface. In BGA, since the mounting area is achieved in terms of surface, the package can be reduced in size relatively easily. In addition, it is not necessary to support narrow pitches on the circuit board side, and high-precision mounting technology is not required. Therefore, if BGA is used, the total mounting cost can be reduced even if the package cost is somewhat high. Become.

  FIG. 12 is a diagram showing a schematic configuration of a general BGA. The BGA 100 has a structure in which an LSI chip 102 is mounted on a glass epoxy substrate 106 via an adhesive layer 108. The LSI chip 102 is molded with a sealing resin 110. The LSI chip 102 and the glass epoxy substrate 106 are electrically connected by a metal wire 104. Solder balls 112 are arranged in an array on the back surface of the glass epoxy substrate 106. The BGA 100 is mounted on the printed wiring board through the solder balls 112.

  Patent Document 1 describes another example of CSP. The publication discloses a system-in-package in which a high-frequency LSI is mounted. In this package, a multilayer wiring structure is formed on a base substrate, and semiconductor elements such as a high frequency LSI are formed thereon. The multilayer wiring structure has a structure in which a core substrate, a copper foil with an insulating resin layer, a solder resist layer, and the like are laminated.

JP 2002-94247 A

  Since the solder resist layer used in the system-in-package including the technology described in the above publication is located in the uppermost layer of the multilayer wiring structure, high workability is required. Further, since a semiconductor element such as a bare chip is directly mounted on the surface of the solder resist layer, high performance is required for moisture absorption characteristics and adhesion. Further, since the solder resist layer plays a role as an inter-wiring insulating film of a wiring pattern embedded in the layer, a reduction in parasitic capacitance is required.

  In addition, due to the demand for miniaturization of packages, it is required to make the solder resist layer thinner.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable and miniaturized element mounting substrate.

  According to the present invention, an element mounting substrate for mounting an element includes a base material, an insulating film provided on the base material, and a solder resist layer provided on the insulating film, An element mounting substrate is provided in which the solder resist layer contains a cardo type polymer.

  According to the present invention, when the solder resist layer contains a cardo type polymer, it is possible to improve various characteristics such as resolution and moisture absorption characteristics of the solder resist layer. Further, the solder resist layer can be thinned. Therefore, it is possible to provide a highly reliable and miniaturized element mounting substrate.

  Moreover, the wiring which connects an element to a soldering resist layer may be provided.

  Further, the glass transition temperature of the solder resist layer may be 180 ° C. or higher and 220 ° C. or lower, and the dielectric loss tangent may be 0.001 or higher and 0.04 or lower when an AC electric field having a frequency of 1 MHz is applied to the solder resist layer.

  Further, the linear expansion coefficient in the region below the glass transition temperature of the solder resist layer may be 50 ppm / ° C. or more and 80 ppm / ° C. or less.

  According to the present invention, there is provided a semiconductor device comprising an element mounting substrate having the above characteristics and a semiconductor element mounted on the element mounting substrate.

  According to the present invention, a highly reliable and miniaturized semiconductor device can be provided by providing a highly reliable and miniaturized element mounting substrate.

  Note that the insulating film may be a single-layer insulating film or a multilayer insulating film.

  In the present invention, the element mounting substrate means a substrate on which a semiconductor element such as an LSI chip or an IC chip is mounted. For example, an interposer substrate in an ISB (registered trademark) structure to be described later can be used. The element mounting substrate may include a rigid core substrate such as a silicon substrate, but may have a coreless structure including a multilayer insulating film made of an insulating resin film without the core substrate.

  According to the present invention, it is possible to provide a highly reliable and miniaturized element mounting substrate.

  Hereinafter, an embodiment of the present invention will be described, but before that, an ISB structure employed in the embodiment will be described. ISB (Integrated System in Board; registered trademark) is a unique package developed by the present applicant. ISB is a unique coreless system-in-package that does not use a core (base material) for supporting circuit components while having a wiring pattern made of copper in packaging of electronic circuits centering on semiconductor bare chips.

  FIG. 1 is a schematic configuration diagram showing an example of an ISB. Here, only a single wiring layer is shown for easy understanding of the entire structure of the ISB, but in actuality, a structure in which a plurality of wiring layers are laminated is shown. This ISB has a structure in which an LSI bare chip 201, a Tr bare chip 202, and a chip CR 203 are connected by a wiring made of a copper pattern 205. The LSI bare chip 201 is electrically connected to a lead electrode or wiring having a solder ball 208 on the back surface by gold wire bonding 204. A conductive paste 206 is provided directly under the LSI bare chip 201, and the ISB is mounted on the printed wiring board through the conductive paste 206. The entire ISB has a structure sealed with a resin package 207 made of an epoxy resin or the like.

According to this package, the following advantages are obtained.
(i) Since it can be mounted corelessly, it is possible to reduce the size and thickness of transistors, ICs and LSIs.
(ii) Since a circuit can be formed by forming a circuit from a transistor to a system LSI, and further a chip type capacitor and resistor, an advanced SIP (System in Package) can be realized.
(iii) Since existing semiconductor elements can be combined, a system LSI can be developed in a short time.
(iv) The semiconductor bare chip is directly mounted on the copper material directly below, and good heat dissipation can be obtained.
(v) Since the circuit wiring is made of copper and has no core material, the circuit wiring has a low dielectric constant and exhibits excellent characteristics in high-speed data transfer and high-frequency circuits.
(vi) Since the electrode is embedded in the package, the generation of particle contamination of the electrode material can be suppressed.
(vii) The package size is free, and the amount of waste per package is about 1/10 of the amount of SQFP package with 64 pins, so the environmental load can be reduced.
(viii) A new concept system configuration can be realized from a printed circuit board on which components are placed to a circuit board with functions.
(ix) ISB pattern design is as easy as printed circuit board pattern design, and can be designed by set manufacturer engineers.

  Next, advantages of the ISB manufacturing process will be described. FIG. 2 is a comparison diagram of manufacturing processes of a conventional CSP and an ISB according to the present invention. FIG. 2B shows a conventional CSP manufacturing process. First, a frame is formed on a base substrate, and a chip is mounted in an element formation region partitioned by each frame. Thereafter, a package is provided for each element by a thermosetting resin, and thereafter, punching is performed using a die for each element. In stamping in the final process, the mold resin and the base substrate are cut at the same time, and surface roughness on the cut surface becomes a problem. In addition, since a large amount of waste material is generated after punching, there is a problem in terms of environmental load.

  On the other hand, FIG. 2A is a diagram showing a manufacturing process of ISB. First, a frame is provided on a metal foil, a wiring pattern is formed in each module formation region, and a circuit element such as an LSI is mounted thereon. Subsequently, a package is applied to each module, and dicing is performed along the scribe region to obtain a product. After the package is completed, before the scribing process, the underlying metal foil is removed, so that dicing in the scribing process cuts only the resin layer. For this reason, it becomes possible to suppress roughening of the cut surface and improve the accuracy of dicing.

First Embodiment FIG. 10B is a cross-sectional view showing an element mounting substrate 400 having a four-layer ISB structure according to this embodiment.

  The element mounting substrate 400 according to the present embodiment has a structure in which an insulating resin film 312 and a photo solder resist layer 328 are sequentially laminated on the upper surface of the base material 302. In addition, an insulating resin film 312 and a photo solder resist layer 328 are sequentially stacked on the lower surface of the base material 302.

  Here, the four-layer ISB structure is a structure having four wiring layers inside, and the wiring layers are embedded in the insulating resin film 312 and the photo solder resist layer 328. The photo solder resist layer 328 is required to have photosensitivity for the convenience of the process of forming a via hole in the layer.

  In the four-layer ISB structure, the same material can be used as the material constituting the insulating resin film 312 on the upper surface and the insulating resin film 312 on the lower surface across the base material 302, and the photo solder resist layer on the upper surface. Since the same material can be used as the material constituting the photo solder resist layer 328 on the lower surface 328, there is a process advantage that the manufacturing process can be simplified.

  In addition, a through hole 327 that penetrates through the base material 302, the insulating resin film 312, and the photo solder resist layer 328 is provided.

  Further, a part of the wiring made of the copper film 308, a part of the wiring made of the copper film 320, a part of the via 311, and the like are embedded in the base material 302. In the insulating resin film 312, a part of the wiring made of the copper film 308, a part of the wiring made of the copper film 320, a wiring 309, a part of the via 311, a part of the via 323 and the like are embedded. In the photo solder resist layer 328, a part of the wiring made of the copper film 320, a part of the via 323, and the like are embedded. The photo solder resist layer 328 is provided with an opening 326.

  Here, the material used for the substrate 302 is not particularly limited to the glass epoxy substrate, and any material having an appropriate rigidity can be used. For example, as the base material 302, a resin substrate, a ceramic substrate, or the like can be used. More specifically, since the dielectric constant is low, a base material having excellent high frequency characteristics can be used. That is, polyphenylethylene (PPE), bismaleidotriazine (BT-resin), polytetrafluoroethylene (Teflon (registered trademark)), polyimide, liquid crystal polymer (LCP), polynorbornene (PNB), epoxy resin, acrylic Resin, ceramic, or a mixture of ceramic and organic base material can be used. Moreover, the thickness of the base material 302 shall be about 60 micrometers, for example.

  The material used for the insulating resin film 312 is a resin material that is softened by heating, and a resin material that can thin the insulating resin film 312 to some extent is used. In particular, a resin material having a low dielectric constant and excellent high-frequency characteristics can be suitably used. In addition, the thickness of the insulating resin film 312 is, for example, about 40 μm.

Here, the insulating resin film 312 can include a filler or a filler such as a fiber. As the filler, for example, particulate or fibrous SiO ₂ or SiN can be used.

  For the photo solder resist layer 328, a cardo type polymer-containing resin film described later is used. Here, the thickness of the photo solder resist layer 328 is preferably about 30 μm or less, for example, and more preferably about 25 μm.

  Here, the cardo type polymer has excellent mechanical strength, heat resistance, and a low linear expansion coefficient due to the bulky substituents inhibiting the movement of the main chain. Therefore, by using a cardo type polymer-containing resin film for the photo solder resist layer 328, a decrease in adhesion or delamination between the photo solder resist layer 328 and its surrounding layers is suppressed in a heat cycle. For this reason, the reliability of the element mounting substrate 400 according to the present embodiment is improved.

  The multilayer wiring structure including the wiring made of the copper film 308, the wiring made of the copper film 320, the wiring 309, the via 311, the via 323, and the like is not limited to the copper wiring, for example, and the aluminum wiring or the aluminum alloy wiring. Also, copper alloy wiring, wire-bonded gold wiring, gold alloy wiring, or mixed wiring of these can be used.

  Further, an active element such as a transistor or a diode, or a passive element such as a capacitor or a resistor may be provided on the surface or inside of the four-layer ISB structure. These active elements or passive elements may be connected to a multilayer wiring structure in the four-layer ISB and connectable to an external conductive member through a via 323 or the like.

  3 to 10 are process cross-sectional views of the element mounting substrate 400 according to this embodiment.

  First, as shown in FIG. 3A, a base material 302 is prepared on which a copper foil 304 having a hole having a diameter of about 150 nm is opened by a drill. Here, the thickness of the base material 302 is, for example, about 60 μm, and the thickness of the copper foil 304 is, for example, about 10 μm to 15 μm. Here, the material used for the substrate 302 is not particularly limited to the glass epoxy substrate, and any material having an appropriate rigidity can be used. For example, as the base material 302, a resin substrate, a ceramic substrate, or the like can be used. More specifically, since the dielectric constant is low, a base material having excellent high frequency characteristics can be used. That is, polyphenylethylene (PPE), bismaleidotriazine (BT-resin), polytetrafluoroethylene (Teflon (registered trademark)), polyimide, liquid crystal polymer (LCP), polynorbornene (PNB), epoxy resin, acrylic Resin, ceramic, or a mixture of ceramic and organic base material can be used.

  As shown in FIG. 3B, a photoetching resist layer 306 is laminated on the upper surface of the copper foil 304.

  Next, the photo-etching resist layer 306 is patterned by exposing with glass as a mask. Thereafter, as shown in FIGS. 4A and 4B, a via hole 307 having a diameter of about 100 nm is formed by, for example, chemical etching using a chemical solution using the photoetching resist layer 306 as a mask. Thereafter, the inside of the via hole 307 is roughened and cleaned by wet processing. Subsequently, as shown in FIG. 4C, the inside of the via hole 307 is filled with a conductive material by electroless plating corresponding to a high aspect ratio and then electrolytic plating, and a via 311 is formed. Then, a copper film 308 is formed on the entire surface. Form.

  The via 311 can be formed as follows, for example. First, after forming a thin film of about 0.5 to 1 μm on the entire surface by electroless copper plating, a film of about 20 μm is formed by electrolytic plating. The electroless plating catalyst is usually palladium, and in order to attach the electroless plating catalyst to a flexible insulating resin, palladium is included in an aqueous solution in a complex state, and the flexible insulating resin is used. It is possible to form a nucleus for initiating plating on the surface of a flexible insulating base material by dipping the base material to attach a palladium complex to the surface and reducing it to metallic palladium directly using a reducing agent. it can.

  As shown in FIG. 5A, a photoetching resist layer 310 is laminated on the upper and lower surfaces of the copper film 308. Subsequently, as shown in FIG. 5B, after patterning by exposing with glass as a mask, the copper plating layer 308 is etched with the photoetching resist layer 310 as a mask, thereby forming a wiring 309 made of copper. To do. For example, it is possible to form a wiring pattern by spraying a chemical etching solution on a portion exposed from the resist to remove unnecessary copper plating.

  Next, as shown in FIG. 6A, the insulating resin film 312 with the copper foil 314 is pressure-bonded from above and below the wiring 309. Here, the thickness of the insulating resin film 312 is, for example, about 40 μm, and the thickness of the copper foil 314 is, for example, about 10 μm to 15 μm.

As the material used for the insulating resin film 312, any material can be used as long as it is softened by heating. For example, epoxy resin, melamine derivatives such as BT resin, liquid crystal polymer, PPE resin, polyimide resin Fluorine resin, phenol resin, polyamide bismaleimide and the like can be used. Here, the insulating resin film 312 can include a filler or a filler such as a fiber. As the filler, for example, particulate or fibrous SiO ₂ or SiN can be used.

  As a pressing method, the insulating resin film 312 with copper foil is brought into contact with the base material 302 and the wiring 309, and the base material 302 and the wiring 309 are inserted into the insulating resin film 312. Next, as shown in FIG. 6B, the insulating resin film 312 is heated under vacuum or reduced pressure to be bonded to the substrate 302 and the wiring 309. Subsequently, as shown in FIG. 6C, the copper foil 314 is irradiated with X-rays, thereby opening a hole 315 that penetrates the copper foil 314, the insulating resin film 312, the wiring 309, and the base material 302.

  As shown in FIG. 7A, a photoetching resist layer 316 is laminated on the upper and lower surfaces of the copper foil 314. Subsequently, as shown in FIG. 7B, after patterning by exposing with glass as a mask, the copper foil 314 is etched with the photoetching resist layer 316 as a mask, thereby forming a wiring 319 made of copper. To do. For example, a chemical etching solution can be sprayed and sprayed onto a portion exposed from the resist to remove unnecessary copper foil, thereby forming a wiring pattern.

  As shown in FIG. 8A, a photoetching resist layer 317 is laminated on the upper and lower surfaces of the wiring 319. Next, as shown in FIG. 8B, after patterning by exposing glass as a mask, via holes 322 having a diameter of about 100 nm are formed by chemical etching using a chemical solution, for example, using the photoetching resist layer 317 as a mask. To do. Thereafter, the inside of the via hole 322 is roughened and cleaned by wet processing. Subsequently, as shown in FIG. 8C, the via hole 322 is filled with a conductive material by electroless plating corresponding to a high aspect ratio, and then by electroplating, and after forming the via 323, a copper film 320 is formed on the entire surface. Form.

  The via 323 can be formed as follows, for example. First, after forming a thin film of about 0.5 to 1 μm on the entire surface by electroless copper plating, a film of about 20 μm is formed by electrolytic plating. The electroless plating catalyst is usually palladium, and in order to attach the electroless plating catalyst to a flexible insulating resin, palladium is included in an aqueous solution in a complex state, and the flexible insulating resin is used. It is possible to form a nucleus for initiating plating on the surface of a flexible insulating base material by dipping the base material to attach a palladium complex to the surface and reducing it to metallic palladium directly using a reducing agent. it can.

  As shown in FIG. 9A, a photoetching resist layer 316 is laminated on the upper and lower surfaces of the copper film 320. Subsequently, as shown in FIG. 9B, after patterning by exposing with glass as a mask, the copper film 320 is etched with the photoetching resist layer 316 as a mask, thereby forming a wiring 324 made of copper. To do. For example, a chemical etching solution can be sprayed and sprayed onto a portion exposed from the resist to remove unnecessary copper foil, thereby forming a wiring pattern.

  As shown in FIG. 10A, a photo solder resist layer 328 is laminated on the upper and lower surfaces of the wiring 324. Here, the thickness of the photo solder resist layer 328 is preferably about 30 μm or less, for example, and more preferably about 25 μm. As conditions for the lamination, for example, a temperature of 110 ° C., a time of 1 to 2 minutes, 2 atmospheres, and the like are used. Thereafter, the photo solder resist layer 328 is partially cured by an after baking process.

  For the photo solder resist layer 328, a cardo type polymer-containing resin film, which will be described later, is used.

  Subsequently, as shown in FIG. 10B, after patterning by exposing glass as a mask, vias formed in the via holes 322 by, for example, chemical etching using a chemical solution using the photo solder resist layer 328 as a mask. For example, a via hole 326 having a diameter of about 100 nm is formed so as to expose 323. Thereafter, the exposed via 323 is plated with gold (not shown).

  Hereinafter, in this embodiment, the effect of using the cardo type polymer-containing resin film for the photo solder resist layer 328 will be described.

Here, the cardo type polymer is a general term for polymers having a structure in which a cyclic group is directly bonded to a polymer main chain, as shown in the formula (I). In the formula (I), R ₁ and R ₂ represent a divalent group such as an alkylene group or a divalent group containing an aromatic ring.

  That is, the cardo type polymer is a polymer having a structure in which a bulky substituent having a quaternary carbon is present substantially perpendicular to the main chain.

  Here, the cyclic portion may include a saturated bond or an unsaturated bond, and may include atoms such as a nitrogen atom, an oxygen atom, a sulfur atom, and a phosphorus atom in addition to carbon. The cyclic part may be a polycycle or a condensed ring. Moreover, even if the cyclic part is couple | bonded with the other carbon chain, it may be bridge | crosslinked further.

  As the bulky substituent, for example, as shown in the formula (I), a structure in which a six-membered ring is bonded to both sides of the five-membered ring and the remaining one carbon atom of the five-membered ring is bonded to the main chain. And cyclic groups such as a fluorenyl group having a condensed ring.

  The fluorenyl group is a group in which the carbon atom at the 9-position of fluorene is dehydrogenated as shown in the formula (II). In the cardo type polymer, it is dehydrogenated as shown in the formula (I). It is bonded to the carbon atom of the alkyl group which is the main chain at the position of the carbon atom.

Since the cardo type polymer is a polymer having the above structure,
(1) Rotation constraint of polymer main chain (2) Conformation regulation of main chain and side chain (3) Inhibition of intermolecular packing (4) Effect of increasing aromaticity by introduction of aromatic substituent on side chain Play.

  Accordingly, the cardo type polymer has characteristics such as high mechanical strength, high heat resistance, solvent solubility, high transparency, high refractive index, low birefringence, and higher gas permeability.

  Here, the cardo type polymer-containing resin film used for the photo solder resist layer 328 can be formed into a thin film in a state in which generation of voids and irregularities is suppressed using a predetermined additive. For this reason, a film having a thickness of about 25 μm can be used for the photo solder resist layer 328, which is about 2 / m as compared to about 35 μm which is the thickness of a resin material usually used for the photo solder resist layer 328. 3 thickness. Therefore, by using a cardo type polymer-containing resin film for the photo solder resist layer 328, the element mounting substrate 400 in the present embodiment can be reduced in size. In addition, by using the cardo type polymer-containing resin film for the photo solder resist layer 328, a film having a thickness of about 25 μm can be used for the photo solder resist layer 328. Therefore, the insulating resin film 312 has a thickness of about The thickness of the photo solder resist layer 328 can be made thinner than 40 μm.

  The cardo type polymer-containing resin film has excellent moisture resistance and adhesion as described later. For this reason, by using a cardo type polymer-containing resin film for the photo solder resist layer 328, it is possible to improve adhesion to elements mounted on the surface of the element mounting substrate 400 and other layers.

  Further, the cardo type polymer-containing resin film has an excellent resolution as will be described later. Moreover, since the thickness of the film used in this embodiment is about 2/3 of the thickness usually used for the photo solder resist layer, the photo solder resist layer 328 using the cardo type polymer-containing resin film is , Have better resolution. For this reason, the dimensional accuracy at the time of forming the via hole 326 can be improved. Therefore, the reliability of the element mounting substrate 400 can be improved.

  The cardo type polymer-containing resin film has excellent dielectric properties as will be described later. Therefore, by using a cardo type polymer-containing resin film for the photo solder resist layer 328, the parasitic capacitance between wirings embedded in the photo solder resist layer 328 is reduced. Therefore, the reliability of the element mounting substrate 400 can be improved.

  Further, since the cardo type polymer-containing resin film has high mechanical strength, even if the thickness of the photo solder resist layer 328 is about 2/3 of the conventional thickness, the mechanical strength can be maintained. Therefore, it is possible to suppress warping of the entire element mounting substrate 400. Therefore, the bonding accuracy of the elements mounted on the element mounting substrate 400 can be improved.

  Further, the spin coating method usually used for forming the photo solder resist layer has room for improvement in that voids are likely to be generated in the outer peripheral portion of the photo solder resist layer. Further, the potting method has room for improvement in that the state before bonding is liquid and voids are likely to occur after coating. On the other hand, the photo solder resist layer 328 in the present embodiment suppresses the occurrence of voids and irregularities when the film is pressure bonded, so the photo solder resist layer 328 of the element mounting substrate 400 to which the film is pressure bonded. There are few voids and irregularities. Therefore, the reliability and manufacturing stability of the element mounting substrate 400 can be improved.

  The cardo type polymer may be a polymer obtained by crosslinking a polymer having a carboxylic acid group and an acrylate group in the same molecular chain. As a conventional general photosensitive varnish, a blend of a carboxylic acid group oligomer having developability and a polyfunctional acrylic is used, but there is room for further improvement in terms of resolution. In place of a general photosensitive varnish, if a cardo type polymer obtained by crosslinking a polymer having a carboxylic acid group and an acrylate group in the same molecular chain is used, a developable carboxylic acid and an acrylate group which is a crosslinking group In the same molecular chain and has a bulky substituent in the main chain and is difficult to radically diffuse. Therefore, there is an advantage that the resolution of the cardo type polymer-containing resin film is improved.

  Moreover, it is desirable that the cardo type polymer-containing resin film satisfy the following physical property values. In addition, the following various physical property values are values for a resin portion that does not contain a filler or the like, and can be appropriately adjusted by adding a filler or the like.

  Here, the glass transition temperature (Tg) of the cardo polymer-containing resin film can be, for example, 180 ° C. or higher, and particularly preferably 190 ° C. or higher. When the glass transition temperature is in this range, the heat resistance of the cardo type polymer-containing resin film is improved.

  Moreover, the glass transition temperature (Tg) of the said cardo type polymer containing resin film can be made into 220 degrees C or less, for example, Most preferably, it is 210 degrees C or less. A cardo type polymer-containing resin film having a glass transition temperature in this range can be stably produced by a normal production method. The glass transition temperature can be measured, for example, by dynamic viscoelasticity measurement (DMA) of a bulk sample.

  Moreover, the linear expansion coefficient (CTE) in the area | region below Tg of the said cardo type polymer containing resin film can be 80 ppm / degrees C or less, for example, Most preferably, it is 75 ppm / degrees C or less. When the linear expansion coefficient is in this range, the adhesion between the cardo type polymer-containing resin film and other members is improved.

  Moreover, the linear expansion coefficient (CTE) in the area | region below Tg of the said cardo type polymer containing resin film can be 50 ppm / degrees C or more, for example, Most preferably, it is 55 ppm / degrees C or more. In addition, a resin composition having a CTE of 20 ppm / ° C. or less can be obtained by blending a filler with the cardo polymer-containing resin film. If the cardo type polymer-containing resin film has a linear expansion coefficient in this range, it can be stably produced by an ordinary production method. The linear expansion coefficient can be measured, for example, by measuring thermal expansion using a thermomechanical analyzer (TMA).

The thermal conductivity of the cardo polymer-containing resin film can be, for example, 0.50 W / cm ² · sec or less, and particularly preferably 0.35 W / cm ² · sec or less. When the thermal conductivity is within this range, the heat resistance of the cardo type polymer-containing resin film is improved.

The thermal conductivity of the cardo type polymer containing resin film, for example, 0.10 W / cm may be a ² · sec or more, and particularly preferably 0.25W / cm ² · sec or more. A cardo type polymer-containing resin film having a thermal conductivity in this range can be stably produced by a normal production method. The thermal conductivity can be measured, for example, by a disk heat flow meter method (ASTM E1530).

  In addition, the via aspect ratio of the 10 to 100 μm diameter via of the cardo polymer-containing resin film can be set to 0.5 or more, and particularly preferably 1 or more. When the via aspect ratio is within this range, the resolution of the cardo type polymer-containing resin film is improved.

  The via aspect ratio of the cardo polymer-containing resin film in a via having a diameter of 10 to 100 μm can be, for example, 5 or less, particularly preferably 2 or less. If the cardo type polymer-containing resin film has a via aspect ratio in this range, it can be stably produced by an ordinary production method.

  Moreover, the dielectric constant at the time of applying the alternating electric field of frequency 1MHz of the said cardo type polymer containing resin film can be 4 or less, for example, Especially preferably, it is 3 or less. When the dielectric constant is within this range, the dielectric properties including the high frequency properties of the cardo type polymer-containing resin film are improved.

  The dielectric constant of the cardo polymer-containing resin film when an AC electric field having a frequency of 1 MHz is applied can be, for example, 0.1 or more, and particularly preferably 2.7 or more. A cardo type polymer-containing resin film having a dielectric constant in this range can be stably produced by an ordinary production method.

  The dielectric loss tangent of the cardo polymer-containing resin film when an AC electric field having a frequency of 1 MHz is applied can be, for example, 0.04 or less, and particularly preferably 0.029 or less. When the dielectric loss tangent is within this range, the dielectric properties including the high frequency properties of the cardo type polymer-containing resin film are improved.

  The dielectric loss tangent of the cardo polymer-containing resin film when an AC electric field having a frequency of 1 MHz is applied can be, for example, 0.001 or more, and particularly preferably 0.027 or more. If the dielectric loss tangent is a cardo type polymer-containing resin film in this range, it can be stably produced by an ordinary production method.

  Further, the 24-hour water absorption (wt%) of the cardo type polymer-containing resin film can be, for example, 3 wt% or less, and particularly preferably 1.5 wt% or less. When the water absorption rate (wt%) for 24 hours is in this range, the moisture resistance of the cardo type polymer-containing resin film can be improved.

  In addition, the 24-hour water absorption (wt%) of the cardo type polymer-containing resin film can be, for example, 0.5 wt% or more, and particularly preferably 1.3 wt% or more. If the 24-hour water absorption (wt%) is within this range, the cardo type polymer-containing resin film can be stably produced by an ordinary production method.

  When the cardo type polymer-containing resin film satisfies the above-mentioned plurality of characteristics, thinning, mechanical strength, heat resistance, other members required for the photo solder resist layer 328 using the cardo type polymer-containing resin film Various properties such as adhesion, resolution, dielectric properties and moisture resistance are realized in a well-balanced manner.

Second Embodiment FIG. 11 is a cross-sectional view schematically showing various mounting methods of semiconductor elements on an element mounting substrate 400 having a four-layer ISB structure in the present embodiment.

  In this embodiment, the cardo polymer-containing resin film is the same as the cardo polymer-containing resin film described in the first embodiment.

  There are many types of semiconductor devices in which semiconductor elements are mounted on the element mounting substrate 400 described in the first embodiment. For example, there is a form of mounting by connecting by flip chip connection or wire bonding. In addition, there is a type in which a semiconductor element is mounted on the element mounting substrate 400 by a face-up structure or a face-down structure. Further, there is a form in which semiconductor elements are mounted on one side or both sides of the element mounting substrate 400. Furthermore, there is a format formed by combining these various formats.

  Specifically, for example, as shown in FIG. 11A, a semiconductor element 500 such as an LSI can be mounted on the element mounting substrate 400 of the first embodiment in a flip-chip format. At this time, the electrode pads 402a and 402b on the upper surface of the element mounting substrate 400 and the electrode pads 502a and 502b of the semiconductor element 500 are directly connected to each other.

  Further, as shown in FIG. 11B, a semiconductor element 500 such as an LSI can be mounted on the element mounting substrate 400 in a face-up structure. At this time, the electrode pads 402a and 402b on the upper surface of the element mounting substrate 400 are wire-bonded to the electrode pads 502a and 502b on the upper surface of the semiconductor element 500 by gold wires 504a and 504b, respectively.

  Further, as shown in FIG. 11C, a semiconductor element 500 such as an LSI is mounted on the element mounting substrate 400 in a flip chip format, and a semiconductor element 600 such as an IC is mounted on the lower portion of the element mounting substrate 400 in a flip chip format. It can be installed with. At this time, the electrode pads 402a and 402b on the upper surface of the element mounting substrate 400 are directly connected to the electrode pads 502a and 502b of the semiconductor element 500, respectively. Further, the electrode pads 404a and 404b on the lower surface of the element mounting substrate 400 are directly connected to the electrode pads 602a and 602b of the semiconductor element 600, respectively.

  Further, as shown in FIG. 11D, a semiconductor element 500 such as an LSI can be mounted on the element mounting substrate 400 in a face-up structure, and the element mounting substrate 400 can be mounted on the printed circuit board 700. At this time, the electrode pads 402a and 402b on the upper surface of the element mounting substrate 400 are wire-bonded to the electrode pads 502a and 502b on the upper surface of the semiconductor element 500 by gold wires 504a and 504b, respectively. Further, the electrode pads 404a and 404b on the lower surface of the element mounting substrate 400 are directly connected to the electrode pads 702a and 702b on the upper surface of the printed circuit board 700, respectively.

  In the semiconductor device having any of the above structures, as described in the first embodiment, the element mounting substrate 400 using the cardo type polymer-containing resin film as the photo solder resist layer 328 constituting the element mounting substrate 400 is provided. Used. Here, the cardo type polymer-containing resin film is excellent in various properties such as moisture resistance, adhesion, dielectric properties, and resolution as described above. Therefore, it has excellent adhesion to an element mounted on the element mounting substrate 400 and the insulating resin film 312 in contact with the photo solder resist layer 328, and improves dimensional accuracy when forming a via hole on the photo solder resist layer 328. And parasitic capacitance can be reduced. Further, a film having high mechanical strength is used for the photo solder resist layer 328 even if it is thinned. Therefore, the warpage of the entire substrate in the element mounting substrate 400 can be suppressed. Therefore, the accuracy in mounting elements on the element mounting substrate 400 can be improved. As a result, by mounting elements on the element mounting substrate 400, a highly reliable and miniaturized semiconductor device can be provided.

  The preferred embodiments of the invention have been described above. However, the present invention is not limited to the above-described embodiments, and it goes without saying that those skilled in the art can modify the above-described embodiments within the scope of the present invention.

  For example, a cardo type polymer-containing resin film may be used for the base material 302 or the insulating resin film 312 in addition to the photo solder resist layer 328.

  By using a cardo type polymer-containing resin film for the base material 302 in addition to the photo solder resist layer 328, the following effects can be obtained.

  The cardo type polymer-containing resin film used for the substrate 302 can be formed into a thin film using a predetermined additive in a state where generation of voids and irregularities is suppressed. For this reason, a film having a thickness of about 40 μm can be used for the base material 302, which is about 2/3 of the thickness of the resin material normally used for the base material, which is about 60 μm. . The cardo type polymer-containing resin film has excellent adhesion and heat resistance as described above. Accordingly, by using the cardo type polymer-containing resin film for the base material 302 in addition to the photo solder resist layer 328, the reliability of the element mounting substrate 400 in the present embodiment is further improved and further miniaturized. Can do. Further, by mounting a semiconductor element on the element mounting substrate 400, it is possible to provide a semiconductor device with further improved reliability and further miniaturization.

  By using a cardo type polymer-containing resin film for the insulating resin film 312 in addition to the photo solder resist layer 328, the following effects can be obtained.

  The cardo-type polymer-containing resin film used for the insulating resin film 312 can be formed into a thin film using a predetermined additive in a state where generation of voids and irregularities is suppressed. For this reason, a film having a thickness of about 25 μm can be used for the insulating resin film 312, which is about 2/3 of the thickness of the resin material normally used for the insulating resin film, which is about 40 μm. It becomes. Therefore, by using the cardo type polymer-containing resin film for the insulating resin film 312 in addition to the photo solder resist layer 328, the element mounting substrate 400 can be further miniaturized. Further, since the cardo type polymer-containing resin film has excellent adhesion, heat resistance, dielectric properties and the like as described above, the interlayer adhesion of the insulating resin film 312 is improved and the parasitic capacitance is reduced. For this reason, the reliability of the element mounting substrate 400 can be improved. Furthermore, since the generation of voids and unevenness is suppressed when the film is pressure bonded, the insulating resin film 312 of the element mounting substrate 400 to which the film is pressure bonded has few voids and unevenness. Therefore, by using the cardo polymer-containing resin film for the insulating resin film 312 in addition to the photo solder resist layer 328, the reliability of the element mounting substrate 400 in the present embodiment is further improved and further miniaturized. be able to. Further, by mounting a semiconductor element on the element mounting substrate 400, reliability and manufacturing stability are remarkably improved, and a further miniaturized semiconductor device can be provided.

  In addition to the photo solder resist layer 328, a cardo type polymer-containing resin film may be used for the base material 302 and the insulating resin film 312.

  Here, as described above, the cardo type polymer-containing resin film is excellent in various properties such as heat resistance, mechanical strength, adhesion, moisture resistance, dielectric properties, resolution properties, and can be molded into a thin film. The base material 302, the insulating resin film 312 and the photo solder resist layer 328 are excellent in various properties such as rigidity, heat resistance, interlayer adhesion, parasitic capacitance, dimensional accuracy when the element is mounted, and flatness. For this reason, in addition to the photo solder resist layer 328, the reliability and manufacturing stability of the element mounting substrate 400 are significantly improved by using a cardo type polymer-containing resin film for all of the substrate 302 and the insulating resin film 312. Therefore, further downsizing can be achieved. Further, by mounting the semiconductor element on the element mounting substrate 400, the reliability and the manufacturing stability are remarkably improved, and a further miniaturized semiconductor device can be provided.

  Moreover, in the said embodiment, although it was set as the structure which uses a cardo type | mold polymer containing resin film for the photo solder resist layer 328 which comprises the element mounting board | substrate 400 provided with 4 layer ISB structure, for example, a wiring layer has four or more layers, For example, a cardo type polymer-containing resin film may be used for a photo solder resist layer of an element mounting substrate having an ISB structure having six wiring layers, or a cardo type polymer containing resin film for a photo solder resist layer of another semiconductor package. May be used.

It is a figure for demonstrating the structure of ISB (trademark). It is a figure for demonstrating the manufacturing process of BGA and ISB (trademark). It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is process sectional drawing which shows the manufacture procedure of the element mounting board | substrate in embodiment of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device in embodiment of this invention It is a figure which shows schematic structure of the conventional general BGA.

Explanation of symbols

  302 substrate, 304 copper foil, 306 photo-etching resist layer, 307 via hole, 308 copper film, 309 wiring, 310 photo-etching resist layer, 311 via, 312 insulating resin film, 314 copper foil, 315 hole, 316 photo-etching resist layer 317 Photoetching resist layer, 319 wiring, 320 copper film, 322 via hole, 323 via, 324 wiring, 326 via hole, 327 through hole, 328 photo solder resist layer, 400 element mounting substrate, 402 electrode pad, 404 electrode pad, 500 Semiconductor element, 502 electrode pad, 504 gold wire, 600 semiconductor element, 602 electrode pad, 700 printed circuit board, 702 electrode pad.

Claims (5)

An element mounting board for mounting elements,
A base material, an insulating film provided on the base material, and a solder resist layer provided on the insulating film,
The element mounting substrate, wherein the solder resist layer contains a cardo type polymer. In the element mounting substrate according to claim 1,
An element mounting substrate, wherein wiring for connecting the element is provided in the solder resist layer. In the element mounting substrate according to claim 1 or 2,
The glass transition temperature of the solder resist layer is 180 ° C. or higher and 220 ° C. or lower,
An element mounting substrate, wherein a dielectric loss tangent of 0.001 or more and 0.04 or less when an alternating electric field having a frequency of 1 MHz is applied to the solder resist layer. In the element mounting substrate according to claim 3,
The element mounting board | substrate characterized by the linear expansion coefficient in the area | region below the glass transition temperature of the said soldering resist layer being 50 ppm / degrees C or more and 80 ppm / degrees C or less. The element mounting substrate according to any one of claims 1 to 4,
A semiconductor element mounted on the element mounting substrate;
A semiconductor device comprising:

Images