JP2005285144A - False path extraction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve estimation accuracy while taking into account a correlation of performance between interconnects or elements when calculating delay distribution in an integrated circuit. <P>SOLUTION: Circuit information 11, performance distribution information 12 of the interconnects or elements in the integrated circuit, and correlation information 13 of performance between the interconnects or elements are inputted (S11). A vertex is selected for calculation (S12), and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information 12 and the correlation information 13 (S13). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for evaluating performance in designing an integrated circuit such as a CMOS / LSI, and particularly relates to a technique relating to delay distribution calculation, false path removal and extraction.

  In the VLSI design in the deep submicron era, it is necessary to consider the variation in the manufacturing process in advance so that a circuit having the required performance is produced with a high yield. Furthermore, as symbolized by techniques such as OPC (Optical Proximity Correction), it has become possible and necessary to control variations by correcting the mask shape. Therefore, in the future VLSI physical design, a technique for designing a circuit with higher integration and higher performance by setting an appropriate design margin for each transistor in consideration of manufacturing variation at the time of design is required.

  In such a design technique, a technique for estimating circuit performance variations such as critical path delay due to manufacturing variations is indispensable. Since the distribution of critical path delay does not depend on the input, the method for estimating the variation can be said to be a statistical static timing analysis method.

  One of the statistical static delay analysis methods is to estimate the maximum delay as there is no correlation in the variation in signal transmission time (M. Hashimoto and H. Onodera, “A performance optimization method by gate resizing”). based on statistical static timing analysis, "Proc. Workshop on Synthesis And System Integration of Mixed Technology (SASIMI 2000), pp.77-82, 2000.).

  On the other hand, as a static delay analysis method for a combinational circuit composed of CMOS logic gates, a given circuit 100 as shown in FIG. 9 is applied to an acyclic graph G = (V, E) as shown in FIG. In this graph G200, there is a method of obtaining the maximum delay required to propagate the value “0” or “1” for each output terminal v.

  In FIG. 10, dashed ellipses 211 correspond to the main input terminal, the main output terminal, and the input / output terminals of the logic gate, respectively. A white point 211 surrounded by an ellipse 211 corresponding to the terminal v is a 0 point v0 of v, and a black point 212 is a 1 point v1 of v. v0 and v1 indicate that the corresponding terminal v takes signal values “0” and “1”, respectively.

  S is the set of incoming sources without branches, and T is the set of outgoing sinks without branches. The source is a point corresponding to the main input terminal, and the sink is a point corresponding to the main output terminal. Further, a directional path from the source to the sink in the graph G is defined as a path. Although the direction of each branch is not shown in FIG. 10, all branches are directed branches that exit from the left point and enter the right point.

  In FIG. 10, each rectangle 221, 222, 223 represents a logic gate constituting the circuit 100. The left point in the rectangle corresponds to the input terminal of the corresponding logic gate, and the right point corresponds to the output terminal. The branches in the rectangle go out of the point representing the input of the logic gate and enter the point representing the output. When the rectangle represents a NAND gate or a NOR gate, the branch corresponds to the pMOS or nMOS in the gate. The way of branching is determined according to the type of logic gate. A branch connecting points belonging to different rectangles corresponds to a wiring. A branch e0 from a point 0 of a certain terminal enters a point 0 of another terminal, and a branch e1 from a point of a certain terminal corresponds to the other terminal. Enter one point.

  The true maximum delay required to propagate the value “0” to the terminal v is d0 (v), and the true maximum delay required to propagate the value “1” is d1 (v). D0 (v) and d1 (v) corresponding to each terminal v of the circuit correspond to the maximum path lengths d (v0) and d (v1) from a certain sink on the graph G to v0 and v1, respectively. Therefore, for each branch e = (v, w), a delay required to transmit the signal value from the terminal v to the terminal w is given as a weight t (e).

By performing a simulation using such an acyclic graph, it is possible to perform a delay analysis of the logic circuit by a relatively simple process.
M. Hashimoto and H. Onodera, "A performance optimization method by gate resizing based on statistical static timing analysis," Proc. Workshop on Synthesis And System Integration of Mixed Technology (SASIMI 2000), pp.77-82, 2000.

  However, in the circuit 100 as shown in FIG. 9, when the delay of the signal z is calculated, if the delay of the signal x and the signal y largely depends on the delay of the signal b, the delay between the signals x and y Are highly correlated. In addition, when the wiring delay varies, there is a correlation with the signal transmission delay of the fan-out of the signal b. Therefore, statistical analysis methods that do not consider correlations are likely to lack accuracy.

  If the accuracy of the delay distribution estimation is poor, normal operation of the integrated circuit must be guaranteed even when multiple worst-case conditions overlap, which are unlikely to occur in probability. The design must include an over margin. For this reason, the designed integrated circuit has a problem that costs such as area and power consumption are increased more than necessary.

  In view of the above problems, an object of the present invention is to make it possible to calculate a more accurate delay distribution in accordance with an actual circuit as a method of calculating a delay distribution of an integrated circuit.

  There are other problems with the prior art.

  The conventional method includes a path (false path) that cannot actually be a simulation target. For this reason, there have been problems such as the calculation time being longer than necessary or the delay estimation accuracy being lowered.

  The false path does not have an input that logically propagates a signal to the path, and there is a logical false path that is not actually activated, and an input that activates the path. In fact, there is a functional false path that is not activated because no such input occurs. For example, in FIG. 11, in a path passing through two AND gates G1 and G6 controlled by opposite signals z and / z, an input x other than z of G1 is set to “1”, and an output y of G6 is set. A path set to “1” corresponds to a logical false path. Further, for example, when a calculation of a series of computing units (X, M, Y) and a series of computing units (A, M, B) is required, if the multiplier M is shared, (A, M, Y) ) Or (X, M, B). However, when the specifications are such that the arithmetic units are not operated simultaneously, these sequences correspond to functional false paths.

  In addition, it is practically impossible to find a logical false path by a human because the circuit scale is large, and a method of automatically finding it using a computer is indispensable.

  In view of the above-described problems, an object of the present invention is to avoid the influence of a false path and further improve the evaluation accuracy as a method for evaluating an integrated circuit. We also propose a method for extracting false paths from the integrated circuit to be designed.

  In order to solve the above problem, the solution provided by the invention of claim 1 is a method for extracting a false path for an integrated circuit to be designed, as a method of extracting uncontrolled signal branches in each logic gate of the integrated circuit. The false path is extracted using activation conditions.

  According to the invention of claim 2, in the invention of claim 1, the value propagated by propagating the logical value listed as the activation condition of the non-control signal branch in the first gate using the propagation operation. Is a control signal, the propagation is repeated, and when there is a contradiction between the propagated value and the activation condition of the non-control signal branch of the second gate, the second gate The route to the gate is detected as a false path.

  According to the present invention, since the correlation of performance between wirings or elements is taken into account in calculating the delay distribution of the integrated circuit, the accuracy of delay estimation is improved. Thereby, an excess margin can be removed from the designed integrated circuit, and an unnecessary area, power consumption, and the like can be reduced.

  Further, in the evaluation of the integrated circuit, the effect of shortening the calculation time and improving the delay estimation accuracy can be obtained by removing the false path.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
In the first embodiment of the present invention, a method for calculating the distribution of the maximum delay value at each terminal v of the circuit will be described. In the following description, the true maximum delay required to propagate the value “0” to the terminal v is d0 (v), and the true maximum delay required to propagate the value “1” is d1 (v).

で与えられる。 First, a given circuit is represented by an acyclic graph G = (V, E) as shown in FIG. For each branch e = (v, w), the delay (weight of branch e) t (e) required to transmit the signal value from the terminal v to the terminal w is treated as a probability variable. The distribution is assumed to be a normal distribution N (μ, σ ² ), and the average μ and variance σ ² of the delay t (e) are expressed as μ (e) and variance σ ² (e), respectively. That is, the probability density function f (t (e)) of the delay t (e) is

Given in.

  Next, the delay t (e) of the branch e corresponding to the wiring will be described. Here, it is assumed that the wiring delay t (e) also has a variation represented by a normal distribution.

  If the branch corresponding to the wiring is a branch e0 = (v0, w0) connecting the 0 points of the points v and w, a branch e1 = (v1, w1) connecting the points v and w exists. However, the variation in the delay t (e1) is not independent of the variation in the delay t (e0). Further, when two or more branches e ′ = (v, w ′), e ″ = (v, w ″) come out from the point v (that is, when there is a fanout), the delay of the branches e ′, e ″ Variations in t (e ′) and t (e ″) are not independent. Therefore, a correlation coefficient r (e ′, e ″) ≠ 0 is introduced for such a set of branches (e ′, e ″) corresponding to the same net. The delay of the branch e ′ corresponding to the wiring and the delay of the branch e ″ not corresponding to the branch or wiring corresponding to the wiring of a different net (included in the logic gate) are independent, and the correlation coefficient r (e ′, e ″) = 0.

  Next, branches corresponding to logic gates and their delays will be described. The maximum delay required to propagate “0” or “1” to the output terminal w of the logic gate is expressed as the maximum path lengths d (w0) and d (0) of the point w on the graph G to the 0 point w0 or 1 point w1. Consider how branches should be created in order to correspond to w1).

First, consider the case where the logic gate is an AND gate. The input terminal of the AND gate is v _i (1 ≦ i ≦ k), and the output terminal is w. The delay d (w1) required to set the output w to “1” is the time after all the inputs v _i become “1”, so that all the inputs v _i are “1”. so,
d (w1) = max [d (v _i 1) + t (e _i 1) | 1 ≦ i ≦ k] (2)
Can be calculated by Therefore, a branch e _i 1 = (v _i 1, w1) is attached to one point w1 from one point v _i 1 to w of each input v _i , and the delay t (e _i 1) of the branch e _i 1 is the input v. _{The time from when i} becomes “1” until the output w becomes “1”.

On the other hand, the delay d (w0) required to set the output w of the AND gate to “0” is determined by the time when one input becomes “0”. Therefore, each input v _j (j ≠ i, 1 ≦ j ≦ k) other than v _i is “0”, and d (v _i 0) + t (e _i 0) ≦ d (v _j 0) + t (e _j 0),
d (w0) = d (v _i 0) + t (e _i 0)
Therefore, d (w0) is
min [d (v _i 0) + t (e _i 0) | 1 ≦ i ≦ k] (3)
It seems to be given in.

However, if all inputs v _j except v _i are 1,
d (w0) = d (v _i 0) + t (e _i 0)
Therefore, for each 1 ≦ i ≦ k, if the condition that all the inputs v _j other than v _i are “1” is satisfied, the maximum delay among the delays required to set w to “0” D (w0) is
d (w0) = max [d (v _i 0) + t (e _i 0) | 1 ≦ i ≦ k] (4)
It is obtained with.

Therefore, the branch e _i 0 = (v _i 0, w0) is added from the 0 point v _i 0 of each input v _i to the 0 point w0 of the output w, and the delay t (e _i 0) of the branch e _i 0 is input. v _i is the output w from getting to the "0" and the time until the "0".

  By adding branches to the inside of the AND gate and determining the delay in this way, both the delays d (w1) and d (w0) can be calculated using the maximum value calculation.

Next, the case where the logic gate is a NAND gate will be specifically described. In this case, in the above formulas (2) and (4), only the case where the output w is set to “1” and the case where the output w is set to “0” are interchanged, so the delays d (w1) and d (w0) are
d (w1) = max [d (v _i 0) + t (e _i 0) | 1 ≦ i ≦ k] (5)
d (w0) = max [d (v _i 1) + t (e _i 1) | 1 ≦ i ≦ k] (6)
It can be calculated that.

Therefore, given the respective input v branch from 0 point v _i 0 of _i to 1 point w1 output w e _i 0 = (v _i 0, w1), the output w from one point v _i 1 for each input v _i A branch e _i 1 = (v _i 1, w0) is attached to the 0 point w0. Branch e _i 0 of delay t (e _i 0) and e _i 1 of the delay t (e _i 1), the time until the output w from when the input v _i is "0" respectively to "1", The time from when the input v _i becomes “1” until the output w becomes “0”. If the logic gate is an inverter, k = 1 may be set.

When the logic gate is an OR (or NOR) gate, d (w0) (d (w1) in the case of NOR gate) and d (w1) (d (w0) in the case of NOR gate) are obtained from the same argument. ,
d (w0) = max [d (v _i 0) + t (e _i 0) | 1 ≦ i ≦ k] (7)
d (w1) = max [d (v _i 1) + t (e _i 1) | 1 ≦ i ≦ k] (8)
Can be calculated by

  Therefore, the way of attaching branches to the OR gate is the same as that of the AND gate, and the way of attaching branches to the NOR gate is the same as that of the NAND gate. In the case of a CMOS composite gate, branches may be added in the same manner as in the case of a NAND (NOR) gate.

However, in the case of an XOR gate, the value “0” of the input v _i may change the value of the output w to “0” or “1”. Further, the value “1” of the input v _i may change the value of the output w to “0” or “1”. For this reason, branch e _i 00 = (v _i 0, w0) and e _i 01 = (v _i 0, w1) are transferred from 0 point v _i 0 of input v _i to 0 point w0 and 1 point w1 of output w. From the 1 point v _i 1 of the input v _i to the 0 point w 0 and 1 point w 1 of the output w, branches e _i 10 = (v _i 1, w0) and e _i 11 = (v _i 1, w1) Are attached respectively. The delay t (e _i bb ′) of these branches e _i bb ′ = (v _i b, wb ′) is the time from when the input v _i becomes b to when the output w becomes b ′. Here, b and b ′ both represent “0” or “1”.

  If the branch inside the logic gate is generated in this way, when the maximum path length to each sink is obtained in the acyclic graph G = (V, E), this becomes a candidate for a critical path delay.

  Next, variations in delay within the logic gate will be described.

In the case of NAND gates, NOR gates or CMOS composite gates, branch delays t (e _i 0) and t (e _i 1) are considered switching delays associated with the pMOS and nMOS to which the input v _{i of} the gate is connected. good. Such a switching delay is a time during which the transistor is in the saturation region, and is determined by the saturation drain current I _dsat , the load capacitance C to be driven, the rising speed of the gate voltage, and the like. The saturated drain current I _dsat has variations, which most depend on the variations in the gate length L. Since the variation in the gate length L is expressed by a normal distribution as in the case of the threshold voltage V _th , the switching delay t (e _i b) also has a normal distribution N (μ, σ ² ). To do.

The variation in the gate length L is influenced by the interval P between adjacent polysilicon gates, the transistor gate width W, the length L _DIF of the diffusion region, and the like. Therefore, when the relationship between these values and the variation in the gate length L can be found, the values of the interval P, the gate width W, and the diffusion region length _LDIF can be obtained from the layout pattern to predict the variation in the gate length L. Then, the variation in switching delay can be estimated.

  Since the delay variation is affected by the interval between the adjacent polysilicon gates, the delay variation of the branch corresponding to the adjacent transistor is not independent. Therefore, a correlation coefficient r (e ′, e ″) ≠ 0 is introduced for the set of branches (e ′, e ″) included in the same logic gate. Such correlation is also considered for logic gates other than NAND gates and NOR gates. If there is no correlation, the correlation coefficient r (e ′, e ″) = 0 may be set.

  Since only the branches included in the same logic gate have correlation, the delays of the branches e ′ and e ″ included in different gates are independent, and r (e ′, e ″) = 0. Further, in the case of a NAND gate or a NOR gate, the delays of the branches e ′ and e ″ corresponding to different types of MOS are also independent.

  Since the delay variation is correlated only between the branches corresponding to the wiring of the same net and between the branches in one logic gate, there is a (directed) path that passes through the branches correlated to the delay. do not do. Thus, for any branch on a path, their delay is independent.

  Next, the distribution calculation of the maximum value of the delay of the target circuit will be described using the delay distribution of the logic gate and the wiring and their correlation.

とする（C.E. Clark, "The greatest of a finite set of random variables" Operations Research, vol.9, pp.145-152, 1961. に開示）。 When random variables x and y having a correlation coefficient R [x, y] = ρ have normal distributions N (μ ₁ , σ ₁ ² ) and N (μ ₂ , σ ₂ ² ), respectively, t ( = Exp [t] and variance Var [t] are approximated by assuming that t is a two-variable normal distribution, on condition that σ ₁ −σ ₂ = ρ−1 = 0,
Exp [t] = μ ₁ · Φ (β) + μ ₂ · Φ (−β) + α · φ (β) (9)
Var [t] = (μ ₁ ² + σ ₁ ² ) · Φ (β) + (μ ₂ ² + σ ₂ ² ) · Φ (−β)
+ (Μ ₁ + μ ₂ ) · α · φ (β) −Exp [t] ² (10)
Is required. here,

(Disclosed in CE Clark, "The greatest of a finite set of random variables" Operations Research, vol.9, pp.145-152, 1961.).

で与えられる。 Furthermore, the correlation coefficient R [t, z] between t and a normally distributed random variable z is such that the correlation coefficients between z and x and z and y are R [x, z] = ρ1, R [ When y, z] = ρ2, using a normal distribution of three variables x, y, z,

Given in.

In order to use these, the following formula regarding the probability is required. Bivariate x _1, when the probability density function of x ₂ and the f (x _1, x _2), the average Exp [x ₁ + x _2] and variance Var [x ₁ + x _2] of x ₁ + x ₂ is

から、下に示す式（１８），（１９）によって求められる。
Ｅｘｐ［ｘ₁＋ｘ₂］＝Ｅｘｐ［ｘ₁］＋Ｅｘｐ［ｘ₂］……（１８）
Ｖａｒ［ｘ₁＋ｘ₂］＝Ｖａｒ［ｘ₁］＋Ｖａｒ［ｘ₂］＋２Ｃｏｖ［ｘ₁，ｘ₂］ ……（１９）

From the following equations (18) and (19).
Exp [x ₁ + x ₂ ] = Exp [x ₁ ] + Exp [x ₂ ] (18)
Var [x ₁ + x ₂ ] = Var [x ₁ ] + Var [x ₂ ] + 2Cov [x ₁ , x ₂ ] (19)

から、次式（２２）で計算することができる。
Ｃｏｖ［ｘ₁＋ｘ₂，ｘ₃ ］＝Ｃｏｖ［ｘ₁，ｘ₃］＋Ｃｏｖ［ｘ₂，ｘ₃］
……（２２） Here, Cov [x ₁ , x ₂ ] is covariance, and is defined by the following equation (20) when the correlation coefficient is R [x ₁ , x ₂ ].
Cov [x ₁ , x ₂ ] = SQRT [Var [x ₁ ] Var [x ₂ ]] · R [x ₁ , x ₂ ] (20)
3 If the probability density function of the variables x _1, x _2, x ₃ and f (x _1, x _2, x _3), the covariance Cov of x ₁ + x ₂ and _{x 3 [x 1 + x 2} , x 3] is ,

Therefore, it can be calculated by the following equation (22).
Cov [x ₁ + x ₂ , x ₃ ] = Cov [x ₁ , x ₃ ] + Cov [x ₂ , x ₃ ]
...... (22)

  A given graph has a plurality of serial branches. Therefore, here, the two serial branches e ′ = (u, v), e ″ = (v, w) are reduced to one branch e * = (u, w) using the above-described equation. The procedure to do is shown.

Obviously, the delays t (e ′) and t (e ″) are independent from the way of making the graph, and t (e *) = t (e ′) + t (e ″) can be obtained. 23) and (24) hold.
μ (e *) = μ (e ′) + μ (e ″) (23)
σ ² (e *) = σ ² (e ′) + σ ² (e ″) (24)

で得られる。これは、

で確かめられる。このようにして直列枝の縮約を行っても、パス上の枝の遅延の独立性は変化しない。すなわち、ｅとｅ＊を同時に通るようなパスがある場合には、ρ（ｅ＊，ｅ）＝０ である。 Furthermore, from the above equations (20) and (22), the correlation coefficient ρ (e *, e) between t (e *) and the delay t (e) of the other branch e is

It is obtained with. this is,

Can be confirmed. Even if the reduction of the serial branch is performed in this way, the independence of the delay of the branch on the path does not change. That is, ρ (e *, e) = 0 when there is a path that passes through e and e * simultaneously.

で与えられる。ここで、（ｘ−μ）はベクトル、（ｘ−μ）τ は（ｘ−μ）の転置ベクトルであり、（ｘ−μ）τ ＝（ｘ₁−μ₁ ｘ₂−μ₂ ．．． ｘ_n−μ_n）である。また、σ_ijは、

で示される対称行列であり、σ^ij＝（σ_ij）^-1である。また｜σ^ij｜はその行列式である。ここで、μ，σ²，ρはそれぞれ平均値、分散、相関係数に相当する。 The probability density function f (x ₁ , x ₂ ,..., x _n ) of the n-variate normal distribution is

Given in. Where (x−μ) is a vector and (x−μ) τ Is a transposed vector of (x−μ), and (x−μ) τ = (X ₁ −μ ₁ x ₂ −μ ₂ ... X _n −μ _n ). Also, σ _ij is

And σ ^ij = (σ _ij ) ⁻¹ . | Σ ^ij | is the determinant. Here, μ, σ ² , and ρ correspond to the average value, variance, and correlation coefficient, respectively.

で与えられ、相関係数ρ＝１のとき、２変量ｘ₁，ｘ₂ の間には、

なる関係がある。 The probability density function f (x ₁ , x ₂ ) of the bivariate normal distribution of the correlation coefficient ρ is

When the correlation coefficient ρ = 1, the bivariate x ₁ , x ₂ is

There is a relationship.

で与えられる。また、確率Ｐｒｏ［ｍａｘ［ｘ₁，ｘ₂，．．．，ｘ_n］≦Ｄ］が指定された値Ｙ以下になるようなＤの値は、

で示される積分方程式を解くことによって、求められる。 If the probability density function of n variables is f (x ₁ , x ₂ ,..., X _n ), the probability Pro [max [x ₁ , x ₂ ,. . . , X _n ] ≦ D]

Given in. Also, the probability Pro [max [x ₁ , x ₂ ,. . . , X _n ] ≦ D] is less than the specified value Y, the value of D is

It is calculated | required by solving the integral equation shown by these.

<Delay distribution calculation>
Next, a method for obtaining the delay distribution of the integrated circuit using the relationship described above will be described.

で求めることができる。 That is, the distribution of the maximum delay d (v) to the points v (vεT) of the sink set T (that is, the average Exp [d (v)] and the variance Var [d (v)]), and the points of the sink set T A correlation coefficient R [d (v), d (w)] of a delay between v and w (v, wεT) is obtained. If these are obtained, the probability that the critical path delay max [d (v) | vεT] is D or less is assumed that all d (v) have a normal distribution of | T | 31). When examining the distribution, the equation (31) is differentiated by D,

Can be obtained.

  These can be obtained by numerical calculation, but in this case, the calculation time is very long. On the other hand, if the equation (33) is approximated by a normal distribution, the distribution can be calculated at high speed by repeatedly using the following method (equation (9) to equation (15)).

  In the following, the maximum delay to each point v (the longest path length from a certain source u (uεS) to v) is d (v), and the average and variance are m (v) (= Exp [d (v )]), S (v) (= Var [d (v)]). Further, the correlation coefficient between the maximum delays d (v) and d (w) to the two points v and w is expressed as r (v, w) (= R [d (v), d (w)]. The correlation coefficient between the maximum delay d (v) to the point v and the delay t (e) of the branch e is c (v, e) (= R [d (v), t (e)]). It expresses.

  FIG. 1 is a flowchart showing a delay distribution calculation method according to the first embodiment of the present invention. In this embodiment, the distribution of the maximum delay d (v) from the source to each point v (vεV) is calculated in the topological order in the acyclic graph G = (V, E). To do. To this end, consider a set of points Front where the following conditions (A), (B), and (C) always hold.

  (A) For each point v (vεFront), the average m (v) and variance s (v) of the maximum delay d (v) are known.

  (B) The correlation coefficient r (v, u) of the maximum delays d (v) and d (u) is known for any two points v and u (v, uεFront).

(C) For each point v (vεFront), the correlation coefficient c (v, e) between the maximum delay d (v) and the delay t (e) of an arbitrary branch e (eεE) is known It is.
Note that the serial branches are reduced to one branch by the method described above.

  First, in the input step S11, circuit information 11 representing the connection relationship of each element in the integrated circuit, performance distribution information 12 representing the performance distribution of each element such as a wiring and a logic gate included in the integrated circuit, and the wiring and the element Correlation information 13 representing the correlation of the delay distribution is input. Based on the circuit information 11, an acyclic graph representing the integrated circuit is generated.

  Next, in the calculation point selection step S12, calculation points to be subjected to delay distribution calculation are selected. Initially, Front = S (a set of sources), and m (u) = s (u) = 0 for each point u (uεS). At this time, all the correlation coefficients between the different points in the set front may be set to 0, so the above condition is satisfied. If there is a deviation or variation in the signal transmission time of the main input, it can be incorporated in advance here. In subsequent iterations, a point is selected from the acyclic graph based on the topological order.

  Next, in the partial circuit delay distribution calculation step S13, the correlation between the delay distribution at the calculation point selected in the calculation point selection step S12 and the already selected point is calculated. Then, while satisfying the above conditions (A), (B), and (C), a new point w is added to the set Front.

Now, let the points of the set front be v _i (i = 1, 2,..., K,..., H), and consider a point w such that all incoming branches come from the set front. In order to simplify the description, let e _i = (v _i , w) (i = 1, 2,..., K) be a branch that enters the point w. Also, a set of points v _i (v _i εFront) at which all the end points u of the outgoing branches (v _i , u) are included in Front ｗ [w] is denoted as Eliminate.

を用いて求めることができる。 If d ′ _i (w) represents the maximum delay of a path from a certain source through the branch e _i = (v _i , w) to the point w,
d ′ _i (w) = d (v _i ) + t (e _i ) (34)
Since it is, using equation (18) to (20), 'I mean _{i (w) m' d i} (w) and variance s' _i a (w),

Can be obtained using

Here, the delay branch e _i is what both branches of delay on the path because it is independent leading to v _i, d (v _i) and t (e _i) are also independent, c (v _i, e _i ) = 0. Therefore,
s ′ _i (w) = Var [d _i (w)]
= S (v _i ) + σ ² (e _i ) (36)
The relationship is established.

であるから、

の関係が成立する。ここでｓ（ｕ）＝０の場合には、ｒ’_i（ｗ，ｕ）＝０としておく。 Also, from equations (20) and (22), for any point u (uεFront) and any branch e (eεE) where s (u) ≠ 0,

Because

The relationship is established. Here, when s (u) = 0, r ′ _i (w, u) = 0.

Next, let d _i (w) be the maximum delay of the path from the source v0 to any one of the branches e _j = (v _j , w) (j = 1, 2,..., I). That is,
d _i (w) = max [d _j ′ (w) | 1 ≦ j ≦ i] (41)
And

Obviously, d ₁ (w) = d ′ ₁ (w). Therefore, when the distribution regarding d _i-1 (w) is obtained, that is,
m _i-1 (w) = Exp [d _i-1 (w)] (42)
s _i-1 (w) = Var [d _i-1 (w)] (43)
r _i-1 (w, u) = R [d _i-1 (w), d (u)] (44)
c _i-1 (w, e) = R [d _i-1 (w), t (e)] (45)
Consider that the following equations (46) to (49) are obtained.
m _i (w) = Exp [d _i (w)] (46)
s _i (w) = Var [d _i (w)] (47)
r _i (w, u) = R [d _i (w), d (u)] (48)
c _i (w, e) = R [d _i (w), t (e)] (49)
For this reason, Formula (50) is used.
d _i (w) = max [d _i-1 (w), d ′ _i (w)] (50)
If i = 2k is calculated in order from the case of i = 2 and the distribution of d (w) is obtained, the point w can be included in the set Front. It can be seen that the above conditions (A), (B), and (C) are satisfied for the new set Front = (Front-Eliminate) ∪ [w] when the point w is put in the set Front.

から計算できる。したがって、

とすれば、

によって、ｄ_i（ｗ）の分布を計算することができる。したがって、回路内の点ｗを集合Ｆｒｏｎｔに入れるという操作を繰り返すことにより、回路のすべての点を集合Ｆｒｏｎｔに入れることができ、相関を考慮した回路の遅延分布を計算することができる。 The distribution of d _i (w) is expressed by Equation (9) to Equation (15), that is,
α = SQRT [s _i−1 (w) + s ′ _i (w) −2SQRT [s _i−1 (w) s ′ _i (w)] · r ′ _i (w, w)] (51)
Calculate using. Here, r ′ _i (w, w) = R [d _i−1 (w), d ′ _i (w)] is

Can be calculated from Therefore,

given that,

Can calculate the distribution of d _i (w). Therefore, by repeating the operation of putting the point w in the circuit into the set front, all the points of the circuit can be put into the set front, and the delay distribution of the circuit considering the correlation can be calculated.

  In this way, the operation of removing the set Eliminate from the set Front and putting the point w into the set Front is repeated, and if Front = T is finally established, the processing is ended. This determination is performed in the end condition determination step S14.

  When the delay distribution calculation for all points is completed, in the output step S15, the delay distribution information 14 of the output terminal, that is, the average and variance of the delays at each point of the sink T are output, and the process ends. Otherwise, the process returns to the calculation point selection step S12 to continue the process.

  In this embodiment, the correlation information is represented by the correlation coefficient in the delay distribution, but may be represented by the degree of correlation of the delay value itself instead of the delay distribution. It is also possible to calculate a delay distribution using a correlation regarding performance other than delay.

  For example, correlation information may be generated by referring to a layout of an integrated circuit to be designed using correlation characteristic information. Here, the “correlation characteristic information” represents the relationship between the correlation of the performance of the wiring or the element and the feature on the layout. FIG. 12 is a flowchart showing a method for generating correlation information.

  The element characteristic information includes delay, gate width, gate length, oxide film thickness, ion implantation concentration, saturation current between source and drain, threshold voltage, and the like. These process variations include completely random factors and factors that change depending on layout information such as shape, position, and orientation. For example, since the ion implantation concentration of the transistor diffusion layer depends on the direction of the implantation apparatus at the time of manufacture, it is easier to obtain the same characteristics when arranged in the same direction. In addition, since the ion implantation concentration, oxide film thickness, etc. tend to change continuously depending on the arrangement position, when comparing the characteristics of the two elements, the probability of showing similar characteristics increases as they are arranged closer to each other. . Further, the gate width and the gate length are likely to change depending on the surrounding layout shape such as the distance to other gates. Further, it is considered that the correlation between the variations of delays of different paths for the same logic gate and wiring delays when the common wiring branches in the middle is strong.

An example of correlation characteristic information is shown.
(1) Between the distance D between the two elements and the correlation coefficient R of the delay distribution of the two elements,
When there is a relationship of R = a · exp (−D / b) (a and b are constants)
(2) When the correlation coefficient is c when two elements are arranged in the same direction, but e when they are in different directions (c and e are constants)
(3) When the wiring branches in the middle, when the ratio of the common portion in the total wiring length is w, the correlation of the mutual wiring delay is R = f · w (f is a constant)
(4) In the case where the correlation coefficient of the element delay caused by the same element is g, but is h in the case of another element (g and h are constants)
Etc. A part of these relational expressions may be used, or a combined expression may be used.

  The correlation characteristic information can be obtained by measurement. For example, manufacture an integrated circuit for characteristic evaluation that includes many sample elements with different orientations, surrounding layout shapes, and distances between elements, measure the characteristics of each element, and calculate the average value and variance of the element characteristics Find it. FIG. 13 is a flowchart showing a method for generating correlation characteristic information. Even if the correlation of the delay distribution is not directly obtained, it is known that the saturation current of the transistor is almost proportional to the delay, the gate length is inversely proportional to the saturation current, and the gate width is proportional to the saturation current. Therefore, if a correlation between the layout conditions and the gate length, gate width, saturation current, and the like can be obtained, it can be used as a delay correlation.

  Thus, the correlation characteristic information may be obtained in advance according to the process before designing the integrated circuit. In actual integrated circuit design, correlation information between elements may be obtained based on information such as an actual layout from the correlation characteristic information.

  For example, the distance between the elements is D, and the correlation coefficient R of the delay distribution of two elements arranged in the same direction is obtained by R = f (D, c, h). Here, f (x, y, z) is an arbitrary function, for example, a function of f (x, y, z) = Kyz / x (K is a constant).

(Second Embodiment)
The second embodiment of the present invention relates to a method for evaluating a circuit by removing a false path for a given circuit.

  A “logical false path” can be characterized using information about the connection structure of the circuit. That is, in the acyclic graph G = (V, E), it can be defined as a path that passes through two points x and y simultaneously. The “functional false path” can be specified as a path including a cause partial path, and the cause partial path is a path from a point x of X to a point y of Y using a point set pair (X, Y). (Disclosed in HC Chen and DH Du, “Path sensitization in critical path problem,” IEEE Trans. Computer-Aided Design of ICs and Systems, vo.12, no.2, pp.196-207, 1993).

  That is, in FIG. 2, a false path can be defined as a path that specifies a point set pair (X, Y) and passes through a point 41 of X and a point 42 of Y at the same time. Therefore, these paths are removed from the graph G400. If possible, the accuracy of the critical path delay can be increased.

  Here, a false path removal method that can be designated by a point set pair (X, Y) will be described. However, it is assumed that there is no directional road between two different points x ′ and x ″ included in X, and there is no directional road between two different points included in Y. In the logic circuit, x This assumption is not unnatural, since ∈ X and y ∈ Y correspond to the input and output of the gate, respectively: a directed path from a point x of X and an existence to a point y of Y A set of points where both directions are present is U ′, and a set obtained by removing X and Y from U ′ is U (= U′−X−Y). 43 is G [U] = (U, E [U]), where E [U] = [(v, w) εE | vεU, wεU].

Further, in FIG. 3, the end point of the branch coming out from the set G [U], the set 52 of points other than the Y point 42 is set to Out, and the start point of the branch entering the set G [U] is set. A set 51 of points other than the point 41 of X is In. That is,

  At this time, the following properties are apparent.

  i. Out and In do not have a common element, and there is no path from the point v of Out to the point w of In. Because, assuming that there is a directed road from point v to point w, there is a directed road from point X to point Y at the same time for point v or point w. This is contrary to the assumption of the set U.

  ii. There is no path from Out point v to Y point y.

  iii. There is no path from the point x of X to the point v of In. If such a path exists, the point v must be included in U, contrary to the assumption of the set U.

  FIG. 4 shows a flowchart of the circuit performance evaluation method of the present invention. In FIG. 4, first, in the input step S <b> 21, circuit information 21 representing the connection relationship and performance of the circuit to be evaluated and false path information 22 are input. In the false path information 22, each false path is represented by a set of two points on a graph representing an integrated circuit.

  Next, in an equivalent circuit generation step S22, an equivalent circuit that does not include a false path is generated from the input circuit information 21. When there are a plurality of false paths, this equivalent circuit generation may be repeated. Then, in the equivalent circuit evaluation step S23, circuit evaluation such as delay and power consumption is performed using the equivalent circuit information 23 not including the false path.

  FIG. 5 is a flowchart showing the process of the equivalent circuit generation step S22. Here, an equivalent circuit is generated by performing a deformation operation of the acyclic graph G = (V, E) on the point set pair (X, Y).

  First, in the partial circuit extraction step S22a, the partial circuit G [U] 43 is extracted as shown in FIG. Next, as shown in FIG. 6, in the partial circuit duplication step S22b, the partial circuit G [U] 43 is duplicated to create a graph G ″ 62 corresponding to the second partial circuit, and the original partial circuit G [U]. 43 is a graph G′61 corresponding to the first partial circuit.Next, in the partial circuit connection changing step S22c, all branches from the point of the graph G′61 to y42 are removed, and instead the correspondence of the graph G ″ 62 The branch EG1 from the point to y42 is attached. Further, a duplicate EG3 of the branch EG2 that enters the point of the graph G′61 from the point of In51 is added between the point of In51 and the corresponding point of the graph G ″ 62. The branch EG4 entering the point is left as it is.

  Further, when a new sink is born in the graph G′61 or a new source is born in the graph G ″ 62, the operation of removing both such points and branches connected thereto is repeated, and the graph G Make sure there are no sinks or sources in '61 and G ″ 62. The cyclic graph generated in this way is represented as G <(X, Y)>.

  The following properties hold for this graph G <(X, Y)>.

  (I) In G <(X, Y)>, there is no path that passes through the point x of X and the point y of Y at the same time.

  (Ii) All paths in the original graph G that do not pass the X point and the Y point simultaneously exist in G <(X, Y)>.

  (Iii) Every path existing in G <(X, Y)> has a path corresponding to this path (the same point as the passing point and branch) in the original graph G.

  Therefore, when the variation in critical delay is obtained in G <(X, Y)>, the variation in the maximum delay of the path that does not pass through the point X and the point Y in the original graph G is obtained.

  FIG. 7 is a diagram showing another example of a graph transformation process for generating an equivalent circuit that satisfies the above-described properties. That is, in the partial circuit connection changing step S22c, all branches from the point of the graph G′61 corresponding to the first partial circuit to the Y point 42 are removed, and instead the graph G ″ 62 corresponding to the second partial circuit. The branch EG5 is reassigned from the corresponding point of Y to the point 42 of Y. Then, after adding G ″ 62 to G′61, the duplicate EG7 of the branch EG6 entering the point of Out52 from the point of G′61 is changed to the corresponding G The points from “62” to the point of Out 52 are also removed, and all branches entering the point of G′61 from the points of In51 are removed, and instead, the branches EG8 are replaced with the corresponding points of “G51” from In51.

  In the example of FIG. 6, the graph G ′ 61 corresponding to the first partial circuit is connected to the first point 41, In 51 and Out 52, and is not connected to the second point 42. On the other hand, the graph G ″ 62 corresponding to the second partial circuit is connected to the second point 42 and In51, and is not connected to the first point 41 and Out52. There is no path from the point 41 to the second point 42.

  In the example of FIG. 7, the graph G ′ 61 corresponding to the first partial circuit is connected to the first point 41 and Out 52, and is not connected to the second point 42 and In 51. On the other hand, the graph G ″ 62 corresponding to the second partial circuit is connected to the second point 42, In 51 and Out 52, and is not connected to the first point 41. There is no path from the point 41 to the second point 42.

  Hereinafter, the equivalent circuit generation method according to the present embodiment will be described in a generalized manner.

  A set of all false paths to be removed is represented by a set of point set pairs F = [(Xi, Yi) | i = 1, 2,..., F]. Therefore, to remove all these false paths from G, the above deformation operation is repeated for each pair (X, Y) (εF). At this time, when G is deformed to create G <X, Y>, since the point of U is duplicated, a pair (X ′, Y ′) other than (X, Y) (∈F − [( X, Y)]) is modified using U as follows:

I. When X'∩U ≠ f:
If the replica remains in G <X, Y> at X'∩U, instead of becoming a new sink or source, put that replica in X '.

II. When Y'∩U ≠ f:
If the replica remains in G <X, Y> at Y'∩U, and does not become a new sink or source, put that replica in Y ′.

  Now, the pair before update is represented as (X ′, Y ′), and the updated pair is represented as (X ″, Y ″). Clearly, in G <X, Y>, there is no directed road connecting the points of X ″, and there is no directed road connecting the points of Y ″. Further, in G, a set of paths that simultaneously pass the points X and Y is P (X, Y), and a set of paths that simultaneously pass the points X ′ and Y ′ is P (X ′, Y ′). In G <X, Y>, a set of paths that simultaneously pass through the points X ″ and Y ″ is represented as P ′ (X ″, Y ″). At this time, any path included in P ′ (X ″, Y ″) corresponds to any path in P (X ′, Y ′). That is, a path corresponding to the path P (X ′, Y ′) and existing in G <X, Y> is included in P ′ (X ″, Y ″). Therefore, no G path other than P (X ′, Y ′) is included in P ′ (X ″, Y ″).

  Therefore, if a graph obtained by performing a transformation operation on (X ′, Y ′) with respect to G <(X, Y)> is denoted by G ″, G ″ represents P ′ (X ″, Y ″). Since all the paths have been removed, all the paths from G to P (X ′, Y ′) have been removed. That is, the following properties hold.

  (I) G ″ has neither a path corresponding to P (X, Y) nor a path corresponding to P (X ′, Y ′).

  (Ii) All paths other than P ′ (X ″, Y ″) in G <X, Y> exist in G ″. Therefore, P (X, Y), P (X ′, Y in G) All paths other than ') exist in G ″.

  (Iii) Any path that exists in G ″ has a corresponding one in G <X, Y> and therefore also in G.

  From this, if the graph from which all false paths specified by F are removed by repeating the above-described graph transformation operation and point set pair update operation is G * = (V *, E *), G The following relationship is established between the path on * = (V *, E *) and the path on the original graph G = (V, E).

  (I) For any pair (X, Y) εF, there is no path on G * that passes through the point x of X and the point y of Y at the same time.

  (Ii) All G paths other than the false path specified by F exist in G *.

  (Iii) Any path existing in G * has a corresponding one in G.

  This operation can be expressed as follows.

For F = [(X _i , Y _i ) | i = 1, 2,..., F], G_ (1) = G <X_ (1), Y_ (1)>, G _i = G _i−1 <X _i ⁱ⁻¹ , Y _i ⁱ⁻¹ > (i = 2,..., F). Here, G _i−1 <X _i ⁱ⁻¹ , Y _i ⁱ⁻¹ > (i = 2,..., F) is (X _i ⁱ⁻¹ , Y _i ⁱ ) with respect to the graph G _i−1 . ⁻¹ ) is a graph obtained by performing a transformation operation on (X _i ⁱ⁻¹ , Y _i ⁱ⁻¹ ) (i = 2,..., F) is (X _i ⁱ⁻² , Y _i ^{i−−). 2} ) is a pair obtained by performing an update operation using U _i-1 defined by (X _i-1 ^i-2 , Y _i-1 ^i-2 ).

This U _i-1 is obtained from the point of X _i-1 ^i-2 on G _i-1 = G_ (i-2) <X _i-1 ^i-2 , Y _i-1 ^i-2 >. those from a set of points both Yukodo to point towards the road and Y _i-1 ^i-2 is present, remove the point X _i-1 in terms of ^i-2 and Y _i-1 ^i-2 It is.

Starting from G_ (0) = G, X_ (1) ^ (0) = X_ (1), Y_ (1) ^ (0) = Y_ (1), each (X _i , Y _i ) (i = 1, 2,..., F), the operation of generating G _i = G _i-1 <X _i ^i-1 , Y _i ^i-1 > is repeated to obtain G _f . Thus, if a set of all paths on G specified by F is P (F) = ∪iP (X _i , Y _i ), there is a path corresponding to P (F) on G _f. Without passing, the path other than P (F) of G has a corresponding path on G _f .

(Third embodiment)
The third embodiment of the present invention relates to a method for extracting a false path from a circuit to be designed. The extracted false path can be deleted by using the method disclosed in the second embodiment.

  As already described in the second embodiment, the “logical false path” can be characterized using information about the connection structure of the circuit. That is, in the acyclic graph G = (V, E), it can be defined as a path that passes through two points x and y simultaneously.

  Now, a signal value whose output is determined when a value is given to one input of a logic gate, such as a signal value “0” in an AND gate, is called a “control signal”. A signal value such as the value “1” that does not determine the output even when the value is given to one input of the logic gate is called a “non-control signal”. Each of the AND, OR, NAND, and NOR gates has a control signal and a non-control signal, and they are in a negative relationship with each other. In contrast, in the inverter, both “0” and “1” are control signals, and in the XOR gate, both “0” and “1” are non-control signals. That is, in each of the AND, OR, NAND, and NOR gates and the inverter, when a control signal is given to one input, the output is determined.

  Therefore, a control signal propagation operation is determined for each of these gates. For example, in FIG. 11, when z = “1”, the output of the inverter G4 is “0”, and the output c of the AND gate G5 is “0”. For this reason, z = 1 leads to c = 0 by the propagation operation. Therefore, when c = 1, z = 0. This relationship can also be derived by a back propagation operation.

  In each of the AND, OR, NAND, and NOR gates, all other inputs must be non-control signals in order to activate the path through which the non-control signal passes. On the other hand, in order to activate the path through which the control signal passes, a non-control signal is input to each input other than the input v through which the path passes, or a control signal is input after the control signal reaches v. Either. Therefore, a delay amount is inevitably required to determine whether or not the path through which the control signal passes is activated. On the other hand, it is possible to determine whether the path through which the non-control signal passes is activated only by the connection relation and the gate type regardless of the time factor.

  Therefore, in the graph G = (V, E), for each branch e = (v, w) in the logic gate through which the non-control signal passes, the condition for activating that branch, that is, other than w is entered. The condition that the non-control signal passes through all branches of is given. This is called “an activation condition for the non-control signal branch e”. The condition that the non-control signal s enters the other branch e ′ = (u, w) entering w is expressed as Net (u) = s, where Net (u) associated with u of G is Net (u). .

  When the signal s of Net (u) has a fan-out other than u, and it enters another logic gate L as a control signal, the value of the output of L is determined by a propagation operation. Therefore, the logical value listed as the activation condition of the non-control signal branch is propagated using the propagation operation. For example, in FIG. 11, the activation condition of (v1, w1) in the gate G1 as the first gate is z = 1, that is, Net (u) = 1, but this is because the input a = 1 of the gate G4. , And can be propagated to the input c = 0 of the gate G6. Then, if c = 1, z = 0, so that the activation conditions c = 1 and z = 1 of the branch (b1, y1) in the AND gate G6 as the second gate are not compatible, and there is a contradiction. You can see that it happens. That is, since the branch (v1, w1) and the branch (b1, y1) cannot be activated at the same time, a path that passes through these branches simultaneously can be determined to be a false path. Such a false path can be designated by a point pair (v1, b1).

  FIG. 8 is a flowchart showing a false path extraction method according to the third embodiment of the present invention. As shown in FIG. 8, circuit information 31 is first input in an input step S31. Next, in the necessary condition determining step S32, the necessary condition of the signal for activating the non-control signal in each gate is determined. Assume that Enc = (unc, wnc) is a branch in the gate and the input corresponds to the non-control signal ncs, and a set of branches having Net (u) = ncs as an activation condition is RE (enc) = [(vnc, wnc) εE]. Net (u) = ncs can also determine the value of each net by a propagation operation.

  Then, in the signal change contradiction extraction step S33, signal changes of the gates that are not activated simultaneously are extracted from the necessary conditions determined in the necessary condition determining step S32. Assume that the value of an input c of a certain gate G is set to a G control signal cs, and that G has an input b other than c. At this time, if c in the gate G is a branch corresponding to the control signal ncs, enc ′ = (cnc, ync), each branch (bnc, ync) of RE (enc ′) = [(bnc, yncεE)] ) Uses Net (c) = ncs as an activation condition, so the branch (vnc, wnc) (∈RE (enc)) and the branch (bnc, ync) (∈RE (enc ′)) are not activated at the same time. Accordingly, in the gate G, when a set of points that can be reached from the point v by a directed road is suc (v), the point pair (vnc, bnc) is a point pair that specifies a false path.

Also, finding all such point pairs for one branch enc can be done with O (m), where m is the number of branches in the graph, so finding all point pairs is O It can be done with a calculation amount of (m ² ).

As described above, the solving means taken by the first invention is a method of calculating a delay distribution for an integrated circuit to be designed, as a method of calculating a delay distribution, and a correlation indicating a correlation between performances of wirings or elements included in the integrated circuit. The delay distribution is calculated with reference to the information.

  According to the first aspect of the invention, when calculating the delay distribution of the integrated circuit, the correlation information representing the correlation of the performance of the wirings or elements included in the integrated circuit is referred to. Thereby, the delay distribution of the integrated circuit can be calculated with high accuracy.

  In the second invention, the correlation information in the first invention represents a delay correlation as the performance correlation.

  In the third invention, the correlation information in the first invention is represented by a correlation coefficient in the performance distribution.

  According to a fourth invention, in the first invention, a step of generating a graph representing the integrated circuit based on circuit information representing a connection relation of each element in the integrated circuit, and the integrated circuit includes And a step of calculating a delay distribution for each point in the graph using the performance distribution information representing the performance distribution of the wirings and elements and the correlation information.

  And in 5th invention, the calculation process in the said 4th invention selects the point which does not belong to the set which consists of the point from which the delay distribution was already calculated from the said graph, The said 1st process, A second step of calculating a delay distribution and a correlation of performance between each point belonging to the set based on the performance distribution information and correlation information for the calculation point selected by one step, and It is assumed that the first and second steps are repeated while adding the calculation points for calculating the delay distribution to the set.

  According to a sixth aspect of the present invention, in the first aspect of the present invention, the correlation characteristic information representing the correlation between the performances of the wirings or between the elements and the characteristics on the layout is used, and the layout of the integrated circuit is referred to. And a step of generating the correlation information.

  In the seventh invention, the correlation characteristic information in the sixth invention represents at least the relationship between the distance between elements and the correlation of performance.

  In the eighth invention, it is assumed that the correlation characteristic information in the sixth invention represents at least the relationship between the element orientation and the performance correlation.

  In the ninth invention, the correlation characteristic information in the sixth invention represents at least the relationship between the presence or length of a common portion in two wirings and the correlation of performance.

  According to a tenth aspect, in the sixth aspect, the characteristics of each wiring or element are evaluated for the characteristic evaluation integrated circuit, and based on the evaluation result and the layout of the characteristic evaluation integrated circuit. And a step of generating the correlation characteristic information.

  The eleventh aspect of the present invention provides a signal transmission path corresponding to a false path based on circuit information representing a connection relation of components in the integrated circuit as a method for evaluating an integrated circuit to be designed. And a second step of evaluating the integrated circuit using the equivalent circuit generated by the first step.

  According to the eleventh aspect, the evaluation can be performed using an equivalent circuit that does not include a false path. Therefore, the performance of the integrated circuit can be evaluated at high speed and with high accuracy.

  In the twelfth invention, the eleventh invention uses false path information representing a false path, and the false path information represents the false path by two points on the graph representing the integrated circuit. It shall be.

  Furthermore, in the thirteenth invention, the first step in the twelfth invention is a first step in which the first point is an input and the second point is an output among two points representing a false path. A partial circuit extracting step for extracting the partial circuit, a partial circuit duplicating step for duplicating the first partial circuit and generating it as a second partial circuit, the first and second partial circuits, A partial circuit connection changing step for changing the connection with the circuit so that there is no path from the first point to the second point is provided.

  In the fourteenth invention, in the partial circuit connection changing step in the thirteenth invention, a set of branch starting points entering the first partial circuit other than the first point is set to In, and the second If the set of the end points of the branches coming out of the first partial circuit other than the point is Out, then either one of the first and second partial circuits is the first point and In and Out. And the second point is not connected to the second point, and the other is connected to the second point and In, and not connected to the first point and Out. Shall be changed.

  In the fifteenth aspect, in the partial circuit connection changing step according to the thirteenth aspect, a set of branch start points entering the first partial circuit other than the first point is In, and the second If the set of the end points of the branches coming out of the first partial circuit other than the point is Out, then either one of the first and second partial circuits is connected to the first point and Out. And the second point and In are not connected, and the other is connected to the second point and In and Out, and is not connected to the first point. Shall be changed.

  According to a sixteenth aspect of the present invention, as a method for extracting a false path for an integrated circuit to be designed, an activation condition of an uncontrolled signal branch in each logic gate included in the integrated circuit is used. A false path is extracted.

  In the seventeenth invention, in the sixteenth invention, the logic value listed in the activation condition of the non-control signal branch in the first gate is propagated using the propagation operation, and the value to propagate is controlled. When the signal is a signal, the propagation is repeated, and when there is a contradiction between the propagated value and the activation condition of the non-control signal branch of the second gate, the first gate to the second gate. Is detected as a false path.

  In the false path extraction method according to the present invention, since the correlation of performance between wirings or elements is taken into account in the calculation of the delay distribution of the integrated circuit, the delay estimation accuracy is improved, so that the design of the integrated circuit is excessive. The present invention relates to a technique for evaluating the performance in designing an integrated circuit such as a CMOS / LSI, for example. It is useful as a technique related to delay distribution calculation and false path removal and extraction.

It is a flowchart which shows the delay distribution calculation method which concerns on the 1st Embodiment of this invention. It is a figure showing the designation | designated expression of a false path | pass. It is a figure showing the graph before a change. It is a flowchart which shows the circuit performance evaluation method which concerns on the 2nd Embodiment of this invention. 6 is a flowchart of equivalent circuit generation processing in the circuit performance evaluation method of FIG. It is a figure showing the graph after a change. It is a figure showing the other example of the graph after a change. It is a flowchart which shows the false path | pass extraction method which concerns on the 3rd Embodiment of this invention. It is a figure showing an example of a logic circuit. It is a figure showing the acyclic graph showing the circuit of FIG. It is a figure which shows the logic circuit containing a false path | pass. It is a flowchart which shows the method of producing | generating correlation information. It is a flowchart which shows the method of producing | generating correlation characteristic information.

Explanation of symbols

11 Circuit information 12 Performance distribution information 13 Correlation information 22 False path information 41 First point 42 Second point 43 First partial circuit 51 Set In
52 Set Out
61 Graph corresponding to the first partial circuit 62 Graph corresponding to the second partial circuit 200 Acyclic graph G1 First gate G6 Second gate

Claims (2)

A method of extracting a false path for an integrated circuit to be designed,
A false path extracting method, wherein the false path is extracted using an activation condition of a non-control signal branch in each logic gate of the integrated circuit. In claim 1,
Propagating the logical value listed in the activation condition of the non-control signal branch in the first gate using a propagation operation,
While the value to be propagated is a control signal, the propagation is repeated,
When a contradiction occurs between the propagated value and the activation condition of the non-control signal branch of the second gate, the path from the first gate to the second gate is detected as a false path. And a false path extraction method.

Images