JP2005284841A - Data communication device and data communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable each CPU to write to and read from a dual port memory without reading pointers to compute a writable or readable area. <P>SOLUTION: The CPUs 111 and 121 exchange data via the dual port memory 103. A storage device 101 holds a use status of the dual port memory 103. An interrupt/memory management device 102 reads in the use status of the dual port memory 103 from the storage device 101 and, according to the use status, generates a memory address and generates an interrupt signal to start data exchange to the CPUs 111 and 121. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data communication device and a data communication method for performing data communication between a plurality of circuits, and in particular, to a data communication device and a data for performing data communication between a plurality of CPUs using a dual port memory. It relates to a communication method.

  FIG. 8 is a block diagram showing a configuration of a conventional inter-CPU data communication device (see Patent Document 1).

In this inter-CPU data communication device, for example, when data communication is performed with the CPU 11 as a transmission side, the read pointer 23 indicating the read data address in the dual port memory 15 in order for the CPU 11 to write data into the dual port memory 15. Then, the CPU 11 reads the write pointer 21 indicating the unread data address in the dual port memory 15, and the CPU 11 needs to calculate whether data can be written and the range in which data can be written. On the other hand, in order for the CPU 13 on the receiving side to read data from the dual port memory 15, it is necessary to read the read pointer 23 and the write pointer 21 by the CPU 13 and calculate the range in which the data can be read by the CPU 13.
JP 2002-207713 A

  However, in the conventional inter-CPU data communication apparatus, when writing to and reading from the dual port memory, each CPU needs to read the read pointer and the write pointer to calculate the writable range or the readable range. This increases the processing load on the CPU.

  The present invention has been made in view of this point, and at the time of data transmission / reception, each CPU reads the read pointer and the write pointer and calculates the writable range or the readable range to the dual port memory. An object of the present invention is to provide a data communication apparatus and a data communication method capable of writing and reading data and reducing the processing load on the CPU.

  The data communication device according to the present invention is installed outside a plurality of CPUs, a dual port memory that temporarily stores and relays data when the data is transmitted and received between the plurality of CPUs. Based on the size of the transmitted / received data and the usage status of the dual port memory, the memory address of the area where the data is stored in the dual port memory, and each CPU writes or reads data to this area. And a management means for managing the timing to perform.

  A data communication device according to the present invention includes a plurality of CPUs that perform data transmission / reception with each other, a dual port memory that is used for data transmission / reception between the plurality of CPUs, a storage device that holds a usage status of the dual port memory, The usage status of the dual port memory is read from a storage device, and the data in the dual port memory is sent to each CPU based on the size of data transmitted and received between the plurality of CPUs and the usage status of the dual port memory. And a management device for generating an interrupt signal for starting transmission / reception of the data.

  In the data communication device according to the present invention, in the configuration described above, the management device reads the usage status of the dual port memory from the storage device during data transmission, and determines the size of the data and the usage status of the dual port memory. Based on the above, a usable memory area in the dual port memory is calculated, a memory address corresponding to the calculated memory area is generated, the memory address is notified to the CPU on the transmitting side by an interrupt, and the calculated While the attribute of the memory area is updated during writing, at the time of data reception, the memory address of the memory area that has been written by the sending CPU is notified to the receiving CPU by an interrupt, and the writing is completed. It takes a configuration to update the attributes of while reading.

  According to these configurations, at the time of data transmission / reception, each CPU can read and write to the dual port memory without reading the read pointer and the write pointer and calculating the writable range or the readable range. The processing load on the CPU can be reduced.

  In the data communication device according to the present invention, in the configuration described above, when the management device cannot secure a memory area in which the data can be written, the management device suspends the data write request from the transmission side CPU, and the reception side CPU stores the data After completing the reception, it is determined again whether or not the memory area can be secured.If the memory area can be secured, the memory address of the secured memory area is notified to the CPU on the transmission side by an interrupt. The data write request from the sending CPU is again held.

  According to this configuration, even when the memory area having the data size requested by the transmission side CPU cannot be secured immediately, the transmission side CPU can be made to write the transmission data when the memory area can be secured.

  In the above configuration, the data communication device according to the present invention includes a timer that starts counting a predetermined time when it is determined that the management device cannot secure a memory area in which the data can be written, and the predetermined time If a memory area in which the data can be written cannot be secured before the time elapses, a notification is sent to the CPU on the transmission side.

  According to this configuration, when the memory area having the data size requested by the transmission side CPU cannot be secured, the transmission side CPU can be prevented from waiting for data transmission for a long time.

  The communication terminal device of the present invention employs a configuration including any of the data communication devices described above.

  According to this configuration, it is possible to provide a communication terminal device having the same operational effects as described above.

  The data communication method of the present invention is used in a data communication apparatus including a plurality of CPUs and a dual port memory that temporarily stores and relays data when the data is transmitted and received between the plurality of CPUs. A data communication method, wherein a memory address of an area in which data is stored in the dual port memory and a timing at which each CPU writes or reads data in this area are provided outside the plurality of CPUs. The managed device is managed based on the size of the transmitted / received data and the usage status of the dual port memory.

  According to this method, at the time of data transmission / reception, each CPU can read and write to the dual port memory without reading the read pointer and the write pointer and calculating the writable range or readable range. CPU processing load can be reduced.

  As described above, according to the present invention, at the time of data transmission / reception, each CPU reads the read pointer and the write pointer, and writes to the dual port memory without calculating the writable range or the readable range. Reading can be performed, and the processing load on the CPU can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, a case where data transmission / reception is performed between two CPUs will be described as an example.

(Embodiment 1)
FIG. 1 is a block diagram showing the main configuration of the data communication apparatus according to Embodiment 1 of the present invention.

  The data communication device according to the present embodiment includes a storage device 101, an interrupt / memory management device 102, a dual port memory 103, a CPU 111, an interrupt signal line 112, an interrupt signal line 113, a local bus 114, a CPU 121, an interrupt signal line 122, It has an interrupt signal line 123 and a local bus 124.

  Each unit of the data communication apparatus according to the present embodiment performs the following operation.

  The CPU 111 and the CPU 121 exchange data between a plurality of CPUs. The dual port memory 103 is used for data transmission / reception. The storage device 101 holds the memory usage status of the dual port memory 103. The interrupt / memory management device 102 reads and updates the memory usage status of the dual port memory 103 from the storage device 101, generates a memory address for the CPU 111 or the CPU 121, and causes the CPU 111 and the CPU 121 to start a data transmission / reception operation. Generate an interrupt signal. The interrupt signal line 112, the interrupt signal line 113, the interrupt signal line 122, and the interrupt signal line 123 transmit an interrupt signal. The local bus 114 is for transmitting and receiving data among the CPU 111, the interrupt / memory management device 102, and the storage device 101. The local bus 124 is for transmitting and receiving data among the CPU 121, the interrupt / memory management device 102, and the storage device 101.

  Next, the operation of the entire data communication apparatus having the above configuration will be described.

  FIG. 2 is a sequence diagram showing a series of operations of each part of the data communication apparatus. Here, a case where data is transmitted from the CPU 111 to the CPU 121 will be described as an example.

  CPU 111 on the transmission side transmits a data transmission request including the data size to be written to interrupt / memory management apparatus 102 in order to write data to dual port memory 103 (ST1110). The interrupt / memory management apparatus 102 transmits a memory usage status request to the storage device 101 in order to read the memory usage status of the dual port memory 103 stored in the storage device 101 (ST1120). The storage device 101 responds to the interrupt / memory management device 102 with respect to the stored memory usage status of the dual port memory 103 (ST1130). The interrupt / memory management device 102 compares the read memory usage status of the dual port memory 103 with the write data size included in the data transmission request of ST1110, and the memory area equivalent to the requested data size is found. It is determined whether or not it can be secured (ST1135). When the memory area can be secured, the interrupt / memory management apparatus 102 makes a memory usage status update request to the storage apparatus 101 to indicate that the secured memory area is being used for writing by the transmission side CPU 111 ( (ST1140) The attribute of this memory area is updated with information indicating that writing is in use. Further, as soon as the memory usage status update response is made from the storage device 101 (ST1150), the interrupt / memory management device 102 transmits a data transmission response by interruption to the CPU 111 on the transmission side (ST1160). This data transmission response includes the start address of the usable memory area of the dual port memory 103 (the start address of this area). Receiving the data transmission response in ST1160, the transmission side CPU 111 starts data transmission from the start address of the usable memory area of the dual port memory 103, and starts data writing (ST1170). Then, as soon as the data writing is completed, the transmission-side CPU 111 transmits a data transmission completion notification to the interrupt / memory management apparatus 102 (ST1180).

  Next, the interrupt / memory management apparatus 102 notified of the completion of data transmission in ST1180 has a usable memory area in the dual port memory 103 (a memory area in which a start address is transmitted by a data transmission response in ST1160) as a reception side. In order to indicate that the reading is in use by the CPU 121, a memory usage status update request is sent to the storage device 101 (ST1190), and the attribute of this memory area is updated with information indicating that the reading is in use. Further, as soon as a memory usage status update response is received from the storage device 101 (ST1200), the interrupt / memory management device 102 transmits a data reception request by interruption to the receiving CPU 121 (ST1210). This data reception request includes the start address and end address (or written data size) of the memory area of the dual port memory 103 into which the transmission side CPU 111 has written the transmission data. Receiving the data reception request in ST1210, the receiving CPU 121 starts data reception from the designated start address to the end address or the data size from the designated start address in the memory area in the dual port memory 103. Data reading is started (ST1220). Upon completion of data reading, the receiving CPU 121 transmits a data reception completion notification to the interrupt / memory management apparatus 102 (ST1230). This data reception completion notification includes the start address of the memory area in the dual port memory 103 where the data reading has been completed.

  The interrupt / memory management apparatus 102 notified of the completion of data reception in ST1230 makes a memory usage status update request to the storage apparatus 101 to indicate that no CPU is using the dual port memory 103 (ST1240). Then, the attribute of the memory area of the dual port memory 103 that has been read (the memory area in which the start address was included in the data reception completion notification in ST1230) is updated. By sending a memory usage status update response from the storage device 101 to the interrupt / memory management device 102, data transmission from the CPU 111 on the transmission side to the CPU 121 on the reception side is completed (ST1250).

  Note that data can be transmitted from the CPU 121 to the CPU 111 in the same sequence as described above.

  FIG. 3 is a diagram illustrating an example of the contents of the memory usage status holding table in the storage device 101. This data table holds the memory usage status of the dual port memory 103.

  This data table includes a start address A1, an end address A2, and a region attribute P1. The area attribute P1 is described as “CPU111W” when the CPU 111 is using writing, and “CPU121W” is described when the CPU 121 is using writing. The area attribute P1 is described as “CPU111R” when the CPU 111 is being read and used, and “CPU121R” is described when the CPU 121 is being read and used. On the other hand, when none of the CPUs use the dual port memory 103, a flag indicating that the CPU is not used is described in the area attribute P1. In this data table, the area size of data to be written (or written) can be used instead of the end address A2.

  Thus, according to the present embodiment, the storage device 101 and the interrupt / memory management device 102 are provided, and the storage device 101 holds the memory usage status of the dual port memory 103, while the interrupt / memory management device. 102 calculates a memory address of a memory area (a writable range and a readable range) that can be used in the dual port memory 103 based on the contents (write data size) held in the storage device 101, The CPU 111 and the CPU 121 are notified. Each CPU writes or reads data to or from the dual port memory 103 according to the memory address notified from the interrupt / memory management device 102.

  That is, the feature of this embodiment is that a management device that centrally manages the memory area of the dual port memory is provided separately from the CPU that transmits and receives data, and each CPU writes or receives data according to the notification from the management device. To read.

  By adopting this configuration, it is not necessary for each CPU to read a read pointer and a write pointer for writing to and reading from the dual port memory and calculate a writable range or a readable range at the time of data transmission / reception. Therefore, the processing load on the CPU can be reduced.

(Embodiment 2)
The data communication apparatus according to the second embodiment of the present invention has the same basic configuration as the data communication apparatus according to the first embodiment. Therefore, the description is omitted.

  FIG. 4 is a sequence diagram showing a series of operations of each part of the data communication apparatus according to the present embodiment. Here, a case where data is transmitted from the CPU 111 to the CPU 121 will be described as an example. Note that a series of operations according to the present embodiment has a part of the same steps as the series of operations shown in FIG. 2 of the first embodiment, and the same steps are denoted by the same reference numerals.

  The processing of ST1110 to ST1135 is the same as that of the first embodiment. A feature of the present embodiment is that a subsequent process is defined when it is determined in ST1135 that a memory area equivalent to the data size requested from the CPU 111 cannot be secured in the dual port memory 103.

  In such a case, the interrupt / memory management apparatus 102 suspends the response to the data transmission request in ST1110 and temporarily stores information such as the data size included in the data transmission request in the internal memory. Then, a wait process is performed until a data reception completion notification is received from the receiving CPU 121 (ST2010).

  Thereafter, when a data reception completion notification is received from the receiving CPU 121 (ST2020), the interrupt / memory management apparatus 102 updates the attribute of the corresponding memory area with information indicating that no CPU is in use. Then, by transmitting a memory usage status update request (ST2030) and receiving a memory usage status update response thereto (ST2040), it is recognized that the memory usage status update has been completed. After recognizing the update of the memory usage status, the interrupt / memory management device 102 again checks whether an available memory area equivalent to the data size included in the information temporarily stored in the internal memory can be secured in the dual port memory 103. Determine (ST2050).

  If it is determined in ST2050 that a memory area can be secured, as already described in the first embodiment, the interrupt / memory management apparatus 102 issues a memory usage status update request to the storage apparatus 101 (ST1140). The attribute of this memory area is updated during writing use. Further, as soon as a memory usage status update response is made (ST1150), the interrupt / memory management apparatus 102 transmits a data transmission response (ST1160). Receiving this data transmission response, the sending CPU 111 starts writing data (ST1170). Then, as soon as the data writing is completed, the transmission-side CPU 111 transmits a data transmission completion notification to the interrupt / memory management apparatus 102 (ST1180). The subsequent procedure is the same as that in the first embodiment.

  If the memory area cannot be secured again in ST2050, the processes of ST2010 to ST2050 are repeated.

  As described above, according to the present embodiment, in response to a data transmission request from the CPU, if a memory area of a size necessary for data writing cannot be immediately secured in the dual port memory, the CPU until the memory area can be secured. The CPU waits for data transmission, and when the memory area is secured, the CPU transmits (writes) transmission data.

(Embodiment 3)
FIG. 5 is a block diagram showing the main configuration of the data communication apparatus according to Embodiment 3 of the present invention. This data communication apparatus has the same basic configuration as that of the data communication apparatus shown in the first embodiment, and the same components are denoted by the same reference numerals and description thereof is omitted.

  A feature of the present embodiment is that it further includes a timer 301, and when a data write is requested by the CPU on the transmission side and a memory area equivalent to the requested write data size cannot be secured, a fixed time (timer expiration time) Is to notify the interrupt / memory management device 102 of the expiration of the timer.

  FIG. 6 is a sequence diagram showing a series of operations of each unit of the data communication apparatus according to the present embodiment. Here, a case where data is transmitted from the CPU 111 to the CPU 121 will be described as an example. Note that the processing of ST1110 to ST1135 is the same as the steps already shown in FIG. 2 of the first embodiment, and a description thereof will be omitted.

  If it is determined in ST1135 that the memory area cannot be secured in the dual port memory 103, the interrupt / memory management apparatus 102 suspends the response to the data transmission request in ST1110 and the data included in the data transmission request Information such as size is temporarily stored in the internal memory, and a timer start request is transmitted to the timer 301 (ST3010). The timer start request includes both a timing start instruction and timer expiration time information. The timer 301 counts the instructed timer expiration time, and notifies the interrupt / memory management device 102 of the timer expiration after this time has elapsed.

  If the timer 301 cannot secure a memory area equivalent to the data size requested from the CPU 111 before the timer expires, the timer 301 transmits a timer expiration notification to the interrupt / memory management apparatus 102 (ST3020). Receiving the timer expiration notification, interrupt / memory management apparatus 102 transmits a data transmission rejection response to CPU 111 on the transmission side (ST3030).

  FIG. 7 is a sequence showing a series of processes when the memory area can be secured before the timer expires, that is, when the interrupt / memory management apparatus 102 receives a data reception completion notification from the receiving CPU 121 before the timer expires. FIG. Note that the processing of ST1110 to ST3010 is as already described.

  When the data reception completion notification is received from the CPU 121 (ST3100), the interrupt / memory management apparatus 102 transmits a memory usage status update request (ST3110) and receives a memory usage status update response (ST3120). Recognizing that the update of the memory usage status has been completed, it is determined again whether or not a memory area can be secured (ST3130). If the memory area can be secured, interrupt / memory management apparatus 102 transmits a timer stop request to timer 301 (ST3140), and stops the timer.

  Thereafter, as already described in the first embodiment, the interrupt / memory management device 102 makes a memory usage status update request to the storage device 101 (ST1140), and updates the attribute of this memory area during writing use. Further, as soon as a memory usage status update response is made (ST1150), the interrupt / memory management apparatus 102 transmits a data transmission response (ST1160). Receiving this data transmission response, the sending CPU 111 starts writing data (ST1170). Then, as soon as the data writing is completed, the transmission-side CPU 111 transmits a data transmission completion notification to the interrupt / memory management apparatus 102 (ST1180). The subsequent procedure is the same as that in the first embodiment.

  In ST3130, if the memory area cannot be secured again, as in ST3100, a waiting process is performed until a data reception completion notification is received again from CPU 121, and then the processes of ST3110 to ST3130 are repeated.

  As described above, according to the present embodiment, when a memory area equivalent to the write data size requested by the transmission-side CPU cannot be secured, the transmission-side CPU waits for data transmission for a long time. Can be prevented.

  Note that the above-described timer expiration time may be set by the transmission-side CPU 111 according to the transmission data.

  Further, when transmitting the data transmission rejection response in ST3030, the interrupt / memory management apparatus 102 may notify the size of the usable memory area of the dual port memory 103 at that time.

  The data communication apparatus according to the present invention is not limited to the first to third embodiments, and can be implemented with various modifications.

  The data communication apparatus according to the present invention can be mounted on a communication terminal apparatus and a base station apparatus in a mobile communication system, thereby providing a communication terminal apparatus and a base station apparatus having the same effects as described above. be able to.

  Here, the case where data is transmitted and received between two CPUs has been described as an example. However, the number of CPUs is not limited to two, and the data communication apparatus according to the present invention transmits data between a plurality of CPUs. The present invention can also be applied to transmission / reception. Further, the partner of data transmission / reception is not limited to the CPU, but may be another circuit.

  Further, here, a case has been described as an example where the present invention is configured with hardware, but the present invention can also be implemented with software.

  The data communication apparatus and the data communication method according to the present invention can be applied to uses such as a system for transmitting and receiving data between a plurality of CPUs using a dual port memory.

1 is a block diagram showing a main configuration of a data communication apparatus according to a first embodiment. FIG. 3 is a sequence diagram showing a series of operations of each unit of the data communication apparatus according to the first embodiment. The figure which shows an example of the content of the memory usage condition holding table which concerns on Embodiment 1 FIG. 9 is a sequence diagram showing a series of operations of each unit of the data communication apparatus according to the second embodiment. FIG. 9 is a block diagram showing the main configuration of a data communication apparatus according to Embodiment 3. Sequence diagram showing a series of operations of each part of the data communication apparatus according to the third embodiment (when a memory area cannot be secured before the timer expires) Sequence diagram showing a series of operations of each part of the data communication apparatus according to the third embodiment (when a memory area can be secured before the timer expires) The block diagram which shows the structure of the conventional data communication apparatus between CPUs

Explanation of symbols

101 Storage Device 102 Interrupt / Memory Management Device 103 Dual Port Memory 111, 121 CPU
301 timer

Claims (7)

Multiple CPUs;
A dual port memory that temporarily stores and relays data when data is transmitted and received between the plurality of CPUs;
Based on the size of the data to be transmitted / received and the usage status of the dual port memory installed outside the plurality of CPUs, the memory address of the area where data is stored in the dual port memory, and the area Management means for managing the timing at which each CPU writes or reads data;
A data communication apparatus comprising: A plurality of CPUs that transmit and receive data to and from each other;
A dual port memory used for data transmission / reception between the plurality of CPUs;
A storage device for holding the usage status of the dual port memory;
The usage status of the dual port memory is read from the storage device, and based on the size of data transmitted / received between the plurality of CPUs and the usage status of the dual port memory, the CPU in the dual port memory A management device for generating a memory address of a writable memory area and an interrupt signal for starting transmission and reception of the data;
A data communication apparatus comprising: The management device
At the time of data transmission, the usage status of the dual port memory is read from the storage device, and based on the size of the data and the usage status of the dual port memory, a usable memory area in the dual port memory is calculated, While generating a memory address corresponding to the calculated memory area, and notifying this memory address to the CPU on the transmission side by an interrupt and updating the attribute of the calculated memory area while writing,
During data reception, the memory address of the memory area that has been written by the sending CPU is notified to the receiving CPU by an interrupt, and the attribute of the memory area that has been written is updated during reading.
The data communication apparatus according to claim 2. The management device
If the memory area where the data can be written cannot be secured, the data write request from the sending CPU is suspended, and after the receiving CPU completes the data reception, it is determined again whether the memory area can be secured. ,
If it can be secured, the memory address of the secured memory area is notified to the CPU on the transmission side by an interrupt,
If it cannot be secured, the data write request from the CPU on the transmitting side is again suspended.
4. The data communication apparatus according to claim 2, wherein the data communication apparatus is a data communication apparatus. The management device
A timer that starts counting a predetermined time when it is determined that a memory area in which the data can be written cannot be secured;
If a memory area where the data can be written cannot be secured before the predetermined time elapses, this fact is notified to the CPU on the transmission side.
3. The data communication apparatus according to claim 1, wherein the data communication apparatus is a data communication apparatus.   A communication terminal apparatus comprising the data communication apparatus according to claim 1. A data communication method used in a data communication device comprising a plurality of CPUs and a dual port memory that temporarily stores and relays data when data is transmitted and received between the plurality of CPUs,
The transmission / reception of a memory address of an area where data is stored in the dual-port memory and a timing at which each CPU writes or reads data in this area is performed by the management device installed outside the plurality of CPUs. Managing based on the size of the data to be processed and the usage status of the dual port memory,
A data communication method characterized by the above.

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