JP2005284174A - Display device and its driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which provides diversified images while suppressing increase of power consumption. <P>SOLUTION: After displaying images by sequentially selecting scanning electrodes (for example, COM<SB>1</SB>to COM<SB>m</SB>), a plurality of scanning electrodes (for example, COM<SB>m+1</SB>to COM<SB>n</SB>) are selected in block and desired background colors and patterns are displayed. The display device provided with a color filter is constituted so that an optional background color is displayed by adding desired voltage to each of signal electrodes when the scanning electrodes are selected in block. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device, and more particularly to a display device operable with low power consumption.

  As display devices for portable information devices such as mobile phones, liquid crystal display devices, EL display devices, and the like that have the advantages of being light and thin and having low power consumption have been actively developed. Cellular phones and the like are required to have high definition in order to display with high visibility, and further to reduce power consumption in order to use them for a long time.

  Display devices are classified into a passive matrix type and an active matrix type, but it is a common requirement to simultaneously realize high definition and low power consumption of the display device. However, for example, in a passive matrix liquid crystal display device, when the number of scan electrodes is increased for higher definition, the duty ratio becomes higher, the drive voltage needs to be increased, and power consumption increases.

Therefore, in a passive matrix type liquid crystal display device, when displaying information on only a part of the screen such as a standby screen of a mobile phone, it is driven without selecting a scanning electrode of a non-display part where no information is displayed. A method for reducing the duty ratio has been proposed. This driving method is called partial display because it performs display by partially driving only a part of the screen (for example, Patent Document 1).
Japanese Patent Application Laid-Open No. 07-281632

  In partial display, for example, a liquid crystal display device is provided with n scanning electrodes, and when displaying an image, m scanning electrodes are used for displaying data such as information, and the remaining scanning electrodes are used for displaying data. In this case, a selection voltage is sequentially applied only to m scanning electrodes used for data display in one frame period, and driving is performed with a 1 / m duty.

  In this way, partial display sequentially applies a selection voltage only to the scan electrodes used for displaying information, so the duty ratio is lowered compared to the normal display method in which the selection voltage is sequentially applied to all the scan electrodes. Thus, the drive voltage can be kept low, and the power consumption can be reduced.

  In partial display, a non-selection voltage is applied to the scan electrodes in the non-display portion. For this reason, in a normally white display device, a non-display portion can be displayed in white, and in a normally black display device, a non-display portion can only be displayed in black. That is, in the conventional partial display, the image of the non-display portion is the same as the image displayed in a state where the power is turned off, and the display is monotonous.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a display device that enables various displays while suppressing power consumption.

  In order to achieve the above object, a display device according to a first aspect of the present invention includes n scan electrodes (n is a natural number of 3 or more) and a plurality of signal electrodes intersecting with the scan electrodes. A display panel, a first operation mode in which a selection voltage is sequentially applied to the n scan electrodes of the display panel, and m scan electrodes among the n scan electrodes (m is a natural number of 2 or more, Select a second operation mode in which a selection voltage is sequentially applied to each of m <n) and a selection voltage is applied to all (n−m) scan electrodes excluding the m scan electrodes. A scanning electrode drive circuit that operates by switching, and in the first operation mode, a gradation designation corresponding to an image to be displayed by a pixel formed by intersecting the n scanning electrodes and the signal electrode The signal voltage corresponding to the data is sequentially output to the signal electrode. In the second operation mode, a partial display signal voltage corresponding to gradation designation data corresponding to an image to be displayed on a pixel formed by crossing the m scanning electrodes and the signal electrodes, nm) The background display signal voltage corresponding to the gradation designation data corresponding to the background color to be displayed on the pixel formed by intersecting the scan electrodes and the signal electrodes is set to the plurality of signal electrodes. And a signal electrode driving circuit for applying a signal voltage to each.

  The scan electrode driving circuit includes a designation unit that designates m consecutive scan electrodes among n scan electrodes, and in the second operation mode, the consecutive m scan electrodes designated by the designation unit. Alternatively, the selection voltage may be sequentially applied to each of the scan electrodes, and the selection voltage may be applied collectively to (n−m) scan electrodes excluding the m scan electrodes.

  In the above configuration, since the display is performed by applying the selection voltage to the m scanning electrodes at once, the increase in the number of divisions can be suppressed to only one compared with the conventional partial display method.

  In each of the above configurations, a color filter including three colored layers may be further provided, and the color filter may be arranged so that a colored layer colored in the same color overlaps with one signal electrode. .

  According to the above configuration, since the signal electrode and the colored layer of any one color overlap, if a desired voltage is applied to the signal electrode, each of the m scanning electrodes and the signal electrode selected at once It is possible to perform color display by combining pixels formed by crossing. That is, it is possible to perform color display by applying a selection voltage to m scanning electrodes at once.

  A drive circuit for a display device according to a second aspect of the present invention drives a display device having n scan electrodes (n is a natural number of 3 or more) and a plurality of signal electrodes intersecting with the scan electrodes. A first operation mode in which a selection voltage is sequentially applied to the n scan electrodes of the display panel, and m scan electrodes (m of the n scan electrodes) Applies a selection voltage sequentially to each of a natural number of 2 or more, m <n), and further applies a selection voltage to all (n−m) scan electrodes excluding the m scan electrodes. A scan electrode drive circuit that operates by selectively switching between the n scan electrodes and the signal electrode in the first operation mode, and an image to be displayed in the first operation mode. The signal voltage corresponding to the gradation designation data corresponding to A portion corresponding to gradation designation data corresponding to an image to be displayed on a pixel which is sequentially output to the signal electrode and is displayed in a pixel formed by intersecting the m scanning electrodes and the signal electrode in the second operation mode. A display signal voltage, and a background display signal voltage according to gradation designation data corresponding to a background color to be displayed on a pixel formed by intersecting the (nm) scan electrodes and the signal electrodes, A signal electrode driving circuit that applies a signal voltage to each of the plurality of signal electrodes.

  In each of the above configurations, in the first operation mode, the means for determining the operation mode of the scan electrode drive circuit is repeatedly counted from zero to (n−1), and the count value is output. In the operation mode, the counter further includes a counter that repeatedly counts a value from zero to m and outputs a count value, and the scan electrode driving circuit indicates the count value supplied from the counter in the first operation mode. A selection voltage is sequentially applied to the scan electrodes, and in the second operation mode, when the count value is a value from zero to (m−1), the selection voltage is sequentially applied to the scan electrodes indicated by the count value. When the count value is m, it is possible to apply a selection voltage to the (n−m) scan electrodes.

  As described above, according to the present invention, it is possible to provide a display device that can be driven while suppressing an increase in power consumption and can perform various displays.

(Embodiment 1)
Hereinafter, a passive matrix liquid crystal display device according to a first embodiment of the present invention will be described with reference to the drawings.

  1A is a configuration diagram of the liquid crystal display device according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line A-A ′ of the liquid crystal display panel shown in FIG.

  As shown in FIG. 1A, the liquid crystal display device according to the first embodiment includes a display panel 1, a scan electrode drive circuit 2, a signal electrode drive circuit 3, and a display controller 4.

  As shown in FIG. 1, the display panel 1 includes substrates 5 and 6, a color filter 7, a planarizing film 8, a signal electrode 9, a scanning electrode 10, an alignment film 11, a liquid crystal 12, and a sealing agent. 13.

  The substrate 5 and the substrate 6 face each other with the liquid crystal 12 interposed therebetween, and are bonded together using a sealant 13.

  A color filter 7 is formed on the surface of one substrate 5 facing the substrate 6. The color filter 7 includes a red colored layer 7a, a blue colored layer 7b, and a green colored layer 7c. The colored layers 7 a to 7 c are arranged so that one of the colored layers 7 a, 7 b, or 7 c overlaps with one signal electrode 9. A planarizing film 8 is formed on the color filter 9.

  On the planarizing film 8, k (plural) signal electrodes 9 having a rectangular shape whose longitudinal direction is the column direction are provided. As described above, each of the signal electrodes 9 overlaps one of the red colored layer 7a, the blue colored layer 7b, and the green colored layer 7c with the planarizing film 8 interposed therebetween.

  On the other hand, on the surface of the substrate 6 facing the substrate 5, n (plural) scanning electrodes 10 having a rectangular shape whose longitudinal direction is the row direction are provided.

An alignment film 11 is provided on each of the signal electrode 9 and the scanning electrode 10. The surface of the alignment film 11 is rubbed, and the substrate 5 and the substrate 6 are bonded to each other with the rubbing direction of each alignment film 11 intersecting at an angle corresponding to the liquid crystal alignment method.
The liquid crystal 12 is filled in a gap formed by the alignment film 11 and the sealing agent 13, and maintains a predetermined alignment state by the alignment regulating force by the alignment film 11. The liquid crystal 12 is composed of a nematic liquid crystal or a chiral smectic ( ^* Sm) liquid crystal, for example, a ferroelectric liquid crystal (FLC) or an antiferroelectric liquid crystal (AFLC). As an alignment method of the nematic liquid crystal, for example, an STN (Super Twisted Nematic) method, a TN (Twisted Nematic) method, or a vertical alignment (Vertical Aligned Nematic: VAN) method can be used.

The scan electrode drive circuit 2 shown in FIG. 1A applies a selection voltage or a non-selection voltage to each scan electrode 10 and scans it.
When the number of scan electrodes 10 is n and COM ₁ to COM _n are described in order from the upper side of FIG. 1A, the scan electrode driving circuit 2 normally applies a selection voltage to the n scan electrodes 10 in sequence. After the selection voltage is sequentially applied to the upper m scan electrodes 10 (COM _{1 to} COM _m ), the remaining (n−m) scan electrodes 10 (COM _{m + 1 to} COM _n ) are applied. Two operation modes of a standby operation mode in which selection voltages are applied in a batch are provided, and the operation is performed in one operation mode in accordance with a signal input from the display controller 4.
The signal electrode drive circuit 3 applies a signal voltage corresponding to the gradation designation data input from the display controller 4 to each signal electrode 11 during a period in which the selection voltage is applied to the scan electrode 10.

The display controller 4 is connected to the scanning electrode driving circuit 2 and the signal electrode driving circuit 3, and in accordance with an instruction from an external control circuit, a normal operation mode for displaying information on the entire display panel 1, and the display panel 1. A standby operation mode in which information is displayed only on the top of the display is determined, and signals for controlling the respective circuit operations are output to the scan electrode driving circuit 2 and the signal electrode driving circuit 3 in accordance with the determined operation mode.
Specifically, in the normal operation mode, the display controller 4 causes the scan electrode drive circuit 2 to sequentially apply a selection voltage to the _n scan electrodes 10 (COM _{1 to} COM _n ), and causes the signal electrode drive circuit 3 to A signal voltage corresponding to a gradation to be displayed is applied to each signal electrode 9, and the scanning electrode 10 to which the selection voltage is applied and each signal electrode 9 (S _{1 to} S _k ) intersect to form a pixel Display a desired luminance on one line of pixels.
Further, in the standby operation mode, the display controller 4 causes the scan electrode drive circuit 2 to sequentially apply the selection voltage to the upper m scan electrodes 10 (COM _{1 to} COM _m ) and display the signal electrode drive circuit 3 on the floor. After the signal voltage corresponding to the tone is applied, the selection voltage is applied to the remaining (n−m) scan electrodes 10 (COM _{m + 1 to} COM _n ) in a lump, and the signal electrode drive circuit 3 A voltage for displaying a predetermined background color is applied to the signal electrode 9 (S _{1 to} S _k ).

  As illustrated in FIG. 2, the scan electrode driving circuit 2 includes an address decoder 21, an OR circuit 22, and a drive circuit 23. The display controller 4 includes a control unit 41, a counter 42, and a logic circuit block 43.

The control unit 41 outputs the clock CK, the upper limit value m or n−1 of the count value of the counter 42, the mode signal S _mode, and the gradation designation data D _glayscale . As shown in FIGS. 3A and 4A, the cycle of the clock CK is equal to one horizontal scanning period (selection period of one scanning electrode 10), and the clock CK is used in the normal operation mode and the standby operation mode. The cycle changes. As shown in FIGS. 3C and 4C, the signal level of the mode signal S _mode changes between the normal operation mode and the standby operation mode.

The counter 42 operates in accordance with the clock CK supplied from the control unit 41 and outputs address data D _ad .

Specifically, the clock CK is supplied from the control unit 41 to the counter 42, and the counter 42 counts up in response to the rising edge of the clock CK, and the count value is shown in FIG. 3 (b) and FIG. 4 (b). as shown in, and outputs it as the address data D _ad. The address data D _ad is a signal that indicates the address of the scan electrode 10 to which the selection voltage is applied.

In the counter 42, the control unit 41 sets n-1 as the count upper limit value in the normal operation mode, m in the standby operation mode, and is reset when the count value exceeds the upper limit value. Thus, the counter 42 is in the normal operation mode counts repeatedly from 0 to (n-1), outputs one way a count value of 0 in one frame period _{T i} (n-1). On the other hand, in the standby operation mode, the counter 42 repeatedly counts ₀ to m, and outputs a count value of ₀ to m in one frame period Ti.

The logic circuit block 43 operates according to the mode signal S _mode input from the control unit 41 and the address data D _ad input from the counter 42, and outputs the scan control signal S _scan .

Specifically, when the mode signal S _mode designating the normal operation _mode is input from the control unit 41, the logic circuit block 43 scans the inactive level (L level) as shown in FIG. A control signal S _scan is output.

On the other hand, when the mode signal S _mode for designating the standby operation _mode is input from the control unit 41, the logic circuit block 43, as shown in FIG. 4D, is one horizontal line in which the address data D _ad becomes “m”. A scan control signal S _scan that is active level (H level) only during the scanning period and inactive level (L level) during the remaining period is output.

The address decoder 21 constituting the scan electrode driving circuit 2 decodes the address data D _ad input from the display controller 4 and outputs an output terminal corresponding to the address data D _ad among the _n output terminals O ₁ to On. Outputs an active level signal, and outputs an inactive level signal from the remaining output terminals.

Output terminal O ₁ of the first to m address decoder 21 ~ O _m is directly connected to the input terminal _I 1 ~I _m of the first to m drive circuit 23. Further, (m + 1) -th address decoder 21 output O _m + 1 ~ O _n th to n are connected to the input terminal I _m + 1 ~I _n one of the corresponding OR circuit 22 to _m + 1 through 22 _n ing.

A scan control signal S _scan (FIG. _3D , FIG. 4E) is supplied from the logic circuit block 43 to the other input terminal of the OR circuit. The output terminal of the OR circuit 22 are connected to the input terminal I _{m + 1} ~I _n of the (m + 1) ~ n-th drive circuit 23.

Drive circuit 23 has an input end and I ₁ ~I _n of the n, and an output terminal O ₁ ~ O _n of the n corresponding to the input end. The input terminal I ₁ ~I _m of the first to m drive circuit 23 is supplied a signal from the address decoder 21, an OR circuit 22 corresponding to the input terminal I _m + 1 ~I _n of the m + 1 to the n Output signal is supplied.

The drive circuit 23 applies a scanning voltage to each of the scanning electrodes 10 (COM _{1 to} COM _n ) provided corresponding to the _n output terminals O ₁ to On.

  Specifically, as shown in FIGS. 3E and 4E, the drive circuit 23 sequentially applies to the scan electrodes 10 whose corresponding inputs are at the active level in synchronization with the falling edge of the clock CK. A selection voltage is applied, and a non-selection voltage is applied to the other scan electrodes 10.

The drive circuit 23 in order to AC drive the liquid crystal, in response to a frame inversion signal (not shown), the selection voltage and the non-selected applied to scan electrodes 10 in each frame period T _i (COM ₁ ~COM _n) The voltage potential is inverted with respect to the reference.

On the other hand, the signal electrode drive circuit 3 has gradation designation data for designating display of pixels on the scanning electrode in a selected state in synchronization with the falling edge of the clock CK shown in FIGS. 3 (a) and 4 (a). D _glayscale is converted into a signal voltage and applied to the signal electrode 9.

The signal electrode driving circuit 3, in response to a frame inversion signal (not shown) to invert the signal voltage with respect to the reference for each frame period T _i.

Next, a series of operations of the liquid crystal display device will be described separately for a normal operation mode and a standby operation mode. FIG. 3 is a timing chart for explaining the driving in the normal operation mode, and FIG. 4 is a timing chart for explaining the driving in the standby operation mode.
In the following description of the operation, the display panel 1 displays information at the top of the screen in the standby operation mode, the background color in the remaining portion, and displays a desired image on the entire screen in the normal operation mode. And

(Normal operation mode)
The control unit 41 of the display controller 4 sets the cycle of the clock CK to T _i / n (T _i : frame period, n: total number of scan electrodes), and sets the mode signal S _mode to the inactive level.

The control unit 41 of the display controller 4 sets the upper limit of the count value of the counter 42 to n-1. The counter 42 counts up in response to the rising edge of the clock CK (FIG. 3 (a)), repeatedly counts 0 to (n-1), and the count value as shown in FIG. 3 (b). _Is supplied to the logic circuit block 43 as address data _Dad .

As shown in FIG. _3D , the logic circuit block 43 outputs a scan control signal S _scan that is always in an inactive level in accordance with the mode signal S _mode (FIG. 3C) supplied from the control unit 41. .

Address decoder 21 decodes the address data D _ad supplied from the counter 42, and sequentially outputs one horizontal scanning period (one clock cycle) a selection signal which becomes active level from the output terminal O ₁ ~ O _n of the n .

Since the inactive level scan control signal S _scan is input to the other input terminal, the OR circuit 22 outputs the active level signal input from the address decoder 21 as it is. Therefore, the signal output from the output terminal O ₁ ~ O _n of the address decoder 21 is supplied directly to the input terminal I ₁ ~I _n drive circuit 23.

As shown in FIG. 3E, the drive circuit 23 applies a selection voltage to the scanning electrode 10 (COM _p ) corresponding to the input terminal I _p to which an active level signal is input for only one horizontal scanning period, A non-selection voltage is applied to the remaining scan electrodes to which no selection voltage is applied.

On the other hand, the control unit 41 _supplies gradation designation data _Dglayscale corresponding to a desired image to the signal electrode drive circuit 3 for each scanning line. The signal electrode drive circuit 3 converts the grayscale designation data _Dglayscale corresponding to the display of the pixels on each line into a signal voltage in synchronization with the falling edge of the clock CK (FIG. 3A), _thereby converting the signal electrode 9 Apply to. With the above operation, a desired image is formed on the entire surface of the display panel.

(Standby operation mode)
The control circuit 41 sets m to the counter 42 as the count upper limit value. The counter 42 counts up in synchronization with the rising edge of the clock CK, repeatedly counts 0 to m, and outputs the count value as address data D _ad as shown in FIG. 4B.

The logic circuit block 43 receives the address control data D _ad from the counter 42 and, as shown in FIG. 4D, outputs a scan control signal S _scan that is active only during the period when the address data D _ad is “m”. Output to the OR circuit 22.

The address decoder 21 included in the scan electrode driving circuit 2 decodes the address data D _ad input from the counter 42, and the first to m- _th output terminals O ₁ among the _n output terminals O _{1 to On.} sequentially outputs a signal which becomes an active level by one horizontal scanning period from ~ O _m (1 clock period).

Signals output from the _first to m-th output terminals O _{1 to} O _m of the address decoder 21 are supplied to the _first to m-th input terminals I _{1 to} I _m of the drive circuit 23 as they are. Therefore, during a period in which the address data D _ad is 0 to (m−1), the output of the address decoder 21 is supplied to the drive circuit 23 as it is, and the drive circuit 23 synchronizes with the falling edge of the clock CK. As shown in FIG. 4E, the selection voltage is applied to each of the scanning electrodes 10 (COM _{1 to} COM _m ) for one horizontal scanning period, and the remaining (n−1) scans to which no selection voltage is applied. A non-selection voltage is applied to the electrode 10.

When the address data D _ad reaches “m”, as shown in FIG. 4D, the scan control signal S _scan becomes an active level, and all OR circuits 22 output an active level signal. Thus, the active level signal is supplied to an input terminal I _{m + 1} ~I _n of the first m +. 1 to the n-th drive circuit 23. Since the OR circuit 22 is not provided at the first to m-th input terminals I _{1 to} I _m of the drive circuit 23, an inactive level signal is directly output from the output terminals O _{1 to} O _{m of} the address decoder 21. Supplied. For this reason, as shown in FIG. 4E, the drive circuit 23 applies a non-selection voltage to COM _{1 to} COM _m among n scan electrodes 10, and selects it to COM _{m + 1} to COM _n. Apply voltage. That is, in the standby operation mode, the selection voltage is applied collectively to the scan electrodes 10 (COM _{m + 1 to} COM _n ) in the region for displaying the background color.

On the other hand, when the standby operation mode is designated, the control unit 41 specifies gradation designation data _Dglayscale (corresponding to the pixels on the first line to the m-th line) that designates an image to be displayed in the data display area. Gradation designation data D _glayscale ) and gradation designation data D _glayscale (m + 1 line pixel to n line pixel) for designating a color / pattern to be displayed in the background color display area _glayscale ) to the signal electrode drive circuit 3.

The signal electrode drive circuit 3 converts the gradation designation data _Dglayscale corresponding to the display of the pixels of each line into a signal voltage, and applies it to each signal electrode 9 in synchronization with the falling edge of the clock CK. Thus, the pixels from the first line to the (m + 1) th line are sequentially displayed, and the data area is displayed. Next, the gradation designation data _Dglayscale constituting the color / pattern to be displayed in the background color display area is converted into a signal voltage and applied to each signal electrode 9 in synchronization with the falling edge of the clock CK. Displays the background color display area. As a result, an arbitrary image is displayed in the data display area, and a background color or pattern is displayed in the background display area.

  Thus, in the standby operation mode, the upper m scan electrodes are sequentially selected, and the remaining (nm) scan electrodes are selected at a time, and are driven with a duty of 1 / (m + 1).

  As described above, in the driving method according to the first embodiment, in the standby operation mode, the duty ratio is less increased than in the normal partial display, so that it is possible to display a color background color while suppressing an increase in power consumption. . For this reason, various expressions can be made, and images with improved display quality can be provided.

  In the display panel 1, only one of the colored layers 7 a to 7 c constituting the color filter 7 overlaps with one signal electrode 9. For this reason, by changing the magnitude of the signal voltage applied to the signal electrode 9, the intensity of the transmitted light of the colored layers 7a to 7c can be changed to display a free color. In addition, an arbitrary color pattern (vertical stripe) can be displayed.

(Embodiment 2)
In the first embodiment, the positions and sizes of the data display area and the background color display area are fixed on the display panel 1, but the positions and sizes may be changed. Hereinafter, a passive matrix liquid crystal display device according to a second embodiment in which the positions and sizes of the data display area and the background color display area can be appropriately changed will be described with reference to the drawings.

  The basic configuration of the liquid crystal display device of the second embodiment is the same as that of the liquid crystal display device of the first embodiment shown in FIG. However, as illustrated in FIG. 5, the internal configurations of the display controller 4 and the scan electrode drive circuit 2 are different from the configuration of the first embodiment shown in FIG. 2. Hereinafter, this difference will be mainly described.

  The scan electrode driving circuit 2 includes an address decoder 21, an OR circuit 22 and an AND circuit 24, and a drive circuit 23. The display controller 4 includes a control unit 41, a counter 42, an adder 44, and a logic circuit block 43.

The controller 41 includes a value m indicating the number of scanning electrodes in the data display area, a value j indicating the head position of the data display area, a mode signal S _mode indicating whether the normal mode and the standby mode are different, and scanning of the data display area. A clock CK whose cycle changes according to the number of electrodes m, and gradation designation data _Dglayscale are output.

The counter 42 counts up in response to the rising edge of the clock CK, repeatedly counts 0 to n-1 in the normal display mode, and repeatedly counts values from 0 to m in the standby display mode. .
The adder 44 adds the offset value j to the count value of the counter 42 and outputs it as the address data D _ad shown in FIGS. 3B and 6C.

The logic circuit block 43 is supplied with the address data D _ad from the adder 44, and is supplied with the clock CK, the value m, n, the offset value j, and the mode signal S _mode (FIG. 3 (c), FIG. 6 (d)). ) And are supplied respectively.

The logic circuit block 43 maintains an inactive level when the mode signal S _mode designates the normal operation mode, and adds an adder when the mode signal S _mode designates the standby operation mode. A scan control signal S _scan that is active only during a period in which the sum of the address data D _ad input from 44 and the sum of the value m supplied from the control unit 41 and the offset value j coincides is output.
Specifically, the logic circuit block 43, as shown in FIG. 3 (e), when the mode signal S _mode designates the normal operation mode, the scan to maintain the inactive level during one frame period T _i Control signals S _{scan1 to} S _scann are output. Further, as shown in FIG. 6C, when the mode signal S _mode designates the standby operation mode, the scan control signals S _{scan1 to} S _scanj that maintain the inactive level for one frame period T _{i. -1} and S _{scanm + j to} S _scann, and scan control signals S _{scanj to} S _{scanj + m-1} which become active levels only during the period when the address data D _ad is (j + m).

The address decoder 21 of the scan electrode driving circuit 2 has _n output terminals O _{1 to} O _n , decodes the address data D _ad input from the adder 44, and activates the active level from the output terminal corresponding to the address value. Inactive level signals are output from the remaining output terminals.

A pair of an OR circuit 22 and an AND circuit 24 is arranged at each of the _n output terminals O _{1 to On of the} address decoder 21.
A mode signal S _mode from the control unit 41 is commonly supplied to one input terminal of the AND circuit 24, and scan control signals S _{scan1 to} S _scann are individually _supplied from the logic circuit block 43 to the other input terminal. Supplied. The output terminal of each AND circuit 24 is connected to one input terminal of the corresponding OR circuit 22. The other input terminal of the AND circuit 24 is connected to the output terminal O ₁ ~ O _n the corresponding address decoder 21.
The output end of each OR circuit 22 is connected to the input terminal I ₁ ~I _n corresponding drive circuit 23.

Drive circuit 23 includes n input terminals I ₁ ~I _n connected to the output terminal of the OR circuit 22, the scan electrode 10 (COM ₁ ~COM _n) connected to the n output terminals O ₁ ~ O comprising a _n, non-selective voltage to the output terminal O _i of the active level of the signal corresponds to the input terminal I _i supplied to the output terminal O _i of the signal inactive level corresponds to the input terminal I _i supplied Outputs a selection signal. Further, the drive circuit 10 inverts the voltage applied to the scan electrode 10 every frame period T _i .

  Next, the operation of the liquid crystal display device of Embodiment 2 will be described separately for the normal operation mode and the standby operation mode. The normal operation mode will be described with reference to FIG. 3, and the standby operation mode will be described with reference to FIG.

(Normal operation mode)
The control unit 41 of the display controller 4 sets the offset value to 0, the cycle of the clock CK to T _i / n (T _i : 1 frame period, n: total number of scan electrodes), and the mode signal S _mode to the inactive level. Set each.

Thus counter 42, in accordance with the clock CK shown in FIG. 3 (a), counts repeatedly from 0 to (n-1) in one frame period T _i, and outputs the count value. Since the offset value of the adder 45 is 0, the count value output from the counter 42 is output as is to the logic circuit block 43 and the address decoder 21 as address data D _ad as shown in FIG. .

The logic circuit block 43 always outputs the scan control signals S _{scan1 to} S _scann at the inactive level as shown in FIG. _3D in accordance with the mode signal S _mode at the inactive level (FIG. 3C).

The output of the address decoder 21 of the scan electrode driving circuit 2 is supplied to one input terminal of the OR circuit 22. The AND circuit 24 connected to the other input terminal of the OR circuit 22 has an inactive level mode signal S _mode (FIG. 3A) and inactive level scan control signals S _{scan1 to} S _scann (FIG. 3 ( Since d)) continues to be output, an inactive level signal is output from the output terminal of the AND circuit 24 to the other input terminal of the OR circuit 22. As a result, the output of the address decoder 21 is supplied as it is to the drive circuit 23 via the OR circuit 22. Thus, as shown in FIG. 3E, the selection voltage is sequentially applied to the scan electrodes 10 (COM _{1 to} COM _n ). Thus, the liquid crystal display panel 1 is driven as in the normal mode of the second embodiment.

(Standby operation mode)
On the other hand, in the standby operation mode, the control unit 41 sets the number m (natural number, usually 2 or more) of scan electrodes used for displaying a desired image among the n scan electrodes, and the head position j ( j designates a natural number, j ≦ n−m). Subsequently, the control unit 41 sets the offset value of the adder 44 to j, the period of the clock CK to T _i / (m + 1) (T _i : one frame period, m: the number of scanning electrodes in the data display area), The mode signal S _mode is set to the active level.

The counter 42 repeatedly counts 0 to m in accordance with the clock CK (FIG. 6B), and as shown in FIG. 6C, the added value of the count value and the offset value j is used as the address data D _ad. Is output. Therefore, the address data D _ad repeats j to j + m.

According to the address data D _ad , the address decoder 21 outputs the j-th output terminal O _j , the j + 1-th output terminal O _{j + 1} , the j + 2-th output terminal O _{j + 2} ,. _An active level signal is sequentially output from _{j + m−1,} and an inactive level signal is output from another output terminal from which the active level signal is not output.

At this stage, all of the scan control signals S _{scan1 to} S _scann (FIG. _6E ) output from the logic circuit block 43 to the AND circuits 24 are at the inactive level. Therefore, all the AND circuits 24 output inactive level signals, and each OR circuit 22 outputs the output of the address decoder 21 supplied to the other input terminal to the output terminal of the drive circuit 23 as it is. Accordingly, the selection voltage is sequentially applied to the jth to j + m−1 scan electrodes 10.

Subsequently, when the address specified by the address data D _ad reaches j + m, the scan control signals S _{scanj to} S _{scanj + m-1} (FIG. 6 (e)) become the active level only for one horizontal scanning period. The generated signal is supplied to one input terminal of the j-th to (j + m−1) AND circuits 24. Since the active level mode signal S _mode is supplied to the other input terminal of each AND circuit 24, the j-th to (j + m-1) -th AND circuits 24 output active level signals. Is supplied to the input terminal of the drive circuit 23 via the OR circuit 22.

On the other hand, as shown in FIG. _6E , since the scan control signals S _{scan1 to} S _scanj-1 and S _{scanj + m-1 to} S _scann remain at the inactive level, the jth to (j + m−1) th The output of the AND circuit 24 in () remains at an inactive level. For this reason, the outputs of the _first to _j−1 and _{j + m−1} to _nth OR circuits 22 are inactive levels.

As a result, as shown in FIG. 6B, when the address specified by the address data D _ad reaches j + m, the drive circuit 23 performs the first to (j−1) th to (j + m) to A selection voltage is applied collectively to the n scan electrodes, and a non-selection voltage is applied to the other scan electrodes.

On the other hand, the control unit 41 includes gradation designation data _Dglayscale of an image to be displayed in the data display area in which the jth to (j + m−1) th scanning electrodes 8 are disposed, and other scanning electrodes 8 are disposed. Gradation designation data D _glayscale for designating a color / pattern or the like to be displayed in a display area (referred to as a background color display area) is supplied to the signal electrode drive circuit 3.

The signal electrode driving circuit 3 applies the gradation designation data _Dglayscale to each of the signal electrodes 9 in synchronization with the clock CK during a period in which the address data D _ad is jth to (j + m−1), and addresses In the period when the data D _ad is the (j + m) th, a signal designating a color / pattern to be displayed in the background color display area is applied to the signal electrode 9. As a result, an arbitrary image is displayed in a display area of an arbitrary size (m scan electrodes) set at an arbitrary position (position starting from the j-th scanning line), and an arbitrary background color or pattern is displayed in the background display area. Is displayed.

  As described above, according to the second embodiment, any position of the display panel can be used for data display.

  If the present invention is applied not only to a display device that performs color display but also to a display device that performs monochrome display, not only white or black display but also halftone display may be employed as the background color in the standby operation mode. Is possible.

  Further, although the present invention has been described by taking a passive matrix display device as an example, the present invention is not based on this. The present invention is applied to an active matrix display device in which a switching element such as a transistor is provided in a display portion, and in a standby operation mode, the operating frequency of a drive circuit is reduced to reduce power consumption and It is also possible to display. In this case, pixels in a plurality of rows are selected at the same time (the pixel active elements are turned on), and gradation designation data is supplied to each pixel capacitor (liquid crystal, a capacitor having an alignment film as a dielectric, or in parallel with this capacitor. To the storage capacity connected to).

  Note that the application of the present invention is not limited to a liquid crystal display device. For example, an EL element that includes a cathode, an anode, and a light emitting layer between the anode and the cathode, and has an EL element that displays light and dark using electroluminescence (EL) is provided in the display unit. The present invention can also be applied to a display device.

It is a figure which shows an example of a structure of the liquid crystal display device of this invention. 4 is a diagram illustrating an example of a configuration of a drive circuit according to Embodiment 1. FIG. 6 is a timing chart for explaining the operation timing of each part in the normal operation mode of the first and second embodiments. 3 is a timing chart for explaining the operation timing of each unit in the standby operation mode of the first embodiment. FIG. 6 is a diagram illustrating an example of a configuration of a drive circuit according to a second embodiment. 10 is a timing chart for explaining the operation timing of each unit in the standby operation mode of the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display panel, 2 ... Scan electrode drive circuit, 3 ... Signal electrode drive circuit, 4 ... Display controller, 5 ... Substrate, 6 ... Substrate, 7 ... Color filter, 7a ... Colored layer, 7b ... Colored layer, 7c ... Colored Layer 8 flattening film 9 signal electrode 10 scan electrode 21 address decoder 22 OR circuit 23 drive circuit 24 AND circuit 41 control unit 42 counter 43 logic Circuit block, 44 ... adder

Claims (4)

a display panel having n scan electrodes (n is a natural number of 3 or more) and a plurality of signal electrodes intersecting with the scan electrodes;
A first operation mode in which a selection voltage is sequentially applied to the n scan electrodes of the display panel; and m scan electrodes among the n scan electrodes (m is a natural number of 2 or more, m <n) A selection voltage is sequentially applied to each of the first and second operation modes in which the selection voltage is collectively applied to (n−m) scan electrodes excluding the m scan electrodes. An operating scan electrode driving circuit;
In the first operation mode, a signal voltage corresponding to gradation designation data corresponding to an image to be displayed by a pixel formed by intersecting the n scanning electrodes and the signal electrode is sequentially applied to the signal electrode. And in the second operation mode, a partial display signal voltage corresponding to gradation designation data corresponding to an image to be displayed on a pixel formed by crossing the m scanning electrodes and the signal electrodes, , A background display signal voltage corresponding to gradation designating data corresponding to a background color to be displayed on a pixel formed by crossing the (nm) scan electrodes and the signal electrodes. A signal electrode driving circuit for applying a signal voltage to each of the signal electrodes;
A display device comprising: The scan electrode driving circuit includes a designation unit that designates m consecutive scan electrodes among n scan electrodes,
In the second operation mode, a selection voltage is sequentially applied to each of the continuous m scan electrodes designated by the designation means, and (n−m) number of the scan electrodes excluding the m scan electrodes are further applied. Apply a selection voltage to the scan electrodes at once,
The display device according to claim 1.   The color filter comprising three colored layers is further provided, wherein the color filter is arranged so that the colored layers colored in the same color overlap each other on one signal electrode. The display device according to 1 or 2. A display device drive circuit for driving a display device having n scan electrodes (n is a natural number of 3 or more) and a plurality of signal electrodes intersecting with the scan electrodes,
A first operation mode in which a selection voltage is sequentially applied to the n scan electrodes of the display panel; and m scan electrodes among the n scan electrodes (m is a natural number of 2 or more, m <n) A selection voltage is sequentially applied to each of the first and second operation modes in which the selection voltage is collectively applied to (n−m) scan electrodes excluding the m scan electrodes. An operating scan electrode driving circuit;
In the first operation mode, a signal voltage corresponding to gradation designation data corresponding to an image to be displayed by a pixel formed by intersecting the n scanning electrodes and the signal electrode is sequentially applied to the signal electrode. And in the second operation mode, a partial display signal voltage corresponding to gradation designation data corresponding to an image to be displayed on a pixel formed by crossing the m scanning electrodes and the signal electrodes, , A background display signal voltage corresponding to gradation designating data corresponding to a background color to be displayed on a pixel formed by crossing the (nm) scan electrodes and the signal electrodes. A signal electrode driving circuit for applying a signal voltage to each of the signal electrodes;
A drive circuit for a display device, comprising:

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