JP2005283458A

JP2005283458A - Voltage detection circuit

Info

Publication number: JP2005283458A
Application number: JP2004100491A
Authority: JP
Inventors: Osamu Uehara; 治上原; Kazusuke Sano; 和亮佐野
Original assignee: Seiko Instruments Inc
Current assignee: Seiko Instruments Inc
Priority date: 2004-03-30
Filing date: 2004-03-30
Publication date: 2005-10-13
Anticipated expiration: 2024-03-30
Also published as: JP4350575B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor circuit, capable of using the output terminal of voltage detection circuit as an input terminal. <P>SOLUTION: The voltage detection circuit is constructed by connecting the gate terminal of PchMOSFET of the buffer circuit in the voltage detection circuit with the drain of PchMOSFET, to turn off PchMOSFET of the buffer circuit. As a result, the inflow of the current from an external terminal VOUT is prevented to the input terminal of external circuit, even if input signals are inputted from the input terminal of external circuit via the external terminal VOUT during the period of tests. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は電圧検出回路の回路の構成に係り、さらに詳しくはテスト時に電圧検出回路の出力を入力として使用可能な設計方法に関する。 The present invention relates to a circuit configuration of a voltage detection circuit, and more particularly to a design method that can use an output of a voltage detection circuit as an input during a test.

従来の電圧検出回路としては、図３の回路ブロック図に示されるような電圧検出回路が知られていた。即ち、外部端子ＶＤＤとＶＳＳの間に直列に接続されている抵抗３０１と抵抗３０２とからなる電圧分圧回路の分圧電圧と、一定電圧を発生する基準電圧発生回路３０３の基準電圧とが、それぞれ電圧比較回路３０４に入力されて比較される。電圧比較回路３０４の出力信号は、ＰｃｈＭＯＳＦＥＴ３０５とＮｃｈＭＯＳＦＥＴ３０７とからなるインバーター構成のバッファー回路に入力される。バッファー回路の出力信号はＰｃｈＭＯＳＦＥＴ３０８とＮｃｈＭＯＳＦＥＴ３０６とからなるインバーター構成の出力回路に入力される。出力回路の出力信号は外部端子ＶＯＵＴから外部に出力される。 As a conventional voltage detection circuit, a voltage detection circuit as shown in the circuit block diagram of FIG. 3 has been known. That is, the divided voltage of the voltage dividing circuit composed of the resistor 301 and the resistor 302 connected in series between the external terminals VDD and VSS, and the reference voltage of the reference voltage generating circuit 303 that generates a constant voltage are: Each is input to the voltage comparison circuit 304 and compared. An output signal of the voltage comparison circuit 304 is input to an inverter-structured buffer circuit composed of a Pch MOSFET 305 and an Nch MOSFET 307. The output signal of the buffer circuit is input to an inverter-structured output circuit composed of a Pch MOSFET 308 and an Nch MOSFET 306. The output signal of the output circuit is output to the outside from the external terminal VOUT.

例えば分圧電圧が基準電圧より高い場合は、電圧比較回路３０４の出力電圧、即ち配線３１１の電圧がＨｉとなり、ＰｃｈＭＯＳＦＥＴ３０５がオフしてＮｃｈＭＯＳＦＥＴ３０７がオンするので、バッファー回路の出力電圧、即ち配線２１２の電圧がＬｏとなり、ＰｃｈＭＯＳＦＥＴ３０８がオンしてＮｃｈＭＯＳＦＥＴ３０６がオフするので、出力回路の出力電圧、即ち配線３１３の電圧がＨｉとなり、本電圧検出回路の電圧解除信号として、ＶＤＤの電位が外部端子ＶＯＵＴから出力される。逆に分圧電圧が基準電圧より低い場合は、上記と同様の経路で信号が逆になり、本電圧検出回路の電圧検出信号として、ＶＳＳの電位が外部端子ＶＯＵＴから出力される。
バッファー回路及び出力回路は電圧比較回路３０４の出力信号を増幅して出力する役割を果たしている。また、バッファー回路を消費電流の小さいＣＭＯＳインバーター構成とすることは、電圧検出回路全体の消費電流を少なく抑えることに役に立っている。
特開平９-３１１１４８号公報 For example, when the divided voltage is higher than the reference voltage, the output voltage of the voltage comparison circuit 304, that is, the voltage of the wiring 311 becomes Hi, the Pch MOSFET 305 is turned off, and the Nch MOSFET 307 is turned on. Since the voltage becomes Lo, the Pch MOSFET 308 is turned on and the Nch MOSFET 306 is turned off, the output voltage of the output circuit, that is, the voltage of the wiring 313 becomes Hi, and the potential of VDD is output from the external terminal VOUT as the voltage release signal of this voltage detection circuit. Is done. Conversely, when the divided voltage is lower than the reference voltage, the signal is reversed through the same path as described above, and the potential of VSS is output from the external terminal VOUT as the voltage detection signal of the voltage detection circuit.
The buffer circuit and the output circuit serve to amplify and output the output signal of the voltage comparison circuit 304. In addition, the CMOS inverter configuration having a low current consumption for the buffer circuit helps to reduce the current consumption of the entire voltage detection circuit.
JP-A-9-31148

従来の電圧検出回路では解除時にＶＤＤの電位が外部端子ＶＯＵＴから出力される。テスト時に出力端子に別の回路をつなぎ回路から電圧検出器と結線した場所を経由してＨｉ、Ｌｏを入力した場合電圧検出器からの電圧が別の回路と結線した箇所を通じて逆流して誤作動をおこしてしまうという課題があった。 In the conventional voltage detection circuit, the VDD potential is output from the external terminal VOUT at the time of release. During testing, when another circuit is connected to the output terminal and Hi or Lo is input via the location connected to the voltage detector from the circuit, the voltage from the voltage detector flows backward through the location connected to another circuit and malfunctions. There was a problem that it would cause.

例として図４を用いて電圧検出回路を通じて別の回路から入力電圧を印可した時の誤動作を説明する。図４は従来の電圧検出回路の外部接続図である。 As an example, the malfunction when an input voltage is applied from another circuit through the voltage detection circuit will be described with reference to FIG. FIG. 4 is an external connection diagram of a conventional voltage detection circuit.

図４において電圧検出回路が解除していると外部端子ＶＯＵＴからＶＤＤが出力される。ここで外部端子Ｖ１より入力信号ＨｉまたはＬｏを入力した時、電圧検出回路から出力されるＶＤＤが外部端子Ｖ１へ流れるため入力信号ＨｉまたはＬｏを外部回路４０１に伝えることができるが大電流が流れることが問題となる。
そこで本発明の目的は従来のこのような問題を解決するために、テスト時の電圧検出回路解除時に外部端子ＶＯＵＴをＯＰＥＮにして外部回路にＶＤＤが流れない電圧検出回路を得ることを目的としている。 When the voltage detection circuit is released in FIG. 4, VDD is output from the external terminal VOUT. Here, when the input signal Hi or Lo is input from the external terminal V1, VDD output from the voltage detection circuit flows to the external terminal V1, so that the input signal Hi or Lo can be transmitted to the external circuit 401, but a large current flows. Is a problem.
Accordingly, an object of the present invention is to obtain a voltage detection circuit in which VDD does not flow to an external circuit by setting the external terminal VOUT to OPEN when the voltage detection circuit is released during a test in order to solve such a conventional problem. .

上記課題を解決するために本発明の検出回路ではバッファー回路のＰｃｈＭＯＳＦＥＴのゲート端子又はＮｃｈＭＯＳＦＥＴのゲート端子に、ＰｃｈＭＯＳＦＥＴのドレイン端子又はＮｃｈＭＯＳＦＥＴのドレイン端子を結線し、このＰｃｈＭＯＳＦＥＴ又はＮｃｈＭＯＳＦＥＴをオンすることでバッファー回路のＰｃｈＭＯＳＦＥＴ又はＮｃｈＭＯＳＦＥＴをオフする構造とした。より具体的には、高電圧端子及び低電圧端子と、前記高電圧端子及び低電圧端子からの電源電圧を分割する分圧回路と、基準電圧を発生する基準電圧発生回路と、前記分圧回路からの分割電圧と前記基準電圧とを比較する電圧比較回路と、前記比較回路からの信号を反転するインバーター回路と、前記インバーター回路からの信号を電力増幅して出力端子に出力する出力バッファー回路とを備えた電圧検出回路において、外部信号に基づいて前記出力バッファー回路を制御するための出力バッファー制御手段を設け、前記出力バッファー制御手段は、前記出力端子を前記高電圧端子及び前記低電圧端子に対してオープン状態にすることができるようにした。 In order to solve the above problems, in the detection circuit of the present invention, the PchMOSFET drain terminal or NchMOSFET drain terminal is connected to the PchMOSFET gate terminal or NchMOSFET gate terminal of the buffer circuit, and the PchMOSFET or NchMOSFET is turned on to buffer the buffer circuit. The PchMOSFET or NchMOSFET of the circuit is turned off. More specifically, a high voltage terminal and a low voltage terminal, a voltage dividing circuit for dividing a power supply voltage from the high voltage terminal and the low voltage terminal, a reference voltage generating circuit for generating a reference voltage, and the voltage dividing circuit A voltage comparison circuit that compares the divided voltage from the reference voltage, an inverter circuit that inverts a signal from the comparison circuit, an output buffer circuit that amplifies the signal from the inverter circuit and outputs the amplified signal to an output terminal; An output buffer control means for controlling the output buffer circuit based on an external signal is provided in the voltage detection circuit, and the output buffer control means connects the output terminal to the high voltage terminal and the low voltage terminal. Now it can be opened.

このように、本発明の電圧検出回路では、外部端子ＶＯＵＴから外部回路の入力端子に電流が流れることを防止できる効果がある。これによってテスト時に電圧検出回路の外部端子ＶＯＵＴを経由して入力端子を接続することができるという効果がある。 Thus, the voltage detection circuit according to the present invention has an effect of preventing current from flowing from the external terminal VOUT to the input terminal of the external circuit. This has the effect that the input terminal can be connected via the external terminal VOUT of the voltage detection circuit during the test.

以下では本発明の実施例を説明する。 Examples of the present invention will be described below.

図１は本発明の第１の実施例の電圧検出回路のブロック図である。点線部は外部接続回路を示す。はじめに、本電圧検出回路の構成を説明する。 FIG. 1 is a block diagram of a voltage detection circuit according to a first embodiment of the present invention. A dotted line part shows an external connection circuit. First, the configuration of the voltage detection circuit will be described.

電源電圧を入力するために外部端子ＶＤＤとＶＳＳの間に、直列に接続されている抵抗１０１と抵抗１０２とがあり、入力された電源電圧を所定の比率で分割することができる電源電圧分圧回路を構成している。抵抗１０１と抵抗１０２との接続部は、電圧比較回路１０４の＋入力端子とを接続されている。一方、電源電圧の大きさにかかわらず一定の基準電圧を発生することができる基準電圧回路１０３は、外部端子ＶＳＳと電圧比較回路１０４の−入力端子とに接続されている。入力された、基準電圧と分圧された電源電圧との大きさを比較して、出力信号を切り替えることができる電圧比較回路１０４の出力端子は、ＰｃｈＭＯＳＦＥＴ１０５とＮｃｈＭＯＳＦＥＴ１０７のゲート端子にそれぞれ接続されている。ＰｃｈＭＯＳＦＥＴ１０５のソース端子と基板端子は外部端子ＶＤＤに、またドレイン端子はＮｃｈＭＯＳＦＥＴ１０７のドレイン端子とＰｃｈＭＯＳＦＥＴ１０８のゲート端子とＰｃｈＭＯＳＦＥＴ１０９のドレイン端子と、ＮｃｈＭＯＳＦＥＴ１０６のゲート端子にそれぞれ接続されている。ＮｃｈＭＯＳＦＥＴ１０７のソース端子と基板端子は外部端子ＶＳＳに、またドレイン端子はＰｃｈＭＯＳＦＥＴ１０５のドレイン端子とＰｃｈＭＯＳＦＥＴ１０９のドレイン端子とＮｃｈＭＯＳＦＥＴ１０６のドレイン端子にそれぞれ接続されている。このＰｃｈＭＯＳＦＥＴ１０５とＮｃｈＭＯＳＦＥＴ１０７とでバッファー回路を構成している。ＰｃｈＭＯＳＦＥＴ１０８のソース端子と基板端子はＶＤＤに、またドレイン端子はＮｃｈＭＯＳＦＥＴ１０６のドレイン端子と外部端子ＶＯＵＴにそれぞれ接続されている。ＮｃｈＭＯＳＦＥＴ１０６のソース端子と基板端子は外部端子ＶＳＳに、またドレイン端子はＰｃｈＭＯＳＦＥＴ１０８のドレイン端子と外部端子ＶＯＵＴにそれぞれ接続されている。このＰｃｈＭＯＳＦＥＴ１０８とＮｃｈＭＯＳＦＥＴ１０６とでバッファー回路を構成している。 There is a resistor 101 and a resistor 102 connected in series between the external terminals VDD and VSS in order to input a power supply voltage, and the power supply voltage division that can divide the input power supply voltage by a predetermined ratio The circuit is configured. A connection portion between the resistor 101 and the resistor 102 is connected to the + input terminal of the voltage comparison circuit 104. On the other hand, the reference voltage circuit 103 capable of generating a constant reference voltage regardless of the magnitude of the power supply voltage is connected to the external terminal VSS and the negative input terminal of the voltage comparison circuit 104. The output terminal of the voltage comparison circuit 104 that can compare the input reference voltage and the divided power supply voltage and switch the output signal is connected to the gate terminals of the PchMOSFET 105 and the NchMOSFET 107, respectively. . The source terminal and substrate terminal of PchMOSFET 105 are connected to external terminal VDD, and the drain terminal is connected to the drain terminal of NchMOSFET 107, the gate terminal of PchMOSFET 108, the drain terminal of PchMOSFET 109, and the gate terminal of NchMOSFET 106, respectively. The source terminal and the substrate terminal of the Nch MOSFET 107 are connected to the external terminal VSS, and the drain terminal is connected to the drain terminal of the Pch MOSFET 105, the drain terminal of the Pch MOSFET 109, and the drain terminal of the Nch MOSFET 106, respectively. The Pch MOSFET 105 and the Nch MOSFET 107 constitute a buffer circuit. The source terminal and substrate terminal of the Pch MOSFET 108 are connected to VDD, and the drain terminal is connected to the drain terminal of the Nch MOSFET 106 and the external terminal VOUT. The source terminal and substrate terminal of the Nch MOSFET 106 are connected to the external terminal VSS, and the drain terminal is connected to the drain terminal of the Pch MOSFET 108 and the external terminal VOUT. The Pch MOSFET 108 and the Nch MOSFET 106 constitute a buffer circuit.

次に本電圧検出回路の動作を説明する。 Next, the operation of this voltage detection circuit will be described.

外部端子ＶＤＤとＶＳＳの間に、ある大きさで変化する正の電圧を与え、外部端子ＶＳＳをＧＮＤに固定する。すると与えられた電圧は抵抗１０１と抵抗１０２とで分圧され、さらに分圧された電圧は電圧比較回路１０４に入力され、基準電圧発生回路１０３で発生している基準電圧と比較される。 A positive voltage that changes in a certain magnitude is applied between the external terminals VDD and VSS, and the external terminal VSS is fixed to GND. Then, the applied voltage is divided by the resistor 101 and the resistor 102, and the divided voltage is input to the voltage comparison circuit 104 and compared with the reference voltage generated by the reference voltage generation circuit 103.

ここで、分圧された電圧が基準電圧より高い場合は、電圧比較回路１０４の出力信号、すなわち配線１１１がＨｉとなりＰｃｈＭＯＳＦＥＴ１０５がオフし、ＮｃｈＭＯＳＦＥＴ１０７がオンする。ＮｃｈＭＯＳＦＥＴ１０７がオンすると配線１１２がＬｏになり、ＰｃｈＭＯＳＦＥＴ１０８がオンし、ＮｃｈＭＯＳＦＥＴ１０６がオフする。ＰｃｈＭＯＳＦＥＴ１０８がオンすると配線１１３がＨｉになり、本電圧検出回路の電圧解除信号として、ＶＤＤの電位が外部端子ＶＯＵＴから出力される。 Here, when the divided voltage is higher than the reference voltage, the output signal of the voltage comparison circuit 104, that is, the wiring 111 becomes Hi, the Pch MOSFET 105 is turned off, and the Nch MOSFET 107 is turned on. When the Nch MOSFET 107 is turned on, the wiring 112 becomes Lo, the Pch MOSFET 108 is turned on, and the Nch MOSFET 106 is turned off. When the Pch MOSFET 108 is turned on, the wiring 113 becomes Hi, and the potential of VDD is output from the external terminal VOUT as a voltage release signal of this voltage detection circuit.

一方、分圧された電圧が基準電圧より低い場合は電圧比較回路１０４の出力信号、即ち配線１１１がＬｏとなり、ＰｃｈＭＯＳＦＥＴ１０５がオンし、ＮｃｈＭＯＳＦＥＴ１０７がオフする。ＰｃｈＭＯＳＦＥＴ１０５がオンすると配線１１２がＨｉになり、ＰｃｈＭＯＳＦＥＴ１０８がオフし、ＮｃｈＭＯＳＦＥＴ１０６がオンする。ＮｃｈＭＯＳＦＥＴ１０６がオンすると配線１１３がＬｏになり、本電圧検出回路の電圧解除信号として、ＶＳＳの電位が外部端子ＶＯＵＴから出力される。 On the other hand, when the divided voltage is lower than the reference voltage, the output signal of the voltage comparison circuit 104, that is, the wiring 111 becomes Lo, the Pch MOSFET 105 is turned on, and the Nch MOSFET 107 is turned off. When the Pch MOSFET 105 is turned on, the wiring 112 becomes Hi, the Pch MOSFET 108 is turned off, and the Nch MOSFET 106 is turned on. When the Nch MOSFET 106 is turned on, the wiring 113 becomes Lo, and the potential of VSS is output from the external terminal VOUT as a voltage release signal of this voltage detection circuit.

次に電圧検出回路が電圧解除信号出力時に外部端子ＶＯＵＴをＯＰＥＮにする方法を説明する。 Next, a method for setting the external terminal VOUT to OPEN when the voltage detection circuit outputs a voltage release signal will be described.

電圧検出回路が電圧解除信号出力時に外部端子ＶＯＵＴをＯＰＥＮにするためにＰｃｈＭＯＳＦＥＴ１０８をオフさせる。そのためＰｃｈＭＯＳＦＥＴ１０９のドレインをＰｃｈＭＯＳＦＥＴ１０８のゲートに接続している。外部端子ＶＩＮにＬｏを印加するとＰｃｈＭＯＳＦＥＴ１０９がオンする。ＰｃｈＭＯＳＦＥＴ１０９がオンすると配線１１２がＨｉになりＰｃｈＭＯＳＦＥＴ１０８がオフする。さらに抵抗１１０を通るため電圧降下によって配線１１４がＬｏになりＰｃｈＭＯＳＦＥＴ１０６がオフし外部端子ＶＯＵＴがＯＰＥＮになる。 When the voltage detection circuit outputs a voltage release signal, the Pch MOSFET 108 is turned off to set the external terminal VOUT to OPEN. Therefore, the drain of the Pch MOSFET 109 is connected to the gate of the Pch MOSFET 108. When Lo is applied to the external terminal VIN, the Pch MOSFET 109 is turned on. When the Pch MOSFET 109 is turned on, the wiring 112 becomes Hi and the Pch MOSFET 108 is turned off. Further, since the resistor 110 is passed, the wiring 114 becomes Lo due to the voltage drop, the Pch MOSFET 106 is turned off, and the external terminal VOUT becomes OPEN.

以上のように本発明の電圧検出回路はバッファー回路のＰｃｈＭＯＳＦＥＴのゲート端子にＰｃｈＭＯＳＦＥＴのドレインを接続してバッファー回路のＰｃｈＭＯＳＦＥＴをオフさせる構成とした。その結果外部端子ＶＯＵＴを経由して外部回路の入力端子V１から入力信号を入力しても外部端子ＶＯＵＴからの電流が外部回路の入力端子V1に流れることを防止できた。したがって、出力端子に外部回路が接続され、外部回路に入力信号を入れる場合にも大電流を流すことはなく信号を伝えることができる。 As described above, the voltage detection circuit of the present invention is configured to turn off the PchMOSFET of the buffer circuit by connecting the drain of the PchMOSFET to the gate terminal of the PchMOSFET of the buffer circuit. As a result, even if an input signal is input from the input terminal V1 of the external circuit via the external terminal VOUT, the current from the external terminal VOUT can be prevented from flowing to the input terminal V1 of the external circuit. Therefore, even when an external circuit is connected to the output terminal and an input signal is input to the external circuit, a signal can be transmitted without flowing a large current.

また、出力電圧が低く配線１１１がＬｏを出力している場合には図2に示すようにＮｃｈＭＯＳＦＥＴ１１６のゲート端子に第１の実施例と同様にＮｃｈＭＯＳＦＥＴを入れても同様の効果を得られる。即ち、電圧比較回路２０４の出力信号がＬｏのとき、ＰｃｈＭＯＳＦＥＴ２０５がオンし、ＮｃｈＦＥＴ２０７がオフする。すると配線２１２がＨｉとなりＰｃｈＭＯＳＦＥＴ２０８がオフし、配線２１４がＨｉとなりＮｃｈＭＯＳＦＥＴ２０６がオンする。このときに、ＶｉｎにＬｏレベルを与えることにより、ＰｃｈＭＯＳＦＥＴ２０９がオンし、配線２１４がＬｏとなる。その結果、バッファー回路のＮｃｈＭＯＳＦＥＴはＯＰＥＮとなる。一方、配線２１２は、ＰｃｈＭＯＳＦＥＴ２０５がオンしているのでＨｉレベルが与えられている。そのためにバッファー回路のＰｃｈＭＯＳＦＥＴ２０８はオフの状態を維持する。このようにして、外部端子ＶＯＵＴをＯＰＥＮにすることができる。 When the output voltage is low and the wiring 111 outputs Lo, the same effect can be obtained by inserting an Nch MOSFET in the gate terminal of the Nch MOSFET 116 as shown in FIG. That is, when the output signal of the voltage comparison circuit 204 is Lo, the Pch MOSFET 205 is turned on and the Nch FET 207 is turned off. Then, the wiring 212 becomes Hi and the Pch MOSFET 208 is turned off, and the wiring 214 becomes Hi and the Nch MOSFET 206 is turned on. At this time, by applying a Lo level to Vin, the Pch MOSFET 209 is turned on, and the wiring 214 becomes Lo. As a result, the Nch MOSFET of the buffer circuit becomes OPEN. On the other hand, the wiring 212 is given a high level because the Pch MOSFET 205 is on. Therefore, the Pch MOSFET 208 of the buffer circuit is kept off. In this way, the external terminal VOUT can be set to OPEN.

本発明の電圧検出回路のブロック図である。It is a block diagram of the voltage detection circuit of this invention. 本発明の電圧検出回路のブロック図である。It is a block diagram of the voltage detection circuit of this invention. 従来の電圧検出回路の回路図である。It is a circuit diagram of the conventional voltage detection circuit. 従来の電圧検出回路の外部接続図である。It is an external connection diagram of a conventional voltage detection circuit.

Explanation of symbols

１０１、１０２、２０１、２０２、３０１、３０２抵抗
１０３、２０３、３０３基準電圧発生回路
１０４、２０４、３０４電圧比較回路
１０５、２０５、３０５ＰｃｈＭＯＳＦＥＴ
１０６、２０６、３０６ＮｃｈＭＯＳＦＥＴ
１０７、２０７、３０７ＮｃｈＭＯＳＦＥＴ
１０８、２０８、３０８ＰｃｈＭＯＳＦＥＴ
１０９、２０９ＰｃｈＭＯＳＦＥＴ
１１０、２１０抵抗
１１１、２１１、３１１配線
１１２、２１２、３１２配線
１１３、２１３、３１３配線
１１４、２１４配線
４０１ＮｃｈＭＯＳＦＥＴ 101, 102, 201, 202, 301, 302 Resistance 103, 203, 303 Reference voltage generation circuit 104, 204, 304 Voltage comparison circuit 105, 205, 305 PchMOSFET
106, 206, 306 Nch MOSFET
107, 207, 307 NchMOSFET
108, 208, 308 PchMOSFET
109,209 PchMOSFET
110, 210 Resistance 111, 211, 311 Wiring 112, 212, 312 Wiring 113, 213, 313 Wiring 114, 214 Wiring 401 NchMOSFET

Claims

A high voltage terminal and a low voltage terminal; a voltage dividing circuit for dividing a power supply voltage from the high voltage terminal and the low voltage terminal; a reference voltage generating circuit for generating a reference voltage; a divided voltage from the voltage dividing circuit; A voltage detection circuit comprising: a voltage comparison circuit that compares a reference voltage; an inverter circuit that inverts a signal from the comparison circuit; and an output buffer circuit that amplifies the signal from the inverter circuit and outputs the amplified signal to an output terminal The output buffer control means for controlling the output buffer circuit based on an external signal is provided, and the output buffer control means opens the output terminal with respect to the high voltage terminal and the low voltage terminal. A voltage detection circuit.

The output buffer circuit connects a first P-channel MOS transistor and a first N-channel MOS transistor in series, connects the connection point to the output terminal, and connects the gate of the first P-channel MOS transistor and the first P-channel MOS transistor. The gate of one N-channel MOS transistor is connected via a resistor, and the output of the output buffer control means is input to the gate of the first P-channel MOS transistor and input to the output buffer control means. 2. The voltage detection circuit according to claim 1, wherein the first P-channel MOS transistor is opened by setting the gate of the first P-channel MOS transistor to Hi level in response to an external signal. .

The output buffer circuit connects a first P-channel MOS transistor and a first N-channel MOS transistor in series, connects the connection point to the output terminal, and connects the gate of the first P-channel MOS transistor to the output terminal. The gate of the first N-channel MOS transistor is connected via a resistor, and the output of the output buffer control means is input to the gate of the first N-channel MOS transistor and input to the output buffer control means. 2. The voltage detection circuit according to claim 1, wherein the first N-channel MOS transistor is brought into an open state by setting the gate to Lo level in accordance with an external signal to be performed.

3. The voltage detection circuit according to claim 2, wherein the output buffer control means comprises a second P-channel MOS transistor.

4. The voltage detection circuit according to claim 3, wherein the output buffer control means comprises a second P-channel MOS transistor.

The inverter circuit includes a third P-channel MOS transistor and a third N-channel MOS transistor, and the signal from the comparison circuit is used as the gate of the third P-channel MOS transistor and the gate of the third N-channel MOS transistor. And the output of the third P-channel MOS transistor is applied to the gate of the first P-channel MOS transistor, and the output of the third N-channel MOS transistor is applied to the gate of the first N-channel MOS transistor. 6. The voltage detection circuit according to claim 1, wherein the voltage detection circuit is provided.

The inverter circuit includes a third P-channel MOS transistor and a third N-channel MOS transistor, the source of the first P-channel MOS transistor, the source of the second P-channel MOS transistor, and the third P-channel. A source of a MOS transistor is connected to the high voltage terminal, a drain of the second P-channel MOS transistor and a drain of the third P-channel MOS transistor are connected to a gate of the first P-channel MOS transistor; The drain of the third N channel MOS transistor is connected to the gate of the first MOS transistor, and the source of the first N channel MOS transistor and the source of the third N channel MOS transistor are connected to the low voltage terminal. Voltage detection circuit according to claim 4, characterized in that the.

The inverter circuit includes a third P-channel MOS transistor and a third N-channel MOS transistor, the source of the first N-channel MOS transistor, the source of the second P-channel MOS transistor, and the third N-channel MOS transistor. The source of the MOS transistor is connected to the low voltage terminal, the drain of the second P channel MOS transistor is connected to the gate of the first N channel MOS transistor, and the drain of the third N channel MOS transistor is connected to the drain. 6. The gate of the first N channel MOS transistor is connected, and the source of the first P channel MOS transistor and the source of the third P channel MOS transistor are connected to the high voltage terminal. Voltage detection described in Circuit.