JP2005277816A - Jitter suppressor, method and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a system time clock in which a jitter is reduced. <P>SOLUTION: A jitter suppressor reduces the jitter of time information included in an input digital signal. The jitter suppressor includes a time duration information extraction means for extracting an hour entry from an input digital signal; a time duration information storage means for storing the hour entry extracted by the time duration information extraction means; a data storage means for storing an input digital signal; a clock generating means; a clock measuring means for measuring the clock from the clock generating means; a data generating means for multiplexing the input digital signal; a multiplexing means for multiplexing the input digital signal stored in the data storage means and data generated by the data generating means; a time information correction means for correcting the time information included in the multiplexed data multiplexed by the multiplexing means; and a control means for controlling the time information storage means, the data storage means, the multiplexing means, and the time duration information correction means. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a jitter suppression apparatus, method, and computer program suitable for reducing network jitter that occurs when video and audio are transmitted in real time via an ATM network or the like.

  The MPEG2 system is actively used as a system for compressing and encoding audio / video data and performing multiplex transmission as a bit stream. In this MPEG2 system, in order to synchronize the transmission side and the reception side, a system clock is generated on the transmission side, and this reference information (PCR: Program Clock Reference) is inserted at an appropriate interval in the bit stream. By extracting this and regenerating the system clock using a PLL circuit that phase-locks the oscillator on the receiving side with the PCR, the transmitting side and the receiving side can be synchronized.

  FIG. 3 is a diagram showing the structure of an MPEG2 transport stream. Of the 188-byte transport stream packet, the first 4 bytes (32 bits) are a header. The adaptation field control in the header indicates the presence or absence of the adaptation field. If there is no adaptation field, the header is immediately followed by payload. Data such as video and audio is inserted into this payload and sent. When the presence of an adaptation field is indicated, the adaptation field follows the header and the rest is payload. A stuffing byte can be inserted in the payload following the adaptation field instead of video data.

  The PCR signal included in the adaptation field is 42 bits of actual data, and a transport stream packet including the actual data is transmitted with a period of 0.1 second or less for each program. The last byte of the PCR field is defined as the time standardized position, and the receiver is required to correct the clock according to the value indicated by the PCR field at the arrival of this position.

  The configuration of the system clock recovery PLL circuit in the receiver that receives the MPEG2 transport stream will be described below with reference to FIGS. First, the received TS packet is supplied to the clock regenerator 501 and the MPEG2 decoder 502. The clock regenerator 501 extracts the PCR packet and regenerates the system clock. The reproduced system clock is supplied to the MPEG2 decoder 502.

  FIG. 4 is a detailed block diagram of the clock regenerator 501. A PCR signal is extracted from the packet of the program by the PCR detector 401 from the received TS packet. The PCR value is loaded into the counter 403 that counts the output of the voltage controlled oscillator (VCO) 405 at the time standardization position of the PCR signal detected by the PCR detector 401. The counter value and the received PCR value are subtracted by the subtractor 402. The subtraction result is smoothed by the low-pass filter 404 and supplied to the VCO 405. The output of the VCO 405 is supplied as a system clock to the video and audio decoder via the output terminal 406.

  A system for transmitting an MPEG2 system signal by ATM (Asynchronous Transfer Mode) is known as MPEG over ATM. In this MPEG over ATM, for example, two TS (Transport Stream) packets are formatted into eight ATM cells and transmitted. In this MPEG over ATM, as shown in FIG. 6, for example, two transport stream packets are converted into AAL5 and then decomposed into eight ATM cells for transmission. On the other hand, since the transport packet is assembled on the receiving side when eight ATM cells are received, these two transport packets become burst data as shown in FIG. Here, due to the difference between the transport stream transmission rate and the ATM transmission rate, the position of the PCR fluctuates from the original position, and jitter occurs in the STC generated based on this.

  Further, in ATM transmission in AAL5, as shown in FIG. 7, since the transfer time between the transmission side and the reception side is not guaranteed, further jitter occurs.

  Therefore, the present invention provides a jitter suppression method and jitter suppression apparatus for generating a system time clock with reduced jitter even if the position of the program clock reference of the received MPEG over ATM signal varies, and further, the jitter suppression apparatus It is an object of the present invention to provide an MPEG decoding apparatus having the above-mentioned.

The jitter suppression apparatus of the present invention is a jitter suppression apparatus that reduces jitter of time information included in an input digital signal, and extracts time information from the input digital signal, and is extracted by the time information extraction means. Time information storage means for storing the time information, data storage means for storing the input digital signal, clock generation means, clock measurement means for measuring the clock from the clock generation means, multiplexed to the input digital signal Data generating means, multiplexing means for multiplexing the input digital signal stored in the data storage means and data generated by the data generating means, and time information included in the multiplexed data multiplexed by the multiplexing means Information correction means for correcting, the time information storage means and the data storage And a controlling means for controlling the stage and said multiplexing means and said time information correction means.
The jitter suppression method of the present invention is a jitter suppression method for reducing jitter of time information contained in an input digital signal by a jitter suppression device, a time information extraction procedure for extracting time information from an input digital signal, and an extraction Time information storing procedure for storing the time information in the time information storing means, data storing procedure for storing the input digital signal in the data storing means, clock measuring procedure for measuring the clock from the clock generating means, and multiplexing to the input digital signal A data generation procedure, a multiplexing procedure for multiplexing the input digital signal stored in the data storage means and the data generated by the data generation procedure, and time information included in the multiplexed data multiplexed by the multiplexing procedure. Correction procedure of time information to be corrected, the time information storage procedure and the data storage procedure And characterized in that it has a control procedure for controlling the multiplexing procedure and the time information correction step.
A computer program according to the present invention is a computer program for causing a computer to execute processing for reducing jitter of time information contained in an input digital signal, the time information extraction processing for extracting time information from the input digital signal, and extraction Time information storage processing for storing the time information in the time information storage means, data storage processing for storing the input digital signal in the data storage means, clock measurement processing for measuring the clock from the clock generation means, and multiplexing to the input digital signal A data generation process, a multiplexing process for multiplexing the input digital signal stored in the data storage means and the data generated by the data generation process, and time information included in the multiplexed data multiplexed by the multiplexing process. Time information correction processing to be corrected, and the time information recording It has characteristic processing and said data storage processing and control processing for controlling the multiplexing process and the time information correction process to the point to be executed by a computer.

  According to the present invention, network jitter can be suppressed for a received transport stream packet including network jitter, so that a stable system clock can be reproduced in the transport stream packet decoder. Audio can be easily decoded.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a block diagram showing a configuration of an MPEG decoding apparatus including a PCR jitter suppression apparatus to which the present invention is applied. In FIG. 2, 201 is a PCR jitter suppressor, 202 is a TS decoder, 203 is a PCR regenerator, 204 is a video decoder, and 205 is an audio decoder.

  A transport stream packet including network jitter is input to the PCR jitter suppressor 201. The PCR jitter suppressor 201 outputs a transport stream packet in which network jitter is suppressed by a jitter suppression method described later.

  Transport stream packets with suppressed network jitter are supplied to the TS decoder 202 and separated into transport stream packets including PCR, video and audio packets, respectively, a PCR regenerator 203, a video decoder 204, and an audio decoder, respectively. Is supplied to the generator 205.

  The PCR regenerator 203 extracts the PCR from the transport stream packet, and regenerates the system clock by the PLL circuit. The reproduced system clock is supplied to the video decoder 204 and the audio decoder 205.

  The video decoder 204 and audio decoder 205 decode video and audio packets, respectively, and output video data and audio data.

  Next, a PCR jitter suppression method performed by the PCR jitter suppressor 201 will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a PCR jitter suppressor to which the present invention is applied. In FIG. 1, 101 is a PCR extractor that extracts a PCR value from a received transport stream packet, 102 is a PCR buffer that stores the extracted PCR value, 103 is a 27 MHz oscillator, and 104 is a 27 MHz clock of the 27 MHz oscillator 103. 105, a controller for controlling the writing and reading of the transport stream packet in the memory 106 from the values of the PCR buffer 102 and the counter 104, 106 a memory for storing the received transport stream packet, and 107 for generating a null packet The stuffing generator, 108 is a multiplexer that multiplexes the received transport stream packet and the null packet output from the stuffing generator 107, and 109 is a PCR complement that corrects the PCR value. It is a vessel.

  In FIG. 1, transport stream packets including network jitter are sequentially received, and a PCR value is extracted from a received transport stream packet including PCR multiplexed in the transport stream packet by a PCR extractor 101.

  When the PCR extractor 101 extracts the transport stream packet including the PCR from the received transport stream packet, the PCR extractor 101 outputs a PCR notification signal to the controller 105. Further, the PCR value is held in the PCR buffer 102.

  The controller 105 sequentially writes the received transport stream packets into the memory 106. When receiving a PCR extraction notification signal from the PCR extractor 101, the PCR value extracted by the PCR extractor 101, the PCR value held in the PCR buffer 102, and the measured value of the counter 104 are read. When reading of the measurement value of the counter 104 is completed, the counter 104 is reset. The measured value of the counter 104 is a value obtained by measuring the 27 MHz clock output from the 27 MHz oscillator 103.

  Writing the received transport stream packet into the memory 106, extracting the PCR multiplexed in the received transport stream packet, writing it into the PCR buffer 102, and reading the PCR value and the measurement value of the counter 104 Are performed continuously at intervals of transport stream packets including PCR.

  The controller 105 calculates the time difference between the two read PCR values. This calculated time difference becomes the time difference of each PCR value. Further, the read measurement value of the counter 104 is compared with the calculated PCR time difference.

  As a result of the comparison, if the difference between the PCR time difference and the measured value of the counter 104 is less than the time difference at which one transport stream packet can be transmitted, the received transport stream packet written in the memory 106 is read from the multiplexer 108 Supply to the PCR corrector 109. Reading from the memory 106 is from the transport stream packet including the PCR to the transport stream packet immediately preceding the transport stream packet including the next PCR.

  On the contrary, if the difference between the PCR time difference and the measured value of the counter 104 is equal to or greater than the time difference at which one transport stream packet can be transmitted, the null packet from the multiplexor 108 to the stuffing generator 107 is compared. Insertion is performed in units of transport stream packets until the difference between the resulting PCR time difference and the measurement value of the counter 104 is less than the time difference at which one transport stream packet can be transmitted.

  The transport stream packet output from the multiplexer 108 by this null packet insertion can suppress the network jitter to a jitter less than the time at which one transport stream packet can be transmitted.

  Next, the PCR corrector 109 receives a transport stream packet suppressed to a jitter less than the time at which the one transport stream packet can be transmitted, and transports a PCR value from the multiplexed data output from the multiplexer 108. Extract stream packets.

  The extracted PCR value is corrected with a one-clock accuracy of 27 MHz from the measured value of the counter 104 for jitter less than the time at which the one transport stream can be transmitted.

  By adding the timing of reading from the controller 105 to the memory 106, the difference between the two calculated PCR times, and the time shift amount less than one transport stream packet from the measured value from the counter 104, to the PCR value. The network jitter is suppressed and supplied to the TS decoder 202 of FIG.

  An object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the above-described embodiments to a system or apparatus, and the computer (or CPU or MPU) of the system or apparatus stores the storage medium. Needless to say, this can also be achieved by reading and executing the program code stored in.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code itself and the storage medium storing the program code constitute the present invention.

  As a storage medium for supplying the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (basic system or operating system) running on the computer based on the instruction of the program code. Needless to say, a case where the functions of the above-described embodiment are realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the storage medium is written to a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the board or function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

It is a block diagram which shows the structure of the PCR jitter suppressor to which this invention is applied. It is a block diagram which shows the structure of the MPEG decoding apparatus containing the PCR jitter suppressor to which this invention is applied. It is a figure which shows the structure of the transport stream of MPEG2. It is a block diagram which shows the structure of a system clock regenerator. It is a block diagram which shows the structure of an MPEG2 decoding apparatus. It is a figure which shows the structure of a transport stream packet and an ATM cell. It is a figure which shows the cell transmission / reception timing in ATM-AAL5.

Explanation of symbols

101: PCR extractor 102: PCR buffer 103: 27 MHz oscillator 104: Counter 105: Controller 106: Memory 107: Stuffing generator 108: Multiplexer 109: PCR corrector 201: PCR jitter suppressor 202: TS decoder 203: PCR Regenerator 204: Video decoder 205: Audio decoder

Claims (9)

A jitter suppression device for reducing jitter of time information included in an input digital signal,
Time information extraction means for extracting time information from the input digital signal;
Time information storage means for storing the time information extracted by the time information extraction means;
Data storage means for storing input digital signals;
Clock generation means;
Clock measuring means for measuring a clock from the clock generating means;
Data generating means for multiplexing the input digital signal;
Multiplexing means for multiplexing the input digital signal stored in the data storage means and the data generated by the data generation means;
Time information correction means for correcting time information included in the multiplexed data multiplexed by the multiplexing means;
A jitter suppression apparatus comprising: control means for controlling the time information storage means, the data storage means, the multiplexing means, and the time information correction means.   The input digital signal is a transport stream shown in ISO / IEC13818-1, and the time information is a program clock reference base and a program clock reference extension inserted in the transport stream. The jitter suppression apparatus according to claim 1.   The jitter suppression apparatus according to claim 1, wherein the data generated by the data generation means is a null packet indicated by ISO / IEC13818-1.   2. The jitter suppression apparatus according to claim 1, wherein the control unit writes the time information extracted by the time information extraction unit into the time information storage unit when receiving the extraction notification signal from the time information extraction unit. .   When the control means receives the extraction notification signal from the time information extraction means, it reads out the time information from the time information storage means, calculates the time difference from the previous time information, and outputs the time difference from the clock measurement means. 2. The jitter suppression device according to claim 1, wherein the measurement information is read, the time difference is compared with the measurement information, and the data generated by the data generation means is multiplexed until the measurement information becomes less than a certain value. .   When the control means receives the extraction notification signal from the time information extraction means, it reads out the time information from the time information storage means, calculates the time difference from the previous time information, and outputs the time difference from the clock measurement means. Read measurement information, compare the time difference with the measurement information, and when the value is equal to or greater than a certain value, the data stored in the data storage means is transferred from the transport stream packet including the time information included in the data to the next 2. The jitter suppression apparatus according to claim 1, wherein up to a transport stream packet preceding the transport stream packet including time information is read out.   6. The jitter suppression apparatus according to claim 5, wherein the time information correction unit adds a difference time value between the time difference and the measurement information to time information included in the multiplexed data. A jitter suppression method for reducing jitter of time information included in an input digital signal by a jitter suppression device,
A time information extraction procedure for extracting time information from the input digital signal;
A time information storage procedure for storing the extracted time information in the time information storage means;
A data storage procedure for storing the input digital signal in the data storage means;
A clock measurement procedure for measuring the clock from the clock generation means;
A data generation procedure for multiplexing the input digital signal;
A multiplexing procedure for multiplexing the input digital signal stored in the data storage means and the data generated by the data generation procedure;
A time information correction procedure for correcting time information included in multiplexed data multiplexed by the multiplexing procedure;
A jitter suppression method comprising: a control procedure for controlling the time information storage procedure, the data storage procedure, the multiplexing procedure, and the time information correction procedure. A computer program for causing a computer to execute processing for reducing jitter of time information included in an input digital signal,
Time information extraction processing for extracting time information from the input digital signal;
A time information storage process for storing the extracted time information in the time information storage means;
A data storage process for storing the input digital signal in the data storage means;
Clock measurement processing for measuring the clock from the clock generation means;
Data generation processing to be multiplexed with the input digital signal;
A multiplexing process for multiplexing the input digital signal stored in the data storage means and the data generated by the data generation process;
A time information correction process for correcting time information included in the multiplexed data multiplexed by the multiplexing process;
A computer program for causing a computer to execute control processing for controlling the time information storage processing, the data storage processing, the multiplexing processing, and the time information correction processing.

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