JP2005269621A - Frequency synthesizer, radio communication system using it, and control method of frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer which has a good C/N characteristic and integrates a voltage-controlled oscillator (VCO) with a wide output frequency range at a low cost. <P>SOLUTION: The frequency synthesizer is provided with the VCO (1) having a plurality of frequency bands, stores its prescribed voltage (V1) in a storage circuit (11) by measuring an oscillation frequency of each band in a state of being applied to the VCO (1), compares frequency division ratio setting given from a PLL control circuit (14) with a measured value of the stored frequency, selects one band from the VCO (1) based on the comparison result, further oscillates the VCO (1) at a fixed voltage on the selected band, and decides the frequency band used actually for a frequency phase lock from the oscillation frequency obtained at that time and from an error between the oscillation frequency and a reference frequency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a frequency synthesizer used in a mobile radio device or the like, and more particularly to a frequency synthesizer including a voltage controlled oscillator (VCO) that can oscillate in a plurality of frequency bands.

  In general, in a wireless communication system such as a mobile phone, a frequency synthesizer is used as a local oscillator that generates an oscillation signal having a predetermined frequency to be combined with a reception signal or a transmission signal.

  Among conventional mobile phones, for example, dual-band mobile phones that can handle signals in two frequency bands such as 880 to 915 MHz band GSM (Global System for Mobile Communication) and 1710 to 1785 MHz band DCS (Digital Cellular System). is there. Further, in such a dual-band mobile phone, there is one that can cope with two frequency bands with one PLL circuit by switching the output frequency of the PLL circuit.

  In recent years, in addition to GSM and DCS, there has been a growing demand for triple-band mobile phones that can handle PCS (Personal Communication System) signals in the 1850 to 1915 MHz band, for example. It is expected to be.

  For high-frequency semiconductor integrated circuits (hereinafter referred to as “high-frequency LSIs”) that perform modulation / demodulation of transmission / reception signals used in mobile phones that can handle a plurality of frequency bands, the viewpoints of downsizing and cost reduction of mobile phones Therefore, the direct conversion method is effective. The direct conversion method is relatively easy to handle a plurality of frequency bands, but has a problem that the frequency range in which a voltage controlled oscillator (hereinafter referred to as “VCO”) can oscillate is widened. In other words, if one VCO tries to deal with all frequencies, the sensitivity of the VCO control voltage (oscillation frequency variation per 1 V: unit [Hz / V]) becomes high and weak against external noise and power supply voltage fluctuations. There is a problem that the C / N (Carrier / Noise) characteristics deteriorate.

  On the other hand, since the VCO is generally composed of module parts, it is one of the factors that hinder the miniaturization of mobile phones and the like, and there is an increasing demand for IC integration of the VCO. However, when the VCO is integrated into an IC, there is a problem that the oscillation frequency changes greatly due to manufacturing variations of elements constituting the VCO, and the phase cannot be locked at a desired frequency.

  In order to solve this problem, there is a method in which a plurality of fixed capacitors are connected in parallel to the parallel resonant circuit of the VCO, and the oscillation frequency is set by trimming with a laser or the like during IC manufacture. Therefore, there is a problem of increasing the manufacturing cost. Although there is a method of increasing the VCO control sensitivity, as described above, if the control sensitivity is increased, another problem arises that the C / N characteristics deteriorate due to weakness against external noise and power supply voltage fluctuation.

  For example, Patent Document 1 and Patent Document 2 are known as prior arts related to an oscillation circuit including a VCO.

JP 2003-152535 A JP 2001-339301 A

  In a parallel resonance circuit of a VCO, a configuration is known in which a plurality of capacitors or inductor switching means are provided so that the resonance frequency can be finely switched and a plurality of frequency bands can be used. In a VCO having a single frequency band, as shown in FIG. 2A, the control sensitivity of the VCO is increased because oscillation is performed in a wide range from the frequency fL to the frequency fH. On the other hand, by configuring the VCO to have a plurality of (N) frequency bands, the resonance frequency can be finely switched as shown in FIG. 2B, so that the control sensitivity of the VCO can be lowered and the C / N characteristics can be reduced. Can be improved.

  In such a frequency synthesizer using a plurality of frequency bands VCO, in order to obtain a desired oscillation frequency, it is necessary to determine in which frequency band the phase can be locked.

  In Patent Document 1 or Patent Document 2, in order to avoid the cost increase due to individual adjustment at the time of IC manufacture in the VCO IC conversion, the frequency band is automatically set based on the division ratio setting given from the external PLL control circuit. Is selected.

  The characteristics of the frequency synthesizer of Patent Document 1 are as follows. First, for a VCO having a plurality of frequency bands, the oscillation frequency of each band is previously investigated by the frequency investigation means, and the result is stored in the storage device. In the band selection circuit, the stored value is compared with the desired frequency to select a band. However, in this method, when the operating environment changes such as the temperature change of the IC and the power supply voltage change after storing the oscillation frequency, the oscillation frequency of the VCO changes between the storage operation and the actual operation. For this reason, there is a problem that if the data stored during the storage operation is used as it is, an optimum band cannot always be obtained during the operation. In anticipation of such changes in the oscillation frequency due to changes in the operating environment, it is conceivable to widen the frequency coverage of each band, that is, to increase the control sensitivity of the VCO. As described above, the noise becomes weak against external noise and power supply voltage fluctuation, resulting in a problem that the C / N characteristic is deteriorated.

  On the other hand, the frequency synthesizer of Patent Document 2 is characterized by analogizing the oscillation frequency of the VCO every time the phase is locked, and selecting an optimum band each time. For this reason, not only manufacturing variations but also changes such as temperature and supply voltage can always be handled.

  Specifically, after the frequency division ratio setting is given from the external PLL control circuit, the time difference between the reference signal fref and the comparison signal fdiv is detected in order to estimate the oscillation frequency of the VCO. Furthermore, the band switching and the analogy of the oscillation frequency are repeated until the time difference between the reference signal fref and the comparison signal fdiv is within a predetermined value, that is, until the difference between the VCO oscillation frequency and the desired frequency is within the predetermined value. However, this method has a problem that the lock-up time becomes longer by the time obtained by multiplying the time required for one time difference detection operation by the number of times of the time difference detection operation in order to finally determine the band to be phase locked. .

  Even if the time required to estimate the oscillation frequency per time is shortened in order to shorten the time required for determining the band, the accuracy is lowered, so that the VCO band is not changed until the difference from the desired frequency is within a predetermined range. Since the number of times of switching is increased, the time required to determine the band cannot be reduced so much. In the worst case, the phase cannot be locked due to a decrease in accuracy.

  Further, the manufacturing variation of the VCO also causes a decrease in the accuracy of the oscillation frequency analogy because the oscillation frequency and the relative relationship between the bands change. Further, when the number of bands is increased in order to lower the control sensitivity of the VCO, the number of times of band switching due to the accuracy of the oscillation frequency analogy increases, the time required for band determination increases, and the lockup time increases.

  For these reasons, it is a well-known fact that C / N deteriorates when the constant of the loop filter is changed to satisfy the lock-up time specification when the time required for band determination is not negligible.

  As described above, it is difficult for a conventional VCO band automatic selection circuit to obtain a frequency synthesizer having good C / N characteristics.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a low-cost frequency synthesizer that can obtain good C / N characteristics using a VCO having a plurality of frequency bands. It is in.

  The frequency synthesizer according to the present invention is capable of oscillating in a plurality of frequency bands, and oscillates and outputs a signal having a frequency corresponding to the voltage applied to the control voltage terminal, and the frequency of the voltage controlled oscillator is divided. Compare the phase of the comparison divider that outputs the signal, the reference divider that divides the frequency of the reference signal, the output signal of the comparison divider and the output signal of the reference divider, and find the phase difference A phase comparator to output, a charge pump that converts the output signal of the phase comparator into a voltage, a loop filter that smoothes the output voltage of the charge pump and applies it to the control voltage terminal of the voltage controlled oscillator, and voltage control during oscillation operation A band control circuit for setting a frequency band of the oscillator.

  The band control circuit includes a frequency investigation unit that measures an oscillation frequency for each of a predetermined number of frequency bands of the voltage controlled oscillator, a storage unit that stores an oscillation frequency of each frequency band measured by the frequency investigation unit, and a PLL control circuit Based on the frequency given from the initial band selection means for selecting one frequency band from among the oscillation frequency bands whose oscillation frequencies are stored in the storage means, and in one frequency band selected by the initial band selection means Frequency adjustment means for measuring the oscillation frequency of the voltage controlled oscillator, determining one frequency band to be used for the oscillation operation based on the measured oscillation frequency, and setting the determined frequency band in the voltage controlled oscillator. .

  The frequency synthesizer according to the present invention can be incorporated in a wireless communication system.

  The method according to the present invention is a method for controlling a frequency synthesizer including a voltage controlled oscillator having a plurality of frequency bands. In the control method, a predetermined voltage is applied to the voltage controlled oscillator, the oscillation frequency of the voltage controlled oscillator is measured for each of a predetermined number of frequency bands, the measured oscillation frequency of each frequency band is stored, and the PLL control circuit Based on the frequency given from, one frequency band is selected from each oscillation frequency band in which the oscillation frequency is stored, and a predetermined voltage is applied to the voltage controlled oscillator. The oscillation frequency of the voltage controlled oscillator is measured, one frequency band used for the oscillation operation is determined based on the measured oscillation frequency and the error between the oscillation frequency and the reference frequency, and the determined frequency band is used as the voltage controlled oscillator. Set to.

  According to the present invention, even if there are fluctuations in the oscillation frequency due to manufacturing variations of elements constituting the voltage controlled oscillator (VCO), and even if environmental changes such as IC temperature and power supply voltage occur during the operation of the integrated circuit, the VCO Since the frequency band is determined according to the actual oscillation frequency, the phase can be locked at a desired frequency. In addition, since the VCO can be integrated into an IC, the size and cost can be reduced. Since the resonance frequency of the VCO can be finely switched, the control sensitivity of the VCO can be lowered, and since the oscillation frequency is measured and stored in advance, the VCO oscillation frequency can be accurately estimated, so that the band can be obtained in a short time. Can be determined, and the lock-up time can be shortened. As a result, good C / N characteristics can be obtained.

  Also, by providing this frequency synthesizer in a wireless communication system, a wireless communication system with a small size, low cost, and good communication quality can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1. 1 is a block diagram of a frequency synthesizer according to the present invention.
The frequency synthesizer has a control voltage terminal, a VCO (voltage controlled oscillator) 1 that outputs a signal having a frequency corresponding to a voltage applied to the control voltage terminal, and a prescaler 2 that divides the output signal fvco of the VCO 1. , A counter 3 that counts the output signal of the prescaler 2, a reference oscillation circuit (hereinafter referred to as “TCXO”) 4 that oscillates at a high-precision frequency using a crystal oscillator, and a reference that divides the output signal fosc of the TCXO 4 The frequency divider 5, the phase comparator 6 that compares the phases of the output signal fdiv of the counter 3 and the output signal fref of the reference frequency divider 5 and outputs a phase difference, and the output signal of the phase comparator 6 is the voltage or current. A charge pump 7 for converting the output of the charge pump 7 and a loop filter 8 for smoothing the output of the charge pump 7.

  The VCO 1 has a plurality of frequency bands (bands) and makes it possible to finely switch the oscillation frequency. That is, the VCO 1 has N bands such as a band 1, a band 2,..., A band N from the lowest oscillation frequency as shown in FIG. The prescaler 2 and the counter 3 constitute a pulse swallow type variable frequency divider 20. The phase comparator 6, the charge pump 7, the loop filter 8, the VCO 1, the prescaler 2 and the counter 3 constitute a closed loop, which is the same as the configuration of a general PLL circuit.

  The frequency synthesizer further includes a band controller 50 that controls the frequency band of the VCO 1. The band control unit 50 includes a frequency survey unit 10 that measures the oscillation frequency of each band of the VCO 1 at the fixed voltage V1, a storage circuit 11 that stores a measurement result by the frequency survey unit 10, and an initial band for frequency adjustment. An initial band selection circuit 12 to be determined and a frequency adjustment unit 13 to determine a band group to be actually used are included.

  The storage circuit 11 actually stores frequency division ratio setting information as the oscillation frequency information of each band. This is because the “frequency division ratio setting” and the “oscillation frequency” are in a proportional relationship, and therefore, if the frequency division ratio setting is determined, the oscillation frequency is uniquely determined. In the description of this embodiment, the terms “frequency division ratio setting” and “oscillation frequency” may be used synonymously.

  The initial band selection circuit 12 determines an initial band from the oscillation frequency of the VCO 1 stored in the storage circuit 11 and the frequency division ratio setting 1 provided from the PLL control circuit 14. The frequency adjusting unit 13 determines one band that is actually used when the phase is locked from the band group determined by the initial band selection circuit 12. The band of the VCO 1 can be switched by the VCO control signal 1 from the frequency examining unit 10 or the VCO control signal 2 from the frequency adjusting unit 13.

  The frequency synthesizer has two switches 9 and 18.

  The switch 9 is switched by the SW control signal 1 from the frequency examining unit 10 or the SW control signal 2 from the frequency adjusting unit 13. The switch 9 connects the output of the charge pump 7 or a predetermined bias voltage V 1 to the loop filter 8. The switch 9 may be provided so as to supply the output of the loop filter 8 or a predetermined bias voltage V1 to the VCO1. In the present embodiment, the predetermined bias voltage V1 is set to a voltage equal to the lower limit voltage VL shown in FIG. 2B. The switch 9 is switched to the loop filter 8 side when the frequency synthesizer performs a normal oscillation operation. When the frequency band of the VCO 1 is investigated, the initial band is selected, and the optimum band is set, the voltage is switched. It is switched to the source V1 side.

  The switch 18 switches the frequency division ratio set in the counter 3 and supplies the counter 3 with the frequency division ratio setting 2 from the frequency examining unit 10 or the frequency division ratio setting 1 from the PLL control circuit 14. The switch 18 is switched by the SW control signal 3 from the frequency examining unit 10.

2. 2. Operation of Frequency Synthesizer 2.1 Outline of Operation The frequency synthesizer of this embodiment has the same configuration as that of a general frequency synthesizer except for the band control unit 50, and performs the same oscillation operation. Before starting the oscillation operation, the band control unit 50 determines the most suitable one of the plurality of frequency bands as the frequency band to be used in the VCO 1. An outline of the operation of the band controller 50 is shown below.

(Step 1) Investigation (measurement) and storage of the oscillation frequency of each band of the VCO When the power of the device incorporating the frequency synthesizer is turned on, the band control unit 50 first starts the oscillation frequency ( (Division ratio) is investigated and the result is stored. More specifically, the fixed voltage V1 is applied to the VCO 1, the oscillation frequency (frequency division ratio) is measured for some predetermined bands of the VCO 1, and the measurement result is stored in the storage circuit 11.

  Thereafter, the oscillation frequency (frequency division ratio) is received from the PLL control circuit 14, and the stored oscillation frequency (frequency division ratio) of each band is referred to determine one band to be operated. An oscillation operation is performed in the determined band. More specifically, the following two operations are performed.

(Step 2) Selection of initial band The division ratio setting value from the PLL control circuit 14 is compared with each of the division ratio setting values stored for each band, and the division ratio setting from the PLL control circuit 14 is set. One band having a frequency division ratio close to is selected as the “initial band”.

(Step 3) Optimal Band Setting Thereafter, the frequency band of VCO 1 is set to the selected initial band, a fixed voltage V 1 is applied to VCO 1, and the oscillation frequency on the initial band is measured. An error between the measured oscillation frequency and the reference frequency is detected, and an optimum band actually used for the oscillation operation is selected based on the error. Then, the VCO 1 oscillates in the selected band.

  Hereinafter, details of the operation of the band control circuit 50 will be described for each of the above steps.

2.2 Investigation (Measurement) and Storage of Oscillation Frequency of Each VCO Band This processing is mainly realized by the frequency investigation unit 10 in the band control circuit 50. FIG. 3 is a block diagram of the frequency examining unit 10 in the present embodiment, and FIG. 4 is an operation flowchart of the frequency examining unit 10.

  In FIG. 3, the frequency investigation unit 10 includes counters 101 and 102, a D flip-flop 103, a division ratio switching circuit 104, a determination number counter 106, a reset generation unit 105, a VCO control circuit 107, a SW control circuit 108, and storage data generation. A circuit 109 is included.

  The counter 101 counts the output signal fref of the reference frequency divider 5, and the counter 102 counts the output signal fdiv of the counter 3. The counter 101 and the counter 102 count the same number. The outputs of the counter 101 and the counter 102 are at the L level (hereinafter referred to as “L”) at the time of reset, but become the H level (hereinafter referred to as “H”) at the end of the counting.

  The determination number counter 106 detects the end of the division ratio determination operation based on the output signal CNTref of the counter 101, counts the number of times the end is detected, and outputs the result as a determination number signal. The determination number signal corresponds to the variable j in the flowchart of FIG.

  The frequency division ratio switching circuit 104 determines the increase / decrease amount ΔMn of the frequency division ratio based on this determination number signal (details of the increase / decrease amount ΔMn will be described later).

  The VCO control circuit 107 compares the output of the determination number counter 106 with the determination reference value, and when the determination number reaches the determination reference value, the VCO control circuit 107 determines that the frequency investigation of one band is completed, and the frequency of the next band In order to investigate this, a control signal (VCO control signal 1) for switching the band of the VCO 1 is generated.

  The stored data generation circuit 109 detects that the frequency investigation of one band has been completed when the number of determinations reaches the determination reference value, and stores it from the frequency division ratio setting 2 and the VCO control signal 1 at that time. Data is generated and stored in the storage circuit 11.

  The SW control circuit 108 detects that the frequency is being investigated, and generates a SW control signal 1 and a SW control signal 3 for switching the switch 9 and the switch 18.

  The reset generation unit 105 generates a reset signal 1. The reset signal 1 resets the counters 3, 101, 102 and the prescaler 2 at the start of the division ratio comparison operation, and cancels the reset in synchronization with the output signal fref of the reference frequency divider 5 to thereby increase the accuracy of the comparison operation. To improve.

In general, in order to accurately know the oscillation frequency of the VCO, it is necessary to count the number of clocks of the VCO for one second with a counter or count the number of clocks of the VCO for a predetermined period and convert it to a frequency of one second. is there. However, this requires a relatively complicated calculation. In this embodiment, for each band, the frequency division ratio when the frequency fr of the reference signal fref becomes equal to the frequency fd of the comparison signal fdiv is detected and recorded, and the recorded frequency division ratio is supplied from the outside. The band to be operated by the VCO 1 is determined by comparison with the frequency division ratio setting. According to this method, it is possible to easily calculate which band should be operated. Note that the following relationship holds among the division ratio M to be obtained, the frequency fr of the reference signal fref, and the VCO output fvco.
fvco = fr × M
Hereinafter, the operation of the frequency examining unit 10 will be described with reference to FIG.

  First, the switch 9 is switched, and the predetermined voltage V1 is connected to the loop filter 8 (S11). A fixed voltage V1 is applied to the control terminal of the VCO 1 and waits until the VCO 1 oscillates stably at a constant frequency (S12).

  A variable i designating the band to be investigated is set to 1 (S13). The investigation target band is set to band i (S14). A variable j indicating the number of determinations is set to 1 (S15).

  In this state, the frequency division ratio switching circuit 104 sets a predetermined frequency division ratio M′1 (S16).

  Then, the resetting of the counter 101 and the counter 102 is canceled at the same time, the counting of the reference frequency signal fref and the comparison frequency signal fdiv is started, and the frequency is measured (S17). The outputs of the counter 101 and the counter 102 are “L” at the time of resetting, but become “H” at the end of counting. To the D flip-flop 103, the signal CNTref is connected to the CK input, and the signal CNTdiv is connected to the D input. When the counting of the counter 101 is completed, the signal CNTref changes from “L” to “H”, so that the value of CNTdiv is output from the D flip-flop 103 as the signal Judge. Thereby, the measurement for one time is complete | finished.

  Subsequently, the frequency is determined based on the signal Judge (S17). When the signal Judge is “L”, it means that the counter 102 is still counting when the counter 101 finishes counting. That is, the frequency fd of the output signal fdiv of the counter 3 is lower than the frequency fr of the reference signal fref from the reference frequency divider 5 (fd <fr), and at this time, fvco = fd × M′1 holds. It can be determined that M <M′1. Similarly, when the signal Judge is “H”, it can be determined that M> M′1.

  As can be seen from the above, the change of the signal CNTref from “L” to “H” means the end of one frequency division ratio measurement operation and determination operation. When the end of one frequency division ratio determination operation is detected by the signal CNTref, the frequency division ratio switching circuit 104 increases or decreases the frequency division ratio according to the resulting signal Judge (S18).

  When one frequency division ratio determination operation is completed, the reset generation unit 105 resets the counter 101 and the counter 102 and starts the next frequency division ratio determination operation.

  An increase / decrease amount of the frequency division ratio will be described. The first increase / decrease amount ΔM1 is set to a predetermined positive value. From the second time onward, the nth increase / decrease amount ΔMn is a positive value smaller than the value ΔMn−1 increased or decreased n−1. An increase / decrease in the frequency division ratio will be described with a specific example.

  First, it is assumed that the frequency division ratio in the first frequency division ratio determination operation is M′1, the determination result (S17), and the signal Judge is “H”. At this time, since the frequency division ratio M to be obtained is M′1 <M, the frequency division ratio is increased in the second frequency division ratio determination operation (S18). In the second frequency division ratio determination operation, the frequency division ratio M′2 = M′1 + ΔM1 is set (S16). As a result of the second determination (S17), if the signal Judge is “L”, the division ratio M to be obtained is M <M′2. Together with the first frequency division ratio determination result, it can be seen that M′1 <M <M′2. Thus, the frequency division ratio M is obtained with an accuracy of ΔM1.

  The third determination is performed as the frequency division ratio M′3 = M′3−ΔM2 because the signal Judge is “L” in the second frequency division ratio determination result. Here, 0 <ΔM2 <ΔM1.

  If the signal Judge is “L” as a result of the third determination, the division ratio M to be obtained is M <M′3, and together with the first and second division ratio determination results, M ′ It can be seen that 1 <M <M′3 (<M′2). In the third division ratio determination, it can be seen that M is obtained with an accuracy of ΔM2, and the division ratio M is obtained with better accuracy than the second time.

  The frequency division ratio determination is repeated until the required accuracy is obtained as described above, that is, until the increase / decrease amount ΔMn is equal to or less than a predetermined value (S19, S20). Thereby, the division ratio Mi to be obtained is obtained. The nth increase / decrease amount ΔMn can be efficiently obtained by setting it to 1/2 of the value ΔMn−1 increased / decreased at the n−1th time.

  Further, since the frequency division ratio is determined by comparing the frequency of the output fref of the reference frequency divider 5 and the output fdiv of the counter 3, the pulse swallow frequency divider 20 composed of the prescaler 2 and the counter 3 includes: Even if the frequency division ratio of the output signal changes instantaneously, such as the frequency divider used in a generally known fractional-N frequency synthesizer, Judgment can be made. This is not a problem even if the above-mentioned nth increase / decrease amount ΔMn is a fraction, that is, the division ratio M to be obtained can be obtained with high accuracy.

  Further, if the prescaler 2 having a reset and the counter 3 are used, the phases of the signal fref and the signal fdiv can be aligned by releasing these reset signals in synchronization with the signal fref at the start of the division ratio determination operation. Therefore, the division ratio M to be obtained can be obtained with high accuracy.

  A similar investigation is performed for each of the predetermined bands of the VCO 1 in this way, and the obtained frequency division ratio Mi value is recorded in the storage circuit 11 (S21, S22, S23). Note that it is sufficient to investigate and record the value of the frequency division ratio Mi for only some predetermined bands, and it is not always necessary to investigate all the bands of the VCO 1. The reason for this will be described later. When all the frequencies of the bands to be recorded have been recorded, the frequency division ratio determining operation is terminated and the mode is shifted to the idle mode.

  In the above description, when the count of the counter 101 is finished, the magnitude relationship between the frequency fd of the output signal fdiv and the frequency fr of the reference signal fref from the reference frequency divider 5 is determined from the state of the counter 102. Based on the state of the counter 101 at the end of the counting of the counter 102, the magnitude relationship between these frequencies can also be determined. For this purpose, in the D flip-flop 103, the signal CNTref is connected to the D input, and the signal CNTdiv is connected to the CK input.

  As described above, the frequency synthesizer first investigates and records the oscillation frequency (frequency division ratio) at the predetermined voltage V1 for a predetermined band of the VCO 1 when the power is turned on. Thereafter, according to the division ratio setting from the external PLL control circuit 14, before starting the original oscillation operation of the frequency synthesizer, the stored oscillation frequency (frequency division ratio) of each band is used. Set the optimal band. The optimum band setting operation for the VCO 1 will be described below.

2.3 Initial Band Selection In order to obtain the optimum band, first, one band is selected as the initial band using the frequency division ratio setting (frequency) stored in the storage circuit 11.

  In the frequency synthesizer of this embodiment, the VCO 1 can be phase-locked in a predetermined frequency range (from frequency fH to fL) even if there is an element variation during manufacturing and an environmental change such as temperature or power supply voltage. It is assumed that the oscillation frequency fluctuation is designed to be within the adjacent A bands with respect to environmental changes such as power supply voltage. This is because, when VCO 1 has N bands, if band X is selected under a certain environment and oscillates at oscillation frequency f, band (X-A) and band (X −A + 1)... Band X... Means that oscillation can be performed at the frequency f in any of the band (X + A-1) and the band (X + A). Here, 1 ≦ X−A, X + A ≦ N and 2A + 1 <N. In this case, the initial band (band X) may be selected from band A + 1 to band NA.

  When the initial band (referred to as band X) is determined, the frequency adjustment unit 13 causes (2A + 1) bands (band (X-A), band (X-A + 1)) before and after the initial band (band X). ),..., Band X,..., Band (X + A-1), band (X + A)) are selected for phase locking at the desired frequency (frequency division ratio) indicated by the PLL control circuit 14. The

  The initial band selection is mainly executed by the initial band selection circuit 12. FIG. 5 shows the configuration of the initial band selection circuit 12.

  The initial band selection circuit 12 includes comparators CMP (A + 1),... That compare the frequency division ratio setting set in the counter 3 from the PLL control circuit 14 with the frequency division ratio stored in the storage circuit 11, and the adjacent 2 EOR gate EOG (A + 1),... For calculating exclusive OR of outputs between two comparators. Here, in order to obtain the result by the initial band selection circuit 12 in a short time, as shown in FIG. 5, the number of comparators (CMP (A + 1) to CMP (NA) corresponding to the stored frequency band of the VCO 1 is obtained. ) And (N-2A-1) EOR gates (EOG (A + 1) to EOG (NA-1)) may be provided. According to such a circuit configuration, only the output of the EOR gate at the boundary where the comparison result changes from “L” to “H” becomes the high level, so the band corresponding to the output of the EOR gate is selected as the initial band. If the outputs of the EOR gates EOG (A + 1),... Are all “L”, the band (A + 1) is selected as the initial band, and if all the outputs are “H”, the band (NA) may be selected. If the processing time is sufficient, a comparator, a latch circuit that holds the determination result, and an EOR gate may be provided one by one and operated in a time-sharing manner. Thus, the initial band selection circuit 12 selects a band having a frequency division ratio close to the frequency division ratio setting from the PLL control circuit 14 as the initial band.

  As described above, since the initial band (band X) may be selected from band A + 1 to band NA, the oscillation frequency of VCO 1 should be investigated and stored only for those bands. I know it ’s good. If the desired frequency is a frequency lower than the lowest frequency band (A + 1) among the recorded frequencies, the initial band may be the band (A + 1). This is because if the initial band is (A + 1), the frequency adjustment unit 13 performs band selection in the range from band 1 to band (2A + 1). Similarly, if the desired frequency is higher than the highest frequency band (A + 1) among the recorded frequencies, the initial band may be the band (NA). Therefore, it can be understood that the frequency investigation unit 10 and the storage circuit 11 may investigate and record the band (A + 1 to band (NA)), and the oscillation frequency is investigated in ascending order from band 1 having the lowest frequency. Sometimes, if the oscillation frequency of a certain band becomes higher than fH, it is not necessary to investigate a band having a higher frequency than this band, because a band having a higher frequency cannot be the initial band. For the same reason, when the oscillation frequency is investigated in descending order from the highest frequency band N, when the oscillation frequency of a certain band becomes lower than fL, it is not necessary to investigate the frequency any more.

2.4 Setting Optimal Band After selecting the initial band, the frequency adjustment unit 13 determines the optimum band that is actually used for the oscillation operation and sets it to VCO1. The frequency adjustment unit 13 selects one band that can be phase-locked at a desired frequency from the initial band (band X) and (2A + 1) adjacent bands before and after the initial band.

  FIG. 6 is a block diagram of the frequency adjustment unit 13. The frequency adjustment unit 13 includes counters 601, 602, a time difference detection unit 603, a time difference determination unit 604, a VCO control circuit 605, and a SW control circuit 606.

  First, when the frequency division ratio setting 1 is newly set from the PLL control circuit 14, the initial band information is input to the VCO control circuit 605 from the initial band selection circuit 12. The VCO control circuit 605 oscillates the VCO 1 in the band selected as the initial band. At this time, the SW control circuit 606 switches the switch 9 so that the predetermined voltage V1 is supplied to the VCO1, and oscillates the VCO1 at a constant frequency.

  Thereafter, an adjustment operation of the oscillation frequency is performed. The counters 601 and 602 are simultaneously reset by the time difference determination unit 604, and respectively count the signal fref and the signal fdiv by a certain number (N). The counters 601 and 602 output signals CNTref2 and CNTdiv2 to the time difference detection unit 603 at the end of counting, respectively.

The desired frequency (determined by dividing ratio setting 1) is f, the dividing ratio is Mlock, the oscillation frequency of VCO1 is fv, the elapsed time from reset release of counter 601 to the end of counting is counted from CNTref2, and the counter 602 is counted from reset release. When the elapsed time until the end is CNTdiv2, the following relationship is established.
CNTref2 = N x Mlock x f
CNTdiv2 = N × Mlock × fv

  Therefore, by detecting the time difference between the elapsed time CNTref2 and the elapsed time CNTdiv2 by the time difference detection unit 603, the difference between the desired frequency f and the oscillation frequency of the VCO 1 can be known. Note that the frequency difference between the signal f and the signal fv can be detected more accurately by releasing the reset of the counter 3 and the prescaler 2 in synchronization with the signal fref. The time difference detection unit 603 detects CNTref2 and CNTdiv2, and counts the time difference between the signals with the output signal fck of the prescaler 2. Although the time difference is counted using the output signal fck of the prescaler 2 here, the output signal fosc of the TCXO 4 may be used instead.

  The VCO control circuit 605 predicts the optimum band that can be locked at the desired frequency f based on the time difference detection result and the oscillation frequency data of the VCO 1 stored in the storage circuit 11, and operates the VCO 1 in the predicted band. Switch bands. The prediction of the optimum band is performed as follows as an example when A = 2.

  First, the actual oscillation frequency of VCO 1 in the initial band (band X) is estimated from the time difference detection result and the oscillation frequency data of VCO 1 stored in storage circuit 11. If the estimated initial band oscillation frequency is higher than the desired frequency f and the frequency difference is within one band, the band one band lower (band X-1) is estimated as the optimum band. If the estimated initial band oscillation frequency is lower than the desired frequency f and the frequency difference is within one band, the band X is estimated as the optimum band. If the analog oscillation frequency of the initial band is lower than the desired frequency f and the frequency difference is not less than 1 band and not more than 2 bands, the upper band (band X + 1) is estimated as the optimum band. If the analog oscillation frequency of the initial band estimated is lower than the desired frequency f and the frequency difference is 2 bands or more, the band (band X + 2) in two stages is estimated as the optimum band.

  The above operation is a single frequency adjustment operation.

  The time difference determination unit 604 determines whether or not the desired frequency f can be locked in the current band of the VCO 1 based on the time difference detection result, the time difference detection accuracy, and the band prediction accuracy. When it is determined that the lock is impossible, the reset signal 2 is output again. Then, the frequency adjustment operation is performed again with the new band of VCO 1 after switching, and is repeated until it is determined that the lock is possible.

  As described above, the optimum band is determined, and the determined optimum band is set in the VCO 1 to oscillate.

  In the present embodiment, the oscillation frequency of each band of the VCO 1 is measured and stored, and then the oscillation frequency of the VCO 1 is measured again immediately before the start of the oscillation operation to obtain the optimum band to be finally used. . As a result, even if the operating environment changes from the time when the measured oscillation frequency of each band of the VCO 1 is stored until the start of the oscillation operation, the optimum band is accurately obtained without being affected by the change. Can do.

  Since the frequency adjustment operation is performed after the frequency division ratio setting of the desired frequency is transmitted from the PLL control circuit 14, the time during which the frequency adjustment is operating is added to the lockup time. In the conventional frequency adjustment circuit, since the accuracy of predicting a lockable band is low, the number of frequency adjustment operations increases, and as a result, the lock-up time becomes long. On the other hand, in the present invention, the prediction accuracy of the lockable band can be increased by the following two ideas, and the lock-up time can be shortened.

  First, as described above, the frequency adjustment operation is performed in the band X which is the initial band. As a result, the VCO 1 is designed to oscillate in a total of 2A + 1 bands of the initial band X and its adjacent A bands, so that it is possible to predict up to 2A + 1 lockable bands. Become.

  Secondly, the oscillation frequency of each band is stored. If the stored oscillation frequency of the band X and the current oscillation frequency of the band X estimated from the time difference detection result are known, the current frequency of the other band is determined from the stored oscillation frequency of the other band (for example, the band X + 1). The oscillation frequency can be accurately predicted.

  Thus, according to the present invention, the frequency adjustment operation can be completed in a short time, and the lockup time can be shortened. This makes it possible to obtain a frequency synthesizer with good C / N characteristics for the reasons described above.

3. Application to Radio Communication System FIG. 7 shows an example in which the frequency synthesizer of this embodiment is applied to a radio communication system. With the frequency synthesizer of the present embodiment, it is possible to realize a wireless communication system that is small, inexpensive, and has good communication quality. The example shown in FIG. 7 shows a schematic configuration for a general direct conversion reception system including an antenna 901, a low noise amplifier 902, mixers 903 and 904, a 90 ° phase changer, a frequency synthesizer 800, and a baseband circuit 905. It is a figure. As the frequency synthesizer 800, the above-described frequency synthesizer is used. Needless to say, the frequency synthesizer of the present embodiment can also be applied to a wireless communication system other than the direct conversion method and other electronic devices using the frequency synthesizer.

  The present invention is useful for a frequency synthesizer including a VCO having a plurality of oscillation frequency bands, and for various electronic devices including a frequency synthesizer, for example, a wireless communication system.

The block diagram of the frequency synthesizer of embodiment of this invention Diagram showing the relationship between control voltage and oscillation frequency in a VCO having a single oscillation frequency band Diagram showing the relationship between control voltage and oscillation frequency in a VCO with multiple oscillation frequency bands Block diagram of frequency survey section Operation flow chart of frequency survey section Block diagram of initial band selection circuit Block diagram of frequency adjustment unit Block diagram of a wireless communication system using the frequency synthesizer of this embodiment

Explanation of symbols

1 Voltage controlled oscillator (VCO)
2 Prescaler 3 Counter 4 TCXO
DESCRIPTION OF SYMBOLS 5 Reference frequency divider 6 Phase comparator 7 Charge pump 8 Loop filter 9, 18 Switch 10 Frequency investigation part 11 Memory circuit 12 Initial band selection circuit 13 Frequency adjustment part 14 PLL control circuit 20 Pulse swallow frequency divider

Claims (8)

A voltage-controlled oscillator capable of oscillating in a plurality of frequency bands and oscillating and outputting a signal having a frequency corresponding to a voltage applied to the control voltage terminal;
A comparative frequency divider that outputs a signal obtained by dividing the frequency of the voltage controlled oscillator;
A reference divider for dividing the frequency of the reference signal;
A phase comparator that compares the phase of the output signal of the comparison frequency divider and the output signal of the reference frequency divider and outputs the phase difference;
A charge pump for converting the output signal of the phase comparator into a voltage;
A loop filter for smoothing the output voltage of the charge pump and applying it to a control voltage terminal of the voltage controlled oscillator;
A band control circuit for setting the frequency band of the voltage controlled oscillator during oscillation operation,
The band control circuit includes:
Frequency investigation means for measuring the oscillation frequency for each of a predetermined number of frequency bands of the voltage controlled oscillator;
Storage means for storing the oscillation frequency of each frequency band measured by the frequency investigation means;
Initial band selection means for selecting one frequency band from each oscillation frequency band in which the oscillation frequency is stored in the storage means based on the frequency given from the PLL control circuit;
The oscillation frequency of the voltage controlled oscillator in one frequency band selected by the initial band selection means is measured, one frequency band used for the oscillation operation is determined based on the measured oscillation frequency, and the determined frequency band A frequency synthesizer comprising: frequency adjusting means for setting the voltage controlled oscillator to the voltage controlled oscillator.   The frequency examining means includes a first counter that counts a predetermined number of output signals of the reference frequency divider, and a second counter that counts a predetermined number of output signals of the comparison frequency divider, The end of counting of the first counter is detected, and the oscillation frequency of the voltage controlled oscillator is measured based on the state of the second counter at that time and the division ratio of the comparison frequency divider. Item 2. A frequency synthesizer according to Item 1.   The frequency examining means includes a first counter that counts a predetermined number of output signals of the reference frequency divider, and a second counter that counts a predetermined number of output signals of the comparison frequency divider, 2. The end of counting of the second counter is detected, and the oscillation frequency of the voltage controlled oscillator is measured based on the state of the first counter at that time and the division ratio of the comparison frequency divider. The frequency synthesizer described in 1.   The initial band selection unit includes a comparator that compares a frequency given from the PLL control circuit with each oscillation frequency stored in the storage unit and generates a signal for designating the one frequency band. The frequency synthesizer according to claim 1.   The frequency adjusting means applies a fixed voltage to the voltage controlled oscillator to oscillate in a frequency band selected by the initial band selecting means, and an oscillation frequency obtained at that time, an error between the oscillation frequency and a reference frequency, The frequency synthesizer according to claim 1, wherein one frequency band used for the oscillation operation is determined based on   The frequency adjusting unit is configured to select another frequency based on the frequency difference between the output signal of the reference frequency divider and the output signal of the comparison frequency divider and the oscillation frequency of the frequency band stored in the storage unit. 2. The frequency synthesizer according to claim 1, wherein an oscillation frequency of the band is predicted.   A wireless communication system comprising the frequency synthesizer according to claim 1. A method for controlling a frequency synthesizer comprising a voltage controlled oscillator having a plurality of frequency bands,
In a state where a predetermined voltage is applied to the voltage controlled oscillator, the oscillation frequency of the voltage controlled oscillator is measured for each of a predetermined number of frequency bands,
Store the measured oscillation frequency of each frequency band,
Based on the frequency given from the PLL control circuit, one frequency band is selected from each oscillation frequency band in which the oscillation frequency is stored,
An oscillation frequency of the voltage controlled oscillator in the selected one frequency band is measured in a state where a predetermined voltage is applied to the voltage controlled oscillator, and based on the measured oscillation frequency and an error between the oscillation frequency and the reference frequency. Determine one frequency band to be used for oscillation operation,
A method for controlling a frequency synthesizer, wherein the determined frequency band is set in the voltage controlled oscillator.

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