JP2005268614A - Integrated circuit in which latch-up effect can be avoided - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit which easily prevents latch-up effect. <P>SOLUTION: The integrated circuit is provided with: an internal circuit which is formed on a substrate and has an SCR; an ESD protective element which is formed on the substrate and connected to a connection pad; an active region which is formed on the substrate and connected to the connection pad; a first diversion diode whose anode is connected to the connection pad and cathode is connected to a first power source; a second diversion diode whose cathode is connected to the connection pad and anode is connected to a second power source; and a guard ring surrounding the first diversion diode and the second diversion diode. Length from the first diversion diode and the second diversion diode to the internal circuit, the ESD protective element and the active region is at least 150 μm. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an integrated circuit, and more particularly to an integrated circuit that can prevent a latch-up effect.

  The latch-up effect is related to the reliability of the CMOS-IC, and the parasitic PNPN structure, that is, the silicon control rectifier (SCR) is turned on and becomes a low resistance state. Say. When the latch-up effect occurs, a parallel resistance having a low resistance value is formed between the power supply wiring and the ground, and a large power supply current flows through the power supply wiring. If this current is not limited, logic errors and circuit malfunctions may occur, or the IC may be unable to recover. Unfortunately, PMOS P +, NMOS NWELL, P substrate, and N + naturally form a PNPN structure, and a parasitic SCR of the PNPN structure is inevitably formed by the CMOS manufacturing process.

  There are various factors that cause the latch-up effect in the CMOS, and the revealed factors are the substrate current due to the hot carrier effect during IC operation, and / or the parasitic diode due to the noise present in the connection pad (pad). Forward current.

  FIG. 1 is a circuit diagram showing a conventional integrated circuit.

  Most of the substrate current due to the latch-up effect is injected through a parasitic diode Dp formed in an electrostatic discharge (ESD) protection circuit 14 on the wafer. The parasitic SCR 12 is turned on by conduction of transistors including the parasitic P + / NWELL / P substrate and the NWELL / P substrate / N +. If the voltage Vbe between the base and the emitter is higher than 0.7V, the above two transistors are turned on. This voltage Vbe is determined by the voltage drop across the resistance between NWELL and the P substrate. Therefore, in order to prevent the occurrence of the latch-up effect, it is necessary to reduce the parasitic resistance between the NWELL and the P substrate or the gain of the parasitic PNP transistor and the parasitic NPN transistor.

The conventional latch-up effect prevention method has the following drawbacks.
1. When the latch-up effect is prevented by the semiconductor manufacturing technology, the epitaxial CMOS has a relatively small parasitic resistance between the NWELL and the P substrate, and trench isolation and SOI (Silicon-On-Insulator) are parasitic PNP transistors. And weaken the coupling of the parasitic NPN transistor.

However, this process complicates the manufacturing process and increases the manufacturing cost.
2. Guard rings are often used to prevent latch-up effects by layout techniques. As a result, the latch-up effect prevention value can be increased, coupling between the parasitic bipolar transistors can be removed, and injected carriers can be collected before the latch-up effect occurs in the internal circuit of the CMOS. In other words, the contact ring increases the contact between the NWELL and the P substrate, the distance between the impurity region and the contact can be shortened, and the parasitic resistance value of the NWELL and the P substrate can enhance the latch-up effect. Can be reduced.

  However, the protective ring occupies the layout area of the wafer, increases the size of the wafer, and if there is a layout limitation, it may be difficult to provide the protective ring or increase the number of contacts.

There is also a method of increasing the distance between the I / O injector and the internal circuit. However, this greatly increases the overall size of the wafer and is often limited in use.
3. When the latch-up effect is prevented by circuit technology, the latch-up effect detection circuit proposed by Shen in Patent Document 1 measures the change in the voltage reference of NWELL and the P substrate, and when the latch-up effect occurs, NWELL Return the voltage reference of the P substrate to the original value.

  However, this method complicates the circuit and increases the layout space.

Therefore, it is possible to easily prevent the latch-up effect, and in particular, an integrated circuit that can prevent the latch-up effect even when a protective ring cannot be provided near the internal circuit or the number of contacts cannot be increased. Required.
US Pat. No. 5,942,932

  An object of the present invention is to provide an integrated circuit that can easily prevent a latch-up effect.

  In order to achieve the above object, an integrated circuit of the present invention is formed on a substrate, an internal circuit having an SCR, an ESD protection element formed on the substrate and connected to a connection pad, formed on the substrate, The active region connected to the connection pad, the anode connected to the connection pad, the first shunt diode connected to the first power supply, the cathode connected to the connection pad, and the anode connected to the second power supply A second shunt diode, and a protection ring surrounding the first shunt diode and the second shunt diode, the first shunt diode and the second shunt diode, the internal circuit, the ESD protection element, and the active The distance to the region is 150 μm or more.

  According to the present invention, by providing a shunt diode and shunting the substrate current, the influence of the latch-up effect generation source is weakened and the latch-up effect is generated without changing the layout of the internal circuit and the ESD protection element. Can be reduced.

  In order to make the above objects, features and advantages of the present invention clearer, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  There are various factors that cause the latch-up effect in the CMOS, and the revealed factors are the substrate current due to the hot carrier effect during IC operation, and / or the parasitic diode due to the noise present in the connection pad (pad). Forward current. Further, most of the substrate current due to the latch-up effect is injected through a parasitic diode formed in the ESD protection circuit on the wafer.

  The present invention does not employ a passive method of preventing the occurrence of the latch-up effect by blocking the conduction of the parasitic SCR in the prior art. The feature of the present invention is that the layout of the original internal circuit and the ESD protection element is not changed, a shunt diode is added as a path for shunting the substrate current, the influence of the source of the latch-up effect is weakened, and the latch-up effect This is to reduce the probability of occurrence.

  FIG. 2 is a circuit diagram showing the integrated circuit of the present invention.

  The integrated circuit of the present invention is formed on the substrate 26, the internal circuit 20 having the SCR 12, the ESD protection element 14 formed on the substrate 26 and connected to the connection pad 16, the substrate 26, and the connection pad 16. The active region 18 connected to, the anode is connected to the connection pad 16, the cathode is connected to the first power supply Vdd, the shunt diode D1, the cathode is connected to the connection pad 16, and the anode is connected to the second power supply Vss. And a protective ring 22 surrounding the shunt diode D1 and the shunt diode D2. An external circuit 24 is formed on the substrate 26.

  The distance from the shunt diodes D1 and D2 to the ESD protection element 14 connected to the internal circuit 20 and the connection pad 16, and the distance from the shunt diodes D1 and D2 to the active region 18 is 150 μm or more.

  When an excessive current, for example, a current exceeding a predetermined value flows through the connection pad 16, the shunt diodes D1 and D2 serve as additional current paths. Therefore, the substrate current flowing through the ESD protection element 14 is effectively reduced, and the internal circuit 20 The latch-up effect due to the parasitic SCR 12 inside is prevented.

  Here, the trigger level of the latch-up effect is the maximum current that flows from the connection pad 16 into the internal circuit 20 before the latch-up effect occurs. According to Kirchhoff's Law, when the shunt diodes D1 and D2 exist, the current injected from the connection pad 16 is shared by the ESD protection element 14 and the shunt diodes D1 and D2. Therefore, the substrate current injected from the ESD protection element 14 into the internal circuit 20 is reduced. In other words, the trigger level causing the latch-up effect increases as the number of shunt diodes increases. That is, the present invention reduces the probability that the latch-up effect will occur by increasing the trigger level that causes the latch-up effect.

  In the present invention, the shunt diodes D1 and D2 can be installed in a free area away from the connection pad 16. As a result, the latch-up effect can be effectively prevented even in a special case where the layout space near the connection pad 16 is insufficient and the protective ring cannot be installed.

  The shunt diodes D1 and D2 do not conduct when the circuit operates normally, but do conduct when noise, an overshoot voltage, an undershoot current, or the like is applied to the connection pad 16.

  In the present invention, as the shunt diodes D1 and D2, a low voltage diode or a high voltage diode that has a double diffused drain structure and increases a breakdown voltage can be used.

  Further, as the shunt diodes D1 and D2, parasitic diodes formed in the added ESD protection element 14 may be used. For example, it may be an NMOS or PMOS transistor whose gate electrode is connected to the ground, connected to the RC circuit, or floating connected.

  In order to prevent the latch-up effect due to the parasitic SCR from occurring in the external circuit 24 adjacent to the shunt diodes D1 and D2, the distance X3 between the shunt diodes D1 and D2 and the external circuit 24 not connected to the connection pad 16 is Preferably, the thickness is 80 μm or more.

  Further, a protection ring 22 surrounding the shunt diodes D1 and D2 is provided. Thereby, the carriers injected from the shunt diodes D1 and D2 are collected and removed before causing a latch-up effect of other parasitic SCRs in the vicinity, for example, the parasitic SCR in the external circuit 24. When the protection ring 22 is provided, the distance X3 between the shunt diodes D1 and D2 and the external circuit 24 is preferably 40 μm or more.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to this embodiment, and all modifications to the present invention are within the scope of the present invention unless departing from the spirit of the present invention.

It is a circuit diagram which shows the conventional integrated circuit. It is a circuit diagram which shows the integrated circuit of this invention.

Explanation of symbols

12 SCR
14 ESD protection element 16 Connection pad 18 Active area 20 Internal circuit 22 Protection ring 24 External circuit 26 Substrate

Claims (6)

An internal circuit formed on the substrate and having a silicon controlled rectifier;
An active region formed on the substrate and connected to the connection pad; and a shunt diode connected to the connection pad;
Have
The distance from the shunt diode to the internal circuit and the active region is 150 μm or more;
When a current greater than or equal to a predetermined value flows through the connection pad, the shunt diode forms a shunt path to avoid a latch-up effect in the silicon controlled rectifier element;
Integrated circuit. A guard ring surrounding the shunt diode;
The integrated circuit according to claim 1. The integrated circuit according to claim 1, wherein the shunt diode is a diode having a double diffusion drain structure. The shunt diode is a parasitic diode;
The integrated circuit according to claim 1. An internal circuit formed on the substrate and having a silicon controlled rectifier;
An electrostatic discharge protection element formed on the substrate and connected to the connection pad;
Active areas formed on the substrate and connected to the connection pads;
A first shunt diode having an anode connected to the connection pad and a cathode connected to a first power source;
A second shunt diode with a cathode connected to the connection pad and an anode connected to a second power source; and a guard ring surrounding the first shunt diode and the second shunt diode;
Have
A distance from the first shunt diode and the second shunt diode to the internal circuit, the electrostatic discharge protection element, and the active region is 150 μm or more;
Integrated circuit. The first shunt diode and the second shunt diode are diodes having a double diffused drain structure;
The integrated circuit according to claim 5.

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