JP2005260652A - Signal processing circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a difference in power consumption from occurring between when a logical level is 0 and when the logical level is 1. <P>SOLUTION: A signal conversion circuit 21 converts an Lo or Hi signal bit corresponding to a logical bit 0 or 1 into an LoHi or HiLo two-bit signal bit, respectively and outputs the two-bit signal bit to an encryption processing circuit 22. Then, in the encryption processing circuit 22 of a stage following the signal conversion circuit 21, a one-bit logic is represented by a two-bit signal bit. The encryption processing circuit 22 performs DES (data encryption standard) encryption processing with the inputted LoHi or HiLo two-bit signal bit as one logical bit. This invention is applicable, for example, to an IC chip that performs encryption processing by a bit operation such as DES. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal processing circuit and method, and more particularly to a signal processing circuit and method for preventing a difference in power consumption from occurring due to a difference in logic level in a circuit, for example.

  There is a cryptographic processing circuit that performs cryptographic processing using an algorithm (encryption method) such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), or RSA (Rivest Shamir Adleman). In such a cryptographic processing circuit, in general, the signal level is Lo (Low level) with respect to 0 which is one of 0 and 1 which is two logic levels represented by one logic bit. The signal bit is assigned to the other 1 with a signal level of Hi (High level), and signal processing (encryption processing) is performed.

  In the MOS -IC (Metal Oxide Semiconductor -Integrated Circuit) that constitutes the cryptographic processing circuit, the power consumption of the cryptographic processing circuit by Hi or Lo signal bits should be essentially the same, but in reality, A slight difference in the power consumption of the cryptographic processing circuit is caused by the Hi and Lo signal bits due to leakage current and the like. Further, when the signal bit transitions from Hi to Lo or from Lo to Hi, a large amount of current consumption flows in the circuit.

  A method (DPA: Differential Power Analysis) that deciphers the key by analyzing the current consumption of the cryptographic processing circuit using the difference in power consumption of the cryptographic processing circuit by the Hi and Lo signal bits has been devised ( For example, Non-Patent Document 1).

P. Kocher, J. Jaffe, B. Jun, "Differential Power Analysis," Advances in Cryptology-Crypto 99 Proceedings, Lecture Notes In Computer Science Vol. 1666, M. Wiener ed., Springer-Verlag, 1999.

  However, the conventional encryption processing circuit has not considered a countermeasure against the above-described method of decrypting the key by analyzing the current consumption of the encryption processing circuit.

  As a countermeasure against this, it is conceivable that the difference in power consumption does not occur in the cryptographic processing circuit regardless of the signal bit (signal level) corresponding to the logical bit.

  The present invention has been made in view of such a situation, and prevents a difference in power consumption from occurring due to a difference in logic level in a circuit.

  In the signal processing apparatus of the present invention, the same number of signal bits Lo and Hi are assigned to one of the two logic levels represented by one logic bit, and the other logic level is assigned to the other logic level. Further, the present invention is characterized by comprising encryption-related processing means for performing encryption-related processing using a signal to which a signal bit having a different permutation of Lo and Hi from a signal bit assigned to one logic level is assigned.

  In the encryption-related processing means, the HiLo signal bit is assigned to one logic level, and the encryption-related processing is performed using a signal to which the LoHi signal bit is assigned to the other logic level. Can be made.

The encryption related processing means can perform encryption related processing using DES (Data Encryption Standard).

  An IC chip can be used.

  It is possible to further provide an assigning means for assigning a HiLo signal bit to one logic level and assigning a LoHi signal bit to the other logic level.

  In the signal processing method of the present invention, the same number of signal bits Lo and Hi are assigned to one of the two logic levels represented by one logic bit, and the other logic level is assigned to the other logic level. Further, the present invention is characterized by comprising a cryptographic-related processing step of performing cryptographic-related processing using a signal to which a signal bit having a different permutation of Lo and Hi from a signal bit assigned to one logic level is assigned.

  In the present invention, the same number of signal bits Lo and Hi are assigned to one of the two logic levels represented by one logic bit, and one of the two logic levels is assigned to the other logic level. Encryption-related processing is performed using a signal to which a signal bit having a different permutation of Lo and Hi from the signal bit assigned to the logic level is assigned.

  According to the present invention, it is possible to prevent a difference in power consumption from occurring due to a difference in logic level in a circuit.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

The signal processing circuit according to claim 1 comprises:
In a signal processing circuit (for example, the cryptographic processing circuit 22 in FIG. 1) that performs cryptographic-related processing related to encryption,
The same number of signal bits Lo and Hi are assigned to one of the two logic levels represented by one logic bit, and the one logic level is assigned to the other logic level. It is provided with cryptographic related processing means (for example, cryptographic processing circuit 22 in FIG. 1) for performing cryptographic related processing using a signal to which a signal bit having a different permutation of Lo and Hi is assigned. .

  According to a fourth aspect of the present invention, there is provided a signal processing circuit comprising an IC (Integrated Circuit) chip (for example, the IC chip 11 of FIG. 1).

  6. The signal processing circuit according to claim 5, wherein an assigning means for assigning a HiLo signal bit to one logic level and assigning a LoHi signal bit to the other logic level (for example, the signal conversion of FIG. 1). Circuit 21).

The signal processing method according to claim 6 comprises:
In a signal processing method of a signal processing circuit that performs encryption-related processing related to encryption,
The same number of signal bits Lo and Hi are assigned to one of the two logic levels represented by one logic bit, and the one logic level is assigned to the other logic level. A cryptographic-related processing step (for example, processing in steps S1 to S3 in FIG. 15) that performs cryptographic-related processing using a signal to which a signal bit having a different permutation of Lo and Hi is assigned. And

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration example of an embodiment of an IC chip 11 that performs cryptographic processing to which the present invention is applied.

  The IC chip 11 in FIG. 1 is a signal processing circuit that performs encryption processing using a predetermined algorithm. Here, it is assumed that the IC chip 11 performs encryption processing by DES, for example.

  The IC chip 11 includes a signal conversion circuit 21 and an encryption processing circuit 22. The signal conversion circuit 21 and the encryption processing circuit 22 are signal processing circuits that process a signal to which a signal bit corresponding to a logical bit is assigned (a signal to which a signal level corresponding to a logical level is assigned).

  The signal conversion circuit 21 receives Lo or Hi (signal level) signal bits corresponding to logical bits of predetermined data to be encrypted. For example, a signal bit with a signal level of Lo is input to the signal conversion circuit 21 as a signal bit corresponding to logical bit 0, and a signal bit with a signal level of Hi is input as a signal bit corresponding to logical bit 1 Entered.

  The signal conversion circuit 21 converts the input Lo or Hi signal bits into 2-bit signal bits of LoHi or HiLo, respectively, and outputs them to the encryption processing circuit 22. Therefore, in the encryption processing circuit 22 subsequent to the signal conversion circuit 21, one logical bit is represented by two signal bits. In other words, two signal bits of LoHi are assigned to a logic bit having a logic level of 0. In addition, a HiLo 2-bit signal bit is assigned to a logic bit having a logic level of 1.

  The cryptographic processing circuit 22 performs DES cryptographic processing using the input two LoHi or HiLo signal bits as one logical bit, and outputs a ciphertext (data) as a result of the cryptographic processing.

FIG. 2 shows input and output signals (input signal and output signal) of the signal conversion circuit 21 of FIG. 1 for data X that can be represented by 2 bits. In FIG. 2, X _(Y) means that the data X is represented in Y-base.

The signal bit of the input signal corresponding to the logical bit of data 0 ₍₁₀₎ (00 ₍₂₎ ) is 2-bit LoLo. When the two LoLo signal bits are input to the signal conversion circuit 21 as an input signal, the signal conversion circuit 21 converts the signal. The LoHiLoHi 4-bit signal bit is output from the signal conversion circuit 21 as an output signal. Is done.

The signal bit of the input signal corresponding to the logical bit of data 1 ₍₁₀₎ (01 ₍₂₎ ) is 2-bit LoHi. When the 2-bit signal bit of LoHi is input to the signal conversion circuit 21 as an input signal, the signal conversion circuit 21 converts the signal, and the 4-bit signal bit of LoHiHiLo is output from the signal conversion circuit 21 as an output signal. Is done.

Similarly, a 4-bit output signal HiLoLoHi is output from the signal conversion circuit 21 for an input signal of the 2-bit signal bit HiLo of data 2 ₍₁₀₎ (10 ₍₂₎ ). For the input signal of the 2-bit signal bit HiHi of the data 3 ₍₁₀₎ (11 ₍₂₎ ), a 4-bit output signal of HiLoHiLo is output from the signal conversion circuit 21.

FIG. 3 shows input and output signals (input signal and output signal) of the signal conversion circuit 21 of FIG. 1 for data X ′ that can be represented by 4 bits. In FIG. 3 as well, X ′ _(Y) means that data X ′ is expressed in Y-base.

The signal bit of the input signal corresponding to the logical bit of data 0 ₍₁₀₎ (0000 ₍₂₎ ) is 4-bit LoLoLoLo. When the four signal bits of LoLo LoLo are input to the signal conversion circuit 21 as an input signal, the signal conversion circuit 21 converts the signal, and the 8-bit signal bit of LoHiLoHiLoHiLoHi is output from the signal conversion circuit 21 as an output signal. Is output.

The signal bit of the input signal corresponding to the logic bit of data 1 ₍₁₀₎ (0001 ₍₂₎ ) is 4-bit LoLoLoHi. When the four signal bits of LoLoLoHi are input to the signal conversion circuit 21 as an input signal, the signal conversion circuit 21 converts the signal, and the 8-bit signal bit of LoHiLoHiLoHiHiLo is output from the signal conversion circuit 21 as an output signal. Is done.

Similarly, an 8-bit output signal of LoHiLoHiHiLoLoHi is output from the signal conversion circuit 21 for an input signal of the 4-bit signal bit LoLoHiLo of data 2 ₍₁₀₎ (0010 ₍₂₎ ). An 8-bit output signal of LoHiLoHiHiLoHiLo is output from the signal conversion circuit 21 for the input signal of the 4-bit signal bit LoLoHiHi of data 3 ₍₁₀₎ (0011 ₍₂₎ ).

Further, the signal conversion circuit 21 performs the same signal conversion on the data 4 _{(10) to} 15 ₍₁₀₎ as shown in FIG.

  As described above, the signal conversion circuit 21 assigns a 2-bit signal bit of LoHi to a logic bit having a logic level of 0, and a 2-bit signal bit of HiLo to a logic bit having a logic level of 1. As a result of the assignment, the encryption processing circuit 22 subsequent to the signal conversion circuit 21 can eliminate the difference in current consumption due to the difference in logic level.

  Next, referring to FIG. 4 to FIG. 6, an EXOR process (exclusive OR; processing for calculating exclusive OR), which will be described later, performed in the cryptographic processing circuit 22 of FIG. The case where it carries out using is demonstrated.

FIG. 4 shows a truth table for EXOR processing of input data x and y. When _(y) of data x _(y) is omitted, data x is represented by a decimal number.

  As shown in FIG. 4, in the EXOR process, when either one of the input data x or y is 1, the process result is 1, and in the other case, the process result is 0.

FIG. 5 illustrates a signal in which the 1-bit signal bit Lo or Hi is assigned to the 1-bit logic bit 0 ₍₂₎ or 1 ₍₂₎ , respectively, like the input signal of the signal conversion circuit 21. The processing result when EXOR processing is performed is shown.

  As shown in FIG. 5, in the EXOR process in which one signal bit is assigned to one logical bit, the signal bit obtained by the EXOR process when one of the signal bits of the input signal is Hi. Becomes Hi, and in other cases, the signal bit obtained by the EXOR processing becomes Lo.

FIG. 6 is intended for a signal in which the 2-bit signal bit LoHi or HiLo is assigned to the 1-bit logic bit 0 ₍₂₎ or 1 ₍₂₎ , respectively, like the output signal of the signal conversion circuit 21. The processing result when EXOR processing is performed is shown.

  As shown in FIG. 6, in the EXOR processing in which 2 signal bits are assigned to 1 logical bit, the signal bit obtained by the EXOR processing when one of the signal bits of the input signal is HiLo. Becomes HiLo, and in other cases, the signal bit obtained by the EXOR processing becomes LoHi.

  FIG. 7 shows a detailed configuration example of the cryptographic processing circuit 22 of FIG.

  As described above, the signal processing circuit 21 receives two signal bits corresponding to one logical bit from the signal conversion circuit 21. Therefore, for example, for data represented by 64 logical bits, the input signal input to the cryptographic processing circuit 22 is a 128-bit signal bit that is twice 64 bits. In other words, for example, when the cryptographic processing circuit 22 performs cryptographic processing in units (blocks) of 64 logical bits, the signal lines in the cryptographic processing circuit 22 are provided for 128 bits. In the following description, it is assumed that one logical bit is processed with two signal bits even if not specifically mentioned. In the following, a value represented by 2 signal bits corresponding to 1 logic bit is referred to as 1-bit bit data.

  In DES, plain text (data) is processed in units of 64 logical bits. Therefore, bit data is input to the cryptographic processing circuit 22 in 64-bit units. That is, the encryption processing circuit 22 receives signal bits of data to be encrypted (plain text) in units of 128 bits.

  The 64-bit bit data (128-bit signal bits) input to the cryptographic processing circuit 22 is input to an IP (Initial Permutation) conversion unit 41.

  The IP conversion unit 41 has an IP conversion table that converts (replaces) the arrangement (bit position) of input 64-bit bit data. That is, the IP conversion table, for example, moves the value at the 58th bit position to the first bit position for each input 64-bit bit data, and changes the value at the 50th bit position to the second bit. It is a table having instruction information such as moving to the position. The IP conversion table will be described later with reference to FIG.

  The IP conversion unit 41 performs an IP conversion process for exchanging the bit positions of 64-bit bit data of the input signal according to the IP conversion table. Then, the IP conversion unit 41 outputs the upper 32-bit bit data to the register 51-1, and the lower 32-bit bit data to the register 52-1, among the 64-bit bit data obtained by the IP conversion process. To do.

  Here, since the 1-bit bit data input to the IP conversion unit 41 is represented by 2-bit signal bits as described above, the bit position of the 1-bit bit data is moved. This means that two signal bits corresponding to the bit data are moved as a set.

The register 51-1 stores the 32-bit bit data from the IP conversion unit 41, and outputs the stored 32-bit bit data to the adder circuit 55-1 at a predetermined timing. Note that the 32-bit bit data stored in the register 51-1 to L _0.

The register 52-1 stores the 32-bit bit data from the IP conversion unit 41, and outputs the stored 32-bit bit data to the function processing unit 54-1 and the register 51-2 at a predetermined timing. To do. Note that 32-bit bit data stored in the register 52-1 is R ₀ .

Intermediate key generating unit 53-1, based on the 64-bit common key that is input thereto, to generate a 48-bit intermediate key K _1, and outputs to the function processing section 54-1.

Function processing section 54-1 includes a 32-bit bit data R ₀ from the register 52-1, based on the intermediate key K ₁ of 48 bits from the intermediate-key generating unit 53-1 performs the f function process. Details of the f function processing will be described later with reference to FIG. 10, but new 32-bit bit data is generated by the f function processing. The f function processing is performed based on the 32-bit bit data α and the 48-bit intermediate key (bit data) β, and the 32-bit bit data generated by the f function processing is expressed as f (α, β). In the function processing unit 54-1, 32-bit bit data f (R ₀ , K ₁ ) is generated.

Then, the function processing unit 54-1 outputs new 32-bit bit data f (R ₀ , K ₁ ) obtained by the f function processing to the adding circuit 55-1.

The adding circuit 55-1 corresponds to the bit (L ₀ , K ₁ ) corresponding to the 32-bit bit data L ₀ from the register 51-1 and the 32-bit bit data f (R ₀ , K ₁ ) from the function processing unit 54-1. The EXOR processing described with reference to FIG. 6 is performed for each of the two signal bits representing one logical bit). Then, the adder circuit 55-1 outputs the 32-bit bit data obtained by the EXOR process to the register 52-2.

Here, the 32-bit bit data L ₁ stored in the register 51-2 and the 32-bit bit data R ₁ stored in the register 52-2 can be expressed as follows.

L ₁ = R ₀
R ₁ = L ₀ + f (R ₀ , K ₁ )
... (1)

  Here, “+” represents EXOR processing (EXOR operation).

Above, the register 51-1 and each of 52-1, since the output bit data L ₀ and R ₀ of 32 bits, the subsequent registers 51-2 and 52-2 of the registers 51-1 and 52-1 If the processing until the 32-bit bit data L ₁ and R ₁ represented by the equation (1) is stored is called one round processing, the encryption processing circuit 22 in FIG. Configuration of register 51-1, register 52-1, intermediate key generation unit 53-1, function processing unit 54-1, and adder circuit 55-1 configured to perform two round processes (hereinafter, A configuration similar to that of the one-round processing set is provided in the subsequent stage of the one-round processing set for 15 rounds.

In other words, the encryption processing circuit 22 includes a register 51-i, a register 52-i, an intermediate key generation unit 53-i, a function processing unit 54-i, and an addition circuit 55-i for 16 rounds. . The 32-bit bit data stored in the register 51-i and the register 52-i are represented as L _i-1 and R _i-1 , respectively. Here, the variable i representing the round number represents i = 1, 2,... 16 unless otherwise noted.

In the process of the 16 th 16 rounds, unlike the processing of other 1 to 15 rounds, as shown in FIG. 7, the register 52-16 is stored in 32-bit bit data R _15, register 51 The adder 55-16 in the 16th round outputs the 32-bit bit data obtained by the EXOR process to the register 51-17 instead of the register 52-17. Output.

For the bit data L _i-1 and R _i-1 stored in the 2 to 16 round registers 51-i and 52-i (i = 2,..., 16), respectively, the registers 51-2 and 52-2 Since the same relation as the expression (1) of L ₁ and L ₂ stored in the above holds, the bit data L _i-1 and R _i-1 (i = 1, 2,..., 16) can be expressed as the following equation (2).

L _i = R _i-1
R _i = L _i−1 + f (R _i−1 , K _i ) (i = 1, 2,..., 16)
... (2)

Register 51-17 is a 32-bit bit data obtained by EXOR process from the adding circuit 55-16 is stored as bit data L _16, at a predetermined timing, the bit data L ₁₆ to IP inverse transform unit 61 Output.

Register 52-17 is a 32-bit bit data from the register 52-16 is stored as bit data R _16, at a predetermined timing, and outputs the bit data R ₁₆ in IP inverse transform unit 61.

Therefore, the bit data L ₁₆ and the bit data R ₁₆ can be expressed as shown in Equation (3).

L ₁₆ = L ₁₅ + f (R ₁₅ , K ₁₆ )
L ₁₆ = R ₁₅
(3)

The IP reverse conversion unit 61 receives the 32-bit bit data L ₁₆ from the register 51-17 and the 32-bit bit data R ₁₆ from the register 52-17. Then, the IP reverse conversion unit 61 converts the 32-bit bit data L ₁₆ into the upper 32 bits and performs the IP reverse conversion on the 64-bit bit data having the 32-bit bit data R ₁₆ as the lower 32 bits. Do.

  That is, the IP reverse conversion unit 61 performs IP reverse conversion that is reverse conversion of IP conversion of 64-bit bit data performed by the IP conversion unit 41. Specifically, the IP reverse conversion unit 61 has an IP reverse conversion table corresponding to the IP conversion table of the IP conversion unit 41, and replaces the bit position of 64-bit bit data according to the IP reverse conversion table. Perform the conversion process. Then, the IP conversion unit 61 outputs 64-bit bit data obtained by the IP reverse conversion process to the outside as ciphertext.

  FIG. 8 shows an example of an IP conversion table included in the IP conversion unit 41 of FIG.

  In the IP conversion table of FIG. 8, the position of each bit (a set of 2 bit signal bits representing one logic bit) of 64-bit bit data to be subjected to IP conversion processing is set as an input bit position, and IP conversion is performed. The input bit position and the output bit position are associated with each other (the set of 2-bit signal bits representing one logical bit) of the processed 64-bit bit data as the output bit position.

  The IP conversion unit 41 in FIG. 7 determines the output bit position of each bit of the 64-bit bit data input from the signal conversion circuit 21 with reference to the IP conversion table in FIG. Arrange (move) to the bit position and output to the register 51-1 or 52-1.

  In the IP conversion table shown in FIG. 8, of the 64-bit bit data to be subjected to IP conversion processing, for example, the bit data at the input bit position of the 58th bit surrounded by a dotted circle in the figure is 1 bit. It is specified to be arranged (moved) at the output bit position of the eye. Accordingly, the 58th bit of the 64-bit bit data to be subjected to the IP conversion process is replaced with the first bit by the IP conversion process of the IP conversion unit 41.

  Further, according to the IP conversion table of FIG. 8, for example, the 50th bit of the 64-bit bit data to be subjected to the IP conversion process is replaced with the second bit. Similarly, in the IP conversion table of FIG. 8, the bit positions of the first to 64th bit data other than the 58th and 50th bits described above are arranged as the output bit positions in the IP conversion table of FIG. Whether to do it is specified.

  As described above, the IP conversion unit 41 performs an IP conversion process of replacing the bit positions of the input 64-bit bit data using the IP conversion table.

  FIG. 9 shows an example of an IP reverse conversion table included in the IP reverse conversion unit 61 of FIG.

  In the IP reverse conversion table of FIG. 9, the position of each bit of the 64-bit bit data to be subjected to the IP reverse conversion process is set as the input bit position, and each bit of the 64-bit bit data after the IP reverse conversion process is set. With the position as the output bit position, the input bit position and the output bit position are associated with each other.

  The IP reverse conversion table in FIG. 9 is a table for performing IP reverse conversion, which is reverse conversion of IP conversion of 64-bit bit data performed by the IP conversion unit 41 as described above.

  According to the IP reverse conversion table of FIG. 9, among the 64-bit bit data to be subjected to the IP reverse conversion process, for example, the bit data whose input bit position is the first bit surrounded by a dotted circle in the figure is , It is designated to be arranged (moved) at the output bit position of the 58th bit. Therefore, the first bit of the 64-bit bit data to be subjected to the IP reverse conversion process is replaced with the 58th bit by the IP reverse conversion process of the IP reverse conversion unit 61.

  Similarly, in the IP reverse conversion table of FIG. 9, it is specified what bit the bit data of the second bit to the 64th bit is to be arranged as the output bit position.

  As described above, the IP reverse conversion unit 61 performs the IP reverse conversion process of replacing the bit positions of the input 64-bit bit data using the IP reverse conversion table.

  FIG. 10 shows a detailed configuration example of the function processing unit 54-1 of FIG.

As described above, the function processing unit 54-1 includes the 32-bit bit data R ₀ (represented by 64 bits as signal bits) output from the register 52-1, and the intermediate key generation unit 53-. F function processing is performed based on the 48-bit intermediate key K ₁ output from ₁ (the signal bits are represented by 96 bits).

The 32-bit bit data R ₀ output from the register 52-1 is input to the bit extension unit 101.

The bit expansion unit 101 performs 48-bit expansion processing for expanding 32-bit bit data R ₀ from the register 52-1 to 48-bit bit data in accordance with an E (Expand) table (described later in FIG. 11). Do. Then, the bit extension unit 101 outputs 48-bit bit data obtained by the 48-bit extension process to the adder circuit 102.

The adder circuit 102 receives the 48-bit bit data from the bit extension unit 101 and the 48-bit intermediate key K ₁ from the intermediate key generation unit 53-1.

The adder circuit 102 corresponds to the 48-bit bit data from the bit extension unit 101 and the 48-bit intermediate key K ₁ from the intermediate key generation unit 53-1 (two bits representing one logical bit). EXOR processing is performed for each signal bit set).

Then, the adder circuit 102 outputs 48-bit bit data obtained by the EXOR process to the S box processing units S _{1 to} S ₈ . Incidentally, the addition circuit 102, as shown in FIG. 10, among the 48 bits of the bit data obtained by EXOR process, the 6 bits of the lower 1 to 6 th bit S-box processing section S _8, the lower 7 to 12-bit the 6-bit eyes S box process unit S _7, the 6 least significant bits 13 to 18 th bit S-box processing section S _6, the 6 least significant bits 19 to 24-th bit to the S-box processing section S _5, the lower the 6-bit 25 to bit 30 in S-box processing section S _6, the 6 least significant bits 31 to 36 th bit S-box processing section S _3, the 6 least significant bits 37 to 42 bit S-box processing section S ₂ , 6 bits (upper 6 bits) of the lower 43 to 48 bits are output to the S box processing unit S ₁ , respectively.

The S box processing unit S _j (j = 1 to 8) converts the 6-bit bit data from the addition circuit 102 into 4-bit bit data using the S box function, and outputs the 4-bit bit data to the P conversion unit 103. Note that S box function processing for converting bit data by the S box function will be described later with reference to FIGS. 12 and 13.

4-bit bit data is input to the P conversion unit 103 from each of the S box processing units S _{1 to} S ₈ . Then, the P conversion unit 103 performs P conversion processing on 32-bit bit data obtained by arranging the 4-bit bit data from the S box processing units S _{1 to} S _{8 in} order from the most significant bit.

That is, the P conversion unit 103 has a P conversion table for exchanging bit positions, similar to the IP conversion table (FIG. 8). The P conversion unit 103 performs P conversion processing for replacing the bit positions of the 32-bit bit data input from the S box processing unit S _j according to the P conversion table. Then, the P conversion unit 103 outputs 32-bit bit data obtained by the P conversion process to the adder circuit 55-1 (FIG. 7).

Here, the 1-bit bit data input from the S box processing unit S _j to the P conversion unit 103 is a set of 2-bit signal bits, similar to each bit of the bit data input to the IP conversion unit 41. Since it is represented, moving the bit position of each bit of the bit data means moving two signal bits corresponding to the bit as a set.

  FIG. 11 shows an example of the E table included in the bit extension unit 101 of FIG.

  In the E table of FIG. 11, the position of each bit (a set of 2 signal bits representing one logical bit) of 32-bit bit data to be subjected to 48-bit extension processing is set as an input bit position, and 48 bits. The input bit position and the output bit position are associated with each other (the set of 2-bit signal bits representing one logical bit) of the 48-bit bit data after the extension processing as the output bit position.

  The bit extension unit 101 in FIG. 10 determines the input bit position of each bit of the 48-bit bit data output to the adder circuit 102 with reference to the E table in FIG. Bit data is arranged at the output bit position and output to the adder circuit 102.

  In the E table shown in FIG. 11, of the 48-bit bit data obtained by the bit expansion process, for example, the output bit position is the first bit data, and the input bit position is the 32-bit bit data. Is specified. Further, according to the E table of FIG. 11, of the 48-bit bit data obtained by the bit expansion process, for example, as the bit data whose output bit position is the second bit, the input bit position is the bit of the first bit. It is specified to be data.

  Similarly, in the E table of FIG. 11, the bit data whose output bit position is the 3rd to 48th bit positions is designated as the bit data of the input bit position.

  Since the bit extension unit 101 extends the 32-bit bit data input from the register 52-1 to 48-bit bit data, the 16-bit bit data is input from the register 52-1. Any one of bit data of bits is specified.

  For example, in the E table of FIG. 11, the bit data whose input bit position is the 32nd bit is also designated as the output bit position of the 47th bit in addition to the output bit position of the 1st bit described above.

In this way, the bit extension unit 101 performs 48-bit extension processing for extending the 32-bit bit data R ₀ to 48-bit bit data using the E table.

Next, with reference to FIG. 12 and FIG. 13, the S box function processing performed by the S box processing unit S _{j in} FIG. 10 will be described. FIGS. 12 and 13 show examples of S box function processing when j = 1.

  In the S box function process, a predetermined value as a function value is calculated (determined) by using an S box function with a row (Row Number) and a column (Column Number) as arguments. That is, according to the S box function, a predetermined value is determined by inputting a row (Row Number) and a column (Column Number).

  2 bits and 4 bits are assigned to the row and the column which are arguments of the S box function, respectively. Thus, the row takes any value from 0 to 3 that can be represented by 2 bits, and the column takes any value from 0 to 15 that can be represented by 4 bits.

FIG. 12 shows an example of 6-bit bit data input from the adder circuit 102 to the S box processing unit S ₁ . In FIG. 12, the 6-bit bit data is “011011 ₍₂₎ ” surrounded by a dotted line.

The S box processing unit S ₁ converts the lower 1st bit and the lower 6th bit (upper 1st bit) of the 6-bit bit data “011011 ₍₂₎ ” input from the adder circuit 102 to the lower order, respectively. Two bits “01 ₍₂₎ = 1 ₍₁₀₎ ”, which are bits and higher bits, are set as the value of the row (Row Number).

Further, the S box processing unit S ₁ sets the lower 2nd to 5th bits of the 6-bit bit data “011011 ₍₂₎ ” input from the adder circuit 102 as the lower 1st to 4th bits, respectively. 4-bit “1101 ₍₂₎ = 13 ₍₁₀₎ ” is set as the value of the column (Column Number).

Then, the S box processing unit S ₁ obtains a function value from the S box function shown in FIG. 13 using the row and column values as arguments.

  That is, FIG. 13 shows an S-box function that takes column and row values in the horizontal and vertical directions, respectively.

According to the S box function of FIG. 13, for example, as shown in FIG. 12, when the row (Row Number) is “1 ₍₁₀₎ ” and the column (Column Number) is “13 ₍₁₀₎ ”, A predetermined value “5 ₍₁₀₎ ” (indicated by a dotted line ₎ described at a position specified by the row and column is calculated as a function value.

If “5 ₍₁₀₎ ” calculated by the S box function of FIG. 13 is expressed in binary, it becomes 4 bits “0101 ₍₂₎ ”. Therefore, 6-bit bit data “6101” input from the adder circuit 102 “ 4 bits of bit data “0101 ₍₂₎ ” is output from the S box processing unit S ₁ to the P conversion unit 103 with respect to “011011 ₍₂₎ ”. As described above, the 4-bit bit data “0101 ₍₂₎ ” is represented by a total of 8 signal bits, that is, 4 sets of 2 bit signal bits in terms of hardware. Is.

As described above, each of the S box processing units S _{1 to} S ₈ outputs 4-bit bit data to the P conversion unit 103, and 32-bit bit data is input to the P conversion unit 103 in total. .

  FIG. 14 illustrates an example of a P conversion table included in the P conversion unit 103.

  In the P conversion table of FIG. 14, the position of each bit (a set of 2 bit signal bits representing one logical bit) of 32-bit bit data to be subjected to P conversion processing is set as an input bit position, and P conversion is performed. An input bit position and an output bit position are associated with each other (a set of 2-bit signal bits representing one logical bit) of 32-bit bit data obtained by the processing as an output bit position.

The P conversion unit 103 in FIG. 10 refers to the P conversion table in FIG. 14 and sets the output bit position of each bit of the 32-bit bit data input from the S box processing units S _{1 to} S _8. It is determined, arranged (moved) at the output bit position, and output to the adder circuit 55-1 (FIG. 7).

  In the P conversion table shown in FIG. 14, for example, bit data whose input bit position is 16 bits out of 32-bit bit data to be subjected to P conversion processing is arranged (moved) at the output bit position of the first bit. Is specified. Accordingly, the 16th bit of the 32-bit bit data to be subjected to the P conversion process is replaced with the first bit by the P conversion process of the P conversion unit 103.

  Similarly, in the P conversion table of FIG. 14, it is specified what bit the output bit position of the bit data whose input bit positions are the 1st to 15th bits and the 17th to 32nd bits.

In this manner, the P conversion unit 103 performs P conversion processing for replacing the bit positions of the 32-bit bit data from the S box processing units S _{1 to} S ₈ using the P conversion table.

  Next, the operation of the encryption processing circuit 22 when the encryption processing of FIG. 7 is performed will be described with reference to the flowchart of FIG.

  First, in step S1, the IP conversion unit 41 performs an IP conversion process for replacing the bit positions of the 64-bit bit data of the input signal from the signal conversion circuit 21 (FIG. 1) according to the IP conversion table (FIG. 8). Then, the process proceeds to step S2.

In step S2, the register 51-i, the register 52-i, the intermediate key generation unit 53-i, the function processing unit 54-i, the adder circuit 55-i, the register 51-17, and the register 52-17 perform round processing. Go to step S3. That is, in step S2, the bit data R _i-1 and L _i-1 (i = 1, 2,..., 16, 17) stored in the register 51-i and the register 52-i are described above. The process of (2) or (3) is performed.

  In step S3, the IP reverse conversion unit 61 performs an IP reverse conversion process for replacing the bit positions of 64-bit bit data according to the IP reverse conversion table. Then, the IP conversion unit 61 outputs 64-bit bit data obtained by the IP reverse conversion process to the outside, and ends the process.

  Next, the round process in step S2 of FIG. 15 will be described with reference to the flowchart of FIG.

  First, in step S21, the register 51-1, the register 52-1, the intermediate key generation unit 53-1, the function processing unit 54-1, and the addition circuit 55-1 perform the first round processing (one round processing). ) And the process proceeds to step S22.

  In step S22, the register 51-2, the register 52-2, the intermediate key generation unit 53-2, the function processing unit 54-2, and the addition circuit 55-2 perform the second round processing (two round processing). Then, the process proceeds to step S23.

Similarly, in steps S23 to S36, the register 51-i, the register 52-i, the intermediate key generation unit 53-i, the function processing unit 54-i, and the addition circuit 55-i are respectively connected to the i-th round. Round processing (i round processing) is performed (i = 3,..., 16). However, in the 16 round processing of step S36, as described with reference to FIG. 7, the register 52-16 is a memory to have 32-bit bit data R _15, rather than the register 51-17, output to the register 52-17 And the addition circuit 55-16 outputs 32-bit bit data obtained by the EXOR process to the register 51-17 instead of the register 52-17, which is different from the other 1 to 15 round processes. .

After the step S36, the process proceeds to step S37, the register 51-17 outputs a bit data L ₁₆ stored in the IP inverse transform unit 61, the register 52-17 is bit data R ₁₆ for storing Is output to the IP reverse conversion unit 61.

  Next, referring to the flowchart of FIG. 17, a register 51-1, a register 52-1, an intermediate key generation unit 53-1, a function processing unit 54-1, The operation of the adder circuit 55-1 will be described.

First, in step S51, the register 52-1 outputs the stored 32-bit bit data _R0 to the function processing unit 54-1, and proceeds to step S52.

In step S52, the register 52-1 outputs the stored 32-bit bit data _R0 to the register 51-2 (upper register), and proceeds to step S53.

In step S53, the intermediate key generating unit 53-1, based on the 64-bit common key that is input thereto, to generate a 48-bit intermediate key K _1, and outputs the function processing section 54-1, step Proceed to S54.

In step S54, the function processing unit 54-1, the bit data R ₀ of 32-bit from the register 52-1, based on the intermediate key K ₁ of 48 bits from the intermediate-key generating part 53-1, f function Processing is performed, and the process proceeds to step S55. 32-bit bit data is obtained by this f-function processing, and is output from the function processing unit 54-1 to the adding circuit 55-1.

In step S55, the adder circuit 55-1 includes a bit data L ₀ of 32 bits from the register 51-1, the 32-bit bit data from the function processing unit 54-1, the corresponding bit (one logic bit EXOR processing is performed on each of the signal bits (a set of 2 bits representing). In step S55, the addition circuit 55-1 outputs the 32-bit bit data obtained by the EXOR process to the register 52-2 (lower register), and ends the one round process.

  The same processing as the above-described one-round processing is also performed in each of the 2-round processing to 15-round processing in steps S22 to S35 in FIG.

  In the 16-round process of step S36 in FIG. 16, instead of outputting 32-bit bit data to the upper register (register 51-17) in step S52 described above, the lower register (register 52-17) is used. Except that the 32-bit bit data obtained by the EXOR process is output to the upper register (register 51-17) instead of being output to the lower register (register 52-17) in step S55 described above. Thus, the same processing as the one-round processing in FIG. 17 is performed.

  Next, the f function processing in step S54 in FIG. 17 will be described with reference to the flowchart in FIG.

First, in step S81, the bit extension unit 101 of the function processing unit 54-1 (FIG. 10) converts the 32-bit bit data _R0 from the register 52-1 into a 48-bit bit according to the E table included therein. 48-bit extension processing for extending data is performed, and the process proceeds to step S82.

In step S82, the adder circuit 102 corresponds to each of the corresponding bits of the 48-bit bit data obtained by the 48-bit extension process in the bit extension unit 101 and the 48-bit bit data from the intermediate key generation unit 53-1. Perform EXOR processing for. In step S82, the adder circuit 102 divides the 48-bit bit data obtained by the EXOR process into 6-bit data, and sequentially converts the 6-bit bit data into the S box processing units S _{1 to} S ₁ from the upper side. ₈ and proceeds to step S83.

In step S83, each of the S box processing units S _{1 to} S ₈ performs S box function processing for converting 6-bit bit data from the adder circuit 102 into 4-bit bit data using the S box function, The 4-bit bit data is output to the P conversion unit 103, and the process proceeds to step S84.

In step S84, P converter 103, according to P conversion table, the four bits from each S-box processing section S ₁ to S _8, performs P conversion interchanging the bit position of the 32-bit bit data in total. Then, the P conversion unit 103 outputs 32-bit bit data obtained by the P conversion process to the adder circuit 55-1.

  As described above, in the cryptographic processing circuit 22 (FIG. 1), each processing described with reference to FIGS. 15 to 18 is performed by setting 2 signal bits corresponding to 1 logical bit as a set.

  This eliminates the difference in power consumption between the two LoHi signal bits indicating that the logic level is 0 and the two HiLo signal bits indicating that the logic level is 1. it can. Accordingly, it is possible to prevent the decryption of the key by analyzing the current consumption from the outside of the IC chip 11 of FIG. 1 and to secure the security. For this reason, the IC chip 11 can be said to be a very secure security chip.

  Next, FIG. 19 shows a configuration example of another embodiment of the IC chip 11 that performs encryption processing to which the present invention is applied.

  The IC chip 11 in FIG. 19 is different from the IC chip 11 in FIG. 1 in that the signal conversion circuit 21 is not provided.

  In the cryptographic processing circuit 22 of FIG. 19, the same 1-bit logical bits as those output from the signal conversion circuit 21 of FIG. Is assigned to the signal. That is, when the logic level represented by the logic bit is 0, the LoHi 2-bit signal bit is input to the encryption processing circuit 22 from another device, and when the logic level represented by the logic bit is 1, Two HiLo signal bits are input from another device.

  As in the case described with reference to FIG. 1, the cryptographic processing circuit 22 performs DES cryptographic processing using the input two LoHi or HiLo signal bits as one logical bit, and the ciphertext as a result of the cryptographic processing. (Data) is output.

  Note that the cryptographic processing circuit 22 of FIGS. 1 and 19 can express, for example, 4 logical bits of LoHi LoHi or HiLo HiLo, in addition to representing the logical bit of 1 bit by the two signal bits of LoHi or HiLo as described above. It may be represented by a bit signal bit. That is, the cryptographic processing circuit 22 assigns the same number of signal bits Lo and Hi to the logical level 0 represented by one logical bit, and for the logical level 1 represented by the one logical bit, Encryption processing can be performed using a signal to which a signal bit having a different permutation of Lo and Hi from a signal bit assigned to logic level 0 is assigned.

  In this case, since the same number of Lo and Hi is assigned to each of the logical levels represented by one logical bit, the cryptographic processing circuit 22 has no difference in power consumption due to the difference in logical level. In addition, since there is no difference in power consumption in the circuit, it is possible to prevent the decryption of the key by analyzing the current consumption, such as DPA, and to perform secure cryptographic processing.

  Furthermore, in the above-described example, the cryptographic processing circuit 22 in FIGS. 1 and 19 has been described as performing DES cryptographic processing. However, the cryptographic processing algorithm performed by the cryptographic processing circuit 22 is not limited to DES, and AES or RSA may be used. Furthermore, for example, any algorithm that performs cryptographic processing by bit operation may be used.

  Moreover, although the case where it applied to the IC chip 11 which performs encryption processing was demonstrated in the example mentioned above, this invention performs the decoding process which decodes a ciphertext as a process relevant to encryption, for example. It can also be applied to IC chips.

  The IC chip 11 having the cryptographic processing circuit 22 of FIGS. 1 and 19 is employed in various devices that require secure communication, such as an IC card, a reader / writer, a mobile phone, and other PDAs (Personal Digital Assistants). be able to.

  In the present specification, the steps described in the flowcharts are executed in parallel or individually even if they are not necessarily processed in time series, as well as processes performed in time series in the described order. It also includes processing.

It is a block diagram which shows the structural example of one Embodiment of the IC chip to which this invention is applied. It is a figure which shows the signal of the input of the signal conversion circuit 21 with respect to the data X which has 2 bits, and an output. It is a figure which shows the signal of the input of the signal conversion circuit 21 with respect to the data X which has 4 bits, and an output. It is a figure which shows the truth table of the EXOR process of input data X and Y. It is a figure which shows the process result of an EXOR process when 1 signal bit is allocated to 1 logic bit. It is a figure which shows the processing result of an EXOR process when assigning 2 signal bits to 1 logic bit. 3 is a diagram illustrating a detailed configuration example of an encryption processing circuit 22. FIG. It is a figure which shows the example of the IP conversion table which the IP conversion part 41 has. It is a figure which shows the example of the IP reverse conversion table which the IP reverse conversion part 61 has. It is a figure which shows the detailed structural example of the function process part 54-1. It is a figure which shows the example of E table which the bit expansion part 101 has. It is a figure explaining the S box function process which S box process part _Sj performs. It is a figure explaining the S box function process which S box process part _Sj performs. It is a figure which shows the example of the P conversion table which the P conversion part 103 has. 3 is a flowchart for explaining the operation of the cryptographic processing circuit 22. It is a flowchart explaining a round process. It is a flowchart explaining 1 round process. It is a flowchart explaining f function processing. It is a block diagram which shows the structural example of other embodiment of the IC chip to which this invention is applied.

Explanation of symbols

  11 IC chip, 21 signal conversion circuit, 22 cryptographic processing circuit

Claims (6)

In a signal processing circuit that performs encryption-related processing related to encryption,
The same number of signal bits Lo and Hi are assigned to one of the two logic levels represented by one logic bit, and the one logic level is assigned to the other logic level. A signal processing circuit comprising encryption-related processing means for performing encryption-related processing using a signal to which a signal bit having a different permutation of Lo and Hi from the assigned signal bit is assigned. The encryption-related processing means performs encryption-related processing using a signal in which a HiLo signal bit is assigned to one logical level and a LoHi signal bit is assigned to the other logical level. The signal processing circuit according to claim 1. The signal processing circuit according to claim 1, wherein the encryption-related processing unit performs encryption-related processing using DES (Data Encryption Standard). The signal processing circuit according to claim 1, comprising an IC (Integrated Circuit) chip. The signal processing circuit according to claim 1, further comprising an assigning unit that assigns a HiLo signal bit to one logic level and assigns a LoHi signal bit to the other logic level. In a signal processing method of a signal processing circuit that performs encryption-related processing related to encryption,
The same number of signal bits Lo and Hi are assigned to one of the two logic levels represented by one logic bit, and the one logic level is assigned to the other logic level. A signal processing method comprising: a cryptographic related processing step for performing cryptographic related processing using a signal to which a signal bit having a different permutation of Lo and Hi is assigned.

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