JP2005258617A - Memory contention time measuring device, memory contention time measuring method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory contention time measuring device and the like that can accurately measure a memory contention time. <P>SOLUTION: About every instruction executed by an operation control part OCk, a memory contention counter MCCk identifies an excess period beyond the turnaround time in which a network unit NUk of a central processing unit CPUk starts to access a memory management unit and receives a response from the memory management unit which is in the absence of contention with other central processing units. The period accumulation of excess periods at least about any instruction is identified as a memory contention time. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory contention time measuring apparatus and a memory contention time measuring method for measuring an amount of time that a processor or the like accesses to a memory due to contention with another device.

Conventionally, a shared memory type SMP (Symmetric Multi-Processor) composed of a plurality of CPUs (Central Processing Units) that make read / write requests to a common memory in an equal position is used.
In order to efficiently operate a system in which a plurality of CPUs access a common memory, such as a shared memory type SMP, a delay amount of access time due to contention of accesses to the memory by the plurality of CPUs, that is, a memory It is important to know the contention time and reduce this memory contention time as much as possible.

As a method for obtaining the memory contention time or information related thereto, a method of measuring the amount of delay is known by paying attention to the delay in sending the memory access request due to the contention of access to the memory ( Patent Document 1).
JP-A-2-236692

However, since the method of Patent Document 1 does not measure the memory contention time itself, the memory contention time cannot be accurately known.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory contention time measuring device, a memory contention time measuring method, and a program capable of accurately measuring a memory contention time.

In order to achieve this object, a memory contention time measuring apparatus according to the first aspect of the present invention includes:
The measurement target processor starts the access to the memory by executing an instruction to access the memory, and then the measurement target processor does not exist in a state where there is no other device that accesses the memory. Contention-free turnaround time data storage means for storing contention-free turnaround time data representing the time taken to receive a response from the memory;
Of the period from when the measurement target processor starts accessing the memory by executing the instruction to receiving a response from the memory, the time indicated by the contention-free turnaround time data is exceeded. Individual overtime specifying means for specifying the excess period for each instruction,
Total excess time specifying means for specifying, as a measurement result of memory contention time, a period specified as the excess period for at least one of the instructions;
It is characterized by providing.
According to such a memory contention time measuring apparatus, the memory contention time is accurately measured.

When the instruction is a vector instruction, the individual excess time specifying unit is configured so that the measurement target processor starts the access to the memory according to the last element constituting the vector instruction. Of the period until the response is received from the memory, the period exceeding the time indicated by the contention free turnaround time data may be specified as the excess period for the vector instruction.
With such a configuration, it is possible to avoid complication of processing due to obtaining an excess period for all elements of a vector instruction generally having several hundred elements per one.

The contention-free turnaround time data storage means may have, for example, a plurality of storage areas. In this case, each storage area stores the contention-free turnaround time data and a flag. It may be a storage area.
In this case, the individual excess time specifying means is, for example,
Means for allocating one of the storage areas of the contention-free turnaround time data storage means to the instruction in response to the signal when the measurement target processor issues a signal indicating that the instruction has been received; ,
When the processor to be measured issues a signal indicating that access to the memory has been started by executing the instruction, the storage area allocated to the instruction after responding to the signal and responding to the signal Until the value of the contention-free turnaround time data stored in the table becomes 0, the contention-free turnaround time data is updated to an amount subtracted by an amount corresponding to the elapsed time;
In response to the value of the contention-free turnaround time data stored in the storage area allocated to the instruction being 0, the flag stored in the storage area is set within the excess period for the instruction. Means for updating to a value indicating that there is,
Detects that the memory responds to an access started in accordance with the instruction, and updates the flag stored in the storage area allocated to the instruction to a value indicating that it is outside the excess period for the instruction And a means for
The overall excess time specifying means measures a length of a period in which at least one of the flags takes a value indicating that it is within the excess period, and specifies a measurement result as a measurement result of the memory contention time. It may be provided.

In addition, the memory contention time measuring method according to the second aspect of the present invention includes:
The measurement target processor starts the access to the memory by executing an instruction to access the memory, and then the measurement target processor does not exist in a state where there is no other device that accesses the memory. Stores contention-free turnaround time data representing the time it takes to receive a response from memory,
Of the period from when the measurement target processor starts accessing the memory by executing the instruction to receiving a response from the memory, the time indicated by the contention-free turnaround time data is exceeded. For each order,
Specifying the period specified as the excess period for at least one of the instructions as a measurement result of a memory contention time;
It is characterized by that.
Also by such a memory contention time measuring method, the memory contention time is accurately measured.

A program according to the third aspect of the present invention is:
Computer
The measurement target processor starts the access to the memory by executing an instruction to access the memory, and then the measurement target processor does not exist in a state where there is no other device that accesses the memory. Contention-free turnaround time data storage means for storing contention-free turnaround time data representing the time taken to receive a response from the memory;
Of the period from when the measurement target processor starts accessing the memory by executing the instruction to receiving a response from the memory, the time indicated by the contention-free turnaround time data is exceeded. Individual overtime specifying means for specifying the excess period for each instruction,
Total excess time specifying means for specifying a period specified as the excess period for at least one of the instructions as a measurement result of a memory contention time;
It is for making it function.
The memory contention time is accurately measured even by a computer that executes such a program.

  According to the present invention, a memory contention time measuring apparatus, a memory contention time measuring method, and a program that can accurately measure a memory contention time are realized.

  Embodiments of the present invention will be described below with reference to the drawings, taking an arithmetic system as an example.

  FIG. 1 is a diagram showing a configuration of an arithmetic system according to an embodiment of the present invention. As shown in the figure, this arithmetic system is composed of α central processing units CPU1 to CPUα and β memory management units MMU1 to MMUβ. The central processing units CPU1 to CPUα have substantially the same configuration, and the memory management units MMU1 to MMUβ have substantially the same configuration. This arithmetic system forms an SMP (Symmetric Multi-Processor) in which the central processing units CPU1 to CPUα can access the memory management units MMU1 to MMUβ on an equal basis.

  As shown in FIGS. 1 and 2, the central processing unit CPUk (k is an integer between 1 and α) includes an arithmetic control unit OCk, an address control unit ACk, a network unit NUk, a memory contention counter MCCk, and a crystal. A clock generator (not shown) including an oscillator and the like.

  The arithmetic control unit OCk, the address control unit ACk, and the network unit NUk are connected to each other, and the memory contention counter MCCk is connected to the address control unit ACk and the network unit NUk. The network unit NUk is connected to memory control units MC1 to MCβ (to be described later) of the memory management units MMU1 to MMUβ via a bus. The clock generation unit generates a clock signal and continuously supplies this clock signal to the arithmetic control unit OCk, the address control unit ACk, the network unit NUk, and the memory contention counter MCCk.

The arithmetic control unit OCk is composed of a logic circuit that performs logical operation processing and temporary storage of data. The operation control unit OCk executes an operation according to a command or operand supplied from the network unit NUk, and outputs or temporarily stores data generated as a result of the execution.
The data output from the arithmetic control unit OCk includes, for example, data stored in the memory management units MMU1 to MMUβ, memory access issued to the address control unit ACk (data storage to the memory management units MMU1 to MMUβ, or memory Data load from the management units MMU1 to MMUβ), addresses of storage areas to be accessed by the memory management units MMU1 to MMUβ, and the like.

  The address control unit ACk includes a logic circuit that performs operations such as temporary storage of addresses, addition and subtraction, and input / output. The address control unit ACk acquires a memory access request supplied from the arithmetic control unit OCk, and in accordance with this request, the network unit NUk is sent to the memory management unit to be accessed that is one of the memory management units MMU1 to MMUβ. A control signal for requesting memory access, an address of a storage location to be accessed, and the like are supplied. In response to this request, a signal for notifying that the memory access request has been accepted is supplied to the memory contention counter MCCk. It is assumed that this signal also includes information for specifying which instruction the request is issued by the arithmetic control unit OCk.

  The network unit NUk is composed of a logic circuit or the like, and when the address control unit ACk supplies a control signal, in response to the control signal, the memory contention counter MCCk executes a request to start memory access. Supply a signal to notify. On the other hand, the network unit NUk executes the request by performing memory access to the memory management unit to be accessed via the bus according to the control signal. When performing this memory access, the network unit NUk negotiates (adjusts the timing of the memory access) so that the memory management unit can be accessed at a timing when the bus or the memory management unit to be accessed is not used by a device other than the central processing unit CPUk. Etc.). Further, the memory management unit to be accessed is supplied with the address of the storage location to be accessed.

  Further, when the network unit NUk is supplied with data and other signals loaded from the memory management unit to be accessed as a result of the memory access, in response to these signals, the network unit NUk stores the memory contention counter MCCk in the memory A signal for notifying that the responses from the management units MMU1 to MMUβ have been received is supplied. Further, the data loaded and supplied from the memory management unit to be accessed is supplied to the arithmetic control unit OCk.

  As shown in FIG. 2, the memory contention counter MCCk has R instruction allocation registers (R is preferably a number equal to or greater than the total number of instructions with memory access among instructions that can be executed by the arithmetic processing unit OCk). CARk-0 to CARk- (R-1), an OR operation unit ORk, an overall counter C2k, and a counter control unit (not shown). Among these, the counter control unit is configured by a logic circuit or the like, and stores data in the instruction allocation registers CARk-0 to CARk- (R-1) and the overall counter C2k, and the instruction allocation registers CARk-0 to CARk. -Load data from (R-1) and the counter for the whole C2k, and other processing described later.

The instruction allocation registers CARk-0 to CARk- (R-1) have substantially the same configuration, and perform operations such as temporary storage of data, addition / subtraction, input / output, and other processing described later. It is composed of a logic circuit or the like.
The instruction allocation register CARk-m (m is an integer greater than or equal to 0 and less than R) includes an instruction valid bit storage unit CMVk-m, an instruction-specific counter C1k-m, and a counter valid bit storage unit CTVk-m. It is assumed that the register number “m” is assigned to the instruction assignment register CARk-m.

The instruction valid bit storage unit CMVk-m stores an instruction valid bit composed of 1-bit data, and sets the value of the instruction valid bit to “0” or “1” according to the processing described later.
Note that the instruction valid bit stored in the instruction valid bit storage unit CMVk-m is data indicating whether or not the instruction allocation register CARk-m is allocated to a specific instruction. In the following description, it is assumed that the instruction valid bit takes the value “0” when indicating that it is not assigned to a specific instruction, and takes the value “1” when indicating that it is assigned.

  The instruction-specific counter C1k-m stores a value indicating a non-contention turnaround time, which will be described later, as an initial value in accordance with processing described later, and then decrements this value when in the on state and is in the off state. Sometimes keep the value stored in the source.

The counter valid bit storage unit CTVk-m stores a counter valid bit composed of 1-bit data, and sets the value of the counter valid bit to “0” or “1” according to the processing described later.
The counter valid bit stored in the counter valid bit storage unit CTVk-m is data indicating whether or not the value stored in the instruction-specific counter C1k-m is “0”. In the following, when the counter valid bit takes the value “0”, it indicates that the value stored in the instruction-specific counter C1k-m is not “0”, and when it takes the value “1”, the instruction-specific counter C1k-m In the following description, it is assumed that the value stored in is “0”.

  The OR operation unit ORk generates data representing the logical sum of the values of the R counter effective bits stored in the R counter effective bit storage units CTVk-1 to CTVk- (R-1), and generates a counter C2k for the whole. To supply.

  The overall counter C2k stores a value “0” as an initial value, and when the value of data supplied from the OR operation unit ORk is “1”, the timing at which the clock signal reaches a predetermined state (for example, rise) Each time comes, increments the value stored by itself. (Hereinafter, the predetermined state will be described as the rising edge of the clock signal.)

  MMUj (j is an integer between 1 and β) includes a memory control unit MCj and a random access memory RAMj. The memory control unit MCj and the random access memory RAMj are connected to each other, and the memory control unit MCj is connected to the network units NU1 to NUα of the central processing units CPU1 to αα via the bus described above.

  The memory control unit MCj is configured by a logic circuit or the like. When the memory access is received from the network units NU1 to NUα via the bus and the address of the storage location to be accessed is supplied, the memory control unit MCj follows the memory access. The data is stored in the storage location in the storage area of the random access memory RAMj, or the data is loaded from the storage location. Then, a signal indicating the completion of loading or storing and the loaded data are supplied to the network unit that performed the memory access. When supplying this signal and loaded data, the memory control unit MCj performs negotiation (adjustment of data supply timing, etc.) so that the memory can be accessed at a timing when the bus is not used by a device other than itself. )I do. Further, the memory control unit MCj outputs a predetermined busy signal during execution of data storage or loading, or during a period during which other requests from the network units NU1 to NUα cannot be accepted.

  The random access memory RAMj reads data from the storage location designated by the memory control unit MCj and supplies it to the memory control unit MCj in accordance with the loading process of the memory control unit MCj. Further, according to the store processing of the memory control unit MCj, data is stored in a storage location designated by the memory control unit MCj.

  Next, a procedure for measuring the memory contention time by this arithmetic system will be described with reference to FIG. 3 focusing on the processing executed by the memory contention counter MCCk, taking as an example the case where the central processing unit CPUk accesses the memory management unit MMUj. The description will be given with reference. FIG. 3 is a flowchart showing a procedure for measuring the memory contention time.

First, when the central processing unit CPUk starts operation, the memory contention counter MCCk performs predetermined initialization (FIG. 3, step S1). Specifically, the counter control unit of the memory contention counter MCCk performs the following processes (1) to (4) in step S1. That means
(1) The instruction effective bit values stored in the instruction effective bit storage units CMVk-1 to CMVk- (R-1) are all set to “0”.
(2) The value of the counter valid bit stored in the counter valid bit storage units CTVk-1 to CTVk- (R-1) is set to “0”.
(3) In the counters by instruction C1k-1 to C1k- (R-1), values indicating the non-contention turnaround time are stored as initial values.
(4) The value “0” is stored as an initial value in the overall counter C2k.

Note that the turnaround time of the central processing unit CPUk is based on one instruction, and after the network unit NUk outputs a signal indicating that the memory access is started, the network unit NUk receives from the memory management units MMU1 to MMUβ. This is the time until a signal indicating that a response has been accepted is output. The contention-free turnaround time of the central processing unit CPUk is the turnaround time of the central processing unit CPUk in a state where no central processing unit other than the central processing unit CPUk performs memory access.
The contention-free turnaround time value of the central processing unit CPUk is specified, for example, by conducting an experiment in advance, and stored in advance in the memory contention counter MCCk, and in step S1, it is stored in the instruction-specific counters C1k-1 to C1k-. (R-1) may be loaded. In this case, the memory contention counter MCCk may include a non-volatile memory (not shown) that stores a value of the contention-free turnaround time, for example.
Further, the value indicating the non-contention turnaround time stored in the instruction-specific counters C1k-1 to C1k- (R-1) is, for example, the non-contention turnaround time of the central processing unit CPUk. It is assumed that the integer is substantially equal to the value divided by the period of the clock signal described above.

After the processing in step S1, the address control unit ACk supplies a signal indicating that a memory access request based on a specific instruction (hereinafter, the instruction is referred to as instruction A) to the memory contention counter MCCk. (Step S2). At this time, the counter control unit of the memory contention counter MCCk allocates to the instruction A the one with the smallest register number among the instruction allocation registers whose instruction valid bit value stored in the instruction valid bit storage unit is “0”. (Step S3), and the value of the instruction effective bit stored in the instruction effective bit storage unit of the instruction allocation register allocated to the instruction A is set to “1” (step S4).
However, if the instruction A is a vector instruction, the counter control unit of the memory contention counter MCCk assigns only the last element constituting the instruction A to the instruction allocation register in step S3.

  Next, when the network unit NUk supplies a signal indicating that the memory access based on the instruction A is started to the memory contention counter MCCk, the counter control unit of the memory contention counter MCCk stores the instruction allocation register assigned to the instruction A. The instruction-specific counter is turned on (step S5).

On the other hand, the instructions in the memory contention counter MCCk that are on are decremented by 1 each time the clock signal supplied to the memory contention counter MCCk rises (step S6). ). The instruction-by-instruction counter that has decremented in step S6 determines whether or not the value stored in it is a value other than 0 (step S7). The process of step S6 is continued. On the other hand, the instruction-specific counter determined to be 0 does not further decrement, and the counter valid bit value stored in the counter valid bit storage unit in the same instruction allocation register as itself is changed from “0”. It is rewritten to “1” (step S8).
When the value of the counter valid bit is “1”, the turnaround time of the instruction assigned to the instruction assignment register that stores the counter valid bit exceeds the turnaround time when there is no contention. Is shown.

Then, the counter control unit of the memory contention counter MCCk determines whether or not the network unit NUk has issued a signal indicating that a response from the memory management units MMU1 to MMUβ based on the instruction A has been received (step S9).
If it is determined that the signal is supplied as a result of the determination in step S9, the counter control unit of the memory contention counter MCCk sets the value of the instruction-specific counter of the instruction allocation register allocated to the instruction A to the value of the central processing unit CPUk. The counter is reset to a value indicating the turnaround time at the time of competition, and the instruction-specific counter is turned off (step S10). Further, the values of the instruction effective bit and the counter effective bit stored in the instruction effective bit storage unit and the counter effective bit storage unit of the instruction allocation register are reset to “0”.
On the other hand, if it is determined that the signal is not supplied, the memory contention counter MCCk repeats the process of step S9.

  However, as described above, the overall counter C2k has a value of “1” supplied from the OR operation unit ORk (that is, the counter valid bit storage units CTVk-1 to CTVk− (R−1)). When the value of at least one of the counter valid bits stored in (1) is “1”), the value stored by itself is incremented each time the clock signal rises (steps S11 and S12).

  While the memory contention counter MCCk performs the operations of steps S1 to S12 described above, the counter control unit of the memory contention counter MCCk uses the data indicating the value stored in the overall counter C2k as the memory contention time of the central processing unit CPUk. Is output to the outside as data indicating.

As a result of the above-described operation of the memory contention counter MCCk, the value stored in the overall counter C2k at a specific point in time has no actual turnaround time for any instruction executed by the central processing unit CPUk by that point. It shows the cumulative total of the periods that exceeded the turnaround time at the time of competition. This time is the memory contention time of the central processing unit CPUk up to this point.
Note that if only the last element of a vector instruction is assigned to the instruction allocation register, the accuracy of measuring the memory contention time may be slightly lower than when all elements are assigned, but the processing becomes more complicated. This is useful for avoiding the above-mentioned problem and making the configuration of the memory contention counter MCCk small and simple.

The configuration of the arithmetic system described above is not necessarily limited to that described above.
For example, the configurations of the arithmetic control units OC1 to OCα do not necessarily have to be substantially the same, and the central processing units CPU1 to CPUα need to access the memory management units MMU1 to MMUβ from an entirely equivalent standpoint. Absent.
Further, it is not necessary for the memory contention counter to be provided in all of the central processing units CPU1 to CPUα, and it is sufficient if only the central processing unit that is a target for measuring the memory contention time is provided. The address control unit or network unit of the central processing unit that does not include a memory conflict counter need not have a function of supplying a signal to the memory conflict counter.
Further, the memory contention counter MCCk does not need to be formed integrally with the arithmetic control unit OCk, the address control unit ACk, and the network unit NUk.
Also, all the elements may be allocated under conditions that allow the processing complexity to be allowed by allocating all the elements of the vector instruction to the instruction allocation register.

  Although the embodiment of the present invention has been described above, the memory contention time measuring apparatus according to the present invention can be realized using a normal computer system, not a dedicated system. For example, the above-described instruction allocation registers CARk-0 to CARk- (R-1), the OR operation unit ORk, the overall counter C2k and the counter are added to the personal computer connected to the address control unit ACk and the network unit NUk of the central processing unit CPUk. The memory contention counter MCCk can be configured by installing the program from a recording medium (CD-ROM, MO, flexible disk, etc.) storing a program for executing the operation of the control unit.

Further, for example, this program may be uploaded to a bulletin board (BBS) of a communication line and distributed via the communication line. Also, a carrier wave is modulated by a signal representing this program, and the obtained modulated wave is A device that transmits and receives the modulated wave may demodulate the modulated wave to restore these programs.
The above-described processing can be executed by starting this program and executing it under the control of the OS in the same manner as other application programs.

  When the OS shares a part of the processing, or when the OS constitutes a part of one component of the present invention, a program excluding the part is stored in the recording medium. May be. Also in this case, in the present invention, it is assumed that the recording medium stores a program for executing each function or step executed by the computer.

It is a figure which shows the structure of the arithmetic system which concerns on embodiment of this invention. It is a figure which shows the structure of a central processing unit. It is a flowchart which shows the procedure of the process which measures memory contention time.

Explanation of symbols

CPU1 to CPUα Central processing unit OC1 to OCα Operation control unit AC1 to ACα Address control unit NU1 to NUα Network unit MCC1 to MCCα Memory contention counter CAR1-0 to CARα- (R-1) Instruction allocation counter CMV1-0 to CMVα- ( R-1) Instruction valid bit storage unit C11-0 to C1α- (R-1) Instruction-specific counter CTV1-0 to CTVα- (R-1) Counter valid bit storage unit OR1 to ORα OR operation unit C21 to C2α Counter MMU1-MMUβ Memory management unit MC1-MCβ Memory control unit RAM1-RAMβ Random access memory

Claims (5)

The measurement target processor starts the access to the memory by executing an instruction to access the memory, and then the measurement target processor does not exist in a state where there is no other device that accesses the memory. Contention-free turnaround time data storage means for storing contention-free turnaround time data representing the time taken to receive a response from the memory;
Of the period from when the measurement target processor starts accessing the memory by executing the instruction to receiving a response from the memory, the time indicated by the contention-free turnaround time data is exceeded. Individual overtime specifying means for specifying the excess period for each instruction,
Total excess time specifying means for specifying, as a measurement result of memory contention time, a period specified as the excess period for at least one of the instructions;
A memory contention time measuring apparatus comprising: When the instruction is a vector instruction, the individual excess time specifying unit is configured so that the measurement target processor starts the access to the memory according to the last element constituting the vector instruction. Among the periods until a response is received from the memory, the period exceeding the time indicated by the contention free turnaround time data is specified as the excess period for the vector instruction.
The memory contention time measuring apparatus according to claim 1. The contention-free turnaround time data storage means has a plurality of storage areas, and each storage area is a storage area for storing the contention-free turnaround time data and a flag,
The individual excess time specifying means is:
Means for allocating one of the storage areas of the contention-free turnaround time data storage means to the instruction in response to the signal when the measurement target processor issues a signal indicating that the instruction has been received; ,
When the measurement target processor issues a signal indicating that access to the memory has been started by executing the instruction, the storage area allocated to the instruction after responding to the signal and responding to the signal Until the value of the contention-free turnaround time data stored in is stored at 0, the contention-free turnaround time data is updated to a state subtracted by an amount corresponding to the elapsed time;
In response to the value of the contention-free turnaround time data stored in the storage area allocated to the instruction being 0, the flag stored in the storage area is set within the excess period for the instruction. Means for updating to a value indicating that there is,
Detects that the memory responds to an access started in accordance with the instruction, and updates the flag stored in the storage area allocated to the instruction to a value indicating that it is outside the excess period for the instruction And means for
The total excess time specifying means measures a length of a period in which at least one of the flags takes a value indicating that it is within the excess period, and specifies a measurement result as a measurement result of the memory contention time. Prepare
The memory contention time measuring apparatus according to claim 1 or 2, characterized in that: The measurement target processor starts the access to the memory by executing an instruction to access the memory, and then the measurement target processor does not exist in a state where there is no other device that accesses the memory. Stores contention-free turnaround time data representing the time it takes to receive a response from memory,
Of the period from when the measurement target processor starts accessing the memory by executing the instruction to receiving a response from the memory, the time indicated by the contention-free turnaround time data is exceeded. For each order,
Specifying the period specified as the excess period for at least one of the instructions as a measurement result of a memory contention time;
A memory contention time measuring method characterized by the above. Computer
The measurement target processor starts the access to the memory by executing an instruction to access the memory, and then the measurement target processor does not exist in a state where there is no other device that accesses the memory. Contention-free turnaround time data storage means for storing contention-free turnaround time data representing the time taken to receive a response from the memory;
Of the period from when the measurement target processor starts accessing the memory by executing the instruction to receiving a response from the memory, the time indicated by the contention-free turnaround time data is exceeded. Individual overtime specifying means for specifying the excess period for each instruction,
Total excess time specifying means for specifying, as a measurement result of memory contention time, a period specified as the excess period for at least one of the instructions;
Program to make it function.

Images