JP2005258154A

JP2005258154A - Light emitting unit system

Info

Publication number: JP2005258154A
Application number: JP2004070678A
Authority: JP
Inventors: Chiaki Nakajima; 千明中島
Original assignee: Komaden Corp
Current assignee: Komaden Corp
Priority date: 2004-03-12
Filing date: 2004-03-12
Publication date: 2005-09-22
Anticipated expiration: 2024-03-12
Also published as: JP4653959B2

Abstract

<P>PROBLEM TO BE SOLVED: To enable an address to be efficiently set to a light emitting unit with less labor and to enable normal setting of the address to be easily confirmed. <P>SOLUTION: In a light emitting unit system, a signal line Sb of a leading LED unit 21 is set to logical 1, and microprocessors 31 to 3n of LED units 21 to 2n store address "1" into registers 41 to 4n on the basis of an address write start signal As and set signal lines Sc and signal lines Sd branched from the signal lines Sc to logical 0, and microprocessors 3i to 3n being in the middle of operation determine logic of input-side signal lines Sb on the basis of input of an address write instruction signal Ai. When the input-side signal lines Sb are logical 1, the microprocessors 3i to 3n write and set addresses "i" in registers 4i to non-volatile memories 5i, set signal lines Sc to logical 1 to light LEDs 7i, and set signal lines Sd to logical 1. When the input-side signal lines Sb are logical 0, the microprocessors 3i to 3n update the registers 4(i+1) to 4n to addresses "i+1" by adding one to addresses "i" therein. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、例えば大画面のＬＥＤ表示装置の画素等として用いられる発光ユニットに係り、バス接続の信号線から入力される制御信号に基づき各発光ユニットにアドレスを設定する発光ユニットシステムに関する。 The present invention relates to a light emitting unit used as a pixel of a large-screen LED display device, for example, and relates to a light emitting unit system that sets an address for each light emitting unit based on a control signal input from a signal line connected to a bus.

大画面のＬＥＤ表示装置の画素等として用いられる発光ユニットは、例えば図６のＬＥＤユニット１０の如く構成される。ＬＥＤユニット１０は、Ｒ（赤）、Ｇ（緑）、Ｂ（青）の三原色のＬＥＤ１１が基板１２上に点灯可能に配設され、ＬＥＤ１１及び基板１２は、ＬＥＤ１１の指向方向を開口に向けて箱形のケース１３内に収納される。ケース１３内にはＬＥＤ１１を発光制御するＬＥＤ駆動回路、マイクロプロセッサ、不揮発性メモリ等が収容される。 A light emitting unit used as a pixel or the like of a large screen LED display device is configured as an LED unit 10 of FIG. 6, for example. The LED unit 10 is arranged such that LEDs 11 of the three primary colors R (red), G (green), and B (blue) can be lit on the substrate 12, and the LED 11 and the substrate 12 direct the LED 11 toward the opening. It is stored in a box-shaped case 13. The case 13 houses an LED drive circuit for controlling the light emission of the LED 11, a microprocessor, a nonvolatile memory, and the like.

そして、ＬＥＤユニット１０のアドレスは、特許文献１の１８頁等で示されるようにディップスイッチで入力することにより設定され、設定されたアドレスは不揮発性メモリに記憶される。その後の点灯動作時には、バス接続されるＬＥＤユニット１０のうち所要のＬＥＤユニット１０のアドレスに対する点灯制御信号を送出し、点灯制御信号に応じて前記アドレスのＬＥＤユニット１０がＬＥＤ１１を発光する。 The address of the LED unit 10 is set by inputting with a dip switch as shown on page 18 of Patent Document 1, and the set address is stored in the nonvolatile memory. In the subsequent lighting operation, a lighting control signal for the address of the required LED unit 10 among the LED units 10 connected by the bus is sent, and the LED unit 10 at the address emits the LED 11 in accordance with the lighting control signal.

特表２００１−５１４４３２号公報Special table 2001-514432 gazette

しかしながら、ディップスイッチによるアドレス設定は、個々のＬＥＤユニット毎にディップスイッチを操作してアドレスを設定する必要があることから、アドレスの設定作業に多大な労力を要する。また、ＬＥＤユニットに対して所要のアドレスが正常に設定されたか否かを容易に確認することができる構成も望まれる。 However, the address setting by the DIP switch requires a great effort for address setting work because it is necessary to set the address by operating the DIP switch for each LED unit. In addition, a configuration that can easily confirm whether or not a required address has been normally set for the LED unit is also desired.

本発明は上記課題に鑑み提案するものであって、発光ユニットに少ない労力で効率的にアドレスを設定することができると共に、アドレスの正常設定を容易に確認することができる発光ユニットシステムを提供することを目的とする。 The present invention is proposed in view of the above problems, and provides a light-emitting unit system that can efficiently set an address in a light-emitting unit with little effort and can easily check the normal setting of the address. For the purpose.

本発明の発光ユニットシステムは、制御部と不揮発性メモリと発光体駆動回路が内蔵される各発光ユニットがバス接続されると共にカスケード接続され、バス接続の信号線から入力される制御信号に基づき各発光ユニットにアドレスを設定する発光ユニットシステムであって、先頭の発光ユニットの入力側のカスケード信号線を論理１とし、各発光ユニットの制御部が、バス接続信号線からの第１の制御信号の入力に基づき、設定されている初期アドレスをレジスタに格納すると共に、制御部と発光体駆動回路間の信号線、及び該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理０とし、バス接続信号線からの各発光ユニットのアドレス設定に対応して順次伝送される第２の制御信号の入力に基づき、入力側のカスケード信号線の論理を判定し、入力側のカスケード信号線が論理１の場合に、レジスタに格納されているアドレスを不揮発性メモリに書き込んで設定し、制御部と発光体駆動回路間の信号線を論理１として発光体を点灯し、且つ該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理１し、他方に於いて、入力側のカスケード信号線が論理０の場合に、レジスタに格納されているアドレスから所定の演算規則に基づき次アドレスを取得して、レジスタのアドレスを次アドレスに更新することを特徴とする。 In the light emitting unit system of the present invention, each light emitting unit including a control unit, a nonvolatile memory, and a light emitter driving circuit is connected by a bus and cascaded, and each light emitting unit system is based on a control signal input from a signal line connected to the bus. A light emitting unit system for setting an address to a light emitting unit, wherein the cascade signal line on the input side of the first light emitting unit is set to logic 1, and the control unit of each light emitting unit receives the first control signal from the bus connection signal line. Based on the input, the set initial address is stored in the register, and the signal line between the control unit and the light emitter driving circuit, and the cascade signal line branched from the signal line to the next light emitting unit control unit Based on the input of the second control signal that is sequentially transmitted corresponding to the address setting of each light emitting unit from the bus connection signal line with the logic 0, When the logic of the cascade signal line is determined and the cascade signal line on the input side is logic 1, the address stored in the register is set in the nonvolatile memory, and the signal line between the control unit and the light emitter drive circuit is set. Is set to logic 1, the light emitter is turned on, and the cascade signal line branched from the signal line to the next light emitting unit controller is set to logic 1, while the input side cascade signal line is set to logic 0. In this case, the next address is obtained from the address stored in the register based on a predetermined calculation rule, and the register address is updated to the next address.

また、本発明の発光ユニットシステムは、制御部と不揮発性メモリと発光体駆動回路が内蔵される各発光ユニットがバス接続されると共にカスケード接続され、バス接続の信号線から入力される制御信号に基づき各発光ユニットにアドレスを設定する発光ユニットシステムであって、先頭の発光ユニットの入力側のカスケード信号線を論理１とし、各発光ユニットの制御部が、バス接続信号線からの第１の制御信号の入力に基づき、設定されている初期アドレスをレジスタに格納すると共に、制御部と発光体駆動回路間の信号線、及び該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理０とし、バス接続信号線からの各発光ユニットのアドレス設定に対応して順次伝送される第２の制御信号の入力に基づき、入力側のカスケード信号線の論理を判定し、入力側のカスケード信号線が論理１の場合に、制御部と発光体駆動回路間の信号線を論理１として発光体を点灯し、且つ該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理１とし、他方に於いて、入力側のカスケード信号線が論理０の場合に、レジスタに格納されているアドレスから所定の演算規則に基づき次アドレスを取得して、レジスタのアドレスを次アドレスに更新し、カウントする第２の制御信号の入力回数が全発光ユニット数になることに基づき、若しくは全発光ユニット数の第２の制御信号の出力後に伝送されるバス接続信号線からの第３の制御信号の入力に基づき、レジスタに格納されている各アドレスを不揮発性メモリに書き込んで設定し、正常なアドレス設定ができない場合には、制御部と発光駆動回路間の信号線を論理０として発光体を消灯することを特徴とする。 In the light emitting unit system of the present invention, the control unit, the nonvolatile memory, and each light emitting unit incorporating the light emitter driving circuit are connected to each other by a bus and cascaded, and a control signal input from a signal line connected to the bus In this light emitting unit system, an address is set for each light emitting unit, the cascade signal line on the input side of the first light emitting unit is set to logic 1, and the control unit of each light emitting unit performs the first control from the bus connection signal line. Based on the signal input, the set initial address is stored in the register, the signal line between the control unit and the light emitter driving circuit, and the cascade signal branched from the signal line to reach the next-order light emitting unit control unit Based on the input of the second control signal that is sequentially transmitted corresponding to the address setting of each light emitting unit from the bus connection signal line, the line is set to logic 0. The logic of the cascade signal line on the side is determined, and when the cascade signal line on the input side is logic 1, the light emitter is turned on with the signal line between the control unit and the light emitter drive circuit as logic 1, and from the signal line When the cascade signal line that branches and reaches the next-order light-emitting unit controller is logic 1, and the other side is the logic 0 on the input side, the predetermined operation rule is determined from the address stored in the register. To obtain the next address, update the register address to the next address, and the second control signal to be counted becomes the total number of light emitting units or the second control of the total number of light emitting units Based on the input of the third control signal from the bus connection signal line transmitted after the signal is output, each address stored in the register is written and set in the non-volatile memory, and the normal address is set. If it can not less set is characterized in that turns off the light emitter signal lines between the control unit light emission drive circuit as a logic zero.

また、本発明の発光ユニットシステムは、制御部と不揮発性メモリと発光体駆動回路が内蔵される各発光ユニットがバス接続されると共にカスケード接続され、バス接続の信号線から入力される制御信号に基づき各発光ユニットにアドレスを設定する発光ユニットシステムであって、先頭の発光ユニットの入力側のカスケード信号線を論理１とし、各発光ユニットの制御部が、バス接続信号線からの第１の制御信号の入力に基づき、制御部と発光体駆動回路間の信号線、及び該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理０とし、バス接続信号線からの各発光ユニットのアドレス設定に対応して順次伝送される第２の制御信号及びアドレスの入力に基づき、入力側のカスケード信号線の論理を判定し且つレジスタにアドレスが未格納であるか判定し、入力側のカスケード信号線が論理１で且つレジスタにアドレスが未格納の場合に、入力されたアドレスをレジスタに格納して不揮発性メモリに書き込んで設定し、制御部と発光体駆動回路間の信号線を論理１として発光体を点灯し、且つ該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理１とすることを特徴とする。 In the light emitting unit system of the present invention, the control unit, the nonvolatile memory, and each light emitting unit incorporating the light emitter driving circuit are connected to each other by a bus and cascaded, and a control signal input from a signal line connected to the bus In this light emitting unit system, an address is set for each light emitting unit, the cascade signal line on the input side of the first light emitting unit is set to logic 1, and the control unit of each light emitting unit performs the first control from the bus connection signal line. Based on the signal input, the signal line between the control unit and the light emitter drive circuit, and the cascade signal line that branches from the signal line and reaches the light emitting unit control unit of the next order is set to logic 0, and each signal from the bus connection signal line Based on the input of the second control signal and the address sequentially transmitted corresponding to the address setting of the light emitting unit, the logic of the cascade signal line on the input side is determined and the signal is recorded. If the input cascade signal line is logic 1 and the address is not stored in the register, the input address is stored in the register and written to the non-volatile memory. The signal line between the control unit and the light emitter drive circuit is set to logic 1, and the light emitter is turned on, and the cascade signal line branched from the signal line to the next light emitting unit control unit is set to logic 1. Features.

また、本発明の発光ユニットシステムは、制御部と不揮発性メモリと発光体駆動回路が内蔵される各発光ユニットがバス接続されると共にカスケード接続され、バス接続の信号線から入力される制御信号に基づき各発光ユニットにアドレスを設定する発光ユニットシステムであって、先頭の発光ユニットの入力側のカスケード信号線を論理１とし、各発光ユニットの制御部が、バス接続信号線からの第１の制御信号及び初期アドレスの入力に基づき、入力された初期アドレスをレジスタに格納すると共に、制御部と発光体駆動回路間の信号線、及び該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理０とし、バス接続信号線からの各発光ユニットのアドレス設定に対応して順次伝送される第２の制御信号の入力に基づき、入力側のカスケード信号線の論理を判定し、入力側のカスケード信号線が論理１の場合に、制御部と発光体駆動回路間の信号線を論理１として発光体を点灯し、且つ該信号線から分岐して次順位の発光ユニット制御部に至るカスケード信号線を論理１とし、他方に於いて、入力側のカスケード信号線が論理０の場合に、レジスタに格納されているアドレスから所定の演算規則に基づき次アドレスを取得して、レジスタのアドレスを次アドレスに更新し、カウントする第２の制御信号の入力回数が全発光ユニット数になることに基づき、若しくは全発光ユニット数の第２の制御信号の出力後に伝送されるバス接続信号線からの第３の制御信号の入力に基づき、レジスタに格納されている各アドレスを不揮発性メモリに書き込んで設定し、正常なアドレス設定ができない場合には、制御部と発光駆動回路間の信号線を論理０として発光体を消灯することを特徴とする。 In the light emitting unit system of the present invention, the control unit, the nonvolatile memory, and each light emitting unit incorporating the light emitter driving circuit are connected to each other by a bus and cascaded, and a control signal input from a signal line connected to the bus In this light emitting unit system, an address is set for each light emitting unit, the cascade signal line on the input side of the first light emitting unit is set to logic 1, and the control unit of each light emitting unit performs the first control from the bus connection signal line. Based on the input of the signal and the initial address, the input initial address is stored in the register, and the signal line between the control unit and the light emitter driving circuit and the signal line branch to the next order light emitting unit control unit. Input of second control signal sequentially transmitted corresponding to address setting of each light emitting unit from bus connection signal line with cascade signal line set to logic 0 Based on this, the logic of the cascade signal line on the input side is determined, and when the cascade signal line on the input side is logic 1, the light emitter is turned on with the signal line between the control unit and the light emitter drive circuit as logic 1; When the cascade signal line that branches from the signal line and reaches the light emitting unit controller of the next order is set to logic 1, and on the other hand, the cascade signal line on the input side is logic 0, the predetermined value is determined from the address stored in the register. The next address is obtained based on the calculation rule of (2), the register address is updated to the next address, and the number of times of input of the second control signal to be counted becomes the total number of light emitting units, or the number of all light emitting units Based on the input of the third control signal from the bus connection signal line transmitted after the output of 2 control signals, each address stored in the register is written to the nonvolatile memory and set And it may not be successful address configuration, characterized by turning off the light emitter signal lines between the control unit light emission drive circuit as a logic zero.

尚、本発明には、各発明や実施形態の構成に他の発明や実施形態の構成を追加したものや、各発明や実施形態の構成を他の発明や実施形態の構成に変更したものや、各発明や実施形態の構成を部分的な効果を奏する限度で削除したものも含まれる。また、発光体はＬＥＤ以外の適宜の発光体とすることが可能である。 In the present invention, the configuration of each invention or embodiment is added with the configuration of another invention or embodiment, the configuration of each invention or embodiment is changed to the configuration of another invention or embodiment, Also included are those obtained by deleting the configurations of the inventions and embodiments to the extent that partial effects are achieved. The light emitter can be any appropriate light emitter other than an LED.

本発明の発光ユニットシステムは、アドレス設定装置の操作等で伝送する制御信号でバス接続された発光ユニットにアドレスを設定することが可能であるから、各発光ユニットへ少ない労力で効率的にアドレスを設定することができると共に、発光体の点灯や消灯をアドレス設定に連動させることで、発光ユニットに対するアドレスの正常設定を容易に確認することができる。更に、既に存在する調光制御信号を伝送する信号線やＬＥＤ駆動回路の駆動制御信号を伝送する信号線等を利用して、各発光ユニットにアドレスを設定することができるので、アドレスを設定するための特別な信号線等の器材を用いずにアドレスを設定することができる。 Since the light emitting unit system of the present invention can set addresses to the light emitting units connected by a bus with a control signal transmitted by operating an address setting device or the like, the addresses can be efficiently assigned to each light emitting unit with little effort. In addition to being able to set, it is possible to easily confirm the normal setting of the address for the light emitting unit by linking the lighting of the light emitter to the address setting. Furthermore, an address can be set for each light emitting unit using a signal line for transmitting a dimming control signal that already exists, a signal line for transmitting a drive control signal for an LED drive circuit, and the like. Therefore, an address can be set without using a special signal line or the like.

また、アドレス設定に関する制御信号を伝送し、その制御信号に基づき先頭の発光ユニットが初期アドレスを設定し、例えば初期アドレスに所定値を順次インクリメントして次順位の発光ユニットのアドレスとするなど、所定の演算規則に従い次順位の発光ユニットのアドレスを決定して設定することにより、特別なアドレス管理やアドレス自体の伝送を要せずに、簡単な処理で各発光ユニットにアドレスを設定することができる。他方において、バス接続の信号線で設定するアドレスを発光ユニットに伝送する場合には、発光ユニットに対して任意のアドレスを割り当てることができる。 In addition, a control signal related to address setting is transmitted, and the first light-emitting unit sets an initial address based on the control signal. For example, a predetermined value is sequentially incremented to the address of the next-order light-emitting unit. By determining and setting the address of the next light emitting unit according to the calculation rule, it is possible to set the address to each light emitting unit with a simple process without requiring special address management or transmission of the address itself. . On the other hand, when the address set by the signal line connected to the bus is transmitted to the light emitting unit, an arbitrary address can be assigned to the light emitting unit.

また、制御信号を入力して全ての発光ユニットに設定されるアドレスを保持させた後に、全ての発光ユニットに同時にアドレスを書込設定する構成により、アドレス設定に関連する制御信号の正当性を検証した後に書込を行うことが可能となり、その正当性の検証を容易且つ確実に行うことができると共に、書込作業の中断によるアドレス設定処理の異常終了を極力回避することができる。更に、全ての発光ユニットに対するアドレスが保持された段階でアドレスの設定を行うことにより、前順位の発光ユニットのアドレス書込作業が終了するまでの時間を待たずに、次順位の発光ユニットにアドレスを保持させる処理を行うことができる。 In addition, after the control signal is input and the address set to all the light emitting units is held, the address is set to be written to all the light emitting units simultaneously, thereby verifying the validity of the control signal related to the address setting. Then, writing can be performed, and the validity can be verified easily and reliably, and abnormal termination of the address setting process due to interruption of the writing operation can be avoided as much as possible. Further, by setting the address when the addresses for all the light-emitting units are held, the address of the next-order light-emitting unit is addressed without waiting for the address writing operation of the previous light-emitting unit to be completed. Can be performed.

本発明の発光ユニットシステムについて、第１〜第４実施形態のＬＥＤユニットシステムに基づき説明する。 The light emitting unit system of the present invention will be described based on the LED unit systems of the first to fourth embodiments.

先ず、第１から第４実施形態のＬＥＤユニットシステムは、図１に示すように、ＬＥＤユニット２ｉ（１≦ｉ≦ｎ）がバス接続されていると共に、カスケード接続されている構成であり、ＬＥＤユニット２１、２２、・・２ｎは、アドレス設定装置１に信号線Ｓａでバス接続されており、アドレス設定装置１は、制御プログラムに従って動作する制御部、記憶部、タイマー、操作入力部等を備え、後述するアドレス書込開始信号やアドレス書込指示信号を出力し、信号線Ｓａを介してこれらの信号を各ＬＥＤユニット２ｉに伝送する。バス接続の信号線Ｓａは、アドレス設定後は調光制御信号を伝送する信号線となる。 First, as shown in FIG. 1, the LED unit system of the first to fourth embodiments has a configuration in which LED units 2i (1 ≦ i ≦ n) are connected in a bus and cascade connected, The units 21, 22,..., 2n are connected to the address setting device 1 by a signal line Sa, and the address setting device 1 includes a control unit, a storage unit, a timer, an operation input unit, and the like that operate according to a control program. Then, an address write start signal and an address write instruction signal, which will be described later, are output, and these signals are transmitted to each LED unit 2i via the signal line Sa. The bus-connected signal line Sa becomes a signal line for transmitting a dimming control signal after address setting.

ＬＥＤユニット２ｉは、青のＬＥＤ７ｉ（１≦ｉ≦ｎ）を有すると共に、その内部にマイクロプロセッサ３ｉ（１≦ｉ≦ｎ）を有し、マイクロプロセッサ３ｉは制御プログラムを格納するフラッシュメモリやデータ処理領域となるＲＡＭ等のメモリを内蔵している。４ｉ（１≦ｉ≦ｎ）はマイクロプロセッサ３ｉ内のレジスタである。更に、ＬＥＤユニット２ｉには、ＥＥＰＲＯＭなど書換可能な不揮発性メモリ５ｉ（１≦ｉ≦ｎ）、ＬＥＤ７ｉの点灯・消灯を制御するＬＥＤ駆動回路６ｉ（１≦ｉ≦ｎ）が、それぞれマイクロプロセッサ３ｉに接続して設けられている。尚、図１には省略したが、ＬＥＤユニット２ｉは青のＬＥＤ７ｉ以外に赤や緑のＬＥＤを有し、これらの三原色のＬＥＤはＬＥＤ駆動回路６ｉで点灯や消灯を制御され、また、ＬＥＤユニット２ｉは図示しない電源系統を有する。 The LED unit 2i has a blue LED 7i (1 ≦ i ≦ n) and a microprocessor 3i (1 ≦ i ≦ n) therein, and the microprocessor 3i has a flash memory for storing a control program and data processing A memory such as a RAM serving as a region is incorporated. 4i (1 ≦ i ≦ n) is a register in the microprocessor 3i. Further, the LED unit 2i includes a rewritable non-volatile memory 5i (1 ≦ i ≦ n) such as an EEPROM, and an LED drive circuit 6i (1 ≦ i ≦ n) for controlling the turning on / off of the LEDs 7i, respectively. It is provided in connection with. Although not shown in FIG. 1, the LED unit 2i has red and green LEDs in addition to the blue LED 7i, and these three primary color LEDs are controlled to be turned on and off by the LED drive circuit 6i. 2i has a power supply system (not shown).

また、マイクロプロセッサ３ｉはＬＥＤ駆動回路６ｉの駆動制御信号が入力される信号線Ｓｂ、信号線Ｓｃにそれぞれ接続されており、マイクロプロセッサ３ｉとＬＥＤ駆動回路６ｉは信号線Ｓｃを介して接続され、更に、信号線Ｓｃからは信号線Ｓｄが分岐され、分岐された信号線Ｓｄは次順位のＬＥＤユニット２（ｉ＋１）の信号線Ｓｂに接続されている。即ち、ＬＥＤユニット２ｉとＬＥＤユニット２（ｉ＋１）は、信号線Ｓｂ、Ｓｄを介してカスケード接続されている。 The microprocessor 3i is connected to the signal line Sb and the signal line Sc to which the drive control signal of the LED drive circuit 6i is input. The microprocessor 3i and the LED drive circuit 6i are connected via the signal line Sc. Further, the signal line Sd is branched from the signal line Sc, and the branched signal line Sd is connected to the signal line Sb of the LED unit 2 (i + 1) of the next order. That is, the LED unit 2i and the LED unit 2 (i + 1) are cascade-connected via the signal lines Sb and Sd.

次に、第１実施形態の発光ユニットシステム於けるアドレス設定について説明する。第１実施形態のアドレス設定では、図２に示すように、アドレス設定装置１が操作入力に応じてアドレス書込開始信号Ａｓを出力し、アドレス書込開始信号Ａｓはバス接続の信号線Ｓａを介して各ＬＥＤユニット２１、２２、・・２ｎのマイクロプロセッサ３１、３２、・・３ｎに入力される（Ｓ１０１）。各マイクロプロセッサ３１、３２、・・３ｎは、アドレス書込開始信号Ａｓの入力に応じ、各レジスタ４１、４２、・・４ｎに初期アドレスとして“１”を格納すると共に、所定電圧範囲等で特定される論理０と論理１の状態の内、信号線Ｓｃを論理０とし、更に、信号線Ｓｃから分岐する信号線Ｓｄ、及び信号線Ｓｄと連続する或いは接続される次順位のＬＥＤユニット２ｉの信号線Ｓｂを論理０、換言すれば先頭のＬＥＤユニット２１の信号線Ｓｂ以外の全ての信号線Ｓｂ、Ｓｃ、Ｓｄを論理０とし、リセットする（Ｓ１０２）。また、先頭のＬＥＤユニット２１の信号線Ｓｂは、所定電圧の負荷等で常に論理１としておく。 Next, address setting in the light emitting unit system of the first embodiment will be described. In the address setting of the first embodiment, as shown in FIG. 2, the address setting device 1 outputs an address write start signal As in response to an operation input, and the address write start signal As is connected to a bus-connected signal line Sa. Are input to the microprocessors 31, 32,... 3n of the LED units 21, 22,. Each microprocessor 31, 32,... 3n stores “1” as an initial address in each register 41, 42,... 4n in response to the input of the address write start signal As and is specified by a predetermined voltage range or the like. Of the logic 0 and logic 1 states, the signal line Sc is set to logic 0, and the signal line Sd branched from the signal line Sc and the LED unit 2i of the next order connected to or connected to the signal line Sd The signal line Sb is set to logic 0, in other words, all the signal lines Sb, Sc and Sd other than the signal line Sb of the head LED unit 21 are set to logic 0 and reset (S102). Further, the signal line Sb of the leading LED unit 21 is always set to logic 1 due to a predetermined voltage load or the like.

その後、アドレス設定装置１が操作入力に応じてアドレス書込指示信号Ａ１を出力し、アドレス書込指示信号Ａ１はバス接続の信号線Ｓａを介して各ＬＥＤユニット２１〜２ｎのマイクロプロセッサ３１〜３ｎに入力される（Ｓ１０３）。各マイクロプロセッサ３１〜３ｎは、アドレス書込指示信号Ａ１の入力に応じ、電圧チェック等で入力側の信号線Ｓｂの論理状態が論理０か論理１かを判定する（Ｓ１０４）。 Thereafter, the address setting device 1 outputs an address write instruction signal A1 in response to the operation input, and the address write instruction signal A1 is sent to the microprocessors 31 to 3n of the LED units 21 to 2n via the bus-connected signal line Sa. (S103). Each of the microprocessors 31 to 3n determines whether the logic state of the signal line Sb on the input side is logic 0 or logic 1 by voltage check or the like according to the input of the address write instruction signal A1 (S104).

前記判定の結果、入力側の信号線Ｓｂが論理１である先頭のＬＥＤユニット２１のマイクロプロセッサ３１は、レジスタ４１に格納されているアドレス“１”を不揮発性メモリ５１にＬＥＤユニット２１のアドレスとして書き込み（Ｓ１０５）、正常な書き込みの終了に応じ、出力側の信号線Ｓｃを論理１とする。前記信号線Ｓｃが論理１の状態になることに基づき、その信号線Ｓｃから分岐する信号線Ｓｄ、及び前記信号線Ｓｄに連続する次順位のＬＥＤユニット２２の信号線Ｓｂは論理１となると共に、論理１が入力されるＬＥＤ駆動回路６１は点灯制御でＬＥＤ７１を点灯し、ＬＥＤユニット２１のアドレスの正常な書込を報知し、この後、マイクロプロセッサ３１は全てのＬＥＤユニット２１〜２ｎのアドレス書込終了を書込終了信号等で認識するまで動作を停止する（Ｓ１０６）。他方、Ｓ１０４の判定の結果、入力側の信号線Ｓｂが論理０であるＬＥＤユニット２２〜２ｎのマイクロプロセッサ３２〜３ｎは、レジスタ４２〜４ｎに格納しているアドレス“１”に設定された加算値である１を加算して更新し、各レジスタ４２〜４ｎにアドレス“２”を格納する（Ｓ１０７）。尚、初期アドレスや設定加算値には１以外の適宜の数値を設定することが可能である。 As a result of the determination, the microprocessor 31 of the first LED unit 21 whose input-side signal line Sb is logic 1 uses the address “1” stored in the register 41 as the address of the LED unit 21 in the nonvolatile memory 51. In response to the end of writing (S105) and normal writing, the signal line Sc on the output side is set to logic 1. Based on the fact that the signal line Sc is in the logic 1 state, the signal line Sd branched from the signal line Sc and the signal line Sb of the LED unit 22 of the next order continuous to the signal line Sd become logic 1 and The LED drive circuit 61 to which logic 1 is input lights the LED 71 by lighting control and notifies the normal writing of the address of the LED unit 21, and thereafter, the microprocessor 31 addresses all the LED units 21 to 2n. The operation is stopped until the end of writing is recognized by a writing end signal or the like (S106). On the other hand, as a result of the determination in S104, the microprocessors 32 to 3n of the LED units 22 to 2n whose input-side signal line Sb is logic 0 add the address set to the address “1” stored in the registers 42 to 4n. The value 1 is added and updated, and the address “2” is stored in each of the registers 42 to 4n (S107). It should be noted that an appropriate numerical value other than 1 can be set for the initial address and the set addition value.

また、アドレス設定装置１は、アドレス書込指示信号Ａ１の出力に応じて、アドレス書込指示信号Ａｉを設定されているＬＥＤユニット２１〜２ｎの全個数ｎだけ出力したか判断し（Ｓ１０８）、出力していない場合には、設定されている所定時間をタイマーで計測し、所定時間経過に応じてアドレス書込指示信号Ａ２を出力し、上記Ｓ１０３〜Ｓ１０７と同様の処理を実行し、更に、アドレス書込指示信号Ａｎを出力するまで同様の処理を繰り返し実行する。即ち、アドレス設定装置１がアドレス書込指示信号Ａｉを出力し、各マイクロプロセッサ３１〜３ｎにアドレス書込指示信号Ａｉを入力し、アドレス設定が完了して動作が停止しているＬＥＤユニット以外の各ＬＥＤユニット２ｉ〜２ｎのマイクロプロセッサ３ｉ〜３ｎは、その入力に応じて、信号線Ｓｂの論理が０か１かを判定し、信号線Ｓｂが論理１のＬＥＤユニット２ｉのマイクロプロセッサ３ｉは、レジスタ４ｉのアドレス“ｉ”を不揮発性メモリ５ｉに書き込み、正常な書き込みの終了に応じて出力側の信号線Ｓｃを論理１とし、連続する信号線Ｓｄ、次順位のＬＥＤユニット２（ｉ＋１）の信号線Ｓｂの論理を０とし、動作を停止すると共に、論理１が入力されるＬＥＤ駆動回路６ｉはＬＥＤ７ｉを点灯する。他方、入力側の信号線Ｓｂが論理０のＬＥＤユニット２（ｉ＋１）〜２ｎのマイクロプロセッサ３（ｉ＋１）〜３ｎは、そのレジスタ４（ｉ＋１）〜４ｎに格納しているアドレス“ｉ”に１を加算して更新し、各レジスタ４（ｉ＋１）〜４ｎにアドレス“ｉ＋１”を格納する。 Further, the address setting device 1 determines whether the address writing instruction signal Ai is output by the total number n of the set LED units 21 to 2n according to the output of the address writing instruction signal A1 (S108). If not, the set predetermined time is measured by a timer, the address write instruction signal A2 is output as the predetermined time elapses, and the same processing as in S103 to S107 is executed. The same processing is repeatedly executed until the address write instruction signal An is output. That is, the address setting device 1 outputs the address write instruction signal Ai, inputs the address write instruction signal Ai to each of the microprocessors 31 to 3n, and the LED unit other than the LED unit whose operation is stopped after the address setting is completed. The microprocessors 3i to 3n of the LED units 2i to 2n determine whether the logic of the signal line Sb is 0 or 1 according to the input, and the microprocessor 3i of the LED unit 2i whose signal line Sb is logic 1 The address “i” of the register 4i is written to the nonvolatile memory 5i, and the signal line Sc on the output side is set to logic 1 in accordance with the end of normal writing, and the continuous signal line Sd and the LED unit 2 (i + 1) of the next order The logic of the signal line Sb is set to 0, the operation is stopped, and the LED drive circuit 6i to which the logic 1 is input lights the LED 7i. On the other hand, the microprocessors 3 (i + 1) to 3n of the LED units 2 (i + 1) to 2n whose input-side signal line Sb is logic 0 are assigned 1 to the address “i” stored in the registers 4 (i + 1) to 4n. Is added and updated, and the address “i + 1” is stored in each of the registers 4 (i + 1) to 4n.

そして、アドレス設定装置１が最終のアドレス書込指示信号Ａｎを出力し、アドレス書込指示信号Ａｎが入力されるＬＥＤユニット２ｎのマイクロプロセッサ３ｎが、レジスタ４ｎのアドレス“ｎ”を不揮発性メモリ５ｎに書き込み、出力側の信号線Ｓｃを論理１として動作を停止し、論理１が入力されるＬＥＤ駆動回路６ｎはＬＥＤ７ｎを点灯することにより、アドレス書込指示信号ＡｉのＬＥＤユニット２１〜２ｎの全個数ｎだけの出力が完了した場合には、全てのＬＥＤ７１、７２、・・７ｎが点灯しているか確認し（Ｓ１０９）、点灯している場合にはアドレスの設定処理が完了する。 Then, the address setting device 1 outputs the final address write instruction signal An, and the microprocessor 3n of the LED unit 2n to which the address write instruction signal An is input, sets the address “n” of the register 4n to the nonvolatile memory 5n. And the output signal line Sc is set to logic 1 to stop the operation, and the LED drive circuit 6n to which logic 1 is input turns on the LED 7n, so that all the LED units 21 to 2n of the address write instruction signal Ai are turned on. When the output of the number n is completed, it is confirmed whether all the LEDs 71, 72,... 7n are lit (S109), and when they are lit, the address setting process is completed.

尚、マイクロプロセッサ３ｉが、レジスタ４ｉに格納されているアドレス“ｉ”を不揮発性メモリ５ｉに書込設定する際に、正常な書込設定がなされたか否かを判定する構成としては、例えばＬＥＤユニット２ｉのマイクロプロセッサ３ｉが、不揮発性メモリ５ｉに書き込んだアドレスを読み出し、そのアドレスとレジスタ４ｉに一時格納しているアドレスを対比し、両者が一致するか判定する構成等とする。また、正常な書込設定ができなかった場合には、例えばマイクロプロセッサ３ｉと赤色のＬＥＤのＬＥＤ駆動回路とを接続する信号線を論理１とし、赤色ＬＥＤを点灯するなど、設定されている異常を示す発光パターンでＬＥＤを点灯するようにしてもよい。 As a configuration for determining whether or not the normal write setting is made when the microprocessor 3i writes and sets the address “i” stored in the register 4i to the nonvolatile memory 5i, for example, an LED The microprocessor 3i of the unit 2i reads the address written in the nonvolatile memory 5i, compares the address with the address temporarily stored in the register 4i, and determines whether or not they match. Further, if normal writing setting cannot be made, for example, the signal line connecting the microprocessor 3i and the LED driving circuit of the red LED is set to logic 1, and the red LED is turned on. The LED may be lit with a light emission pattern indicating.

上記第１実施形態に於けるアドレス設定では、各ＬＥＤユニット２ｉに於いて、ＬＥＤアドレスｉの不揮発性メモリ５ｉへの正常な書込終了に応じて出力側信号線Ｓｃを論理１に設定し、ＬＥＤ７ｉを点灯するので、各ＬＥＤユニット２ｉにアドレスｉの正常書込をＬＥＤ７ｉの点灯状態だけで非常に容易に確認することができる。換言すれば、最後のＬＥＤユニット２ｎのＬＥＤ７ｎが点灯していれば、全てのＬＥＤユニット２１〜２ｎに正常にアドレスが設定されたことが分かり、アドレス設定の確認作業が非常に容易になる。また、アドレス設定装置１からはアドレス自体を送信せず、初期アドレスや前順位のアドレスに設定値をインクリメントして次順位のアドレスとするので、簡単な処理でアドレスを設定することができる。 In the address setting in the first embodiment, in each LED unit 2i, the output side signal line Sc is set to logic 1 in accordance with the normal writing end of the LED address i to the nonvolatile memory 5i. Since the LED 7i is lit, normal writing of the address i to each LED unit 2i can be confirmed very easily only by the lighting state of the LED 7i. In other words, if the LED 7n of the last LED unit 2n is lit, it can be understood that the addresses have been normally set in all the LED units 21 to 2n, and the address setting confirmation work becomes very easy. Further, the address setting device 1 does not transmit the address itself, but increments the set value to the initial address or the previous order address to obtain the next order address. Therefore, the address can be set by simple processing.

次に、第２実施形態の発光ユニットシステムに於けるアドレス設定について説明するが、特に言及しない箇所は第１実施形態と同様である。図３に示す第２実施形態のアドレス設定では、先ず、第１実施形態のＳ１０１〜Ｓ１０４と同様の処理であるＳ２０１〜Ｓ２０４を実行し、Ｓ２０４の論理判定の結果、入力側の信号線Ｓｂが論理１である先頭のＬＥＤユニット２１のマイクロプロセッサ３１は、制御プログラムに設定されている設定時間の経過後に信号線Ｓｃを論理１として、その信号線Ｓｃから分岐する信号線Ｓｄと前記信号線Ｓｄに連続する次順位のＬＥＤユニット２２の信号線Ｓｂを論理１にすると共に、論理１が入力されるＬＥＤ駆動回路６１は点灯制御でＬＥＤ７１を点灯する（Ｓ２０５）。他方、Ｓ２０４の判定の結果、入力側の信号線Ｓｂが論理０であるＬＥＤユニット２２〜２ｎのマイクロプロセッサ３２〜３ｎは、そのレジスタ４２〜４ｎに格納しているアドレス“１”に１を加算して更新し、各レジスタ４２〜４ｎにアドレス“２”を格納する（Ｓ２０６）。また、各マイクロプロセッサ３１〜３ｎは、アドレス書込指示信号Ａｉの入力回数をカウントしてメモリの所定記憶領域に保持し、その入力に応じて順次入力回数を更新する。 Next, address setting in the light emitting unit system of the second embodiment will be described. The parts not particularly mentioned are the same as those of the first embodiment. In the address setting of the second embodiment shown in FIG. 3, first, S201 to S204, which are the same processes as S101 to S104 of the first embodiment, are executed. As a result of the logic determination of S204, the signal line Sb on the input side is changed. The microprocessor 31 of the first LED unit 21 that is logic 1 sets the signal line Sc to logic 1 after the set time set in the control program has passed, and the signal line Sd branched from the signal line Sc and the signal line Sd. The signal line Sb of the LED unit 22 of the next sequential order is set to logic 1, and the LED driving circuit 61 to which logic 1 is input lights the LED 71 by lighting control (S205). On the other hand, as a result of the determination of S204, the microprocessors 32 to 3n of the LED units 22 to 2n whose input side signal line Sb is logic 0 add 1 to the address "1" stored in the registers 42 to 4n. The address "2" is stored in each of the registers 42 to 4n (S206). Each of the microprocessors 31 to 3n counts the number of times the address write instruction signal Ai is input, holds it in a predetermined storage area of the memory, and sequentially updates the number of inputs according to the input.

その後、アドレス書込指示信号ＡｉをＬＥＤユニット２１〜２ｎの全個数ｎだけ出力していない場合には（Ｓ２０７）、Ｓ２０３〜Ｓ２０６と同様の処理を繰り返し実行する。即ち、アドレス設定装置１が出力するアドレス書込指示信号Ａｉを各ＬＥＤユニット２１〜２ｎのマイクロプロセッサ３１〜３ｎに入力し、前記入力に応じて動作中の各マイクロプロセッサ３ｉ〜３ｎは入力側の信号線Ｓｂが論理０か論理１かを判定し、入力側信号線Ｓｂが論理１であるＬＥＤユニット２ｉのマイクロプロセッサ３ｉは、論理１の判定から制御プログラムに設定されている設定時間の経過後に信号線Ｓｃ、その信号線Ｓｃから分岐する信号線Ｓｄ、前記信号線Ｓｄに連続する次順位のＬＥＤユニット２（ｉ＋１）の信号線Ｓｂを論理１とし、ＬＥＤ駆動回路６ｉが点灯制御してＬＥＤ７ｉを点灯し、動作を停止すると共に、入力側信号線Ｓｂが論理０であるＬＥＤユニット２（ｉ＋１）〜２ｎのマイクロプロセッサ３（ｉ＋１）〜３ｎが、そのレジスタ４（ｉ＋１）〜４ｎに格納しているアドレス“ｉ”に１を加算して更新し、各レジスタ４（ｉ＋１）〜４ｎにアドレス“ｉ＋１”を格納する。 Thereafter, when the address write instruction signal Ai is not output in the total number n of the LED units 21 to 2n (S207), the same processing as S203 to S206 is repeatedly executed. That is, the address write instruction signal Ai output from the address setting device 1 is input to the microprocessors 31 to 3n of the LED units 21 to 2n, and each of the microprocessors 3i to 3n in operation according to the input is connected to the input side. It is determined whether the signal line Sb is logic 0 or logic 1, and the microprocessor 3i of the LED unit 2i whose input side signal line Sb is logic 1 has passed the set time set in the control program from the determination of logic 1. The signal line Sc, the signal line Sd branched from the signal line Sc, and the signal line Sb of the LED unit 2 (i + 1) of the next order continuous to the signal line Sd are set to logic 1, and the LED drive circuit 6i is controlled to be lit and the LED 7i Is turned on, the operation is stopped, and the microprocessor 3 (i +) of the LED units 2 (i + 1) to 2n whose input side signal line Sb is logic 0 ) 3n is, the register 4 (i + 1) ~4n one to have the address "i" which is stored by adding the update, and stores the address "i + 1" in each register 4 (i + 1) ~4n.

そして、アドレス設定装置１が最終のアドレス書込指示信号Ａｎを出力し、アドレス書込指示信号Ａｎが入力されるＬＥＤユニット２ｎのマイクロプロセッサ３ｎが、論理１の判定から制御プログラムに設定されている設定時間の経過後に信号線Ｓｃを論理０とし、ＬＥＤ駆動回路６ｎでＬＥＤ７ｎを点灯すると共に、マイクロプロセッサ３１〜３ｎが、カウントしているアドレス書込指示信号Ａｉの入力回数がＬＥＤユニット２１〜２ｎの全個数のｎ回になったことを認識した場合には（Ｓ２０７）、各ＬＥＤユニット２１〜２ｎのマイクロプロセッサ３１〜３ｎは、前記入力回数のｎ回到達から設定されている所定時間の経過後に、各レジスタ４１〜４ｎに格納されているアドレス１〜ｎを不揮発性メモリ５１〜５ｎにそれぞれ書き込む（Ｓ２０８）。この際、正常な書き込みが実行できなかった場合には、正常書込ができなかったＬＥＤユニット２ｉのマイクロプロセッサ３ｉは、接続されている信号線Ｓｃを論理０とし、ＬＥＤ駆動回路６ｉでＬＥＤ７ｉを消灯する（Ｓ２０８）。最後に、全てのＬＥＤ７１、７２、・・７ｎが点灯しているか確認し（Ｓ２０９）、点灯している場合にはアドレスの設定処理が完了する。 Then, the address setting device 1 outputs the final address write instruction signal An, and the microprocessor 3n of the LED unit 2n to which the address write instruction signal An is input is set to the control program from the determination of logic 1. After the set time elapses, the signal line Sc is set to logic 0, the LED drive circuit 6n turns on the LED 7n, and the microprocessors 31 to 3n input the address write instruction signal Ai counted by the LED units 21 to 2n. (S207), the microprocessors 31 to 3n of the LED units 21 to 2n have passed a predetermined time set since the number of inputs reached n times. Later, addresses 1 to n stored in the registers 41 to 4n are written in the non-volatile memories 51 to 5n, respectively. S208). At this time, if normal writing cannot be performed, the microprocessor 3i of the LED unit 2i that has failed to perform normal writing sets the connected signal line Sc to logic 0, and causes the LED drive circuit 6i to turn on the LED 7i. The light is turned off (S208). Finally, it is confirmed whether all the LEDs 71, 72,... 7n are lit (S209).

尚、前記構成に代え、ＬＥＤ７ｉを点灯するＳ２０５の際に、アドレス書込動作信号Ａｗが入力されるまでＬＥＤユニット２ｉのマイクロプロセッサ３ｉの動作を停止し、アドレス設定装置１がアドレス書込指示信号Ａｉの出力回数をカウントし、アドレス書込指示信号ＡｉをＬＥＤユニット２１〜２ｎの全個数ｎだけの出力した場合に、設定されている所定時間をカウントし、前記所定時間の経過後にアドレス書込動作信号Ａｗを出力し、他方で、各ＬＥＤユニット２１〜２ｎのマイクロプロセッサ３１〜３ｎが、アドレス書込動作信号Ａｗの入力に応じて、各レジスタ４１〜４ｎに格納されているアドレス１〜ｎを不揮発性メモリ５１〜５ｎにそれぞれ書き込む構成としてもよい。 Instead of the above-described configuration, the operation of the microprocessor 3i of the LED unit 2i is stopped until the address write operation signal Aw is input at S205 when the LED 7i is turned on, and the address setting device 1 When the number of outputs Ai is counted and the address write instruction signal Ai is output for the total number n of the LED units 21 to 2n, the set predetermined time is counted, and the address write is performed after the predetermined time has elapsed. On the other hand, the microprocessors 31 to 3n of the LED units 21 to 2n output addresses 1 to n stored in the registers 41 to 4n in response to the input of the address write operation signal Aw. May be written in the non-volatile memories 51 to 5n, respectively.

上記第２実施形態に於けるアドレス設定では、アドレスｉの不揮発性メモリ５ｉへの書込をアドレス書込開始信号Ａｓ及び全てのアドレス書込指示信号Ａ１〜Ａｎを送信するまで留保し、アドレス書込開始信号Ａｓ及びアドレス書込指示信号Ａ１〜Ａｎの正当性を検証した後にアドレスを書込設定するので、その冗長なフォーマットなど正当性の検証を容易且つ確実に行える。また、各ＬＥＤユニット２ｉの不揮発性メモリ５ｉへのアドレス書込が終了するまでの時間を待たずに、次順位に対するアドレス書込指示信号Ａ（ｉ＋１）を迅速に出力し、短時間でアドレスを設定することができる。また、正常書込ができなかったＬＥＤユニット２ｉはＬＥＤ７ｉを消灯すると共に、正常書込ができたＬＥＤユニット２ｉは点灯状態を維持するので、アドレスの正常設定の確認が非常に容易である。また、ＬＥＤユニット２１〜２ｎで不揮発性メモリ５１〜５ｎへのアドレス１〜ｎの書込を同時に行うので、書込作業の中断によるアドレス設定処理の異常終了を極力回避することができる。また、アドレス設定装置１からはアドレス自体を送信せず、初期アドレスや前順位のアドレスに設定値をインクリメントして次順位のアドレスとするので、簡単な処理でアドレスを設定することができる。 In the address setting in the second embodiment, the writing of the address i to the nonvolatile memory 5i is held until the address writing start signal As and all the address writing instruction signals A1 to An are transmitted, Since the address is written and set after verifying the validity of the write start signal As and the address write instruction signals A1 to An, it is possible to easily and reliably verify the validity of the redundant format. Also, without waiting for the time until address writing to the non-volatile memory 5i of each LED unit 2i is completed, the address writing instruction signal A (i + 1) for the next order is output quickly, and the address can be set in a short time. Can be set. Further, since the LED unit 2i that has not been normally written turns off the LED 7i, and the LED unit 2i that has been normally written maintains the lighting state, it is very easy to confirm the normal setting of the address. Further, since the LED units 21 to 2n simultaneously write the addresses 1 to n to the nonvolatile memories 51 to 5n, it is possible to avoid the abnormal end of the address setting process due to the interruption of the writing operation as much as possible. Further, the address setting device 1 does not transmit the address itself, but increments the set value to the initial address or the previous order address to obtain the next order address. Therefore, the address can be set by simple processing.

次に、第３実施形態の発光ユニットシステムに於けるアドレス設定について説明するが、特に言及しない箇所は第１実施形態等と同様である。図４に示す第３実施形態に於けるアドレス設定では、アドレス設定装置１が操作入力に応じてアドレス書込開始信号Ａｓを出力し、アドレス書込開始信号Ａｓはバス接続の信号線Ｓａを介して各ＬＥＤユニット２１、２２、・・２ｎのマイクロプロセッサ３１、３２、・・３ｎに入力される（Ｓ３０１）。各マイクロプロセッサ３１〜３ｎは、アドレス書込開始信号Ａｓの入力に応じて、信号線Ｓｃを論理０とすると共に、信号線Ｓｃから分岐する信号線Ｓｄ、及び前記信号線Ｓｄと連続する次順位のＬＥＤユニット２ｉの信号線Ｓｂを論理０とし、ＬＥＤユニット２１の信号線Ｓｂ以外の全信号線Ｓｂ、Ｓｃ、Ｓｄを論理０でリセットする（Ｓ３０２）。 Next, address setting in the light emitting unit system of the third embodiment will be described. The parts not particularly mentioned are the same as those in the first embodiment. In the address setting in the third embodiment shown in FIG. 4, the address setting device 1 outputs an address write start signal As in response to an operation input, and the address write start signal As is sent via a bus-connected signal line Sa. Are input to the microprocessors 31, 32,... 3n of the LED units 21, 22,. In response to the input of the address write start signal As, each of the microprocessors 31 to 3n sets the signal line Sc to logic 0, the signal line Sd branched from the signal line Sc, and the next order that is continuous with the signal line Sd. The signal line Sb of the LED unit 2i is set to logic 0, and all the signal lines Sb, Sc, Sd other than the signal line Sb of the LED unit 21 are reset to logic 0 (S302).

その後、アドレス設定装置１は操作入力に応じてアドレス書込指示信号Ａ１及びアドレス“１”を出力し、アドレス書込指示信号Ａ１及びアドレス“１”はバス接続の信号線Ｓａを介して各ＬＥＤユニット２１〜２ｎのマイクロプロセッサ３１〜３ｎに入力される（Ｓ３０３）。各マイクロプロセッサ３１〜３ｎは、アドレス書込指示信号Ａ１の入力に応じ、電圧チェック等で入力側の信号線Ｓｂの論理状態が論理０か論理１かを判定すると共に、各レジスタ４１〜４ｎにアドレスが格納されているか否か判定する（Ｓ３０４）。 Thereafter, the address setting device 1 outputs the address write instruction signal A1 and the address “1” in response to the operation input, and the address write instruction signal A1 and the address “1” are transmitted to each LED via the bus connection signal line Sa. Input to the microprocessors 31 to 3n of the units 21 to 2n (S303). Each of the microprocessors 31 to 3n determines whether the logic state of the signal line Sb on the input side is logic 0 or logic 1 by voltage check or the like according to the input of the address write instruction signal A1, and It is determined whether an address is stored (S304).

Ｓ３０４の判定の結果、入力側信号線Ｓｂが論理１で且つレジスタ４１にアドレスが格納されていない先頭のＬＥＤユニット２１のマイクロプロセッサ３１は、入力されたアドレス“１”をレジスタ４１に格納し、レジスタ４１に格納したアドレス“１”を不揮発性メモリ５１にＬＥＤユニット２１のアドレスとして書き込む（Ｓ３０５）。更に、マイクロプロセッサ３１は、正常な書き込みの終了に応じて出力側の信号線Ｓｃを論理１とし、信号線Ｓｃが論理１の状態になることに基づき、その信号線Ｓｃから分岐する信号線Ｓｄ、及び前記信号線Ｓｄに連続する次順位のＬＥＤユニット２２の信号線Ｓｂは論理１となると共に、論理１が入力されるＬＥＤ駆動回路６１は点灯制御でＬＥＤ７１を点灯し、ＬＥＤユニット２１のアドレスの正常な書き込みを報知し、この後、マイクロプロセッサ３１は全てのＬＥＤユニット２１〜２ｎのアドレス書込終了を書込終了信号等で認識するまで動作を停止する（Ｓ３０６）。 As a result of the determination in S304, the microprocessor 31 of the first LED unit 21 whose input side signal line Sb is logic 1 and whose address is not stored in the register 41 stores the input address “1” in the register 41. The address “1” stored in the register 41 is written in the nonvolatile memory 51 as the address of the LED unit 21 (S305). Further, the microprocessor 31 sets the signal line Sc on the output side to logic 1 in accordance with the end of normal writing, and the signal line Sd branched from the signal line Sc based on the signal line Sc being in the logic 1 state. , And the signal line Sb of the LED unit 22 of the next order continuous to the signal line Sd becomes logic 1, and the LED drive circuit 61 to which logic 1 is inputted lights the LED 71 by lighting control, and the address of the LED unit 21 After that, the microprocessor 31 stops the operation until it recognizes the address writing end of all the LED units 21 to 2n by the writing end signal or the like (S306).

前記Ｓ３０６の処理の後、或いはＳ３０４の判定で信号線Ｓｂが論理１ではない場合若しくはレジスタ４ｉにアドレスが設定されている場合には、アドレス書込指示信号ＡｉをＬＥＤユニット２１〜２ｎの全個数ｎだけ出力しているか否か判断し（Ｓ３０７）、Ｓ３０３〜Ｓ３０６と同様の処理を繰り返し実行する。即ち、アドレス設定装置１から出力されるアドレス書込指示信号Ａｉ及びアドレス“ｉ”をバス接続の信号線Ｓａを介して各ＬＥＤユニット２１〜２ｎのマイクロプロセッサ３１〜３ｎに入力し、アドレス設定が完了しているＬＥＤユニット以外の各ＬＥＤユニット２ｉ〜２ｎのマイクロプロセッサ３ｉ〜３ｎは、その入力に応じて、信号線Ｓｂの論理が０か１かを判定すると共に各レジスタ４ｉ〜４ｎにアドレスが格納されているか否か判定する。更に、入力側信号線Ｓｂが論理１で且つレジスタ４ｉにアドレスが格納されていないＬＥＤユニット２ｉのマイクロプロセッサ３ｉは、入力されたアドレス“ｉ”をレジスタ４ｉに格納し、レジスタ４ｉに格納したアドレス“ｉ”を不揮発性メモリ５ｉにＬＥＤユニット２ｉのアドレスとして書き込み、正常な書き込みの終了に応じて出力側の信号線Ｓｃ、その信号線Ｓｃから分岐する信号線Ｓｄ、及び前記信号線Ｓｄに連続する次順位のＬＥＤユニット２（ｉ＋１）の信号線Ｓｂは論理１とし、ＬＥＤ駆動回路６ｉでＬＥＤ７ｉを点灯して動作を停止する。 After the process of S306, or when the signal line Sb is not logical 1 or the address is set in the register 4i in the determination of S304, the address write instruction signal Ai is sent to the total number of LED units 21 to 2n. It is determined whether or not only n is output (S307), and the same processing as S303 to S306 is repeatedly executed. That is, the address write instruction signal Ai and the address “i” output from the address setting device 1 are input to the microprocessors 31 to 3n of the LED units 21 to 2n via the bus connection signal line Sa, and the address setting is performed. The microprocessors 3i to 3n of the LED units 2i to 2n other than the completed LED units determine whether the logic of the signal line Sb is 0 or 1 according to the input, and the addresses of the registers 4i to 4n are It is determined whether it is stored. Further, the microprocessor 3i of the LED unit 2i whose input side signal line Sb is logic 1 and whose address is not stored in the register 4i stores the input address “i” in the register 4i and the address stored in the register 4i. “I” is written in the nonvolatile memory 5i as the address of the LED unit 2i, and the signal line Sc on the output side, the signal line Sd branched from the signal line Sc, and the signal line Sd are continuous when normal writing ends. The signal line Sb of the LED unit 2 (i + 1) of the next order to be set to logic 1, and the LED drive circuit 6i lights the LED 7i to stop the operation.

そして、アドレス設定装置１が最終のアドレス書込指示信号Ａｎ及びアドレス“ｎ”を出力し、アドレス書込指示信号Ａｎ及びアドレス“ｎ”が入力されるＬＥＤユニット２ｎのマイクロプロセッサ３ｎが、信号線Ｓｂの論理１及びレジスタ４ｎへのアドレス未格納の判定に基づき、入力されたアドレス“ｎ”をレジスタ４ｎへ格納して不揮発性メモリ５ｎに書き込み、正常な書き込みの終了に応じて出力側の信号線Ｓｃを論理１とし、ＬＥＤ駆動回路６ｎでＬＥＤ７ｎを点灯して動作を停止する。最後に、全てのＬＥＤ７１、７２、・・７ｎが点灯しているか確認し（Ｓ３０８）、点灯している場合にはアドレスの設定処理が完了する。 Then, the address setting device 1 outputs the final address write instruction signal An and the address “n”, and the microprocessor 3n of the LED unit 2n to which the address write instruction signal An and the address “n” are input is connected to the signal line. Based on the logic 1 of Sb and the determination that the address is not stored in the register 4n, the input address “n” is stored in the register 4n and written to the non-volatile memory 5n. The line Sc is set to logic 1, and the LED drive circuit 6n turns on the LED 7n to stop the operation. Finally, it is confirmed whether all the LEDs 71, 72,... 7n are lit (S308), and when they are lit, the address setting process is completed.

上記第３実施形態のアドレス設定では、各ＬＥＤユニット２ｉに於いて、ＬＥＤアドレスｉの不揮発性メモリ５ｉへの正常な書込終了に応じて出力側信号線Ｓｃを論理１に設定し、ＬＥＤ７ｉを点灯するので、各ＬＥＤユニット２ｉにアドレスｉの正常書込をＬＥＤ７ｉの点灯状態だけで非常に容易に確認することができる。換言すれば、最後のＬＥＤユニット２ｎのＬＥＤ７ｎが点灯していれば、全てのＬＥＤユニット２１〜２ｎに正常にアドレスが設定されたことが分かり、アドレス設定の確認作業が非常に容易になる。また、アドレス書込指示信号Ａｉに併せてアドレスｉをＬＥＤユニット２ｉに出力するので、ＬＥＤユニット２ｉに対して任意のアドレスを割り当てることができる。 In the address setting of the third embodiment, in each LED unit 2i, the output side signal line Sc is set to logic 1 according to the end of normal writing of the LED address i to the nonvolatile memory 5i, and the LED 7i is turned on. Since it is lit, normal writing of the address i in each LED unit 2i can be confirmed very easily only by the lighting state of the LED 7i. In other words, if the LED 7n of the last LED unit 2n is lit, it can be understood that the addresses have been normally set in all the LED units 21 to 2n, and the address setting confirmation work becomes very easy. In addition, since the address i is output to the LED unit 2i together with the address write instruction signal Ai, an arbitrary address can be assigned to the LED unit 2i.

次に、第４実施形態の発光ユニットシステムに於けるアドレス設定について説明する。図５の第４実施形態に於ける基本的な処理は上記第２実施形態と同様であるが、マイクロプロセッサ３ｉがプログラムに設定されている初期アドレス“１”をレジスタ３ｉに格納する構成に代え、マイクロプロセッサ３ｉがアドレス書込開始信号Ａｓと共に入力される初期アドレス“１”をレジスタ３ｉに格納する点で相違する。即ち、アドレス設定装置１が操作入力に応じてアドレス書込開始信号Ａｓ及びアドレス“１”を出力し、アドレス書込開始信号Ａｓ及びアドレス“１”はバス接続の信号線Ｓａを介して各ＬＥＤユニット２１、２２、・・２ｎのマイクロプロセッサ３１、３２、・・３ｎに入力され（Ｓ４０１）、各マイクロプロセッサ３１、３２、・・３ｎが、アドレス書込開始信号Ａｓの入力に応じて、各レジスタ４１、４２、・・４ｎに入力されたアドレス“１”を格納すると共に、信号線Ｓｃを論理０として、信号線Ｓｃから分岐する信号線Ｓｄ、及び信号線Ｓｄと連続する或いは接続される次順位のＬＥＤユニット２ｉの信号線Ｓｂを論理０とし、先頭のＬＥＤユニット２１の信号線Ｓｂ以外の全ての信号線Ｓｂ、Ｓｃ、Ｓｄを論理０にしてリセットする（Ｓ４０２）。他の構成は第２実施形態と同様であり、Ｓ４０３〜Ｓ４０９の処理はＳ２０３〜Ｓ２０９の処理にそれぞれ対応している。 Next, address setting in the light emitting unit system of the fourth embodiment will be described. The basic processing in the fourth embodiment shown in FIG. 5 is the same as that in the second embodiment, except that the microprocessor 3i stores the initial address “1” set in the program in the register 3i. The microprocessor 3i is different in that the initial address “1” input together with the address write start signal As is stored in the register 3i. That is, the address setting device 1 outputs an address write start signal As and an address “1” in response to an operation input, and the address write start signal As and the address “1” are connected to each LED via a bus connection signal line Sa. Are input to the microprocessors 31, 32,... 3n of the units 21, 22,... 2n (S401), and the respective microprocessors 31, 32,. The address “1” input to the registers 41, 42,... 4n is stored, the signal line Sc is set to logic 0, and the signal line Sd branched from the signal line Sc and the signal line Sd are connected or connected. Reset the signal line Sb of the next order LED unit 2i to logic 0, and set all the signal lines Sb, Sc, Sd other than the signal line Sb of the first LED unit 21 to logic 0. To (S402). Other configurations are the same as those of the second embodiment, and the processes of S403 to S409 correspond to the processes of S203 to S209, respectively.

第４実施形態に於けるアドレス設定では、アドレスｉの不揮発性メモリ５ｉへの書込をアドレス書込開始信号Ａｓ及び全てのアドレス書込指示信号Ａ１〜Ａｎを送信するまで留保し、アドレス書込開始信号Ａｓ及びアドレス書込指示信号Ａ１〜Ａｎの正当性を検証した後にアドレスを書込設定するので、その正当性の検証を容易且つ確実に行える。また、各ＬＥＤユニット２ｉの不揮発性メモリ５ｉへのアドレス書込が終了するまでの時間を待たずに、次順位に対するアドレス書込指示信号Ａ（ｉ＋１）を迅速に出力し、短時間でアドレスを設定することができる。また、正常書込ができなかったＬＥＤユニット２ｉはＬＥＤ７ｉを消灯すると共に、正常書込ができたＬＥＤユニット２ｉは点灯状態を維持するので、アドレスの正常設定の確認が非常に容易である。また、ＬＥＤユニット２１〜２ｎで不揮発性メモリ５１〜５ｎへのアドレス１〜ｎの書込を同時に行うので、書込作業の中断によるアドレス設定処理の異常終了を極力回避することができる。また、アドレス設定装置１からは初期アドレスを出力し、ＬＥＤユニット２１の初期アドレスや前順位のアドレスに設定値をインクリメントして次順位のアドレスとするので、簡単な処理でアドレスを設定することができる。 In the address setting in the fourth embodiment, the writing of the address i to the nonvolatile memory 5i is held until the address writing start signal As and all the address writing instruction signals A1 to An are transmitted, and the address writing is performed. Since the address is written and set after verifying the validity of the start signal As and the address writing instruction signals A1 to An, the validity can be verified easily and reliably. Also, without waiting for the time until address writing to the non-volatile memory 5i of each LED unit 2i is completed, the address writing instruction signal A (i + 1) for the next order is output quickly, and the address can be set in a short time. Can be set. Further, since the LED unit 2i that has not been normally written turns off the LED 7i, and the LED unit 2i that has been normally written maintains the lighting state, it is very easy to confirm the normal setting of the address. Further, since the LED units 21 to 2n simultaneously write the addresses 1 to n to the nonvolatile memories 51 to 5n, it is possible to avoid the abnormal end of the address setting process due to the interruption of the writing operation as much as possible. In addition, the initial address is output from the address setting device 1, and the setting value is incremented to the initial address of the LED unit 21 or the previous order address to obtain the next order address. Therefore, the address can be set by simple processing. it can.

本発明は、例えば大画面のＬＥＤ表示装置の画素として用いられるＬＥＤユニット等のアドレス設定に利用することができる。 The present invention can be used for address setting of, for example, an LED unit used as a pixel of a large-screen LED display device.

第１〜第４実施形態のＬＥＤユニットシステムを示すブロック図。The block diagram which shows the LED unit system of 1st-4th embodiment. 第１実施形態のアドレス設定手順を示すフローチャート。6 is a flowchart illustrating an address setting procedure according to the first embodiment. 第２実施形態のアドレス設定手順を示すフローチャート。The flowchart which shows the address setting procedure of 2nd Embodiment. 第３実施形態のアドレス設定手順を示すフローチャート。The flowchart which shows the address setting procedure of 3rd Embodiment. 第４実施形態のアドレス設定手順を示すフローチャート。The flowchart which shows the address setting procedure of 4th Embodiment. （ａ）はＬＥＤユニットの例を示す平面図、（ｂ）はその正面図、（ｃ）はその側面図。(A) is a top view which shows the example of an LED unit, (b) is the front view, (c) is the side view.

Explanation of symbols

１アドレス設定装置
２１、２２、２ｎ、１０ＬＥＤユニット
３１、３２、３ｎマイクロプロセッサ
４１、４２、４ｎレジスタ
５１、５２、５ｎ不揮発性メモリ
６１、６２、６ｎＬＥＤ駆動回路
７１、７２、７ｎ、１１ＬＥＤ
Ｓａ、Ｓｂ、Ｓｃ、Ｓｄ信号線 1 Address setting device 21, 22, 2n, 10 LED units 31, 32, 3n Microprocessor 41, 42, 4n Register 51, 52, 5n Non-volatile memory 61, 62, 6n LED drive circuit 71, 72, 7n, 11 LED
Sa, Sb, Sc, Sd signal lines

Claims

Each light emitting unit with a built-in control unit, nonvolatile memory, and light emitter driving circuit is bus-connected and cascade-connected, and light emission is set for each light-emitting unit based on a control signal input from a signal line connected to the bus A unit system,
The cascade signal line on the input side of the first light emitting unit is set to logic 1,
The control part of each light emitting unit
Based on the input of the first control signal from the bus connection signal line, the set initial address is stored in the register, and the signal line between the control unit and the light emitter driving circuit, and the signal line is branched to the next. The cascade signal line leading to the light emitting unit controller of the order is set to logic 0,
Based on the input of the second control signal sequentially transmitted corresponding to the address setting of each light emitting unit from the bus connection signal line, the logic of the cascade signal line on the input side is determined, and the cascade signal line on the input side is logic In the case of 1, the address stored in the register is written to the nonvolatile memory and set, the signal line between the control unit and the light emitter drive circuit is set to logic 1, the light emitter is turned on, and the signal line is branched off. When the cascade signal line leading to the light emitting unit controller of the next order is logical 1 and the cascade signal line on the input side is logical 0 on the other side, the address stored in the register is used based on a predetermined calculation rule. A light emitting unit system characterized in that a next address is acquired and a register address is updated to the next address.

Each light emitting unit with a built-in control unit, nonvolatile memory, and light emitter driving circuit is bus-connected and cascade-connected, and light emission is set for each light-emitting unit based on a control signal input from a signal line connected to the bus A unit system,
The cascade signal line on the input side of the first light emitting unit is set to logic 1,
The control part of each light emitting unit
Based on the input of the first control signal from the bus connection signal line, the set initial address is stored in the register, and the signal line between the control unit and the light emitter driving circuit, and the signal line is branched to the next. The cascade signal line leading to the light emitting unit controller of the order is set to logic 0,
Based on the input of the second control signal sequentially transmitted corresponding to the address setting of each light emitting unit from the bus connection signal line, the logic of the cascade signal line on the input side is determined, and the cascade signal line on the input side is logic In the case of 1, the signal line between the control unit and the light emitter drive circuit is set to logic 1, and the light emitter is turned on, and the cascade signal line branched from the signal line to the next light emitting unit control unit is set to logic 1. On the other hand, when the cascade signal line on the input side is logic 0, the next address is obtained from the address stored in the register based on a predetermined calculation rule, and the address of the register is updated to the next address.
The third control signal from the bus connection signal line transmitted based on the number of times of input of the second control signal to be counted becomes the total number of light emitting units or after the output of the second control signal of the total number of light emitting units. Based on the input, each address stored in the register is written to the nonvolatile memory and set.
When a normal address cannot be set, the light emitting unit system is characterized in that the signal line between the control unit and the light emission drive circuit is set to logic 0 and the light emitter is turned off.

Each light emitting unit with a built-in control unit, nonvolatile memory, and light emitter driving circuit is bus-connected and cascade-connected, and light emission is set for each light-emitting unit based on a control signal input from a signal line connected to the bus A unit system,
The cascade signal line on the input side of the first light emitting unit is set to logic 1,
The control part of each light emitting unit
Based on the input of the first control signal from the bus connection signal line, the signal line between the control unit and the light emitter drive circuit, and the cascade signal line branched from the signal line to the next light emitting unit control unit are logically operated. 0,
Based on the input of the second control signal and address sequentially transmitted corresponding to the address setting of each light emitting unit from the bus connection signal line, the logic of the cascade signal line on the input side is determined and the address is not stored in the register If the cascade signal line on the input side is logic 1 and the address is not stored in the register, the input address is stored in the register, written to the nonvolatile memory, set, and the controller and the light emission A light-emitting unit system characterized in that a signal line between body drive circuits is set to logic 1, and the light-emitting body is turned on, and a cascade signal line branched from the signal line to the next-order light-emitting unit controller is set to logic 1. .

Each light emitting unit with a built-in control unit, nonvolatile memory, and light emitter driving circuit is bus-connected and cascade-connected, and light emission is set for each light-emitting unit based on a control signal input from a signal line connected to the bus A unit system,
The cascade signal line on the input side of the first light emitting unit is set to logic 1,
The control part of each light emitting unit
Based on the input of the first control signal and the initial address from the bus connection signal line, the input initial address is stored in the register, and the signal line between the control unit and the light emitter driving circuit and the signal line are branched. And the cascade signal line leading to the light emitting unit controller of the next order is set to logic 0,
Based on the input of the second control signal sequentially transmitted corresponding to the address setting of each light emitting unit from the bus connection signal line, the logic of the cascade signal line on the input side is determined, and the cascade signal line on the input side is logic In the case of 1, the signal line between the control unit and the light emitter drive circuit is set to logic 1, and the light emitter is turned on, and the cascade signal line branched from the signal line to the next light emitting unit control unit is set to logic 1. On the other hand, when the cascade signal line on the input side is logic 0, the next address is obtained from the address stored in the register based on a predetermined calculation rule, and the address of the register is updated to the next address.
The third control signal from the bus connection signal line transmitted based on the number of times of input of the second control signal to be counted becomes the total number of light emitting units or after the output of the second control signal of the total number of light emitting units. Based on the input, each address stored in the register is written to the nonvolatile memory and set.
When a normal address cannot be set, the light emitting unit system is characterized in that the signal line between the control unit and the light emission drive circuit is set to logic 0 and the light emitter is turned off.