JP2005257757A - Display apparatus and display method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus and a display method capable of alleviating a processing capability of a host circuit and reducing a storing capacity of an internal memory. <P>SOLUTION: The liquid crystal display apparatus 10 is equipped with; a first liquid crystal display panel 101; a second liquid crystal panel 102 in which the number of a display column and the number of a display row are fewer than those of the first display panel 101; a gate driver 103; source drivers 105 to 107; display data storing memories 109 to 111; and a control circuit 112. Display data storing memories 109 to 111 have a memory capacity of a multiplication product of the maximum display number on a scanning line 101G of the first liquid crystal display panel 101 and the maximum display number on a video line 102S of the second liquid crystal display panel 102 and a writing-in speed of a display data is made higher than a reading-out speed of the display data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device and a display method, and more particularly to a display device with a built-in memory having a plurality of display panels (displays) and a display method.

  Recently, a liquid crystal display device having two liquid crystal display panels is incorporated in a mobile phone, a notebook personal computer, and the like. For example, in a mobile phone, the liquid crystal display device includes a main liquid crystal display panel having a large screen size used for the original function of the mobile phone and a sub liquid crystal display panel used for incidental functions such as date and time display and incoming call notification display. And.

  In a liquid crystal display device, display data is transferred from a host circuit to a liquid crystal display driver in consideration of display timing, and a liquid crystal display panel is displayed based on the transferred display data. The liquid crystal display device shown in FIG. 6 includes a main liquid crystal display panel 1, a sub liquid crystal display panel 2, a gate driver 3, a gate line 4, main liquid crystal display panel source drivers 5 and 7, and a main liquid crystal display panel 1. And a common source driver 6 common to the sub liquid crystal display panel 2, a source line 8, and a host circuit 9.

  A gate driver control signal (GCONT) output from the host circuit 9 is input to the gate driver 3. The gate driver 3 selects the gate line 4 corresponding to the input of the gate driver control signal, and performs on / off control of the scanning lines of the main liquid crystal display panel 1 and the sub liquid crystal display panel 2. Further, liquid crystal display data, a data control signal and a source driver control signal (SCONT) output from the host circuit 9 are input to the source drivers 5, 6 and 7. The source drivers 5, 6 and 7 select source lines based on input of liquid crystal display data and the like, and perform on / off control of video lines of the main liquid crystal display panel 1 and the sub liquid crystal display panel 2. An image based on the liquid crystal display data is displayed on the main liquid crystal display panel 1 and the sub liquid crystal display panel 2 by the on / off control of the scanning lines and the video lines. Here, the liquid crystal display data is a write data signal (WD). The data control signal includes a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), and a data valid signal (DE).

  Next, the liquid crystal shown in FIG. 6 has m effective display rows and n effective display columns of the main liquid crystal display panel 1, and i effective display rows and j effective display columns of the sub liquid crystal display panel 2. The liquid crystal display operation in the display device will be described.

  As shown in FIG. 7, the “one screen processing period” of the two liquid crystal display panels of the main liquid crystal display panel 1 and the sub liquid crystal display panel 2 is “the blanking period of the vertical synchronization signal” in the “transfer period of the write data signal”. (Vertical sync signal low level section) ". In this one-screen processing period, write data is transferred using the vertical synchronization signal, horizontal synchronization signal, and data valid signal. The write data signal is transferred during the high level interval of the vertical synchronization signal, the high level interval of the horizontal synchronization signal, and the high level interval of the data valid signal. When the write data signals for “m + i rows” are transferred in total, the data transfer for one screen is completed. Specifically, as shown in an enlarged view in the lower left part of FIG. 7, in the sub liquid crystal display panel 2, j pieces of write data D1 to Dj corresponding to the number of columns for one row correspond to the number of i rows. Transferred within the screen processing period. As shown enlarged in the lower right part of FIG. 7, in the main liquid crystal display panel 1, n pieces of write data D1 to Dn corresponding to the number of columns for one row are equivalent to the number of m rows for one screen processing period. Forwarded in.

  The liquid crystal display operation of the two liquid crystal display panels of the main liquid crystal display panel 1 and the sub liquid crystal display panel 2 is started from the rising edge of the vertical synchronization signal from the low level to the high level. The gate driver 3 is driven to select a scanning line via the gate line 4, the source drivers 5 to 7 are driven to select a video line via the source line 8, and a pixel (pixel) selected by these is selected. A write data signal (display data) is written. By writing the write data signal, the main liquid crystal display panel 1 and the sub liquid crystal display panel 2 perform liquid crystal display.

On the other hand, Patent Document 1 below discloses a liquid crystal driver with a built-in memory and a liquid crystal display with a built-in memory for storing liquid crystal display data. This liquid crystal driver with built-in memory is configured to convert the liquid crystal display data stored in the memory into a liquid crystal applied voltage and output it to the liquid crystal display panel for display, thereby improving the system operating efficiency.
Japanese Patent Laid-Open No. 7-64514

  However, in the liquid crystal display device having the two liquid crystal display panels of the main liquid crystal display panel 1 and the sub liquid crystal display panel 2 described above, as shown in FIG. Since data is transferred and liquid crystal display is performed, the driving load of the host circuit 9 is heavy. For this reason, most of the processing capability of the host circuit 9 is spent on the liquid crystal display operation. For example, in the mobile phone, other processing such as communication processing and voice processing cannot be executed by the host circuit 9. In order to improve the processing capability, a new system design such as increasing the circuit scale of the host circuit 9 is required, so that the manufacturing cost of the liquid crystal display device increases.

  On the other hand, the liquid crystal driver with built-in memory and the liquid crystal display described in Patent Document 1 are premised on having one liquid crystal display panel. When the system operation efficiency is improved in the liquid crystal display device having the two liquid crystal display panels shown in FIG. 6, the storage capacity corresponding to the main liquid crystal display panel 1 or the main liquid crystal display panel 1 and the sub liquid crystal display panel is used. It is necessary to incorporate a memory having a storage capacity corresponding to each of the two. For this reason, in the liquid crystal display device, the storage capacity of the built-in memory increases. The incorporation of a memory with a large storage capacity causes an increase in the manufacturing cost of the liquid crystal display device.

  The present invention has been made in view of the above points, and an object thereof is to provide a display device and a display method capable of reducing the processing capacity of a host circuit and reducing the storage capacity of a built-in memory. And

  The display device of the present invention includes a first display panel, a second display panel having a smaller number of display rows and display columns than the first display panel, and scanning of the first and second display panels. A gate driver for driving a line; a source driver for outputting display data to video lines of the first and second display panels; a maximum number of displays on the scanning lines of the first display panel; and the second display. The display data has a storage capacity multiplied by the maximum display number on the video line of the panel, and the display data with respect to the speed at which the display data is transferred from the source driver to the first and second display panels in one screen display period. Control the operation of the display data storage memory, the gate driver, the source driver and the display data storage memory, and write the display data to the display data storage memory. A configuration that includes a writing control circuit.

  According to this configuration, the display data storage memory having a writing speed that is at least faster than the transfer speed of the display data from the source driver to the first and second display panels is provided, and the display data is temporarily stored at a high speed operation. , And can be transferred to the first and second display panels. As a result, display data is not transferred from the host circuit to the first and second display panels over the entire one-screen display period, and the processing capacity of the host circuit can be reduced. Furthermore, since the display data storage memory having a high writing speed can repeatedly write and read display data in the one-screen display period, the maximum display number on the scanning line of the first display panel and the video line on the second display panel are displayed. The storage capacity can be set to be smaller than the storage capacity corresponding to the total display number of the first display panel multiplied by the maximum display number. As a result, the storage capacity of the display data storage memory can be reduced.

  The display device of the present invention employs a configuration further comprising a host circuit that transfers display data to the control circuit.

  According to this configuration, it is not necessary to transfer display data to the control circuit during the entire one-screen display period, so that the processing capacity of the host circuit can be reduced.

  In the display device according to the present invention, the control circuit reads a display address stored in the display data storage memory to the source driver, and a write address for writing the display data from the host circuit to the display data storage memory. The display data storage memory is controlled to operate as a first-in first-out (FIFO) circuit.

  According to this configuration, since the display data storage memory can be operated as a first-in first-out circuit, it is possible to prevent the display data read address signal from overtaking the display data write address signal.

  The display device of the present invention employs a configuration in which the control circuit has a function of requesting the host circuit to transfer display data before the display data read from the display data storage memory becomes empty.

  According to this configuration, since it is only necessary to request the host circuit to transfer the display data before the display data read from the display data storage memory becomes empty, the processing capacity of the host circuit can be reduced.

  In the display device of the present invention, the control circuit has a function of displaying only the second display panel and having a function of stopping the source driver and the display data storage memory that do not need to be activated.

  According to this configuration, the source driver and the display data storage memory that do not need to be activated can be stopped, so that the processing capability of the host circuit can be reduced. Further, useless power consumption can be eliminated.

  According to the display method of the present invention, the maximum number of displays on the scanning lines of the first display panel and the maximum number of displays on the video lines of the second display panel having a smaller number of display rows and display columns than the first display panel. And the step of storing display data at regular intervals and continuously transferring the display data stored at regular intervals to the video lines of the first and second display panels. A configuration with stages is adopted.

  According to this method, the display data can be stored at regular intervals within one screen display period, and the stored display data is continuously applied to the video lines of the first and second display panels. Since the data can be transferred, the display data storing process can be stopped at intervals of storing the display data at regular intervals. That is, the processing capacity of the host circuit can be reduced at the interval for storing the display data.

  According to the present invention, it is possible to provide a display device and a display method capable of reducing the processing capacity of the host circuit and reducing the storage capacity of the built-in memory.

  The gist of the present invention has a storage capacity obtained by multiplying the maximum display number on the scanning line of the main display panel by the maximum display number on the video line of the sub display panel, and the stored display data is used as the main display panel and the sub display panel. Display data storage memory that stores display data faster than the video line transfer speed, temporarily stores display data in the display data storage memory, and stores the stored display data in the main display panel. And transferring to the video line of the sub display panel.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that this embodiment describes an example in which the present invention is applied to a liquid crystal display device.

[Configuration of liquid crystal display device]
The liquid crystal display device 10 according to the embodiment of the present invention includes a first liquid crystal display panel (main liquid crystal display panel) 101 and a second number of display rows and display columns smaller than those of the first liquid crystal display panel 101. Liquid crystal display panel (sub liquid crystal display panel) 102, gate driver 103 for driving scanning line 101G of first liquid crystal display panel 101 and scanning line 102G of second liquid crystal display panel 102, and first liquid crystal display panel Source drivers 105 to 107 that output display data to the video line 101S of 101 and the video line 102S of the second liquid crystal display panel 102; the maximum number of displays on the scanning line 101G of the first liquid crystal display panel 101; It has a storage capacity multiplied by the maximum display number on the video line 102S of the liquid crystal display panel 102, and the source drivers 105 to 10 in one screen display period. Display data storage memories 109-111, source drivers 105-107, and display data whose display data write speed is faster than the display data transfer speed from the first to the second liquid crystal display panel 101 and the second liquid crystal display panel 102. A control circuit 112 that controls the operation of the storage memories 109 to 111 and writes display data to the display data storage memories 109 to 111 is provided.

  Further, the liquid crystal display device 10 includes a host circuit 113. In the present embodiment, the host circuit 113 is described as an internal circuit of the liquid crystal display device 10, but may be an external circuit of the liquid crystal display device 10. Specifically, for example, a main processor of a mobile phone or a wireless communication device may be used as a host circuit, and the liquid crystal display device 10 may be connected to the host circuit.

  The host circuit 113 outputs a write data signal WD, a write address signal WAD, a write control signal WCONT, and a vertical synchronization signal VSYNC to the control circuit 112. The write data signal WD is display data for performing liquid crystal display in each of the first liquid crystal display panel 101 and the second liquid crystal display panel 102. On the other hand, the control circuit 112 outputs a write request signal WREQ to the host circuit 113.

  The control circuit 112 selects one of the display data storage memories 109 to 111 based on the write address signal WAD, writes the write data signal WD1 to the display data storage memory 110, and writes the write data signal to the display data storage memory 109. WD2 is written and the display data storage memory 111 is written with a write data signal WD3. In the display data storage memory 110, the stored write data signal WD1 is output to the source driver 106 as a read data signal RD1. Similarly, in the display data storage memory 109, the stored write data signal WD2 is output to the source driver 105 as a read data signal RD2. In the display data storage memory 111, the stored write data signal WD3 is output to the source driver 107 as a read data signal RD3. The display data storage memories 109 to 111 operate as a FIFO circuit. A write request signal WREQ for controlling the write operation of the display data storage memories 109 to 111 is generated in the control circuit 112 and output from the control circuit 112 to the host circuit 113.

  Further, the control circuit 112 outputs a source driver control signal SCANT to the source drivers 105 to 107 and outputs a gate driver control signal GCONT to the gate driver 103. In the gate driver 103, in response to the input of the gate driver control signal GCONT, the scanning line 101G extending through the gate line 104 in the first liquid crystal display panel 101 in the vertical direction in FIG. In 102, on / off control of each scanning line 102G extending in the vertical direction is performed. The source drivers 105 to 107 output a voltage corresponding to the input of the source driver control signal SCONT, pass through the source line 108, and the video line 101 </ b> S extending in the left-right direction in FIG. 1 on the first liquid crystal display panel 101. In the second liquid crystal display panel 102, display data is transferred to each of the video lines 102S extending in the left-right direction.

  Although not shown in detail in FIG. 1, in the first liquid crystal display panel 101, one pixel disposed at the intersection of the scanning line 101 </ b> G that is turned on and the video line 101 </ b> S to which display data is transferred. Liquid crystal display is performed at (pixel). Similarly, in the second liquid crystal display panel 102, liquid crystal display is performed in one pixel arranged at the intersection of the scanning line 102G controlled to be on and the video line 102S to which the display data is transferred. During the one-screen processing period, all the pixels of the first liquid crystal display panel 101 are displayed, and the pixels of the second liquid crystal display panel 102 are displayed, and liquid crystal display is performed.

  Further, when performing liquid crystal display on the first liquid crystal display panel 101 and the second liquid crystal display panel 102, the output timing of the gate driver control signal GCONT and the source driver control signal SCONT, the output timing of the read data signals RD1 to RD3, and Are controlled by a vertical synchronization signal VSYNC.

  In the present embodiment, a static random access memory (SRAM) can be practically used as the display data storage memories 109 to 111. The SRAM has a performance that the display data writing speed is faster than the display data transfer speed from the source drivers 105 to 107 to the first liquid crystal display panel 101 and the second liquid crystal display panel 102 in one screen display period. ing. The display data storage memories 109 to 111 are not limited to the SRAM, and a dynamic random access memory (DRAM) having a property that the display data writing speed is high can be used. Further, in this embodiment, the display data storage memories 110 common to the first liquid crystal display panel 101 and the second liquid crystal display panel 102 and the left and right sides thereof are arranged (in FIG. Although the case where a total of three display data storage memories 109 to 111, that is, display data storage memories 109 and 111 provided are described, is not limited to this number, one, two, or Three or more display data storage memories can be provided.

[Liquid crystal display operation of liquid crystal display]
Next, the effective display row of the first main liquid crystal display panel 101 is m rows and the effective display column is n columns, the effective display row of the second liquid crystal display panel 102 is i row, and the effective display column is j column. The liquid crystal display operation of the liquid crystal display device 10 shown in FIG. 1 will be described with reference to FIG.

  The “one screen processing period” of the two liquid crystal display panels of the first liquid crystal display panel 101 and the second liquid crystal display panel 102 is “the blanking period of the vertical synchronization signal” in the “transfer period of the display data (write data signal WD)”. This is a period obtained by adding “period (low level section of vertical synchronizing signal)”. In this one-screen processing period, display data is transferred using the vertical synchronization signal VSYNC and the write data WD.

  The display data storage memories 109 to 111 have a storage capacity obtained by multiplying the maximum display number on the scanning line 101G of the first liquid crystal display panel 101 by the maximum display number on the video line 102S of the second liquid crystal display panel 102. ing. That is, the display data storage memories 109 to 111 have a storage capacity (i rows × n) obtained by multiplying the number of pixels for i rows of the second liquid crystal display panel 102 by the number of pixels for n columns of the first liquid crystal display panel 101. Column) and display data corresponding to the storage capacity can be written. Write data signal WD writes to display data storage memories 109 to 111 in units of i rows, which is the number of display rows of second liquid crystal display panel 102.

  In the present embodiment, the display data storage memories 109 to 111 are transferred from the host circuit 113 through the control circuit 112 to display data (write data signal WD) for i rows three times and for (m-2i) rows. The display data is set to be transferred four times in total, one time, and display data transfer within one screen display period is completed. Within this one-screen display period, display data is transferred (write data signal WD is written) based on the write request signal WREQ when the write request signal WREQ is output from the control circuit 112 to the host circuit 113. The display data storage memories 109 to 111 are periodically performed from the circuit 113 through the control circuit 112.

  In the second liquid crystal display panel 102, the transfer of display data for one row is a transfer of j write data signals WD (D1 to Dj) as shown in the lower left part of FIG. . In the first liquid crystal display panel 101, transfer of display data for one row is transfer of n write data signals WD (D1 to Dn) as shown in the enlarged central portion in FIG. .

  The display data stored in the display data storage memories 109 to 111 is read after the vertical synchronization signal VSYNC rises, and when the gate driver 103 and the source drivers 105 to 107 are driven, the first liquid crystal display panel 101 and the first display data are stored. Liquid crystal display is performed on the second liquid crystal display panel 102. When the display data is read from the display data storage memories 109 to 111, the write request signal WREQ is output from the control circuit 112 to the host circuit 113 when the display data storage area of the display data storage memories 109 to 111 is freed to some extent. In the host circuit 113, the write data signal WD can be sequentially transferred to the display data storage memories 109 to 111 based on the write request signal WREQ.

  The display data is not transferred from the host circuit 113 to the display data storage memories 109 to 111 between the transfer of the display data and the transfer of the next display data. That is, the host circuit 113 can be in a dormant state or perform another process between display data transfers.

  In the embodiment, the number of times display data is transferred within one screen display period is not limited to four times, but the size of the first liquid crystal display panel 101 (number of effective display rows × number of effective display columns). ) And the size of the second liquid crystal display panel 102 (the number of effective display rows × the number of effective display columns).

[Configuration of control circuit]
Next, a detailed configuration of the control circuit 112 of the liquid crystal display device 10 described above and a connection configuration of the control circuit 112, display data storage memories 109 to 111, source drivers 105 to 107, and gate driver 103 will be described. .

  As shown in FIG. 3, the control circuit 112 includes an address management unit 201, a write control unit 202, a read control unit 203, a driver control unit 204, a write request control unit 205, and a stop control unit 206. ing.

  In the control circuit 112, the write address signal WAD, the write control signal WCONT, and the write data signal WD are input from the host circuit 113 to the write control unit 202. The write control unit 202 determines whether to write the write data signal WD to any of the display data storage memories 109 to 111 based on the write address signal WAD in which the display data storage memories 109 to 111 are regarded as one memory. to decide. Here, when it is determined that data is written to the display data storage memory 110 shared by the first liquid crystal display panel 101 and the second liquid crystal display panel 102, the display data storage memory 110 is written from the write control unit 202. The write address signal WAD1, the write control signal WCONT1, and the write data signal WD1 are output to the display data storage memory 110, and the write data signal WD1 is stored. Similarly, when it is determined that writing to the display data storage memory 109 is performed, a write address signal WAD2, a write control signal WCONT2, and a write data signal WD2 are output from the write control unit 202 to the display data storage memory 109, and the display data storage is performed. Write data signal WD 2 is stored in memory 109. When it is determined that the display data storage memory 111 is to be written, the write control unit 202 outputs the write address signal WAD3, the write control signal WCONT3, and the write data signal WD3 to the display data storage memory 111. A write data signal WD3 is stored.

  On the other hand, in the control circuit 112, the read control unit 203 and the driver control unit 204 detect the rising edge of the vertical synchronization signal VSYNC. Based on the detection of the vertical synchronization signal VSYNC, the read control unit 203 generates a read address signal RAD in which the display data storage memories 109 to 111 are regarded as one memory. In the display data storage memory 110, based on the read address signal RAD1 and the read control signal RCONT1 generated by the read control unit 203, the stored display data is output to the source driver 106 as the read data signal RD1. Similarly, the display data storage memory 109 outputs the stored display data to the source driver 105 as the read data signal RD2 based on the read address signal RAD2 and the read control signal RCONT2 generated by the read control unit 203. The display data storage memory 111 outputs the stored display data to the source driver 107 as a read data signal RD3 based on the read address signal RAD3 and the read control signal RCONT3 generated by the read control unit 203.

  The driver control unit 204 receives the read address signal RAD output from the read control unit 203 and controls one of the source drivers 106 to 107 to be driven and the gate driver 103.

  The address management unit 201 compares the write address signal WAD with the read address signal RAD generated by the read control unit 203. In the address management unit 201, when the read address signal RAD exceeds the write address signal WAD, the read address holding signal RADH is output to the read control unit 203. The read control unit 203 can hold the read address RAD without outputting it based on the address hold signal RADH.

  The address management unit 201 compares the address set by the address setting signal ASET output from the host circuit 113 with the read address signal RAD generated by the read control unit 203 (not shown). The address management unit 201 outputs a write notification signal WREP to the write request control unit 205 when the read address signal RAD is larger than the address signal set based on the address setting signal ASET. The write request control unit 205 outputs a write request signal WREQ to the host circuit 113 based on the write notification signal WREP.

  A liquid crystal selection signal PSEL output from the host circuit 113 is input to the stop control unit 206. Based on the liquid crystal selection signal PSEL, the stop control unit 206 controls whether to use both the first liquid crystal display panel 101 and the second liquid crystal display panel 102 or to use the second liquid crystal display panel 102. Do. When both the first liquid crystal display panel 101 and the second liquid crystal display panel 102 are used, the stop control unit 206 does not perform stop control. When only the second liquid crystal display panel 102 is used, the stop control unit 206 detects the liquid crystal display state based on the liquid crystal selection signal PSEL and generates a stop signal STP. The stop signal STP is output to the write control unit 202, the read control unit 203, and the driver control unit 204. Based on the stop signal STP, the write control unit 202 and the read control unit 203 stop the operations of the display data storage memories 109 to 111. Further, based on the stop signal STP, the driver control unit 204 stops the source drivers 105 to 107.

[Configuration of Address Manager]
Next, a detailed configuration of the address management unit 201 of the control circuit 112 will be described. As illustrated in FIG. 4, the address management unit 201 includes a write / read address comparison unit 211, a read address comparison unit 212, and a write address setting unit 213. The write / read address comparison unit 211 compares the write address signal WAD with the read address signal RAD, and outputs the read address holding signal RADH to the read control unit 203 when the read address RAD exceeds the write address WAD. In the read control unit 203, the display data storage memories 109 to 111 can be operated as a FIFO circuit based on the read address holding signal RADH.

  An address setting signal ASET is input to the write address setting unit 213. Based on the address setting signal ASET, the write address setting unit 213 sets the value of the address setting signal ASET. The read address comparison unit 212 compares the address setting signal ASET set by the write address setting unit 213 with the read address signal RAD. When the read address signal RAD is larger than the value of the address setting signal ASET, the read address comparison unit 212 outputs the write notification signal WREP to the write request control unit 205 shown in FIG.

[Liquid crystal display method of liquid crystal display device]
Next, a liquid crystal display method of the liquid crystal display device 10 will be briefly described with reference to FIG.

  First, as shown in step S1, display data is input from the host circuit 113 to the control circuit 112 (see FIG. 1). This transfer of display data is performed in a capacity obtained by multiplying the maximum display number on the scanning line 101G of the first liquid crystal display panel 101 by the maximum display number on the video line 102S of the second liquid crystal display panel 102.

  As shown in step S2, based on the display data input, the control circuit 112 stores the display data in the display data storage memories 109 to 111 (step S3) and reads out the stored display data (step S4). Do. Further, the control circuit 112 controls the source drivers 105 to 107 (step S5) and controls the gate driver 103 (step S6).

  Here, the display data is stored in the display data storage memories 109 to 111 based on the control circuit 112 and the stored display data is read out, and the maximum number of displays on the scanning line 101G of the first liquid crystal display panel 101 and the first display number. The display data can be stored in the display data storage memories 109 to 111 at regular intervals in a capacity multiplied by the maximum display number on the video line 102S of the two liquid crystal display panels 102. The display data stored in 111 can be continuously transferred to the video line 101S of the first liquid crystal display panel 101 and the video line 102S of the second liquid crystal display panel 102.

  The first liquid crystal display driven by the source driver 105 to 107 through the source line 108 and the video line 101S of the first liquid crystal display panel 101 and the gate driver 103 driven through the gate line 104. Display data is transferred to the pixels arranged at the intersection of the panel 101 with the scanning line 101G, and liquid crystal display is performed on the first liquid crystal display panel 101 as shown in step S7. Further, the display data is transferred to the pixels arranged at the intersection between the video line 102S of the second liquid crystal display panel 102 and the scanning line 102G of the second liquid crystal display panel 102, and the second liquid crystal display panel 102. A liquid crystal display is performed at.

  As described above, according to the present embodiment, display data whose writing speed is at least faster than the speed at which display data is transferred from the source drivers 105 to 107 to the first liquid crystal display panel 101 and the second liquid crystal display panel 102. Storage memories 109 to 111 are provided, and display data can be temporarily stored at a high speed operation and transferred to the first liquid crystal display panel 101 and the second liquid crystal display panel 102. As a result, display data is not transferred from the host circuit 113 to the first liquid crystal display panel 101 and the second liquid crystal display panel 102 over the entire one-screen display period, and the processing capacity of the host circuit 113 is reduced. be able to.

  Further, since the display data storage memories 109 to 111 having a high writing speed can repeatedly write and read display data in the one-screen display period, the maximum display number on the scanning line 101G of the first liquid crystal display panel 101 and the second display data are displayed. The storage capacity can be set smaller than the storage capacity corresponding to the total display number of the first liquid crystal display panel 101 by multiplying the maximum display number on the video line 102S of the liquid crystal display panel 102. As a result, the storage capacity of the display data storage memories 109 to 111 can be reduced.

  The display device and the display method according to the present invention have the effect that the processing capacity of the host circuit can be reduced and the storage capacity of the built-in memory can be reduced. In particular, an organic electroluminescence (EL) display, It is effective for a display device having a display such as a plasma display.

Block diagram of a liquid crystal display device according to an embodiment of the present invention Timing chart for explaining the liquid crystal display operation of the liquid crystal display device shown in FIG. 1 is a block diagram showing a control circuit, a display data storage memory, a source driver and a gate driver of the liquid crystal display device shown in FIG. Block diagram of the address management unit of the control circuit shown in FIG. Flowchart for explaining a liquid crystal display operation of the liquid crystal display device according to the embodiment of the present invention. Block diagram of a liquid crystal display device according to the prior art FIG. 6 is a timing chart for explaining a liquid crystal display operation of the liquid crystal display device shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 101 1st liquid crystal display panel (main liquid crystal display panel)
101G, 102G Scan lines 101S, 102S Video lines 103 Gate drivers 104 Gate lines 105-107 Source drivers 109-111 Display data storage memory 112 Control circuit 113 Host circuit 201 Address management unit 202 Write control unit 203 Read control unit 204 Driver control unit 205 Write Request Control Unit 206 Stop Control Unit 211 Write / Read Address Comparison Unit 212 Read Address Comparison Unit 213 Write Address Setting Unit

Claims (6)

A first display panel;
A second display panel having fewer display rows and display columns than the first display panel;
A gate driver for driving scanning lines of the first and second display panels;
A source driver for outputting display data to the video lines of the first and second display panels;
A storage capacity obtained by multiplying the maximum display number on the scanning line of the first display panel by the maximum display number on the video line of the second display panel; And a display data storage memory in which the display data write speed is higher than the transfer speed of the display data to the second display panel;
A control circuit that controls operations of the gate driver, the source driver, and the display data storage memory, and writes the display data to the display data storage memory;
A display device comprising:   The display device according to claim 1, further comprising a host circuit that transfers display data to the control circuit.   The control circuit controls a read address signal for reading display data stored in the display data storage memory to the source driver and a write address signal for writing display data from the host circuit to the display data storage memory, 3. A display device according to claim 2, further comprising a function of operating the display data storage memory as a first-in first-out circuit.   3. The display device according to claim 2, wherein the control circuit has a function of requesting the host circuit to transfer display data before the display data read from the display data storage memory becomes empty.   3. The display device according to claim 2, wherein the control circuit has a function of displaying only the second display panel and stopping the source driver and the display data storage memory that do not need to be activated. In a capacity obtained by multiplying the maximum display number on the scanning line of the first display panel by the maximum display number on the video line of the second display panel, which has a smaller number of display rows and display columns than the first display panel, Storing display data at regular intervals;
Continuously transferring the display data stored at every predetermined period to the video lines of the first and second display panels;
A display method characterized by comprising:

Images