JP2005253106A - Power-on reset circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow stable operation, independently of the speed of start-up after power supply is turned on, with low power consumption, related to a power-on reset circuit. <P>SOLUTION: In the power-on reset circuit, the circuit is initially set, by generating a reset signal when a power supply is turned on. The circuit comprises a charging circuit 1, composed of a resistor R1 and a capacitor C1; a C-MOS inverter 2 for generating the reset signal, until the charge voltage of the capacitor C1 of the charging circuit 1 exceeds a prescribed value; a switch 3 which is positioned between the charging circuit 1 and a power source Vcc and controls supplying of a power source Vcc to the charging circuit 1; an operating voltage setting circuit 4 for setting the voltage for operating the switch 3; a discharging circuit 5 for discharging the charging circuit 1, after the power source Vcc is cut off; and a clamping circuit 6 that maintains the switch 3 in on-state, after the completion of charging. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a semiconductor device including a latch circuit with reset and the like, and more particularly to a power-on reset circuit that generates a reset signal when power is turned on to set an initial value of a latch.

The power-on reset circuit generates a stable reset signal that does not depend on the rise and fall of the power supply voltage after the power is turned on, thereby reducing the size of the capacitor and enabling it to be embedded in a semiconductor device. In addition, it is desired to realize low power consumption by suppressing the power supply current.

   FIG. 6 shows a conventional power-on reset circuit. The conventional power-on reset circuit includes a charging circuit 31 including a resistor R11 and a capacitor C11 connected in series, and a PMOS transistor P11 and an NMOS that input signals between the capacitor C11 and the resistor R11 of the charging circuit 31 to the gates, respectively. It is composed of a transistor N11 and a C-MOS inverter 32 that generates a reset signal.

  In the power-on reset circuit of FIG. 6, when the power supply Vcc is turned on, charging of the capacitor C11 is started. Immediately after the power supply Vcc is turned on, the charging voltage of the capacitor C11 is low, and the output point of the charging circuit 31 is Since it is “L” (low) level, the PMOS transistor P11 of the C-MOS inverter 32 is turned on, the NMOS transistor N11 is turned off, and the output signal of the C-MOS inverter 32 becomes “H” (high) level. This “H” level becomes a reset signal.

   The output signal is actually generated after the power supply Vcc exceeds the threshold value of the PMOS transistor P11.

 Then, the charging voltage of the capacitor C11 increases corresponding to the rise of the power supply Vcc, and when this charging voltage exceeds one half of the power supply Vcc, the input signal of the C-MOS inverter 32 becomes "H" level, The PMOS inverter P11 is turned off, the NMOS transistor N11 is turned on, the output signal from the C-MOS inverter 32 is inverted to "L" level, and continues to output "L" level until the power is cut off.

  In the power-on reset circuit described above, if the rise of the power supply Vcc is delayed, it is necessary to increase the values of the resistor R11 and the capacitor C11, and the size of each of these elements increases. It becomes difficult to incorporate in the device.

 Therefore, a circuit having a function of setting a power supply voltage for starting charging as shown in FIG. 7 can be considered.

The power-on reset circuit shown in FIG. 7 is a charging circuit 41 comprising two stages of NMOS transistors N12 and N13 and a capacitor C12 connected in series to these NMOS transistors.
And a CMOS inverter 42 for generating a reset signal, and a low threshold value and a high voltage, respectively, and a PMOS transistor P11 and an NMOS transistor N11 for inputting signals between the capacitor C12 of the charging circuit 41 and the NMOS transistor N13 to the gates, respectively. It comprises a discharge circuit 43 comprising a resistance NMOS transistor N14.

 According to this circuit, when the power supply Vcc is shut off after the charging of the capacitor C12 is completed, the discharge circuit 43 having a low threshold voltage is turned off with a slight delay, so that the charge charged in the capacitor C12 is During this time, the discharge circuit 43 discharges.

 Therefore, the charge of the capacitor C12 when the power supply Vcc is raised again can be kept low, and malfunction can be prevented.

Further, the charging circuit 41 having the two-stage NMOS transistors N12 and N13 has a high threshold voltage (2Vth) and does not turn on until the power supply Vcc sufficiently rises. Delayed until a reset signal is reliably generated.
Patent Documents 1 and 2 are disclosed as the related art.
Japanese Patent Laid-Open No. 6-311003 JP-A No. 64-12719

  Since the conventional power-on reset circuit shown in FIG. 6 may prevent stable operation when the power supply Vcc rises slowly as described above, the resistance in the charging circuit 31 can be avoided. Countermeasures such as increasing the time constant of R11 and capacitor C11 are required. In this case, since each element having a high resistance and a large capacity is required, it is difficult to incorporate the element into a semiconductor device, resulting in an increase in size.

  Further, in the power-on reset circuit shown in FIG. 7, the potential accumulated in the capacitor C12 when the charging of the capacitor C12 is completed is higher than the voltage of the power supply Vcc. Since the voltage is lowered by the sum (2Vth), a potential difference necessary for the operation occurs between the gate and the source of the PMOS transistor P11, and the PMOS transistor P11 is turned on.

  For this reason, a through current flows from the power source Vcc to the PMOS transistor P11 and the NMOS transistor N11 of the C-MOS inverter 42.

 Further, in the case of this circuit, a current constantly flows through the NMOS transistor N14 constituting the discharge circuit 43, so that the power supply current increases and the power consumption increases.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems and to realize a circuit that can perform a stable operation and has low power consumption regardless of whether the power supply rises or not.

  In order to solve the above problems, the present invention provides a power-on reset circuit that initializes a circuit by generating a reset signal when the power is turned on. A charging circuit to which a transistor defining a voltage is connected in series; an output signal of the charging circuit; and a C− connected between a point between the transistor and the resistor in the charging circuit and a ground electrode. It is characterized by comprising a MOS inverter, a level shift circuit for increasing the voltage level of the output signal of the C-MOS inverter, and a discharge circuit for discharging the charging circuit after the power supply is shut off.

  According to the power-on reset circuit of the present invention, charging to the charging circuit 1 is started after rising to a predetermined voltage after the power supply Vcc is turned on by the operation of the switch 3 and the operating voltage setting circuit 4 of the switch 3. Regardless of the rise or fall of the power supply Vcc, the reset signal can be reliably generated.

  In addition, since the clamp circuit 6 controls the switch 3, a through current of the C-MOS inverter 2 that flows after completion of charging can be prevented, so that power consumption can be suppressed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a principle diagram of a power-on reset circuit according to a first aspect of the present invention. A charging circuit 1 comprising a resistor R1 and a capacitor C1, and a PMOS transistor P1 and an NMOS transistor which operate by inputting an output signal of the charging circuit 1. A C-MOS inverter 2 composed of N1, a switch 3 composed of a PMOS transistor P2 located between the charging circuit 1 and the power source Vcc, and an operating voltage setting circuit 4 composed of a PMOS transistor P3 for setting the operating voltage of the switch 3. And a discharge circuit 5 comprising a PMOS transistor P4 for discharging after the power supply is cut off, and a switch 3 is securely connected to prevent a through current from the power supply Vcc of the C-MOS inverter 2 comprising two stages of NMOS transistors N2 and N3. And a clamp circuit 6 which is turned on.
In this circuit, the capacitor C1 of the charging circuit 1 is charged by the start of the operation of the switch 3, and the operating voltage of the switch 3 is determined by the PMOS transistor P3 in the operating voltage setting circuit 4. .

That is, when the voltage of the power source Vcc becomes higher than the sum of the threshold voltage Vth of the PMOS transistor P3 in the operating voltage setting circuit 4 and the threshold voltage Vth of the PMOS transistor P2 constituting the switch 3, the switch 3 Works.
Therefore, for example, when the threshold voltages Vth of the PMOS transistors P3 and P4 are 0.6 [V] and the parasitic capacitance of the capacitor C1 is 0.4 [V], the voltage is 1. When the voltage rises to 6 [V], charging of the capacitor C1 of the charging circuit 1 is started.

In general, the threshold value of a MOS transistor is about 0.8 [V], but current starts to flow little by little from around 0.6 [V]. It demonstrated as 0.6 [V].
On the other hand, the threshold voltage of the C-MOS inverter 2 is, for example, about one-half of the power supply voltage. When the input portion, that is, the charging voltage of the charging circuit 1 is less than half of the power supply voltage, “L” Since the PMOS transistor P1 is on and the NMOS transistor N1 is off at the level, the output signal of the C-MOS inverter 2 is at the “H” level, and this is the reset signal.
Then, the charging voltage rises with time, and when this voltage becomes more than half of the power supply voltage, the input signal becomes “H” level, the PMOS transistor P1 is turned off, and the NMOS transistor N1 is turned on. Therefore, the output signal of the C-MOS inverter 2 is inverted to the “L” level and continues until the power is shut off.
As described above, after the output signal of the C-MOS inverter 2 is inverted to the “L” level, according to this circuit, the clamp circuit 6 composed of two stages of NMOS transistors N2 and N3 lowers the input voltage of the switch 3. By suppressing the voltage, the switch 3 is reliably maintained in the ON state, and the output voltage of the charging circuit 1 is maintained at the same level as the power source Vcc.
Accordingly, since the PMOS transistor P1 is not turned on, a through current of the C-MOS inverter 2 flowing from the power source Vcc can be prevented.
That is, when the voltage of the power supply Vcc increases, the two-stage NMOS transistors N2 and N3 in the clamp circuit 6 are turned on, so that the level of the input point of the switch 3 is the sum of the threshold voltages Vth of the NMOS transistors N2 and N3. Lower the power supply voltage by the amount.
Since the PMOS transistor P2 of the switch 3 operates when its gate voltage is lower than the power supply voltage by the threshold voltage Vth, the level of the gate of the PMOS transistor P2 is set by the two-stage NMOS transistors N2 and N3 as described above. It is low enough to make sure it is on. For this reason, the level between the switch 3 and the charging circuit 1 is the same level as the power supply voltage, and the level of the output point of the charging circuit 1 when charging is completed is also the same. Therefore, when the output of the charging circuit 1, that is, the input of the C-MOS inverter 2 is at "H" level, the PMOS transistor P1 of the C-MOS inverter 2 is not turned on, and no through current is generated.
Finally, when the power supply Vcc is shut off, the discharge circuit 5 operates to discharge the charge charged in the capacitor C1 in the charging circuit 1. As a result, the voltage level at the output point of the charging circuit 1 is sufficiently lowered, so that it is possible to prevent malfunction when the power supply Vcc is turned on again.
As described above, according to the present invention, it is possible to reliably generate a reset signal regardless of whether the power supply rises or not, and to prevent a through current after charging.
Next, examples of the present invention will be described.
FIG. 2 is a circuit diagram for explaining an embodiment of the present invention. The charging circuit 11, the C-MOS inverter 12, the switch 13, the operating voltage setting circuit 14, the discharging circuits 15, 17 and the clamp circuit 16 are shown in FIG. It is composed of
The charging circuit 11, the C-MOS inverter 12, and the clamp circuit 16 in the present embodiment are the same as the circuit described in FIG.
The switch 13 is composed of a PMOS transistor P2 connected between the power supply Vcc and the charging circuit 11, and a resistor R2 connected to the gate thereof, and an operating voltage for controlling the operating voltage of the switch 13 The setting circuit 14 includes a PMOS transistor P3, a resistor R2 positioned between the gate of the PMOS transistor P3 and the ground, a resistor R4 connected in series to the PMOS transistor P3, and a capacitor C2.
The discharge circuit 15 includes a PMOS transistor P4 connected between the input point of the charging circuit 11 and the ground point, and a resistor R5 connected between the gate and the power source Vcc.
Further, in this embodiment, in order to discharge the electric charge accumulated in the clamp circuit 16, the PMOS transistor P5 connected between the gate of the NMOS transistor N3 and the ground point, the gate of the PMOS transistor P5 and the power source Vcc. And a discharge circuit 17 comprising a resistor R6 connected between the two.
The operation of this circuit will be described with reference to the voltage graph of FIG.
FIG. 3 is a graph showing the voltage level of the power supply Vcc and the main points in the circuit of FIG. 2 as time elapses. The solid line indicates the power supply Vcc, the broken line indicates the output point A of the charging circuit 11, and The change of the input point C of the switch 13 is shown by the output point B of FIG.
In the circuit of this embodiment, when the power supply Vcc is first turned on, the voltage rises with a predetermined gradient as shown in FIG.
In this embodiment, a power supply of 2.5 [V] is used, and after reaching 2.5 [V], a stable state is obtained.
The supply of the power source Vcc to the charging circuit 11 is controlled by the switch 13 and the operating voltage setting circuit 14 for setting the operating voltage of the switch 13 as in the circuit of FIG. This is started when the sum of the threshold voltages Vth of the transistors P2 and P3 is added to the parasitic capacitance, for example, 1.6 [V].
Therefore, as shown in FIG. 3, the voltage level at the output point A of the charging circuit 11 rises according to the time constant of the resistor R1 and the capacitor C1 after the power source Vcc becomes 1.6 [V], As will be described later, the operation of the clamp circuit 16 and the switch 13 stabilizes at the same level as the power supply Vcc after a predetermined time.
On the other hand, when the input signal of the C-MOS inverter 12 is at "L" level, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off, but the PMOS transistor P1 has a source voltage with respect to its gate voltage. Since the operation is performed when the threshold value Vth is increased, an output voltage is generated when the voltage of the power source Vcc serving as the source voltage becomes 0.8 [V] higher than the charging circuit 11 serving as the gate voltage.
That is, as shown in FIG. 3, since the output voltage A of the charging circuit 11 is initially 0.4 [V], the power supply Vcc is higher by 1.2 [V] than the threshold voltage Vth. At this point, the voltage at the output point B of the C-MOS inverter 12 starts to rise.
The output voltage B of the C-MOS inverter 12 continues to rise as shown in FIG. 3 and becomes the same level as the power supply Vcc after a predetermined time, and this becomes the "H" level, that is, the output of the reset signal of this circuit.
Thereafter, the output voltage B of the C-MOS inverter 12 continues to rise with the power supply Vcc until the on / off of the PMOS transistor P1 and the NMOS transistor N1 is inverted, and then falls.

The output signal of the C-MOS inverter 12 is inverted when the input signal is changed from the L level to the H level, but becomes the H level when it exceeds a half of the power supply Vcc.
In the case of this embodiment, as shown in FIG. 3, when the power supply Vcc is 2.0 [V], the output voltage A of the charging circuit 11 exceeds 1.0 [V], and at this time, the PMOS transistor P1 The NMOS transistor N1 is turned on and off, and the output voltage B of the C-MOS inverter 12 starts to decrease and becomes 0 [V] after a predetermined time.
The clamp circuit 16 constituted by two stages of NMOS transistors N2 and N3 determines the level of the input point C of the switch 13 as the sum of threshold voltages Vth of both transistors N1 and N2, for example 1.6 [V]. Only after the charging of the charging circuit 12 is completed, the voltage level of the input point C of the switch 13 is clamped to a sufficiently low value, that is, 0.9 [V]. doing.
Therefore, the PMOS transistor P2 constituting the switch 13 is surely maintained in the ON state, and the level of the output point A of the charging circuit 11 is maintained equal to the level of the power supply Vcc as shown in FIG.
For this reason, there is no potential difference between the gate and the source of the PMOS transistor P1 of the C-MOS inverter 12, and this does not turn on, so that a through current from the power source Vcc of the C-MOS inverter 12 can be reliably prevented. it can.
Further, when the power supply Vcc is shut off, the discharge circuits 15 and 17 operate to charge the capacitor C1 in the charging circuit 11 and the charge accumulated in the gate of the NMOS transistor N3 in the clamp circuit 16. Each can be discharged.
As a result, when the power supply Vcc is turned on again, the voltage level at each point is sufficiently low, so that malfunction can be prevented.
As is clear from FIG. 3, the level of the output point A of the charging circuit 11 and the level of the input point C of the switch 13 require a predetermined operating voltage for the PMOS transistors P4 and P5 in the discharge circuits 15 and 17. Therefore, although a constant potential remains, there is no problem because the potential has been sufficiently discharged up to the correct operation.
In the operating voltage setting circuit 14, a resistor R4 and a capacitor C2 are connected in series between the drain of the PMOS transistor P3 and the ground point. This is because the PMOS transistor P3 is connected from the output point C of the clamp circuit 16. This is provided to prevent a steady current from escaping.
As described above, according to the power-on reset circuit of the present embodiment, the C-MOS inverter 12 is charged before the charging of the charging circuit 11 is started without increasing the values of the resistor R1 and the capacitor C1 of the charging circuit 11. Therefore, the “H” level (reset signal) can be reliably output at the start of this operation.
Therefore, it is possible to use a small resistor R1 and capacitor C1, so that this circuit can be built in a semiconductor device.
In addition, since the through current of the C-MOS inverter 12 flowing from the power source Vcc can be surely prevented, the power consumption can be suppressed, which is suitable for applications that require low power consumption such as a mobile phone.
In this embodiment, the charging start voltage of the charging circuit 11 is controlled by the PMOS transistor P3 of the operating voltage setting circuit 14 and the PMOS transistor P2 of the switch 13. However, for example, an NMOS transistor is added to the operating voltage setting circuit 14. Thus, the charging start voltage can be further increased by the threshold voltage Vth.
In this case, the NMOS transistor has a drain and a gate connected to the output point C of the clamp circuit 16 and a source connected to the source of the PMOS transistor P3.
Further, the PMOS transistors P2 to P5 constituting the switch 13, the operating voltage setting circuit 14, and the discharge circuits 15 and 17 can be replaced with PNP-type bipolar transistors, and the same action can be expected.
Further, although the clamp circuit 16 uses two stages of NMOS transistors N2 and N3, the same effect can be obtained by using two stages of PMOS transistors.
In this case, the source of the first-stage PMOS transistor is connected to the power supply Vcc, the gate and drain are short-circuited and connected to the source of the second-stage PMOS transistor, and the gate is connected to the source of the PMOS transistor P5 of the discharge circuit 17. The gate and drain of the second stage PMOS transistor are short-circuited and connected to the switch 13 and the voltage setting circuit 14.
FIG. 4 is a circuit diagram for explaining an embodiment of the second invention suitable for use of a power supply Vcc having a relatively high voltage.
The power-on reset circuit of this embodiment includes a charging circuit 21, a C-MOS inverter 22 that inverts the output signal of the charging circuit 21, and a level shift circuit 24 that converts the voltage level of the output signal of the C-MOS inverter 22. And a discharge circuit 25 for discharging the charge accumulated in the charging circuit 21 after the power supply Vcc is shut off.
Although not particularly shown, a C-MOS inverter or a through circuit may be further provided for logical matching or as a buffer.
The charging circuit 21 is constituted by a series circuit of two-stage NMOS transistors N7 and N8 connected to the power supply Vcc side, a resistor R6 and a capacitor C3, and when the power supply Vcc reaches a predetermined voltage after being turned on, Charging with the capacitor C3 is started.
The C-MOS inverter 22 includes a PMOS transistor P8 and an NMOS transistor N6. The source electrode of the PMOS transistor P8 is connected between the NMOS transistor N6 of the charging circuit 21 and the resistor R6, so that a high-potential power source can be used. It is low.
The level shift circuit 24 includes an NMOS transistor N5 to which the output signal of the C-MOS inverter 22 is input, an NMOS transistor N4 to which the output signal of the charging circuit 21 is input, and a PMOS connected between the NMOS transistor N5 and the power source Vcc. The gate electrode of the PMOS transistor P7 is the drain electrode of the PMOS transistor P6, and the gate electrode of the PMOS transistor P6 is the drain of the PMOS transistor P7. Each point is connected to an electrode, and a point between the PMOS transistor P6 and the NMOS transistor N4 is used as an output signal.
The discharge circuit 25 includes a PMOS transistor P9 whose source electrode is connected to the output point of the charging circuit 21, and a resistor R7 connected between the gate electrode of the PMOS transistor P9 and the power source Vcc.
The operation of the power-on reset circuit having the above configuration will be described with reference to the voltage graph of FIG.
FIG. 5 is a graph showing the voltage level of the power source Vcc and the main points in the circuit of FIG. 4 as time elapses. The power source Vcc is indicated by a thick solid line, the output point A of the charging circuit 21 is indicated by a broken line, The level B between the transistor N8 and the resistor R6, the dotted line indicates the output point C of the C-MOS inverter 22, and the alternate long and short dash line indicates the change in the level shift circuit 24, that is, the output point D of the power-on reset circuit.
In FIG. 5, there are actually portions that overlap the voltage levels at each point, but are shown slightly shifted for easy understanding. In the circuit of this embodiment, when the power supply Vcc is first turned on, the voltage rises with a predetermined gradient as shown in FIG.
In this embodiment, a power supply of 5.0 [V] is used, and after reaching 5.0 [V], a stable state is obtained.
The supply start of the power source Vcc to the charging circuit 21 is defined by the two-stage NMOS transistors N7 and N8. The sum of these threshold voltages Vth, for example, 1.2 [V], the parasitic capacitance of the capacitor C3, For example, it starts when the power supply Vcc rises to a voltage obtained by adding 0.4 [V].
Therefore, as shown in FIG. 5, the voltage level at the output point A of the charging circuit 21 rises according to the time constant of the resistor R6 and the capacitor C3 after the power source Vcc becomes 1.6 [V], It stabilizes at a value 1.2 [V] lower than the voltage level of the power supply Vcc.
The level between the NMOS transistor N8 and the resistor R6 serving as the high potential power supply for the C-MOS inverter 22 in the next stage is proportional to the voltage rise of the power supply Vcc from around 1.6 [V], similar to the output point A. Then, the voltage starts to rise and stabilizes at a value 1.2 [V] lower than the voltage level of the power supply Vcc.
Next, when the signal is output from the charging circuit 21 (initially “L” level), the C-MOS inverter 22 turns on the PMOS transistor P8 and turns off the NMOS transistor N6. The voltage rapidly rises to the H "level, that is, the same voltage as point B serving as a high potential power source.
After that, it continues to rise with the B point level until the on / off state of the PMOS transistor P8 and NMOS transistor N6 constituting the C-MOS inverter 22 is inverted, and then falls.
The output signal of the C-MOS inverter 22 is inverted when the input signal changes from the “L” level to the “H” level, but becomes “H” level when the voltage exceeds half of the voltage at the point B. .
In the case of this embodiment, as shown in FIG. 5, when the voltage at the point B is 3.8 [V], the output voltage A of the charging circuit 21 exceeds 1.9 [V]. Transistor P8 and NM
The on / off state of the OS transistor N6 is switched, and the output voltage C of the C-MOS inverter 22 starts to decrease and becomes 0 [V] after a predetermined time.
Finally, the level shift circuit 24 shifts the level of the output C of the C-MOS inverter 22 having an amplitude from the ground potential to 3.8 [V] to an amplitude up to the power supply voltage Vcc. It is as follows.
First, before the start of charging in the charging circuit 21, that is, until the power source Vcc is near 1.6 [V], the output point D of the level shift circuit 24 is 0 [V] and the power source Vcc is the same as the output point C. The voltage starts to rise when the voltage exceeds 1.6 [V] and rises steeply to the level of the power supply Vcc. Thereafter, it continues to rise corresponding to the power supply Vcc, and falls simultaneously with the inversion of the signal at the output point C of the C-MOS inverter 22. That is, immediately after the start of voltage increase at the output point D of the level shift circuit 24, the signal input to the gate electrode of the NMOS transistor N5 of the level shift circuit 24 is turned on at "H" level and input to the gate electrode of the NMOS transistor N4. The signal to be turned off is “L” level.
Accordingly, the potential of the gate electrode of the PMOS transistor P6 becomes 0 [V], the PMOS transistor P6 is turned on, and the output signal D becomes “H” level. The “H” level output of the signal D becomes a reset signal as shown in FIG. At this time, the “H” level is input to the gate electrode of the PMOS transistor P7, and the PMOS transistor P7 is in the OFF state. This state continues until the logic of the signal A input to the C-MOS inverter 22 is inverted. That is, when the signal A changes from the “L” level to the “H” level as the charging voltage increases, the output signal C changes from the “H” level to the “L” level, and the NMOS of the level shift circuit 24. The transistor N5 is turned off, the NMOS transistor N4 is turned on, the output signal D becomes “L” level, and the output of the reset signal is released.
Incidentally, at this time, the input signal to the gate electrode of the PMOS transistor P7 is “L” level and turned on, and the input signal to the gate electrode of the PMOS transistor P6 is “H” level and turned off.
Finally, when the power supply Vcc is shut off, the discharge circuit 25 operates to discharge the charge charged in the capacitor C3 in the charging circuit 21. As a result, the voltage level at the output point of the charging circuit 21 is sufficiently lowered, so that it is possible to prevent malfunction when the power supply Vcc is turned on again.
According to the present embodiment, since the source electrode of the PMOS transistor P8 of the C-MOS inverter 22 to be controlled is connected to the point B by the output signal of the charging circuit 21, the level of the high potential power supply is lowered. After completion, it is possible to prevent generation of a through current due to the PMOS transistor P8 being turned on.
That is, when the charging of the capacitor C3 of the charging circuit 21 is completed, the signal A input to the C-MOS inverter 22 and the potential of the high potential power supply B are the same, and the gate electrode of the PMOS transistor P8 Since there is no potential difference between the source electrode and the source electrode, the PMOS transistor P8 is not turned on.
However, the output signal C of the C-MOS inverter 22 has a small voltage amplitude because the high potential power supply is low.

  For this reason, for example, in the case of a circuit having an inverter in the next stage, the “H” level voltage input to the inverter becomes low, and an unnecessary current flows due to a malfunction of a transistor constituting the inverter. .

In order to prevent the malfunction caused by the low voltage amplitude as described above, the level shift circuit 24 for increasing the voltage amplitude is provided.
According to the power-on reset circuit of the present invention described above, charging to the charging circuit is started after the power supply voltage has risen to a predetermined value, so that the reset signal can be reliably transmitted regardless of the rise and fall of the power supply Vcc. Can be generated. For this reason, it is not necessary to particularly increase the values of the resistor and the capacitor constituting the charging circuit, and the semiconductor device can be embedded.
In addition, since the clamp circuit controls the switch, it is possible to prevent a through current of the C-MOS inverter flowing from the power source after the completion of charging, so that power consumption can be suppressed.

It is a circuit diagram for demonstrating the principle of 1st invention. It is a circuit diagram for demonstrating the Example of 1st invention. It is a graph which shows the change of the voltage level in the Example of 1st invention. It is a circuit diagram for demonstrating the Example of 2nd invention. It is a graph which shows the change of the voltage level in the Example of 2nd invention. It is a figure for demonstrating the conventional power-on reset circuit (1). It is a figure for demonstrating the conventional power-on reset circuit (2).

Claims (2)

In a power-on reset circuit that initializes the circuit by generating a reset signal when the power is turned on,
A resistor, a capacitor, and a charging circuit, which is located on the power source side, and in which a transistor that defines a charging start voltage of the capacitor is connected in series;
An input signal of the charging circuit, and a C-MOS inverter connected between a point between the transistor and the resistor in the charging circuit and a ground electrode;
A level shift circuit for raising the voltage level of the output signal of the C-MOS inverter;
A power-on reset circuit comprising: a discharge circuit that discharges the charging circuit after power is shut off. The level shift circuit includes:
An NMOS transistor to which an output signal of the C-MOS inverter is input;
An NMOS transistor to which an output signal of the charging circuit is input;
A PMOS transistor connected between the NMOS transistor and a power source Vcc;
A PMOS transistor connected between the NMOS transistor and a power source Vcc;
The gate electrode of the PMOS transistor is connected to the drain electrode of the PMOS transistor, the gate electrode of the PMOS transistor is connected to the drain electrode of the PMOS transistor, and the output terminal is between the PMOS transistor and the NMOS transistor. The power-on reset circuit according to claim 1.

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