JP2005252544A - Signal transfer circuit and its design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transfer circuit for obtaining an output without waveform disturbance from a signal line of a poststage, where a signal is input from a starting end of a signal line of a prestage and a termination resistor matched with an impedance of the signal line at the poststage is connected to a termination of the signal line of the poststage, in a plurality of signal lines which have impedances and are connected in series, and also to provide a design method of the circuit. <P>SOLUTION: In the signal transfer circuit, a damping resistor having a resistance value being a difference obtained by subtracting an impedance value of the signal line of the poststage from an impedance value of the signal line of the prestage is inserted between an output of an output driver to which the signal is input and the starting end of the signal line of the prestage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal transmission circuit and a design method thereof. In particular, the present invention relates to a signal transmission circuit capable of matching characteristic impedances of signal lines constituting the signal transmission circuit, and a design method thereof. More specifically, even when a signal is branched from one signal line to a plurality of signal lines, and the signal is distributed from the signal line after branching, the output signal waveform after distribution is matched by matching the characteristic impedance of the line system. The present invention relates to a signal transmission circuit that keeps a good state and a design method thereof.

Since the signal line of the signal transmission circuit has characteristic impedance, the signal input from the input end of the signal line is reflected at the end of the open signal line when nothing is dealt with. Then, the signal waveform at the input end is obtained by superimposing the reflected wave on the input signal waveform. In order to eliminate the influence of this reflected wave, it is generally known to match the impedance by inserting a termination resistor at the end of the signal line. Thus, the signal waveform at the input end of the signal line where the impedance is matched becomes the input signal waveform.
Further, as shown in FIG. 9, the output driver 2 and the semiconductor device 21 are mounted on the multilayer substrate 20, and a signal input from the input terminal 1 on the substrate 20 is branched into a plurality of signal lines in the semiconductor device 21. In the case of a complicated line system that distributes to the output terminals 24 and 25, the influence of reflection cannot be eliminated by the simple method described above. An example of a signal transmitted through such a line system is a clock signal.
The signal transmission circuit that is a line system shown in FIG. 9 includes an input terminal 1, an output driver 2 that transmits a signal input from the input terminal 1 to a subsequent stage, and an inside of the substrate 20 to which an output of the output driver 2 is transmitted. A substrate inner layer wiring 22 that is a layer wiring of the semiconductor device, an external terminal (point 1) of the semiconductor device 21 connected to the wiring 22, a device inner layer wiring 23 that is a layer wiring in the semiconductor device connected to the terminal, The signal lines 3 and 5 branched inside the device constituting the wiring 23, an output terminal 24 for outputting a plurality of signals distributed from the signal line 3, and an output terminal for outputting a plurality of signals distributed from the signal line 5 25, and the signal lines 3 and 5 extending from the branch point are further extended, and the layer wiring 22 is provided in the substrate 20 via the external terminal and extends to the point 6 via the external terminal. FIG. 5 shows a schematic circuit diagram equivalent to the signal transmission circuit of FIG. In FIG. 5, the impedance of the layer wiring from the output of the output driver 2 until branching the signal line 3 to 5 can be ignored, are each Z ₂ each impedance of the signal line 3 and 5, after branching in the device 21 Assume that each end (point 6) of signal lines 3 and 5 is open. In this case, when a signal is input from the input end 1, the signal is reflected at each end of the signal lines 3 and 5. Therefore, a termination resistor 4 or 6 having a resistance value Rt = Z ₂ is connected between each of these terminations and the ground potential. The signal lines 3 and 5 are matched in impedance by these termination resistors. Accordingly, since there is no reflection at the terminal ends of the signal lines 3 and 5, the waveform of the signal at the point 1 is not superimposed with the reflected wave, and a waveform close to the waveform of the input signal is obtained. In this way, reflected waves are also output from the output terminals 24 and 25 (not shown in FIG. 5; see FIG. 9) for outputting the signals distributed from the signal lines 3 and 5, respectively. It is known that an unaffected signal waveform can be obtained.
Japanese Patent Application Laid-Open No. 2003-43066 discloses a device in which a terminal resistor is connected to each signal line in the same manner as in FIG. 5 in order to make a signal distributed and output from each signal line after branching unaffected by reflected waves. ing.
JP 2003-43066 A

However, as shown in FIG. 9, a signal line having an impedance Z ₁ that is actually formed by the layer wiring 22 in the substrate between the output driver 2 and the external terminal (point 1) of the device 21. There are 12. When viewed line system overall impedance illustrated from the output of the output driver 2, the impedance of the entire line system by the influence of the impedance Z ₁ is not matched. The signal waveform at point 1 is a disturbed waveform including a reflection component. The signal transmission circuit of FIG. 9 is assembled in an actual machine, and a signal waveform (upper rectangular wave) input to the input terminal 1 in FIG. 5 which is a circuit diagram corresponding to FIG. 9 and signal points 1, 2, 3, 4, 5 6 show signal waveforms (each waveform with a lower curve) in FIG. Further, the upper waveform in FIG. 7 is a signal waveform input to the input terminal 1 in the signal transmission circuit in FIG. 5, and the lower waveform is a signal waveform output from the receiver circuits 7, 8, 9, 10 and 11. . FIG. 8 is an enlarged view of a signal waveform in a portion surrounded by a broken line in FIG. Incidentally, each Rt is 40 [Omega, _{Z 2} are each 40 [Omega, the output impedance of the output driver 2 50 [Omega, also the impedance _{Z 1} of the signal line 12 is 50 [Omega. If the signal waveform on the signal line 3 is not affected by the reflected wave, the signal input from the input terminal 1 is in the order from the input terminal 1 to the termination point 6 on the line. , 9, 10, and 11 are output as signals that are sequentially delayed in this order. However, when the signal at point 1 is a disturbed signal waveform including a reflection component as shown in FIG. 6, the output order of the signals from each receiver circuit as shown in FIG. The receiver circuits 10, 9, 11, 8, and 7 are different in order from the above. The reason why the order is different is that when the signal waveform on the signal line 3 is disturbed due to the influence of the reflected wave, the time when the disturbed signal exceeds the input threshold value in each receiver circuit is also disturbed. It is to become a thing. As a result, as shown in FIG. 8, the signal output from each receiver circuit has a disordered timing skew in the output order.
It is also known to insert a damping resistor between the output driver 2 and the signal line 12 in order to reduce the influence of a signal having a distorted waveform due to the influence of the reflected wave. In this case, although the peak value of the disturbed signal waveform decreases, the disturbed waveform does not become a normal waveform, and only an effect of reducing the influence on the subsequent circuit exerted by the signal having the disturbed waveform can be obtained. Therefore, the method of simply inserting a damping resistor cannot be an essential solution to the problem of obtaining a signal having a normal waveform with no influence of reflection and obtaining a normal timing skew.
The object of the present invention is to make the output signal waveform of the output driver 2 have a normal waveform without the influence of reflection, and as a result, the output terminals 24 and 25 distributed and output from the signal lines 3 and 5, respectively. It is to provide a signal transmission circuit having a normal timing skew and a design method thereof so that each signal output from the signal has a normal waveform.

To solve the above problem,
(1) The signal transmission circuit according to the present invention includes an output driver for inputting a signal, a first signal line connected in series with the output driver, and the first line end not connected to the output driver. A second signal line that is connected in series to the signal line and distributes and outputs a signal from within the signal line, and a terminal that is not connected to the first signal line, and is connected to the terminal of the second signal line. In the signal transmission circuit having a termination resistor that matches the impedance of the second signal line, the first signal is inserted between the output of the output driver and the first signal line. It has a damping resistor having a resistance value of a difference value obtained by subtracting the impedance value of the second signal line from the impedance value of the line.
(2) The second signal line of the signal transmission circuit of the present invention described in (1) includes a plurality of lines branched into a plurality of points with a connection point with the first signal line as a branch point. The termination resistors that match the impedance of each line are connected to the respective ends of the line, and the impedance of the second signal line is a combined impedance of the plurality of lines. .
(3) The resistance value of each termination resistor connected to the plurality of lines of the signal transmission circuit of the present invention described in (2) is the same as the impedance value of the line to which the termination resistor is connected, The output impedance value of the output driver is the same as the impedance value of the first signal line.
(4) In the design method of the signal transmission circuit according to the present invention, a signal is input to an output driver, the output driver and the first signal line are connected in series, and the first line is not connected to the output driver. One signal line is connected in series with a second signal line that distributes and outputs a signal from within the signal line, and is connected to an end of the second signal line that is not connected to the first signal line. The resistance value of the termination resistor to be set to a value that matches the impedance of the second signal line, and the resistance value of the damping resistor inserted between the output of the output driver and the first signal line To the resistance value of the difference value obtained by subtracting the impedance value of the second signal line from the impedance value of the first signal line.

  As described above, according to the present invention, the impedance of the signal input terminal of the first signal line obtained by terminating the first signal line with the termination resistor having the same resistance value as the impedance of the first signal line is obtained at the impedance. In the line system to which the second signal line having the above is connected, the connection end to the first signal line is a resistor connected to the other end of the other second signal line. A signal is input to the second signal line via the resistor, and the signal is transmitted to the first signal line via the second signal line. Then, by determining the resistance value of this resistor from the impedance of both the first and second signal lines, the signal waveform at the connection point of the first and second signal lines can be obtained when a signal is input through this resistor. As a result, the waveform of the signal distributed from the first signal line can be changed to a normal waveform that is not affected by the reflection, and each distributed signal has no problem of timing skew. Can solve the problem. Each signal distributed without being affected by reflection has a waveform that does not change in level even near the threshold level of each receiver circuit. This eliminates the problem of timing skew.

Next, the best mode for carrying out the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same reference numerals are given to the same parts as in the other drawings.
The configuration of the signal transmission circuit of the present invention will be described with reference to FIG. In FIG. 1, the signal line 12 having an impedance Z ₁ between the point 1 which is a branch point of the signal lines 3 and 5 and the output of the output driver 2 having the output impedance Z ₁ is different from the conventional example of FIG. And a damping resistor 13 having a resistance value Rd connected in series via a point 7 is inserted. The signal transmission circuit which is a line system shown in FIG. 1 includes an input terminal 1, an output driver 2 for transmitting a signal input from the input terminal 1 to a subsequent stage, and a damping resistor 13 connected to the output of the output driver 2. The signal line 12 connected in series with the damping resistor 13, the signal line 3 connected to the signal line 12 via the point 1, which is the terminal of the signal line 12, and branched at the point 1, Receiver circuits 7, 8, 9, 10, 11 for receiving the received signals, receiver circuits for receiving the signals distributed from the signal lines 5, and terminations (points) of the signal lines 3 and 5 extending from the branch points It is composed of termination resistors 4 and 6 connected to 6).
Incidentally, in FIG. 9 of the conventional example, although the signal line 12 originally existed, the impedance of the signal line 12 was not taken into consideration. The present invention considers the influence of the impedance of the signal line 12. The resistor 13 is conventionally known as a damping resistor. However, if only the role as a conventional damping resistor is considered, it is merely a matter of lowering the peak value of the signal, as described in the problem column. The inventor of the present invention makes the influence of reflection hardly appear in the signal waveform at point 1 by setting the resistance value of the damping resistor 13 to the difference value between the impedance of the signal line 12 and the combined impedance of the signal lines 3 and 5. I found out.
First, the resistance values Rt of the termination resistors 4 and 6 connected to the respective ends of the signal lines 3 and 5 having the impedance Z ₂ are set to be substantially the same as the impedance Z ₂ .
Rt = Z ₂
That means
(Resistance value of termination resistor) = (impedance value of signal line terminated and terminated by termination resistor) (1)
Thus, the reflected signal returning from the point 6 to the point 1 is eliminated.
Furthermore, the combined impedance of the signal line 3 and 5 a later stage of the impedance among viewed from the input terminal 1 two impedances in series connection, both impedance, each with a value of Z ₂ in line 3 and line 5 is in parallel since going _on, it is a _Z 2/2. Then, the impedance of the preceding stage of the signal line 12 is Z _1, the resistance value Rd of the damping resistor 13 in this case,
_{Rd = Z 1 - (Z 2} /2)
That means
(Resistance value of the damping resistor) = (impedance of the signal line in the previous stage) − ((combined) impedance of the signal line in the subsequent stage) (2)
With the present inventor got the finding that it is possible to eliminate the disturbance of the signal waveform at point 1 due to the influence of signal line 12 having an impedance Z _1. This point is verified by observing the signal waveform for each signal point of the actual product.
FIG. 2 shows the case where Z ₁ = 50Ω and Rt = Z ₂ = 40Ω in the signal transmission circuit of FIG. 1, that is, the same conditions as those in FIG. ) And signal waveforms (waveforms with a lower curve) at signal points 1, 2, 3, 4, 5, and 6. Each impedance Z ₂ of the signal line 3 and 5 are aligned with the terminal resistors Rt. The combined impedance in the subsequent stage in this case is _Z 2/2 = 20 [Omega, is set to Rd = 30 [Omega according to equation (2).
3 is a signal waveform input to the input terminal 1 in the signal transmission circuit of FIG. 1, and the lower waveform is a signal waveform output from the receiver circuits 7, 8, 9, 10 and 11. . FIG. 4 is an enlarged view of a signal waveform in a portion surrounded by a broken line in FIG. If the signal waveform on the signal line 3 is not affected by the reflected wave, the signals input from the input terminal 1 are in the order from the input terminal 1 to the termination point 6 on the line. , 9, 10, and 11 are output as signals that are sequentially delayed in this order. In FIG. 4, the order of output signal waveforms is the same as that described above, such as receiver circuits 7, 8, 9, 10, and 11. The reason for this correct order is that if the signal waveform on the signal line 3 is a waveform that is not affected by the reflected wave, the time during which the signal having this waveform exceeds the input threshold value in each receiver circuit It is because it became the order which appears. As described above, as shown in FIG. 4, the signals output from the respective receiver circuits have the correct order of timing skew which is the output order.
Incidentally, FIG. 1 shows an example in which the signal line branched at the point 1 is divided into two lines. If Z ₂ and Rt are matched and the Rd value according to the equation (2) is obtained, as shown in FIG. It was shown that an output signal waveform with normal timing skew can be obtained. This effect can be obtained even if the signal line is not branched at the point 1 and is a single signal line. However, it is necessary to insert a resistor having a damping resistance value satisfying the relationship of the expression (2), with the signal line at the subsequent stage terminated by a resistor having the same resistance value as the impedance value of this line.

It is a figure which shows schematic structure of the signal transmission circuit by one Embodiment of this invention. The input signal waveform (upper) to the input terminal 1 in FIG. 1 and the signal waveforms of signal points 1, 2, 3, 4, 5 and 6 (lower). FIG. 1 shows an input signal waveform (upper) to the input terminal 1 in FIG. 1 and output signal waveforms of the receiver circuits 7, 8, 9, 10 and 11 (lower). FIG. 4 is a partial enlarged view of a signal waveform surrounded by a broken line in FIG. 3. It is a figure which shows schematic structure of the signal transmission circuit in background art. It is the input signal waveform (upper) to the input terminal 1 in FIG. 5 and the signal waveforms of signal points 1, 2, 3, 4, 5 and 6 (lower). 5 is an input signal waveform (upper) to the input terminal 1 in FIG. 5 and output signal waveforms of the receiver circuits 7, 8, 9, 10 and 11 (lower). It is the elements on larger scale of the signal waveform enclosed with the broken line of FIG. It is a block diagram of one specific implementation example of the signal transmission circuit in the background art.

Explanation of symbols

1: Input terminal 2: Output driver 3, 5: Signal line 4, 6: Termination resistor 7, 8, 9, 10, 11: Receiver circuit 12: Signal line 13: Damping resistor 20: Device mounting substrate 22: Substrate inner layer wiring 23: Device inner layer wiring 24, 25: Output terminal

Claims (4)

An output driver; a first signal line that receives an output signal of the output driver at one end and transmits the output signal to the other end; a second signal line having one end connected to the other end of the first signal line; A signal transmission circuit connected to the other end of the second signal line and having a termination resistor matching the impedance of the second signal line, between the output of the output driver and one end of the first signal line. A signal transmission circuit comprising a damping resistor inserted and having a resistance value of a difference value obtained by subtracting the impedance value of the second signal line from the impedance value of the first signal line. The second signal line includes a plurality of lines branched into a plurality of points with a connection point with the first signal line as a branch point, and the termination resistor that matches the impedance of each line at each end of the plurality of lines 2. The signal transmission circuit according to claim 1, wherein the impedance of the second signal line is a combined impedance of the plurality of lines. The resistance value of each termination resistor connected to the plurality of lines is the same as the impedance value of the line to which the termination resistor is connected, and the output impedance value of the output driver is the value of the first signal line. The signal transmission circuit according to claim 2, wherein the signal transmission circuit has the same impedance value. A signal is input to the output driver, the output driver and the first signal line are connected in series, and the first signal line at the line end of the first signal line not connected to the output driver is , Connected in series with a second signal line that distributes and outputs a signal from within the signal line, and connected to a line end of the second signal line that is not connected to the first signal line. The step of setting the resistance value of the termination resistor to a value that matches the impedance of the second signal line, and the resistance value of the damping resistor inserted between the output of the output driver and the first signal line, And a resistance value of a difference value obtained by subtracting the impedance value of the second signal line from the impedance value of the first signal line.

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