JP2005252160A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of focusing highly precisely on a metal thin-film resistor when performing laser trimming processing. <P>SOLUTION: The semiconductor device comprises a metal thin-film resistor 21 on an underground dielectric 5 which is formed on a semiconductor device 1, wherein an alignment mark 24 is formed on the region of the underground thin film 5 different from that where the metal thin-film resistor 21 is formed. The alignment mark 24 includes a metal thin-film pattern 24a, and a different level 24c which is formed by selectively removing the underground dielectric 5 using the metal thin-film pattern 24a as a mask. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a metal thin film resistor on a base insulating film formed on a semiconductor substrate.

In an analog integrated circuit, a resistance element is frequently used as an important element. In recent years, among resistive elements, a resistor made of a metal thin film (referred to as a metal thin film resistor) has attracted attention because of its low temperature dependency (hereinafter referred to as TCR). Examples of the material for the metal thin film resistor include chromium silicon (CrSi), nickel chromium (NiCr), tantalum nitride (TaN), chromium silicide (CrSi ₂ ), chromium nitride silicide (CrSiN), and chromium silicon oxy (CrSi0). Used.
In a semiconductor device provided with a metal thin film resistor, in order to satisfy the demand for higher integration, the metal thin film resistor is often formed with a thin film thickness of 1000 Å (angstrom) or less with the aim of higher sheet resistance.

  Some semiconductor devices are subjected to a laser trimming process in which a fuse element or a resistance element is irradiated with laser light to be cut or altered for performance adjustment after the physical device is completed. In such a semiconductor device, an alignment mark is prepared in order to specify a position where the laser beam is irradiated. Various techniques relating to alignment marks are disclosed.

For example, one that suppresses grain growth in order to maintain the reflectance of aluminum forming the alignment mark (see, for example, Patent Document 1), and one that includes aluminum and polysilicon as the alignment mark (For example, refer to Patent Document 2), a semiconductor device including an alignment mark in a fuse element box (for example, refer to Patent Document 3) and a Cu wiring as a countermeasure against defocus due to warpage of a wafer. Some include a fuse element made of the uppermost Cu wiring and an alignment mark (see, for example, Patent Document 4).
The purpose of these prior arts is to place an alignment mark in the same layer as possible as the fuse element, and to place aluminum with high reflectivity on the layer that forms the prototype of the alignment mark. Note that polysilicon or a metal material is used as the fuse element.

In an alignment mark formed by forming an alignment target made of polysilicon formed on the same insulating film with the same material as the fuse element made of polysilicon, and further forming aluminum on the insulating film and the alignment target, In order to improve the edge shape, the insulating film is selectively removed using the alignment target as a mask, and then aluminum is formed on the insulating film and the alignment target to sharpen the edge shape of the aluminum constituting the alignment mark. There is a conventional technique (see, for example, Patent Document 5).
The prior art described above relates to an alignment mark when polysilicon or a metal material is used as a fuse element.

Further, as a laser trimming process, there is a method in which a resistance element made of a metal thin film resistor is irradiated with laser light to be cut or altered (for example, see Patent Document 6).
In laser trimming processing for a resistance element, when laser light is transmitted through an insulating film such as a silicon oxide film and irradiated onto a semiconductor substrate, for example, a silicon substrate, when the laser trimming processing is performed, the insulating film or silicon irradiated with the laser light is irradiated. There was a problem that the substrate was damaged and the reliability of the semiconductor device was lowered. In a trimming process (referred to as online trimming) in which trimming is performed while measuring the performance of the semiconductor device, a laser beam is irradiated onto the silicon substrate, whereby electron-hole pairs are generated in the silicon substrate. Such an electron-hole pair becomes noise during performance measurement, and cannot be measured correctly, and there is a problem that high-precision trimming cannot be performed.

  In order to reduce such inconveniences, a method of disposing a coating for blocking the transmission of laser light around the resistance element (see, for example, Patent Document 7), or polysilicon between a fuse element made of polysilicon and a silicon substrate. There is a method of arranging a laser light shield formed of a refractory metal or a refractory metal silicide (see, for example, Patent Document 8).

Conventionally, there are the following methods for electrically connecting metal thin film resistors.
1) A method of directly connecting a metal wiring to a metal thin film resistor (see, for example, Patent Document 9).
2) A method of forming an interlayer insulating film after forming a metal thin film resistor, forming a connection hole in the interlayer insulating film, and connecting metal wiring through the connection hole (see, for example, Patent Document 10 and Patent Document 11) .)
3) A method of forming a barrier film on the metal thin film resistor layer and connecting metal wiring to the barrier film (see, for example, Patent Document 12 and Patent Document 13).
4) An electrode is formed in the connection hole formed in the insulating film, a resistor film is formed on the base insulating film, and then the resistor film is dry-etched so as to connect to the electrode. A method of forming a pattern (see, for example, Patent Document 9).

A method for electrically connecting the metal thin film resistors 1) to 4) will be described below.
Referring to FIG. 30, 1) a method of directly forming a metal wiring on a metal thin film resistor will be described.
A first interlayer insulating film 5 is formed on a wafer-like silicon substrate 1 on which an element isolation oxide film 3 and transistor elements (not shown) have been formed, and a metal is formed on the first interlayer insulating film 5. A thin film resistor 101 is formed. A wiring metal film is formed on the entire surface of the first-layer interlayer insulating film 5 including the metal thin film resistor 101, and the first-layer metal wiring pattern 103 is formed by patterning the wiring metal film by a wet etching technique. To do.
In a general manufacturing process of a semiconductor device, a dry etching technique is used for etching a metal film for wiring. However, in a situation where a thin metal thin film resistor 101 exists directly under the metal film for wiring, Since the metal thin film resistor 101 is etched by over-etching, the dry etching technique cannot be used. Therefore, it is necessary to form the first layer metal wiring pattern 103 by patterning the wiring metal film by the wet etching technique.

Referring to FIG. 31, 2) a method of forming a metal thin film resistor, forming an interlayer insulating film, forming a connection hole in the interlayer insulating film, and connecting metal wiring through the connection hole will be described. .
After the element isolation oxide film 3, the first layer interlayer insulating film 5 and the metal thin film resistor 101 are formed on the silicon substrate 1, a metal is formed on the first layer interlayer insulating film 5 including the metal thin film resistor 101. A CVD (chemical vapor deposition) oxide film 105 is formed as an interlayer insulating film with the wiring. On the CVD oxide film 105, a resist pattern having openings corresponding to both ends of the metal thin film resistor 101 for forming a metal wiring connection hole is formed. As a mask, the CVD oxide film 105 is selectively removed to form a connection hole 107. After removing the resist pattern, a wiring metal film made of an AlSiCu film is formed on the CVD oxide film 105 including the inside of the connection hole 107, and the first metal wiring pattern 109 is formed by patterning the wiring metal film. .
In a general semiconductor device manufacturing process, a dry etching technique is used to form the connection hole 107. However, if the metal thin film resistor 101 is thinner than 1000 mm, the connection hole 107 penetrates the metal thin film resistor 101. It is difficult to prevent this, and it is necessary to form the connection hole 107 by a wet etching technique.

Referring to FIG. 32, 3) a method of forming a barrier film on the metal thin film resistor layer and connecting metal wiring to the barrier film will be described.
After the element isolation oxide film 3, the first layer interlayer insulating film 5 and the metal thin film resistor 101 are formed on the silicon substrate 1, a metal is formed on the first layer interlayer insulating film 5 including the metal thin film resistor 101. A refractory metal film such as TiW that forms a barrier film with the wiring is formed, a metal film for wiring is further formed thereon, and the metal film for wiring is patterned by a dry etching technique to form a first layer metal wiring pattern 111 is formed. At this time, since the refractory metal film is formed under the wiring metal film, the metal thin film resistor 101 is not etched even if the dry etching technique is used. Thereafter, the refractory metal film pattern 113 is formed by selectively removing the refractory metal film using the first layer metal wiring pattern 111 as a mask by wet etching technique. Here, since the refractory metal film is located immediately above the metal thin film resistor 101, it is difficult to pattern the refractory metal film by a dry etching technique.

Referring to FIG. 33, 4) an electrode is formed in the connection hole formed in the insulating film, a resistor film is formed on the base insulating film, and then dry-etched so as to connect to the electrode. A method of forming a resistor pattern will be described. Here, the case where a metal wiring pattern is further formed in the upper layer of the metal wiring pattern provided under the connection hole will be described.
After the first layer interlayer insulating film 5 is formed on the silicon substrate 1, the first layer metal wiring pattern 115 is formed on the first layer interlayer insulating film 5. After forming the insulating film 117 on the first-layer interlayer insulating film 5, the first connection holes are formed in the insulating film 117 on the first-layer metal wiring pattern 115 disposed corresponding to both ends of the metal thin film resistor. 119 is formed, and a conductive plug (electrode) 121 is formed by embedding a conductive material in the first connection hole 119. At this time, a connection hole for electrically connecting the first layer metal wiring pattern 115 and the second layer metal wiring pattern formed in a later process is not formed. Next, a metal thin film for a metal thin film resistor is formed on the entire surface of the insulating film 117, and the metal thin film is patterned to form the metal thin film resistor 101 on the conductive plug 121 and the insulating film 117.

  An insulating film 123 is formed on the entire surface of the insulating film 117 to prevent the metal thin film resistor 101 from being etched when a second-layer metal wiring pattern formed in a subsequent process is patterned by a dry etching technique. . The second connection is made to the insulating films 117 and 123 on the first-layer metal wiring pattern 115 arranged for establishing electrical connection with the second-layer metal wiring pattern in a region different from the region where the metal thin film resistor 101 is formed. A hole 125 is formed, and a conductive material is embedded in the second connection hole 125 to form a second conductive plug 127. A metal film for the second layer metal wiring pattern is formed on the insulating film 123 including the formation region of the second conductive plug 127, and the metal film is patterned by photolithography and dry etching techniques, A second-layer metal wiring pattern 129 is formed on the two conductive plugs 127 and the insulating film 123.

Further, although not a metal thin film resistor, a semiconductor integrated circuit device including a resistor formed on an uppermost wiring electrode via an insulating film and connected to the uppermost wiring electrode is disclosed ( For example, refer to Patent Document 14.)
A case where such a structure is applied to a metal thin film resistor will be described with reference to FIG.

  A first layer interlayer insulating film 5 is formed on the silicon substrate 1 on which the element isolation oxide film 3 is formed, and a first layer metal wiring pattern 115 is formed on the first layer interlayer insulating film 5. A base insulating film 131 is formed on the entire surface of the first-layer interlayer insulating film 5 including the first-layer metal wiring pattern 115. A connection hole 133 is formed in the base insulating film 131 on the first-layer metal wiring pattern 115 by photolithography and dry etching techniques. A metal thin film for forming a metal thin film resistor is formed on the entire surface of the base insulating film 131 including the formation region of the connection hole 133, and the metal thin film is patterned into a predetermined shape to form the metal thin film resistor 101. .

  Further, as a semiconductor device provided with a metal thin film resistor, an integrated circuit in which a metal thin film resistor is mounted on an insulating film of a semiconductor integrated circuit, wherein the metal thin film resistor is in contact with the metal wiring at the electrode portion of the metal thin film resistor. In addition, there is disclosed one configured to be formed on at least a part of the end surface and the upper surface of the end portion of the metal wiring (see, for example, Patent Document 15).

With reference to FIG. 35, a method of making contact between the metal thin film resistor and the metal wiring on at least a part of the end surface and the upper surface of the end of the metal wiring will be described.
A first-layer interlayer insulating film 5 is formed on the silicon substrate 1 on which the element isolation oxide film 3 is formed, a first-layer metal wiring pattern 115 is formed on the first-layer interlayer insulating film 5, and the first layer After the plasma nitride film 135 is formed on the entire surface of the first interlayer insulating film 5 including the layer metal wiring pattern 115, a part of the plasma nitride film 135 is removed and the end surface and the upper surface of the first layer metal wiring pattern 115 are formed. Expose part of Thereafter, a metal thin film for the metal thin film resistor is deposited, and the metal thin film is patterned to form the metal thin film resistor 101.

JP 11-87219 A JP 2001-35924 A JP 2002-368090 A JP 2003-163268 A Japanese Patent Publication No. 7-63073 JP-A-8-124729 JP-A-56-58256 JP-A-58-170 JP 2002-124039 A JP 2002-261237 A Japanese Patent No. 2699559 Japanese Patent No. 2932940 Japanese Patent No. 3185777 JP 58-148443 A JP-A-61-100956

  For example, in a semiconductor device having a metal thin film resistor on a base insulating film formed on a semiconductor substrate as in the prior art described with reference to FIGS. 30 to 35, laser trimming processing on the metal thin film resistor When laser light passes through an insulating film such as a silicon oxide film and is irradiated onto a semiconductor substrate, for example, a silicon substrate, the insulating film or silicon substrate irradiated with the laser light is damaged, and the reliability of the semiconductor device There was a problem that decreased. In addition, when online trimming is performed, a laser beam is applied to the silicon substrate, whereby electron-hole pairs are generated in the silicon substrate. Such electron-hole pairs become noise during performance measurement, and cannot be measured correctly, and there is a problem that high-precision trimming cannot be performed.

  Therefore, if the energy of the laser beam is efficiently used, damage to the substrate can be suppressed, and such inconvenience can be reduced, and the trimming process can be made more efficient. In order to maximize the energy efficiency of the laser beam, it is preferable to focus the laser beam on the metal thin film resistor that is the laser beam irradiation body. This is more important than the polysilicon fuse because the metal thin film resistor is thin. Therefore, not only the planar accuracy but also the accuracy in the depth direction is important for the items required for the alignment mark in order to specify the position where the laser beam is irradiated.

Further, since the thickness of the metal thin film resistor is generally 1000 mm or less, it is difficult to use the metal thin film for the metal thin film resistor as the alignment mark. For example, in a semiconductor device in which a metal wiring pattern is formed on a base insulating film of a metal thin film resistor as in the prior art described with reference to FIG. 30 to FIG. 32 or FIG. A metal film can be used for the alignment mark.
However, although the metal thin film resistor and the alignment mark are formed on the same base insulating film, the metal film for the metal wiring pattern has a film thickness of, for example, about 5000 mm, and is significantly different from the metal thin film resistor. Therefore, even if the alignment of the laser beam is adjusted using the alignment mark during the laser trimming process, there is a problem that the focus is shifted on the metal thin film resistor.
In the configuration in which the metal thin film resistor is electrically connected to the metal wiring pattern on the lower layer side through the connection hole as in the prior art described with reference to FIG. 33 or FIG. 34, the metal wiring pattern It is conceivable to form an alignment mark using a metal film for the purpose, but since the metal thin film resistor and the alignment mark are not in the same layer, it can be expected that the focus will be further shifted.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device including an alignment mark that can focus on a metal thin film resistor with high accuracy during laser trimming.

The present invention comprises a metal thin film resistor on a base insulating film (also simply referred to as a base film) formed on a semiconductor substrate, wherein the base is formed in a region different from the formation region of the metal thin film resistor. A metal thin film pattern formed on the insulating film, and an alignment mark having a step portion formed by selectively removing the base insulating film using the metal thin film pattern as a mask.
In the claims and the specification of the present application, the base insulating film formed on the semiconductor substrate may be formed directly on the semiconductor substrate, or may be formed on the semiconductor substrate via another layer. Good. In addition, the base insulating film may be a single-layer insulating film or a laminated film including a plurality of insulating films.

  In the present invention, a protective insulating film may be further provided on the metal thin film resistor and the metal thin film pattern.

  Further, a metal nitride film covering the upper surface of the metal thin film resistor may be provided, and no metal oxide film may be formed between the upper surface of the metal thin film resistor and the metal nitride film.

Incidentally, regarding the method of electrically connecting the metal thin film resistors, in the method 1) described with reference to FIG. 30, as described above, the first-layer metal wiring pattern is directly formed on the metal thin film resistor 101. 103 is formed, however, the patterning of the metal film for the first-layer metal wiring pattern 103 cannot be performed by a dry etching technique, and it is difficult to form a fine pattern, which hinders high integration of circuits. There was a problem of becoming.
Further, the metal thin film resistor 101 is generally easily oxidized, and even if the metal film for the first layer metal wiring pattern 103 is formed in a state where the surface of the metal thin film resistor 101 is oxidized, the metal thin film resistor 101 There was a problem that good electrical connection between the first layer 101 and the first layer metal wiring pattern 103 could not be obtained. In a general semiconductor device manufacturing process, a natural oxide film on the surface of a silicon substrate or the like can be removed with a hydrofluoric acid aqueous solution to obtain a good electrical connection with a metal wiring. Since the etching is not a little caused by the acid, if the oxide film removal treatment with hydrofluoric acid is performed before the metal film for the first layer metal wiring pattern 103 is formed, the resistance value of the metal thin film resistor 101 may vary. was there.

In the method 2) described with reference to FIG. 31, the metal film for the first layer metal wiring pattern 109 is patterned by forming the interlayer insulating film 85 on the metal thin film resistor 101. It can be performed by a dry etching technique.
However, as described above, the formation of the connection hole 107 for electrically connecting the metal thin film resistor 101 and the first layer metal wiring pattern 109 needs to be opened by the wet etching technique. This hinders high integration. Further, a hydrofluoric acid aqueous solution is used in the wet etching process for forming the connection hole 107. To prevent the metal thin film resistor 101 from being etched by the hydrofluoric acid, a barrier is formed on the metal thin film resistor 101. Measures such as newly adding a process for forming and patterning a film are necessary, and there is a problem that the number of processes increases.

In the method 3) described with reference to FIG. 32, the etching process of the metal film for the first-layer metal wiring pattern 111 can be performed by a dry etching technique, and the formation of a connection hole is unnecessary. . However, as described above, since it is necessary to perform patterning of the refractory metal film for forming the refractory metal film pattern 113 that substantially determines the length of the metal thin film resistor 101 by the wet etching technique, The melting point metal film pattern 113 is etched wider than the desired etching region, the substantial length of the metal thin film resistor 101 varies, and as a result, the resistance value varies greatly and miniaturization is difficult. There was a problem of becoming.
Further, when the refractory metal film for the refractory metal film pattern 113 is formed, the surface of the metal thin film resistor 101 is oxidized, so that the electrical connection with the refractory metal film pattern 113 is good. The removal of the oxide film on the surface of the metal thin film resistor 101 with a hydrofluoric acid aqueous solution is required. There was a risk of causing variation.

As described above, in the above methods 1) to 3) described with reference to FIGS. 30 to 32, the wet etching process is required in any step due to the thin film thickness of the metal thin film resistor. In other words, miniaturization is hindered and resistance values are varied.
Furthermore, since the metal thin film resistor is easily oxidized and it is difficult to form a good electrical connection with the metal wiring, the addition of a barrier film formation process dedicated to the metal thin film resistor and the removal of the surface oxide film with hydrofluoric acid aqueous solution Processing is required, which increases the number of processes and causes variations in resistance value.

  In order to eliminate such inconveniences, in the first aspect of the semiconductor device of the present invention, the lower insulating film formed under the base insulating film, the wiring pattern formed on the lower insulating film, and the above A connection hole formed in the base insulating film on the wiring pattern is provided, and the metal thin film resistor is formed from the base insulating film to the inside of the connection hole, and is electrically connected to the wiring pattern in the connection hole. It was like that.

  Further, when a part of the metal thin film resistor is formed in the connection hole formed in the insulating film on the wiring pattern, as shown in FIG. 34, on the inner wall side surface of the connection hole 133, particularly on the bottom side of the connection hole 133. There is a problem that the step coverage (step coverage) of the metal thin film resistor 101 is deteriorated, and the contact resistance between the metal thin film resistor 101 and the first-layer metal wiring pattern 115 increases and varies.

In order to eliminate such a problem, in the first aspect, at least the upper end portion of the connection hole is formed in a tapered shape, and at least the wiring pattern and the material of the base insulating film and Ar (argon) are included in the components. ) Containing reverse sputtering residue may be formed on the inner wall of the connection hole.
Such a reverse sputtering residue and the tapered shape of the upper end portion of the connection hole are formed by performing a reverse sputtering process using Ar gas (hereinafter referred to as Ar reverse sputtering process) after forming a connection hole in the base insulating film on the wiring pattern. It can be formed by applying.

  According to a second aspect of the semiconductor device of the present invention, a lower insulating film formed under the underlying insulating film, a wiring pattern formed on the lower insulating film, and the underlying insulating film on the wiring pattern. A connection hole formed and a conductive plug formed in the connection hole are provided, and the metal thin film resistor is formed from the base insulating film to the conductive plug.

In the second aspect, the second connection hole formed in the base insulating film on the wiring pattern in a region different from the connection hole, and the second connection hole are formed simultaneously with the formation of the conductive plug. And a metal wiring pattern formed on the second conductive plug and on the base insulating film. The conductive plug and the second conductive plug include the connection hole and the second conductive plug. Formed of a first conductive material formed on the inner wall surface of the second connection hole and a second conductive material formed on the first conductive material, and formed under the metal thin film resistor. In the connection hole, the upper end portion of the first conductive material is formed at a distance from the upper end portion of the connection hole and the upper surface of the second conductive material, and the outer periphery of the upper surface of the second conductive material Above the connection hole The portion is formed in a tapered shape, and in the space between the inner wall of the connection hole and the second conductive material on the first conductive material, at least the material of the base insulating film, the first A reverse sputtering residue containing a conductive material and Ar may be formed.
In the tapered shape and the reverse sputtering residue, a conductive material is embedded in the connection hole and the second connection hole to form a conductive plug and a second conductive plug, and further on both the conductive plug and the insulating film. After the metal film for the metal wiring pattern is formed, the metal film on the conductive plug and the first conductive plug are formed when the metal film is selectively removed to form the metal wiring pattern. It can be formed by performing Ar reverse sputtering treatment on the base insulating film in a state where the upper portion of the conductive material is removed and a depression is formed around the conductive plug.

  A third aspect of the semiconductor device of the present invention includes a wiring pattern formed on the base insulating film, and the metal thin film resistor is formed from the base insulating film to the wiring pattern.

In the third aspect, a reverse sputtering residue containing at least the material of the wiring pattern and Ar as components may be formed on the surface of the wiring pattern on the base insulating film side.
Such a reverse sputtering residue can be formed by performing an Ar reverse sputtering process after forming a wiring pattern.

  In the third aspect, the wiring pattern further includes a sidewall made of an insulating material, and the metal thin film resistor is formed over the wiring pattern from the base insulating film through the sidewall surface. You may be made to do.

Furthermore, a reverse sputtering residue containing at least the sidewall material and Ar as components may be formed on the surface of the sidewall on the base insulating film side.
Such a reverse sputtering residue can be formed by performing an Ar reverse sputtering process after forming a wiring pattern and sidewalls.

  According to a fourth aspect of the semiconductor device of the present invention, the semiconductor device includes: a lower insulating film formed under the base insulating film; and a wiring pattern formed on the lower insulating film. The metal thin film resistor is formed from the base insulating film to the wiring pattern with a film thickness that exposes the upper surface.

  In the semiconductor device of the present invention, a laser light transmission preventing film made of a metal material may be further provided between the base insulating film and the semiconductor substrate in a region below the metal thin film resistor.

  As an example of a semiconductor device to which the semiconductor device of the present invention is applied, a semiconductor device provided with a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistor elements and adjusting the voltage output by laser irradiation to the resistor elements. Can be mentioned.

  As another example of the semiconductor device to which the semiconductor device of the present invention is applied, a divided resistor circuit for dividing an input voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and the division A semiconductor device including a voltage detection circuit having a comparison circuit for comparing the divided voltage from the resistor circuit with the reference voltage from the reference voltage generation circuit can be given. The divided resistor circuit constituting the voltage detection circuit includes a metal thin film resistor constituting the semiconductor device of the present invention and a resistor element to which the alignment mark is applied.

  As still another example of a semiconductor device to which the semiconductor device of the present invention is applied, an output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying the divided voltage, and a reference voltage A reference voltage generation circuit for supplying, and a comparison circuit for comparing the divided voltage from the division resistor circuit and the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result A semiconductor device provided with a constant voltage generation circuit can be given. The divided resistor circuit constituting the constant voltage generation circuit includes a metal thin film resistor constituting the semiconductor device of the present invention and a resistor element to which the alignment mark is applied.

  In the semiconductor device of the present invention, the metal thin film pattern formed on the base insulating film in a region different from the region where the metal thin film resistor is formed, and the base insulating film is selectively removed using the metal thin film pattern as a mask. Since the alignment mark having a step portion formed in this way is provided, the upper surface of the metal thin film resistor and the upper surface of the alignment mark can be arranged at the same height (depth of focus). In addition, the metal thin film resistor can be focused with high accuracy.

  Further, the stepped portion can be formed by wet etching technique using the metal thin film pattern as a mask. However, if a protective insulating film is provided on the metal thin film pattern, the stepped portion of the alignment mark is formed. Even when dry etching technology is used, it is possible to prevent the metal thin film pattern from being removed by the protective insulating film, which is higher than when the step portion of the alignment mark is formed using wet etching technology. An accurate and fine alignment mark can be formed. If the step portion can be formed under conditions where the etching selectivity between the metal thin film pattern and the base insulating film is high by dry etching, the step portion can be dry-etched even if no protective insulating film is provided. Can be formed.

  Furthermore, if a metal nitride film is provided to cover the upper surface of the metal thin film resistor, and no metal oxide film is formed between the upper surface of the metal thin film resistor and the metal nitride film, the metal thin film resistor The oxidation of the upper surface can be eliminated, and the resistance value of the metal thin film resistor can be stabilized and the accuracy can be improved.

In the first aspect of the semiconductor device of the present invention, in addition to the configuration provided with the alignment mark, a lower-layer insulating film formed under the base insulating film, a wiring pattern formed on the lower-layer insulating film, and wiring A connection hole formed in the base insulating film on the pattern was provided, and the metal thin film resistor was formed from the insulating film to the inside of the connection hole so as to be electrically connected to the wiring pattern in the connection hole.
According to such a configuration, as in the prior art described with reference to FIGS. 30 to 32, the wiring pattern for making electrical connection with the metal thin film resistor after forming the metal thin film resistor is provided. It is not necessary to perform a wet etching process for forming. Further, since the contact surface of the metal thin film resistor with the wiring pattern is not exposed to the atmosphere, the metal thin film resistor can be obtained without performing the surface oxide film removal treatment and the etching prevention barrier film formation on the metal thin film resistor. A good electrical connection between the body and the wiring pattern can be obtained stably. Thereby, miniaturization of the metal thin film resistor and stabilization of the resistance value can be realized without increasing the number of steps regardless of the film thickness of the metal thin film resistor.

Further, in the first aspect, at least an upper end portion of the connection hole is formed in a tapered shape, and a reverse sputtering residue containing at least the wiring pattern, the material of the base insulating film, and Ar as a component is the above-mentioned If it is formed on the inner wall of the connection hole, the step coverage of the metal thin film resistor in the connection hole can be improved by the presence of the reverse sputtering residue, and the contact resistance with the wiring pattern of the metal thin film resistor. Can be realized. Further, the tapered shape formed at least at the upper end of the connection hole prevents the metal thin film deposited near the upper end of the connection hole from being formed in the connection hole when forming the metal thin film for the metal thin film resistor. The influence of the metal thin film on the deposition of the metal thin film can be reduced, and the step coverage of the metal thin film, and thus the step coverage of the metal thin film resistor can be improved.
Conventionally, the metal thin film resistor has a problem in that the resistance value fluctuates due to the composition of the base film, the elapsed time from the base film formation, and the like, and the metal thin film resistor is affected by the base film. As described above, the reverse sputtering residue and the tapered shape of the upper end of the connection hole in this embodiment can be formed by performing Ar reverse sputtering after forming the connection hole in the insulating film on the wiring pattern, Before forming the metal thin film for the metal thin film resistor, Ar reverse sputtering treatment is performed on the base film of the metal thin film resistor, thereby reducing the sheet resistance of the metal thin film resistor and the change over time. There is also an effect that reduction can be achieved.
The effect obtained by applying the Ar reverse sputtering process to the base film of the metal thin film resistor will be described in detail later.

In a second aspect of the semiconductor device of the present invention, a lower insulating film formed under the underlying insulating film, a wiring pattern formed on the lower insulating film, and the underlying insulating film on the wiring pattern Since the connection hole formed and a conductive plug formed in the connection hole, the metal thin film resistor is formed from the base insulating film to the conductive plug. As in the first embodiment, it is not necessary to perform a wet etching process for forming a wiring pattern for establishing electrical connection with the metal thin film resistor after the metal thin film resistor is formed. Since the contact surface with the conductive plug is not exposed to the atmosphere, the metal thin film resistor can be removed without performing surface oxide film removal treatment and etching prevention barrier film formation on the metal thin film resistor. The good electrical connection of the conductive plug can be stably obtained with. Thereby, miniaturization of the metal thin film resistor and stabilization of the resistance value can be realized without increasing the number of steps regardless of the film thickness of the metal thin film resistor.
Furthermore, since the metal thin film resistor is formed on the conductive plug and the insulating film, the metal thin film resistor and the wiring pattern are connected via the connection holes formed on the wiring pattern described with reference to FIG. As in the case of forming the electrical connection, there is no fluctuation in the resistance value of the metal thin film resistor and increase in the contact resistance with the electrode due to the deterioration of the step coverage of the metal thin film resistor.

In the second aspect, the second connection hole formed in the base insulating film on the wiring pattern in a region different from the connection hole, and the second connection hole are formed simultaneously with the formation of the conductive plug. And a metal wiring pattern formed on the second conductive plug and on the base insulating film. The conductive plug and the second conductive plug include the connection hole and the second conductive plug. Formed of a first conductive material formed on the inner wall surface of the second connection hole and a second conductive material formed on the first conductive material, and formed under the metal thin film resistor. In the connection hole, the upper end portion of the first conductive material is formed at a distance from the upper end portion of the connection hole and the upper surface of the second conductive material, and the outer periphery of the upper surface of the second conductive material Above the connection hole The portion is formed in a tapered shape, and in the space between the inner wall of the connection hole and the second conductive material on the first conductive material, at least the material of the base insulating film, the first If a reverse sputtering residue containing a conductive material and Ar is formed,
Compared with the case where the tapered shape and the reverse sputtering residue are not formed, the step coverage of the metal thin film resistor in the vicinity of the first connection hole can be improved, and the resistance value of the metal thin film resistor is stabilized and accurate. Can be improved.
Further, the taper shape and the reverse sputtering residue are formed on the base insulation in a state where the upper portion of the first conductive material constituting the conductive plug is removed and a depression is formed around the conductive plug, as described above. It can be formed by performing Ar reverse sputtering treatment on the film, but by performing Ar reverse sputtering treatment on the base film of the metal thin film resistor before forming the metal thin film for the metal thin film resistor. Also, there is an effect that it is possible to reduce the dependency of the sheet resistance of the metal thin film resistor on the base film and the change with time. The effect obtained by applying the Ar reverse sputtering process to the base film of the metal thin film resistor will be described in detail later.

In the third aspect of the semiconductor device of the present invention, the wiring pattern formed on the base insulating film is provided, and the metal thin film resistor is formed from the base insulating film to the wiring pattern. In this embodiment, it is not necessary to perform a wet etching process for forming a wiring pattern for electrical connection with the metal thin film resistor after the metal thin film resistor is formed. Further, since the contact surface of the metal thin film resistor with the wiring pattern is not exposed to the atmosphere, the metal thin film resistor can be obtained without performing the surface oxide film removal treatment and the etching prevention barrier film formation on the metal thin film resistor. A good electrical connection between the body and the wiring pattern can be obtained stably. Thereby, also in this aspect, regardless of the film thickness of the metal thin film resistor, the metal thin film resistor can be miniaturized and the resistance value can be stabilized without increasing the number of steps.
Furthermore, since the metal thin film resistor is formed from the base insulating film to the wiring pattern, the electrical connection between the metal thin film resistor and the wiring pattern is formed through the connection hole formed on the wiring pattern. Compared to the above, it is not necessary to perform a series of processes for forming the connection hole, so that the process can be shortened and simplified, and the metal thin film due to the deterioration of the step coverage of the metal thin film resistor due to the connection hole. There is no fluctuation in the resistance value of the resistor and an increase in contact resistance with the electrode.

Further, if a reverse sputtering residue containing at least the material of the wiring pattern and Ar as components is formed on the surface of the wiring pattern on the base insulating film side, the corners on the upper surface of the wiring pattern are formed. Due to the taper shape and the presence of the reverse sputtering residue, the step coverage of the metal thin film resistor can be improved, and the resistance value of the metal thin film resistor can be stabilized.
Furthermore, the reverse sputtering residue can be formed by performing an Ar reverse sputtering process after forming the wiring pattern, but before forming the metal thin film for the metal thin film resistor, the reverse sputtering residue is applied to the base film of the metal thin film resistor. By applying the Ar reverse sputtering treatment, it is possible to reduce the dependence of the sheet resistance of the metal thin film resistor on the base film and the change with time. The effect obtained by applying the Ar reverse sputtering process to the base film of the metal thin film resistor will be described in detail later.

  Further, in the third aspect, a side wall made of an insulating material is provided on a side surface of the wiring pattern, and the metal thin film resistor is formed over the wiring pattern from the base insulating film through the side wall surface. By doing so, it is possible to prevent the step coverage of the metal thin film resistor from being deteriorated due to a steep step caused by the side surface of the wiring pattern, and to stabilize the resistance value of the metal thin film resistor.

  Further, if the reverse sputtering residue containing at least the sidewall material and Ar as components is formed on the surface of the side wall on the base insulating film side, the reverse sputtering residue is a wiring pattern and Although it can be formed by performing Ar reverse sputtering after forming the sidewall, Ar reverse sputtering is performed on the base film of the metal thin film resistor before forming the metal thin film for the metal thin film resistor. As a result, it is possible to reduce the dependence of the sheet resistance of the metal thin film resistor on the underlying film and the change with time. The effect obtained by applying the Ar reverse sputtering process to the base film of the metal thin film resistor will be described in detail later.

  According to a fourth aspect of the semiconductor device of the present invention, the semiconductor device includes a lower insulating film formed under the underlying insulating film and a wiring pattern formed on the lower insulating film, wherein the underlying insulating film is formed of the wiring pattern. Since the upper surface is exposed on the lower insulating film, the metal thin film resistor is formed from the base insulating film to the metal wiring pattern. It is not necessary to perform a wet etching process for forming a wiring pattern for establishing electrical connection with the metal thin film resistor after the metal thin film resistor is formed. Further, since the contact surface of the metal thin film resistor with the metal wiring pattern is not exposed to the atmosphere, the metal thin film resistor can be formed without performing the surface oxide film removal treatment and the etching prevention barrier film formation on the metal thin film resistor. A good electrical connection between the resistor and the wiring pattern can be obtained stably. Thereby, also in this aspect, regardless of the film thickness of the metal thin film resistor, the metal thin film resistor can be miniaturized and the resistance value can be stabilized without increasing the number of steps.

  In the semiconductor device of the present invention, if a laser light transmission preventing film made of a metal material is further provided between the base insulating film and the semiconductor substrate in the region under the metal thin film resistor, the laser trimming process can be performed. Even if the metal thin film resistor is irradiated with a laser beam having sufficient intensity to cut or alter the metal thin film resistor, the laser light transmitted through the insulating film, which is the base film of the metal thin film resistor, is prevented from transmitting the laser beam. Since the film reflects off the semiconductor substrate, the laser beam can be prevented from being irradiated onto the semiconductor substrate. Thereby, for example, it is possible to prevent a decrease in the reliability of the semiconductor device due to the irradiation of the laser beam onto the semiconductor substrate during the trimming process. Further, at the time of online trimming processing, generation of electron-hole pairs due to irradiation of laser light onto the semiconductor substrate can be prevented, and high-precision trimming processing can be performed.

  In addition, in a semiconductor device including a divided resistor circuit that can obtain a voltage output by dividing by two or more resistors and adjust the voltage output by laser irradiation to the resistor element, the resistor element constituting the divided resistor circuit is Since the metal thin film resistor and the alignment mark constituting the semiconductor device are provided, the focus of the metal thin film resistor can be adjusted with high accuracy during the laser trimming process, and the accuracy of the laser trimming process can be improved. The accuracy of the output voltage of the divided resistor circuit can be improved.

  Also, a dividing resistor circuit for dividing the input voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the dividing resistor circuit, and a reference from the reference voltage generating circuit In a semiconductor device having a voltage detection circuit having a comparison circuit for comparing voltages, a metal thin film resistor constituting the semiconductor device of the present invention and a division resistance circuit to which an alignment mark is applied are provided as a division resistance circuit. By doing so, the divided resistor circuit to which the present invention is applied can improve the accuracy of the output voltage, so that the accuracy of the voltage detection capability of the voltage detection circuit can be improved.

  Further, an output driver for controlling the output of the input voltage, a dividing resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and the dividing resistor circuit In a semiconductor device having a constant voltage generation circuit having a comparison circuit for comparing the divided voltage with the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result, as a divided resistance circuit If the divided resistor circuit to which the metal thin film resistor and the alignment mark constituting the semiconductor device of the present invention are applied is provided, the divided resistor circuit to which the present invention is applied can improve the accuracy of the output voltage. Therefore, it is possible to stabilize the output voltage of the constant voltage generation circuit.

  FIG. 1 is a cross-sectional view showing an embodiment of the first aspect, in which (A) is a cross-sectional view showing a formation region of a metal thin film resistor and an alignment mark, and (B) is a portion surrounded by a broken line in (A). It is an expanded sectional view which expands and shows. FIG. 2 is a plan view showing an alignment mark formation region of this embodiment. In FIG. 2, the passivation film is not shown. In the embodiments described below, transistor elements, capacitor elements, and the like are formed on the same substrate, but these elements are not shown in the drawing.

  An element isolation oxide film 3 is formed on the silicon substrate 1. A first interlayer insulating film (lower insulating film) 5 made of a BPSG (Borophospho silicate grass) film or a PSG (phospho silicate glass) film is formed on the silicon substrate 1 including the formation region of the element isolation oxide film 3. Yes. A first-layer metal wiring pattern 11 made of a metal material pattern 7 and a refractory metal film 9 formed on the surface of the metal material pattern 7 is formed on the first-layer interlayer insulating film 5. The metal material pattern 7 is formed of, for example, an AlSiCu film. The refractory metal film 9 is formed of, for example, a TiN film and functions as an antireflection film / barrier film. A part of the first layer metal wiring pattern 11 is formed to extend in the formation region of the metal thin film resistor to constitute the laser light transmission preventing film 13.

  On the first-layer interlayer insulating film 5 including the formation region of the first-layer metal wiring pattern 11 and the laser light transmission preventing film 13, for example, from the lower layer side, the plasma CVD oxide film, the SOG film, and the plasma CVD oxide film A second-layer interlayer insulating film (underlying insulating film) 15 (shown integrally in FIG. 1) is formed. Connection holes 17 are formed in the second-layer interlayer insulating film 15 so as to correspond to both end portions of the metal thin film resistor and the first-layer metal wiring pattern 11.

  As shown in FIG. 5B, the bottom surface of the connection hole 17 is formed by removing a part of the surface side of the refractory metal film 9, and the upper end portion of the connection hole 17 is formed in a tapered shape. A reverse sputtering residue 19 is formed on the inner wall of the connection hole 17. The tapered shape of the upper end portion of the connection hole 17 and the reverse sputtering residue 19 are not shown in FIG. The tapered shape of the upper end portion of the connection hole 17 and the reverse sputtering residue 19 are formed by performing an Ar reverse sputtering process on the second-layer interlayer insulating film 15 in which the connection hole 17 is formed. Therefore, the reverse sputtering residue 19 contains the material of the refractory metal film 9 and the second interlayer insulating film 15 and Ar as components, and here, Ti, N, Si, O, and Ar are included.

  A CrSi thin film resistor (metal thin film resistor) 21 is formed on the second layer interlayer insulating film 15 from the region between the connection holes 17, 17 to the inside of the connection hole 17 and the first layer metal wiring pattern 11. Yes. Both ends of the CrSi thin film resistor 21 are electrically connected to the first-layer metal wiring pattern 11 in the connection hole 17. Under the CrSi thin film resistor 21, a laser light transmission preventing film 13 is disposed via a second interlayer insulating film 15. A protective insulating film 22 is formed on the upper surface of the CrSi thin film resistor 21. The protective insulating film 22 is formed of, for example, a laminated film including a silicon nitride film having a thickness of 1000 mm and a silicon oxide film having a thickness of 1000 mm in order from the lower layer side. In FIG. 1, the protective insulating film 22 is shown integrally.

  A CrSi thin film pattern (metal thin film pattern) 24 a for the alignment mark 24 is formed on the second interlayer insulating film 15 in a region different from the region where the CrSi thin film resistor 21 is formed. A protective insulating film 24b having the same structure as the protective insulating film 22 is formed on the upper surface of the CrSi thin film pattern 24a. The second interlayer insulating film 15 is selectively removed from the second interlayer insulating film 15 in the vicinity of the CrSi thin film pattern 24a and the protective insulating film 24b using the CrSi thin film pattern 24a and the protective insulating film 24b as a mask. Thus, a step portion 24c is formed. The CrSi thin film pattern 24a, the protective insulating film 24b, and the stepped portion 24c constitute an alignment mark 24.

  For example, as shown in FIG. 2, the alignment mark 24 includes two sets of CrSi thin film patterns 24a and protective insulating films 24b, and step portions 24c common to the CrSi thin film patterns 24a and protective insulating films 24b. . The planar dimensions of the CrSi thin film pattern 24a and the protective insulating film 24b are, for example, 7 μm × 50 μm (micrometer). The two sets of the CrSi thin film pattern 24a and the protective insulating film 24b are arranged at a distance b, for example, 50 μm so that the longitudinal directions thereof are orthogonal to each other. An interval a between the outer peripheral portions of the CrSi thin film pattern 24a and the protective insulating film 24b and the stepped portion 24c is, for example, 15 μm. Further, the depth of the stepped portion 24c is preferably 1000 mm or more in order to make the light and darkness of the stepped portion 24c clear during alignment. Although the layout example and dimension example of the alignment mark 24 have been described, the layout and dimension of the alignment mark 24 are not limited to this in the present invention.

  A passivation film 23 (FIG. 1) as a final protective film comprising a silicon oxide film on the lower layer side and a silicon nitride film on the upper layer side on the second interlayer insulating film 15 including the formation region of the CrSi thin film resistor 21 and the alignment mark 24. In FIG.

  In this embodiment, a CrSi thin film pattern 24a, a protective insulating film 24b, and a step are formed on the second interlayer insulating film 15 which is a base film of the CrSi thin film resistor 21 in a region different from the region where the CrSi thin film resistor 21 is formed. Since the alignment mark 24 having the portion 24c is provided, the upper surface of the CrSi thin film resistor 21 and the upper surface of the alignment mark 24 can be arranged at the same height, and the focus is placed on the CrSi thin film resistor 21 during the laser trimming process. Can be adjusted with high accuracy.

  Further, since the laser light transmission preventing film 13 made of a metal material is provided between the second-layer interlayer insulating film 15 and the silicon substrate 1 in the region under the CrSi thin film resistor 21, the CrSi thin film resistor is used during the laser trimming process. Even when the CrSi thin film resistor 21 is irradiated with a laser beam 25 having sufficient intensity to cut or alter the body 21, the laser beam 25 transmitted through the second interlayer insulating film 15 is not transmitted through the laser beam transmission preventing film 13. Thus, it is possible to prevent the silicon substrate 1 from being irradiated with the laser beam 25 that is reflected to the side opposite to the silicon substrate 1. Thereby, it is possible to prevent the reliability of the semiconductor device from being lowered due to the irradiation of the laser beam onto the silicon substrate 1 during the trimming process. Furthermore, at the time of online trimming processing, generation of electron-hole pairs due to irradiation of laser light onto the silicon substrate 1 can be prevented, and highly accurate trimming processing can be performed.

Furthermore, as shown in (B), since the reverse sputtering residue 19 is formed on the inner wall of the connection hole 17, the step coverage of the CrSi thin film resistor 21 in the connection hole 17 is improved. Thereby, stabilization of the contact resistance with the 1st layer metal wiring pattern 11 of the CrSi thin film resistor 21 is realizable.
Furthermore, since the upper end portion of the connection hole 17 is tapered, an overhang of the CrSi thin film deposited in the vicinity of the upper end portion of the connection hole 17 during the formation of the CrSi thin film for forming the CrSi thin film resistor 21 is prevented. Thus, the influence on the deposition of the CrSi thin film in the connection hole 17 can be reduced, and the step coverage of the CrSi thin film and, consequently, the step coverage of the CrSi thin film resistor 21 can be improved.

  FIG. 3 is a process cross-sectional view for explaining an example of a manufacturing method for manufacturing the embodiment described with reference to FIG. FIG. 4 is an enlarged cross-sectional view showing the vicinity of the connection hole after the Ar reverse sputtering process in the manufacturing method. In FIG. 3, illustration of the tapered shape of the side wall formed on the inner wall of the connection hole and the upper end portion of the connection hole is omitted. An example of this manufacturing method will be described with reference to FIGS.

(1) A first layer made of a BPSG film or a PSG film on a wafer-like silicon substrate 1 on which an element isolation oxide film 3 and transistor elements (not shown) have been formed using, for example, an atmospheric pressure CVD apparatus An eye interlayer insulating film 5 is formed to a thickness of about 8000 mm. Thereafter, a heat treatment such as reflow is performed to flatten the surface of the first interlayer insulating film 5.

  For example, using a DC magnetron sputtering apparatus, a wiring metal film made of an AlSiCu film is formed on the first interlayer insulating film 5 to a film thickness of about 5000 mm, and further, a known technique is antireflection. A refractory metal film as a film, here, a TiN film is continuously formed in a thickness of about 800 mm in a vacuum. Here, since the refractory metal film finally functions as a barrier film for stabilizing the contact resistance between the metal material pattern formed from the metal film for wiring in the subsequent process and the metal thin film resistor, It is preferable to continuously form the wiring metal film and the refractory metal film in a vacuum.

  The refractory metal film and the wiring metal film are patterned by a known photolithography technique and etching technique to form a first layer metal wiring pattern 11 including the metal wiring pattern 7 and the refractory metal film 9. At this time, since a refractory metal film functioning as an antireflection film is formed on the wiring metal film, the resist pattern is thickened or thinned to demarcate the formation region of the first layer metal wiring pattern 11. Can be minimized. A part of the first layer metal wiring pattern 11 is formed to extend in the formation region of the metal thin film resistor to constitute the laser light transmission preventing film 13.

  Further, at this stage, the metal thin film resistor is not formed, and the base film of the first layer metal wiring pattern 11 is formed by the first layer interlayer insulating film 5, so that the first layer metal wiring pattern is formed. 11 patterning can be performed by dry etching technology with sufficient over-etching, and there is no need to apply patterning by wet etching technology, which has been a problem of the prior art, and it affects the miniaturization of circuits. Never give.

  For example, a plasma CVD oxide film is formed to a thickness of about 6000 mm on the first-layer interlayer insulating film 5 including the formation region of the first-layer metal wiring pattern 11 by plasma CVD. By performing a known SOG coating process and etch back process, an SOG film is formed on the plasma CVD oxide film and planarized. Further, a plasma CVD oxide film for preventing diffusion of components from the SOG film is formed to a thickness of about 2000 mm. As a result, a second interlayer insulating film 15 composed of a plasma CVD oxide film, an SOG film, and a plasma CVD oxide film is formed in this order from the lower layer side.

A resist pattern for forming connection holes in the second-layer interlayer insulating film 15 corresponding to the regions to be formed at both ends of the metal thin film resistor and the first-layer metal wiring pattern 11 is formed by a known photolithography technique. Form.
For example, using a parallel plate type plasma etching apparatus, resist is applied under the conditions of RF power: 700 W (watts), Ar: 500 sccm (standard cc / min), CHF ₃ : 500 sccm, CF ₄ : 500 sccm, pressure: 3.5 Torr (torr). Using the pattern as a mask, the second interlayer insulating film 15 is selectively removed to form connection holes 17 in the second interlayer insulating film 15. At the bottom of the connection hole 17, the refractory metal film 9 as an antireflection film / barrier film remains with a thickness of about 600 mm.
Thereafter, the resist pattern is removed (see FIG. 3A).

  Here, after the connection hole 17 is formed, a by-product removal step during etching attached to the side wall of the connection hole 17 or the like may be performed. In addition, for the purpose of improving the step coverage of the metal thin film resistor inside the connection hole 17, the shape of the connection hole 17 is formed by taper etching by changing etching conditions, etching processing combining wet etching technology and dry etching technology, or the like. Improvements may be made.

  Further, in the step (1), the etching rate of the refractory metal film 9 is further reduced with respect to the etching rate of the second interlayer insulating film 15 by optimizing the plasma etching conditions for forming the connection hole 17. It can be sufficiently suppressed, and the film thickness of the refractory metal film 9 remaining at the bottom of the connection hole 17 can be made larger than that in this manufacturing method example. Furthermore, the remaining film thickness of the refractory metal film 9 after the connection hole 17 is formed can be secured while suppressing the film thickness at the time of forming the refractory metal film 9 to be low. Thus, since the formation of the connection hole 17 is performed at a stage where the metal thin film resistor is not formed, the connection hole 17 can be processed without any restrictions due to the thinness of the metal thin film resistor, It is possible to pursue miniaturization by applying dry etching technology.

(2) For example, in the Ar sputter etching chamber of a multi-chamber sputtering apparatus, in the vacuum, the connection hole 17 under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr (millitorr), treatment time: 20 seconds Ar reverse sputtering is performed on the surface of the second interlayer insulating film 15 including the inside. This etching condition is the same as that for etching a thermal oxide film formed in a wet atmosphere at 1000 ° C. by about 50 mm. The thickness of the refractory metal film 9 remaining at the bottom of the connection hole 17 after this treatment was about 500 mm.

Subsequently, a CrSi thin film (metal thin film) 27 for the metal thin film resistor is continuously formed without breaking the vacuum state after completion of the Ar reverse sputtering process. Here, after a semiconductor wafer is transferred from an Ar sputter etching chamber to a sputter chamber equipped with a CrSi target, a Si / Cr = 80/20 wt% (weight percent) CrSi target is used and a DC power of 0.7 kW ( (Kilowatt), Ar: 85 sccm, pressure: 8.5 mTorr, treatment time: 9 seconds. A CrSi thin film 27 is deposited on the entire surface of the second interlayer insulating film 15 including the inside of the connection hole 17 to a thickness of about 50 mm. Formed thick.
Further, a silicon nitride film having a thickness of 1000 mm is formed on the CrSi thin film 27 by a known CVD method, and a silicon oxide film having a thickness of 1000 mm is further formed thereon to form a protective insulating film 28. (See FIG. 3B).

  Thus, before forming the CrSi thin film 27 for the metal thin film resistor, the Ar reverse sputtering process is performed on the second interlayer insulating film 15 including the inside of the connection hole 17 as shown in FIG. In addition, a reverse sputtering residue 19 made of the material of the refractory metal film 9 and the second interlayer insulating film 15 and the material containing Ar can be formed on the inner wall of the connection hole 17, and the upper end portion of the connection hole 17. Can be formed into a tapered shape. Further, the step coverage of the CrSi thin film 27 in the connection hole 17 can be improved by the presence of the reverse sputtering residue 19, and the taper shape formed at the upper end portion of the connection hole 17 allows the CrSi thin film 27 to be formed. In this case, the overhang of the CrSi thin film 27 deposited in the vicinity of the upper end of the connection hole 17 can be prevented to reduce the influence on the deposition of the CrSi thin film 27 in the connection hole 17, and the step coverage of the CrSi thin film 27 can be reduced. Can be improved.

Furthermore, by performing the Ar reverse sputtering process, a very small amount of natural oxide film formed on the surface of the refractory metal film 9 at the bottom of the connection hole 17 can be removed, and the first-layer metal wiring pattern 11 and A good electrical connection with the CrSi thin film 27 can be formed.
Further, by performing the Ar reverse sputtering treatment, the dependency of the CrSi thin film resistor formed from the CrSi thin film 27 on the subsequent process can be improved. This effect will be described later.

(3) A resist pattern for defining the formation region of the metal thin film resistor is formed on the protective insulating film 28 by photolithography, and the resist pattern is masked using, for example, an RIE (reactive ion etching) apparatus. Then, the protective insulating film 28 and the CrSi thin film 27 are patterned to form the CrSi thin film resistor 21 and the protective insulating film 22, and the CrSi thin film pattern 24 a and the protective insulating film 24 b are formed in the alignment mark formation region. . Thereafter, the resist pattern is removed (see FIG. 3C). Here, since the CrSi thin film resistor 21 is electrically connected to the first layer metal wiring pattern 11 in the connection hole 17, in order to make an electrical connection on the upper surface of the metal thin film resistor as in the prior art. In addition, it is not necessary to perform a metal oxide film removal process on the surface of the CrSi thin film resistor 21 with a hydrofluoric acid aqueous solution.

(4) A resist pattern 29 for defining a formation region of a stepped portion constituting the alignment mark is formed on the second interlayer insulating film 15 including the formation region of the CrSi thin film resistor 21 by photolithography. To do. The resist pattern 29 has an opening corresponding to the formation region of the CrSi thin film pattern 24a for the alignment mark and the protective insulating film 24b and the vicinity thereof.
For example, using an RIE apparatus, RF power: 700 W, Ar: 500 sccm, CHF 3: 500 sccm, CF ₄ : 500 sccm, pressure: 3.5 Torr, and using the CrSi thin film pattern 24 a, the protective insulating film 24 b and the resist pattern 29 as a mask. Then, the second interlayer insulating film 15 is selectively removed, and a step portion 24 c is formed in the second interlayer insulating film 15. As a result, an alignment mark 24 having a CrSi thin film pattern 24a, a protective insulating film 24b, and a stepped portion 24c is formed (see FIG. 3D).

(5) After removing the resist pattern 29, a silicon oxide film and a silicon nitride film as the passivation film 23 are formed on the second interlayer insulating film 15 including the formation region of the CrSi thin film resistor 21 by, for example, plasma CVD. Are sequentially formed. Thus, the manufacturing process of the semiconductor device is completed (see FIG. 1).

The step 24c of the alignment mark 24 can be formed by a wet etching technique using the metal thin film pattern 24a as a mask. However, in this manufacturing method, the protective insulating film 24b is formed on the metal thin film pattern 24a, and the alignment is performed. Since the step 24c is formed by the dry etching technique while preventing the metal thin film pattern 24a from being removed using the protective insulating film 24b as a mask when the step 24c of the mark 24 is formed, the wet etching technique is used. Compared with the case where the step portion of the alignment mark is formed using the above, a highly accurate and fine alignment mark can be formed.
Note that, under the etching conditions in this embodiment, the silicon oxide film constituting the upper layer side of the protective insulating film 24b during the etching of the second interlayer insulating film 15 is substantially the same as the second interlayer insulating film 15. Although it is etched at the etching rate, the silicon nitride film constituting the lower layer side of the protective insulating film 24b has a small etching rate of 1/4 or less as compared with the silicon oxide film, so that it sufficiently functions as a mask. Can do.

Further, in this embodiment, after the first layer metal wiring pattern 11 and the connection hole 17 are formed, the CrSi thin film resistor 21 is formed, and the CrSi thin film resistor 21 and the first layer metal wiring are formed in the connection hole 17. Since the electrical connection of the pattern 11 is formed, it is not necessary to perform a wet etching process for forming a wiring pattern for electrical connection with the metal thin film resistor after patterning the CrSi thin film resistor 21. Further, since the contact surface of the CrSi thin film resistor 21 with the first layer metal wiring pattern 11 is not exposed to the atmosphere, the surface oxide film removal treatment and the etching prevention barrier film formation for the CrSi thin film resistor 21 are performed. Even if it is not performed, good electrical connection between the CrSi thin film resistor 21 and the first layer metal wiring pattern 11 can be stably obtained.
Thereby, regardless of the film thickness of the CrSi thin film resistor 21, it is possible to realize miniaturization of the CrSi thin film resistor 21 and stabilization of the resistance value without increasing the number of steps.

  Further, since the refractory metal film 9 functioning as a barrier film is interposed between the CrSi thin film resistor 21 and the metal material pattern 7, the contact resistance of the CrSi thin film resistor 21 and the first layer metal wiring pattern 11 is reduced. Variations can be reduced, and resistance accuracy and yield can be improved. Furthermore, in general, in a structure in which a metal thin film resistor and a metal material are in direct contact, the contact resistance largely fluctuates due to heat treatment at a relatively low temperature of about 300 to 400 ° C., but such a problem can be eliminated.

  Further, the refractory metal film 9 also functions as a barrier film and antireflection film, and the refractory metal film 9 can be formed without increasing the number of manufacturing steps compared to the prior art, so that the manufacturing cost is increased. The contact resistance between the metal thin film resistor and the metal wiring pattern can be stabilized.

  With reference to FIG. 5 and FIG. 6, the result of having investigated the characteristic of the metal thin film resistor formed by the same structure as the said Example is shown. FIG. 5 shows the relationship between the sheet resistance and the film thickness of the metal thin film resistor, the vertical axis shows the sheet resistance (Ω / □), and the horizontal axis shows the CrSi film thickness (Å). FIG. 6 shows the relationship between the standard deviation (σ) of the measurement results at 63 points in the wafer surface of the sheet resistance of the metal thin film resistor (σ) divided by the average value (AVE) (σ / AVE) and the CrSi film thickness. The vertical axis represents σ / AVE (%), and the horizontal axis represents the CrSi film thickness (Å).

The conditions for forming the metal thin film resistor are as follows.
Using a multi-chamber sputtering apparatus, the volume time is adjusted for two types of DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, target: Si / Cr = 50/50 wt% and 80/20 wt%. Thus, a sample was prepared with a CrSi thin film having a thickness of 25 to 500 mm. In addition, about the sample of Si / Cr = 50/50 wt%, the film thickness of 500 mm is not produced.

In addition, the Ar reverse sputtering treatment before forming the CrSi thin film was performed using the multi-chamber sputtering apparatus under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, treatment time: 160 seconds. This is a process corresponding to removing 400 nm of a thermal oxide film formed in a wet atmosphere at 1000 ° C. by etching.
In this sample, an AlSiCu film having a thickness of 5000 mm is used as the lower layer metal wiring connected to the metal thin film resistor, and a TiN film on the AlSiCu film is formed at the bottom of the connection hole between the AlSiCu film and the CrSi thin film. Adopted a structure that is not.

The sheet resistance is measured by applying a voltage of 1 V to both ends of one metal thin film resistor out of 20 belt-like patterns having a width of 0.5 μm and a length of 50 μm arranged at intervals of 0.5 μm. This was performed by a two-terminal method.
The plane dimension of the connection hole connecting the metal wiring and the CrSi thin film resistor was 0.6 μm × 0.6 μm.

  As shown in FIG. 5, regardless of the composition of the target (Si / Cr = 50/50 wt% and Si / Cr = 80/20 wt%), the film thickness is increased from a thickness of 200 mm or more to a very thin film thickness of 25 mm. It can be seen that the linearity of the sheet resistance is maintained, and a metal thin film resistor having a fine dimension that cannot be formed by the conventional technique can be formed in a thin film thickness.

  Moreover, even if it sees FIG. 6 which shows the variation of the sheet resistance in 63 places in a wafer surface, the variation in resistance value of both targets (Si / Cr = 50/50 wt% and Si / Cr = 80/20 wt%) It can be seen that the film is hardly affected by the film thickness, and the variation in resistance value is very small and stable. From this, if Ar reverse sputtering treatment is employed as a method for forming the sidewall in the connection hole, an extremely fine metal thin film resistor pattern can be stably formed regardless of the film thickness of the metal thin film resistor.

  FIG. 7 shows the sheet resistance of the CrSi thin film resistor and the base film of the metal thin film resistor when the Ar reverse sputtering treatment is performed and not performed before forming the metal thin film for the metal thin film resistor. It is a figure which shows the relationship with the time which passed since (A) when it does, (B) shows the case where it does not perform. In FIG. 7, the vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the elapsed time (time) after forming the base film.

  As a sample of FIG. 7, two silicon wafers of a plasma SiN film and a plasma NSG (non-doped silicate glass) film formed to a film thickness of 2000 mm by a plasma CVD method as a base film were prepared and formed on these silicon wafers. Using a CrSi thin film resistor, the sheet resistance of the CrSi thin film resistor was measured by the four-terminal method.

The plasma SiN film as a base film is formed using a parallel plate type plasma CVD apparatus under conditions of temperature: 360 ° C., pressure: 5.5 Torr, RF power: 200 W, SiH ₄ : 70 sccm, N ₂ : 3500 sccm, NH ₃ : 40 sccm. Formed with.
The plasma NSG film was formed using a parallel plate plasma CVD apparatus under the conditions of temperature: 400 ° C., pressure: 3.0 Torr, RF power: 250 W, SiH ₄ : 16 sccm, N ₂ O: 1000 sccm.

  The CrSi thin film resistor is formed using a multi-chamber sputtering apparatus under the conditions of Si / Cr = 80/20 wt% target, DC power: 0.7 kW, Ar: 85 sccm, pressure: 8.5 mTorr, volume time: 13 seconds. By performing the treatment, a film thickness of 100 mm was formed.

  A sample subjected to Ar reverse sputtering treatment was subjected to the above-described multi-chamber sputtering apparatus under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, treatment time: 80 seconds. This is a process corresponding to etching and removing a thermal oxide film formed at 1000 ° C. in a wet atmosphere by 200 mm.

As shown in (B), when the Ar reverse sputtering treatment is not performed before the formation of the CrSi thin film, it can be seen that the sheet resistance is greatly different depending on the difference in the base film (on the SiN film and on the NSG film). Furthermore, it can be seen that the time elapsed from the formation of the base film to the formation of the CrSi thin film resistor is greatly affected.
On the other hand, as shown in (A), when Ar reverse sputtering treatment is performed, it can be seen that both the type of the underlying film and the elapsed time hardly affect the sheet resistance of the CrSi thin film resistor.

  From this, after performing Ar reverse sputtering treatment, by forming a metal thin film for a metal thin film resistor continuously in a vacuum, depending on the elapsed time from the previous process, the difference in the underlying film for each product, etc. It can be seen that the variation in the generated resistance value can be greatly improved.

  FIG. 8 is a diagram showing the relationship between the amount of Ar reverse sputtering treatment and the sheet resistance. The vertical axis represents the sheet resistance (Ω / □), and the horizontal axis represents the etching amount (in terms of thermal oxide film etching amount) (Å). For the sample of FIG. 8, the plasma NSG film and the CrSi thin film resistor formed under the same conditions as the sample formation of FIG. 7 were used as the base film and the CrSi thin film resistor. In addition, after performing Ar reverse sputtering process with respect to the plasma NSG film which passed for one week after film-forming, the CrSi thin film resistor was formed on the plasma NSG film. Ar reverse sputtering treatment was performed under the same conditions as the sample in FIG. 7 except for the etching amount. And it adjusted so that it might be set to 0 (no Ar reverse sputtering process), 25 (s), 50 (s), 100 (s), 200 (s), 400 (s), and 1000 (s) in conversion of the etching amount of the thermal oxide film formed in wet atmosphere. The sheet resistance of the CrSi thin film resistor was measured by the 4-terminal method.

  From the results of FIG. 8, it can be seen that if the Ar reverse sputtering process is performed for a film thickness of 25 mm or more in terms of the etching amount of the thermal oxide film formed in the wet atmosphere, the effect of stabilizing the resistance value of the CrSi thin film resistor can be obtained. I understood. In FIG. 8, the sample is manufactured only up to the etching thickness of 1000 mm in terms of the thermal oxide film etching amount under the Ar reverse sputtering treatment condition, but the film thickness is larger than 1000 mm in terms of the thermal oxide film etching amount. Even if the etching is performed by the amount, if the base film remains in the formation region of the metal thin film resistor, the effect of the Ar reverse sputtering process can be expected.

Furthermore, it has been found that the effect of Ar reverse sputtering treatment affects not only the influence of the underlayer but also the stability of the resistance value itself of the CrSi thin film.
FIG. 9 shows the relationship between the time of standing in the atmosphere at a temperature of 25 ° C. and a humidity of 45% after the formation of the CrSi thin film and the rate of change in sheet resistance (ΔR / R0) from the sheet resistance (R0) immediately after formation. The vertical axis represents ΔR / R0 (%), and the horizontal axis represents the standing time (hours).

For the sample of FIG. 9, the plasma NSG film and the CrSi thin film resistor formed under the same conditions as the sample formation of FIG. 7 were used as the base film and the CrSi thin film resistor.
For Ar reverse sputtering treatment, no treatment is performed (without Ar etching), thermal oxide film conversion is 100 liters at a treatment time of 40 seconds (Ar etch: 100 liters), thermal oxide film conversion is 200 liters at a processing time of 80 seconds. Three types (Ar etch: 200 mm) were prepared.

In the sample not subjected to Ar reverse sputtering treatment (without Ar etching), the resistance value increased with time after formation, and the resistance value fluctuated by 3% or more when left for 300 hours or longer. I understand.
In contrast, in the samples subjected to Ar reverse sputtering treatment (Ar etch: 100 Å and Ar etch: 200 Å), the rate of change in resistance value is greatly reduced, and the sheet resistance immediately after formation even after being left for 300 hours or more. There was no deviation from ± 1%.
Further, when comparing Ar etch: 100 Å with Ar etch: 200 影響, it was found that the influence of the Ar reverse sputtering treatment amount is small, and the effect is small with a small etching amount.

As described above, with reference to FIGS. 5 to 9, the effect of the Ar reverse sputtering treatment on the influence of the base film on the sheet resistance and the influence of the air standing time has been described. It is not limited to a CrSi thin film resistor of Si / Cr = 50/50 wt% or 80/20 wt%. In addition, the same effect as the above is observed in all of the CrSi thin film and the CrSiN film formed with the target of Si / Cr = 50/50 to 90/10 wt%.
Also, the Ar reverse sputtering treatment method is not limited to the DC bias sputter etching method used this time.

  FIG. 10 is a diagram showing the results of examining the fluctuations in the metal thin film resistance and the metal wiring contact resistance caused by the heat treatment for the sample in which the refractory metal film is left at the bottom of the connection hole when the connection hole is formed and the sample that is completely removed. It is. The vertical axis represents the value normalized by the contact resistance value before heat treatment, and the horizontal axis represents the number of heat treatments.

As the sample of FIG. 10, by adjusting the dry etching time at the time of forming the connection hole, a sample in which about 500 mm of the refractory metal film at the bottom of the connection hole was left and a sample from which the complete removal was made were prepared.
A TiN film was used as the refractory metal film.
The CrSi thin film resistor was formed to a thickness of 50 mm under the conditions of Si / Cr = 80/20 wt%, DC power: 0.7 KW, Ar: 85 sccm, pressure: 8.5 mTorr, volume time: 6 seconds.
The Ar reverse sputtering treatment before forming the CrSi thin film was performed under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr, treatment time: 160 seconds. This is a process corresponding to removing 400 nm of a thermal oxide film formed in a wet atmosphere at 1000 ° C. by etching.
The plane dimension of the connection hole was 0.6 μm × 0.6 μm. A four-terminal method was used as the contact resistance measurement method.

About said sample, it was investigated how contact resistance changed by adding heat processing for 30 minutes in 350 degreeC and nitrogen atmosphere.
A sample (with TiN) having a TiN film at the bottom of the connection hole hardly changes from the contact resistance before the heat treatment even if the heat treatment is added twice. On the other hand, in the sample from which the TiN film was completely removed (without TiN), the contact resistance fluctuated by 20% or more compared to before the heat treatment due to the addition of two heat treatments. This means that the TiN film has a function as a barrier film that prevents resistance fluctuation due to the interaction between the CrSi thin film and the metal wiring.

  The presence of the TiN film between the CrSi thin film resistor and the metal wiring makes it possible to extremely reduce fluctuations in contact resistance due to heat treatment performed in the manufacturing process such as sintering and CVD, and to perform assembly work as a subsequent process. Fluctuations in contact resistance due to heat treatment such as soldering. As a result, the contact resistance as set can be stably obtained, the fluctuation of the contact resistance before and after assembly can be prevented, and the product can be highly accurate and the yield can be improved.

In the manufacturing method described with reference to FIGS. 1 to 4, in the step (1), the metal film for the first layer metal wiring pattern 11 and the refractory metal film are continuously formed in a vacuum. However, the manufacturing method is not limited to this.
For example, when a metal film for the first layer metal wiring pattern 11 is formed, once exposed to the atmosphere, and then a refractory metal film is formed, the influence of the natural oxide film formed on the surface of the metal film for wiring Thus, it is difficult to ensure electrical continuity between the metal film and the refractory metal film. In such a case, the second-layer interlayer insulating film 15 on the first-layer metal wiring pattern 11 composed of the metal material pattern 7 and the refractory metal film 9 formed by patterning the metal film and the refractory metal film is formed on the second-layer interlayer insulating film 15. By removing all the refractory metal film 9 at the bottom of the connection hole 17 at the stage of forming the connection hole 17, an electrical connection between the first layer metal wiring pattern 11 and the CrSi thin film resistor 21 can be obtained. .

In the step (1), the refractory metal film functioning as an antireflection film / barrier film is formed to a thickness of 800 mm, but the manufacturing method is not limited to this.
In general, the refractory metal film as the antireflection film is formed to a thickness of 500 mm or less. However, when the refractory metal film 9 as the barrier film is desired to remain at the bottom of the connection hole 17, the connection hole 17 is formed. In the case of over-etching (see step (3) above) and Ar reverse sputtering treatment (see step (4) above) during the formation of the metal thin film, a slight film beveling of the refractory metal film 9 occurs. In order to stably obtain the function as, it is preferable to form a film with a thickness of 500 mm or more.

  However, as described above, by optimizing the etching conditions for forming the connection holes 17 and the Ar reverse sputtering treatment conditions, the film verifica- tion of the refractory metal film 9 is minimized even if the film thickness of the refractory metal film 9 is 500 mm or less. It is possible to exhibit the function as a barrier film while limiting to the limit.

  In the above step (2), Ar reverse sputtering is performed immediately before the formation of the CrSi thin film 27. If the refractory metal film 9 as a barrier film remains at the bottom of the connection hole 17, TiN Since the refractory metal film 9 made of a film does not form a natural oxide film that is as strong as the AlSiCu film even when exposed to the atmosphere, the CrSi thin film 27 and the first-layer metal wiring pattern 11 do not have to be subjected to the Ar reverse sputtering process. The electrical connection can be obtained. However, as described above, the stability of the resistance value of the CrSi thin film resistor 21 can be improved by performing the Ar reverse sputtering process immediately before the formation of the CrSi thin film 27. Therefore, the Ar reverse sputtering process can be performed. preferable.

  Further, in the above embodiment, the second interlayer insulating film 15 is flattened by using the SOG film formation and the etch back technique, but the insulating film serving as the base of the metal thin film resistor is It is not limited to this. As an insulating film as a base of the metal thin film resistor, for example, an insulating film that has been flattened using a known chemical mechanical polish (CMP) technique, a plasma CVD oxide film that has not been flattened, or SOG Other insulating films such as an SOG film that has been flattened by applying a heat treatment after coating, and a CVD insulating film formed by HDP (high-density-plasma) -CVD method that has been planarized by etching back Good. However, since many analog resistance elements are used not only in the TCR but also in a configuration in which pairability and specific accuracy are important, in particular, the metal thin film resistor constituting the semiconductor device of the present invention. When the body is applied to an analog resistance element, it is preferable that the insulating film serving as the base of the metal thin film resistor is subjected to a planarization process.

  In the above embodiment, the passivation film 23 is formed on the CrSi thin film resistor 21 via the protective insulating film 22. However, the present invention is not limited to this, and the CrSi thin film resistor is formed. The insulating film formed on 21 may be any insulating film such as an interlayer insulating film for forming a second-layer metal wiring.

  FIG. 11 is a cross-sectional view showing another embodiment of the first mode, (A) is a cross-sectional view showing a formation region of a metal thin film resistor and alignment mark, and (B) is surrounded by a broken line in (A). It is an expanded sectional view which expands and shows a portion. In this embodiment, the plan view of the alignment mark is the same as FIG. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  An element isolation oxide film 3, a first layer interlayer insulating film 5, a first layer metal wiring pattern 11 composed of a metal material pattern 7 and a refractory metal film 9, a laser light transmission preventing film 13, and a first layer on the silicon substrate 1, A second interlayer insulating film 15 is formed. Connection holes 17 are formed in the second-layer interlayer insulating film 15 so as to correspond to both end portions of the metal thin film resistor and the first-layer metal wiring pattern 11. A reverse sputtering residue 19 is formed on the inner wall of the connection hole 17. The upper end portion of the connection hole 17 is formed in a tapered shape.

  On the second interlayer insulating film 15, a CrSi thin film resistor 21 is formed from the region between the connection holes 17, 17 in the connection hole 17 and on the first layer metal wiring pattern 11. Under the CrSi thin film resistor 21, a laser light transmission preventing film 13 is disposed via a second interlayer insulating film 15. A CrSi thin film pattern 24 a and a stepped portion 24 c constituting the alignment mark 24 are formed in the second interlayer insulating film 15 in a region different from the CrSi thin film resistor 21.

A CrSiN film (metal nitride film) 31 is formed on the upper surface of the CrSi thin film resistor 21, and a CrSiN film 24d is formed on the upper surface of the CrSi thin film pattern 24a. CrSiO is not formed between the CrSi thin film resistor 21, the CrSi thin film pattern 24a, and the CrSiN films 31, 24d. The CrSi thin film pattern 24a, the stepped portion 24c, and the CrSiN film 24d constitute an alignment mark 24. The CrSiN film 24d functions as a protective insulating film.
A passivation film 23 is formed on the second interlayer insulating film 15 including the formation region of the CrSi thin film resistor 21 and the CrSiN film 31.

  In this embodiment, the second layer interlayer insulating film 15 is provided with an alignment mark 24 having a CrSi thin film pattern 24a, a stepped portion 24c and a CrSiN film 24b in a region different from the region where the CrSi thin film resistor 21 is formed. The upper surface of the CrSi thin film resistor 21 and the upper surface of the alignment mark 24 can be arranged at the same height, and the CrSi thin film resistor 21 can be focused with high accuracy during the laser trimming process.

  Further, similarly to the embodiment described with reference to FIG. 1, the laser light transmission preventing film 13 made of a metal material between the second interlayer insulating film 15 and the silicon substrate 1 in the region under the CrSi thin film resistor 21. Therefore, even if the CrSi thin film resistor 21 is irradiated with a laser beam 25 having sufficient intensity to cut or alter the CrSi thin film resistor 21 during the laser trimming process, the second interlayer insulating film The laser light 25 transmitted through 15 is reflected to the opposite side of the silicon substrate 1 by the laser light transmission preventing film 13, and the laser light 25 can be prevented from being irradiated onto the silicon substrate 1.

A manufacturing method for manufacturing this embodiment will be described.
On the wafer-like silicon substrate 1 in which the formation of the element isolation oxide film 3 has been completed by the same process (1) described with reference to FIG. 3A, the first-layer interlayer insulating film 5, the metal A first-layer metal wiring pattern 11 and a laser beam transmission preventing film 13, a second-layer interlayer insulating film 15, and a connection hole 17 made of the wiring pattern 7 and the refractory metal film 9 are formed.

  Under the same conditions as in step (2) described above with reference to FIG. 3B, Ar reverse sputtering is performed on the surface of the interlayer insulating film 5 in a vacuum, for example, in an Ar sputter etching chamber of a multi-chamber sputtering apparatus. The reverse sputtering residue 19 and the tapered shape of the upper end portion of the connection hole 17 are formed by performing the processing, and subsequently, the CrSi thin film for the metal thin film resistor is continuously formed without breaking the vacuum after the completion of the Ar reverse sputtering processing. .

Further, after forming the CrSi thin film, a CrSiN film is formed on the CrSi thin film continuously without breaking the vacuum. For example, the Si / Cr = 80/20 wt% CrSi target used in the formation of the CrSi thin film was used, DC power: 0.7 kW (kilowatt), Ar + N ₂ (mixed gas of argon and nitrogen): 85 sccm, pressure: 8 Processing is performed under conditions of 0.5 mTorr, processing time: 6 seconds, and a CrSiN film is formed on the CrSi thin film to a thickness of about 50 mm. Next, the CrSiN film and the CrSi thin film are patterned to form a laminated pattern composed of the CrSiN film 31 and the CrSi thin film resistor 21, and a laminated pattern composed of the CrSiN film 24d and the CrSi thin film pattern 24a.

  Here, similarly to the above-described manufacturing method described with reference to FIGS. 1 to 4, the CrSi thin film resistor 21 is electrically connected to the first layer metal wiring pattern 11. It is not necessary to perform a metal oxide film removal process on the surface of the CrSi thin film resistor 21 with a hydrofluoric acid aqueous solution. Furthermore, since the upper surface of the CrSi thin film resistor 21 is covered with the CrSiN film 31, the upper surface of the CrSi thin film resistor 21 is not oxidized even when exposed to an atmosphere containing oxygen such as air.

Thereafter, the step (4) described with reference to FIG. 3D is performed in the same manner, and a step portion is formed on the second interlayer insulating film 15 by dry etching using the CrSiN film 24d and the CrSi thin film pattern 24a as a mask. 24c is formed to form the alignment mark 24. At this time, the CrSiN film 24d functions as a protective insulating film.
In this example of the manufacturing method, the CrSiN film 24d is formed to a thickness of about 50 mm, but there is a possibility that the CrSiN film 24d and the CrSi thin film pattern 24a may be removed in the dry etching process for forming the stepped portion 24c. The CrSiN film 24d may be formed thick. Further, another insulating film such as a silicon nitride film or a laminated film of a silicon nitride film and a silicon oxide film may be formed on the CrSiN films 24d and 31.
Thereafter, a passivation film 23 is formed on the second interlayer insulating film 15.

In general, a metal thin film has high reactivity with oxygen, and it is known that the resistance value fluctuates when the metal thin film is left for a long time in a state exposed to the atmosphere.
In this embodiment, the CrSiN film 31 is formed on the upper surface of the CrSi thin film resistor 21, thereby preventing the upper surface of the CrSi thin film resistor 21 from being exposed to the air and changing the resistance value of the CrSi thin film resistor 21. ing. Here, when the CrSi thin film for forming the CrSi thin film resistor 21 is formed, the electrical connection between the CrSi thin film and the wiring pattern 11 is completed, so that a new thin film is formed on the CrSi thin film 21. Even if the film is formed, there is no influence on the characteristics.

FIG. 12 is a diagram showing the relationship between the N ₂ partial pressure of the gas for forming the CrSiN film and the resistivity of the CrSiN film, where the vertical axis represents resistivity ρ (mohm · cm (mohm · cm)), and the horizontal axis represents N ₂ partial pressure (%) is indicated. Here, the N ₂ partial pressure of Ar + N ₂ gas is adjusted under the conditions of target: Si / Cr = 50/50 wt%, DC power: 0.7 kW, Ar + N ₂ : 85 sccm, pressure: 8.5 mTorr, treatment time: 6 seconds. Thus, a CrSiN film was formed.

The CrSiN film formed by reactive sputtering with an N ₂ partial pressure of 18% or more is 10 times higher than when a gas not containing N ₂ is used at all (N ₂ partial pressure is 0%). Resistivity is shown. Accordingly, if the CrSiN film is formed by setting the N ₂ partial pressure to 18% or more, even if the CrSiN film is directly formed on the CrSi thin film resistor, the resistance value of the entire CrSi thin film resistor is CrSi. The thin film is determined, and the CrSiN film has little influence on the resistance value. Here, the upper limit of the N ₂ partial pressure is about 90%. If the N ₂ partial pressure is set to be larger than 90%, it is not preferable because the sputtering rate is significantly reduced and the production efficiency is lowered.
Note that the CrSiN film itself can be used as a metal thin film resistor if the CrSiN film is formed by reactive sputtering with an N ₂ partial pressure of about 6 to 11%, for example.

In the above embodiment, the CrSiN film 31 is provided on the CrSi thin film resistor 21, but a CVD insulating film such as a silicon nitride film may be provided on the CrSi thin film resistor 21. Good. However, a CVD chamber is not connected to a general multi-chamber sputtering apparatus, and in order to continuously form a CVD-based insulating film on the CrSi thin film resistor 21 in a vacuum, a corresponding new facility is required. It is necessary to purchase, and the production cost is greatly affected.
If the CrSiN film 31 is formed on the CrSi thin film 27 for the CrSi thin film resistor 21 as in the above manufacturing method example, a CrSi thin film can be used using an existing multi-chamber sputtering apparatus without purchasing a new apparatus. The CrSiN film 31 serving as the oxidation resistant cover film of the resistor 21 can be formed without breaking the vacuum state.

  FIGS. 13 and 14 are cross-sectional views showing still other embodiments of the first aspect, wherein (A) is a cross-sectional view showing a formation region of a metal thin film resistor and alignment mark, and (B) is a cross-sectional view of (A). It is an expanded sectional view which expands and shows the part enclosed with the broken line. In both embodiments, the plan view of the alignment mark is the same as FIG. Parts having the same functions as those in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The embodiment of FIG. 13 differs from the embodiment described with reference to FIG. 11 in that the laser light transmission preventing film 13 made of the metal material pattern 7 and the refractory metal film 9 is different from the first-layer metal wiring pattern 11. It is provided separately. Other structures are the same as those of the embodiment described with reference to FIG. Such a structure is similarly formed by changing the mask for patterning the first-layer metal wiring pattern 11 and the laser light transmission preventing film 13 in the manufacturing method described with reference to FIGS. can do.

  Further, the embodiment of FIG. 14 is different from the embodiment described with reference to FIG. 11 in that the laser light transmission preventing film 13 is not provided. Other structures are the same as those of the embodiment described with reference to FIG. Such a structure can be similarly formed by changing the mask for patterning the first-layer metal wiring pattern 11 in the manufacturing method described with reference to FIGS.

  Also in the embodiment shown in FIGS. 13 and 14, the CrSi thin film pattern 24a is formed on the second interlayer insulating film 15 which is the base film of the CrSi thin film resistor 21 in a region different from the region where the CrSi thin film resistor 21 is formed. Since the protective insulating film 24b and the step 24c or the alignment mark 24 having the CrSi thin film pattern 24a, the CrSiN film 24d and the step 24c are provided, the upper surface of the CrSi thin film resistor 21 and the upper surface of the alignment mark 24 are the same. It can be disposed at a height, and the CrSi thin film resistor 21 can be focused with high accuracy during the laser trimming process.

  In the embodiment shown in FIGS. 13 and 14, the CrSiN films 31 and 24d are provided on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a. However, as in the embodiment shown in FIG. The protective insulating films 22 and 24b may be provided on the body 21 and the CrSi thin film pattern 24a. Further, another insulating film such as a silicon oxide film or a silicon nitride film as a protective insulating film or a laminated film made of a silicon nitride film and a silicon oxide film may be provided on the CrSiN films 31 and 24d. . A structure including CrSiN films 31 and 24d on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a, and a recon oxide film, a silicon nitride film, and a laminated film of a silicon nitride film and a silicon oxide film on the CrSiN films 31 and 24d. The configuration including the above can also be applied to the embodiments described later.

  In the embodiment shown in FIG. 1, FIG. 11 and FIG. 13, the laser light transmission preventing film 13 is formed of the same material as the first layer metal wiring pattern 11 to which the CrSi thin film resistor 21 is electrically connected. However, the first mode of the semiconductor device of the present invention is not limited to this, and the first layer metal wiring pattern is formed separately from the first layer metal wiring pattern 11 in the laser light transmission preventing film. 11 may be formed of a metal material different from 11.

  In the above embodiment, the laser light transmission preventing film 13 and the first layer metal wiring pattern 11 to which the CrSi thin film resistor 21 is electrically connected are both formed on the first layer interlayer insulating film 5. However, the laser light transmission preventing film and the metal wiring pattern to which the metal thin film resistor is electrically connected may be formed on different insulating films.

  15A and 15B are views showing an embodiment of the second mode of the semiconductor device, wherein FIG. 15A is a cross-sectional view, FIG. 15B is an enlarged cross-sectional view showing the vicinity of the first connection hole, and FIG. It is sectional drawing which expands and shows the hole vicinity. In this embodiment, the plan view of the alignment mark is the same as FIG. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  An element isolation oxide film 3 is formed on the silicon substrate 1, and a first interlayer insulating film 5 is formed on the silicon substrate 1 including a region where the element isolation oxide film 3 is formed. A first-layer metal wiring pattern 11 is formed on the first-layer interlayer insulating film 5. The first layer metal wiring pattern 11 is formed of a metal material pattern made of, for example, an AlSiCu film and a refractory metal film formed on the surface of the metal material pattern, for example, a TiN film. The melting point metal film is shown integrally. A part of the first layer metal wiring pattern 11 is formed to extend in the formation region of the metal thin film resistor to constitute the laser light transmission preventing film 13.

  On the first-layer interlayer insulating film 5 including the formation region of the first-layer metal wiring pattern 11, for example, a second-layer interlayer insulation composed of a plasma CVD oxide film, an SOG film, and a plasma CVD oxide film in order from the lower layer side. A film (underlying insulating film) 15 (shown integrally in FIG. 15) is formed. A first connection hole 43 and a second connection hole 45 are formed in the second layer interlayer insulating film 15 corresponding to the first layer metal wiring pattern 11. The first connection hole 43 is for electrically connecting the first layer metal wiring pattern 11 and the metal thin film resistor formed on the second layer interlayer insulating film 15. The second connection hole 45 is for electrically connecting the first layer metal wiring pattern 11 and the second layer metal wiring pattern formed on the second layer interlayer insulating film 15.

  A first conductive plug 47 is formed by embedding a conductive material in the first connection hole 43. A second conductive plug 49 is formed by embedding a conductive material in the second connection hole 45. The first conductive plug 47 and the second conductive plug 49 are made of, for example, titanium, and a barrier metal (first conductive material) 51 formed on the inner surface of the connection hole and tungsten (second second) formed on the barrier metal 51. The conductive material 53 is formed. In (A), the barrier metal 51 and the tungsten 53 are shown integrally with respect to the first conductive plug 47 and the second conductive plug 49.

  As shown in (B), in the first connection hole 43, the upper end portion of the barrier metal 51 is formed with a gap from the upper end portion of the first connection hole 43 and the upper surface of the tungsten 53. The outer peripheral portion of the upper surface of the tungsten 53 and the upper end portion of the first connection hole 43 are formed in a tapered shape (not shown in (A)). Further, in the space between the inner wall of the first connection hole 43 and the tungsten 53 on the barrier metal 51, the reverse sputtering residue 55 ((A)) containing at least the material of the second interlayer insulating film 15, tungsten and Ar as components. Is omitted).

  As shown in (C), in the second connection hole 45, the upper surfaces of the barrier metal 51, tungsten 53, and the second interlayer insulating film 15 are formed at the same height, as in the first connection hole 43. The taper shape and the reverse sputtering residue 55 are not formed.

  A CrSi thin film resistor 21 is formed on the first conductive plug 47 and the second interlayer insulating film 15. Both ends of the CrSi thin film resistor 21 are electrically connected to the first layer metal wiring pattern 11 via the first conductive plug 47. Under the CrSi thin film resistor 21, a laser light transmission preventing film 13 is disposed via a second interlayer insulating film 15.

  A second-layer metal wiring pattern (metal wiring pattern) 57 as the uppermost metal wiring pattern is formed on the second conductive plug 49 and the second-layer interlayer insulating film 15. The second layer metal wiring pattern 37 is electrically connected to the first layer metal wiring pattern 11 via the second conductive plug 49.

Alignment having a CrSi thin film pattern 24a, a protective insulating film 24b, and a step 24c on the second interlayer insulating film 15 in a region different from the formation region of the CrSi thin film resistor 21 and the second layer metal wiring pattern 37 A mark 24 is formed.
A passivation film 23 is formed on the second-layer interlayer insulating film 15 including the formation region of the CrSi thin-film resistor 21, the alignment mark 24, and the second-layer metal wiring pattern 37.

  In this embodiment, similarly to the embodiment described with reference to FIG. 1, the CrSi thin film pattern 24a and the stepped portion 24c are formed on the second interlayer insulating film 15 in a region different from the formation region of the CrSi thin film resistor 21. Since the alignment mark 24 having the CrSiN film 24b is provided, the upper surface of the CrSi thin film resistor 21 and the upper surface of the alignment mark 24 can be arranged at the same height, and the CrSi thin film resistor 21 is subjected to the laser trimming process. The focus can be adjusted with high accuracy.

  Further, since the laser light transmission preventing film 13 made of a metal material is provided between the second-layer interlayer insulating film 15 and the silicon substrate 1 in the region under the CrSi thin film resistor 21, the CrSi thin film resistor is used during the laser trimming process. Even when the CrSi thin film resistor 21 is irradiated with a laser beam 25 having sufficient intensity to cut or alter the body 21, the laser beam 25 transmitted through the second interlayer insulating film 15 is not transmitted through the laser beam transmission preventing film 13. Therefore, it is possible to prevent the silicon substrate 1 from being irradiated with the laser beam 25 by being reflected to the side opposite to the silicon substrate 1.

  FIG. 16 is a process sectional view for explaining an example of a manufacturing method for manufacturing this embodiment. In FIG. 16, a cross-sectional view surrounded by a broken-line circle on the right side shows an enlarged view of the state of the first connection hole in each step. An example of this manufacturing method will be described with reference to FIGS.

(1) Similar to step (1) described with reference to FIG. 3A, on the wafer-like silicon substrate 1 on which the formation of the element isolation oxide film 3 and transistor elements (not shown) has been completed. Then, a first layer interlayer insulating film 5, a first layer metal wiring pattern 11 made of an AlSiCu film and a TiN film, a laser light transmission preventing film 13, and a second layer interlayer insulating film 15 are formed.

A first connection hole 43 and a second connection hole 45 are formed in the second-layer interlayer insulating film 15 corresponding to a predetermined region of the first-layer metal wiring pattern 11 by a known photolithography technique and dry etching technique. .
A barrier metal 51 made of, for example, titanium is formed on the entire surface of the second interlayer insulating film 15 including the inner wall surfaces of the first connection hole 43 and the second connection hole 45 to a thickness of 1000 mm, and further, tungsten 53 is formed on the surface of the second connection hole 45 by 7500 mm. After the film thickness is formed, an etch back process or a CMP process is performed to remove unnecessary tungsten 53 and barrier metal 51. Thereby, the first conductive plug 47 made of the barrier metal 51 and the tungsten 53 is formed in the first connection hole 43, and the second conductive plug 49 made of the barrier metal 51 and the tungsten 53 is formed in the second connection hole 45. .

  For example, using a DC magnetron sputtering apparatus, a metal material film made of, for example, an AlSiCu film is formed on the second-layer interlayer insulating film 15 to a thickness of about 5000 mm, and then continuously, for example, from a TiN film in a vacuum. A wiring metal film 59 is formed by forming a refractory metal film having a thickness of about 500 mm (see FIG. 16A).

(2) After forming a resist pattern 61 on the wiring metal film 59 for defining the formation region of the second-layer metal wiring pattern by photolithography technology, the resist pattern 61 is used as a mask by dry etching technology. The wiring metal film 59 is patterned to form a second layer metal wiring pattern 37 (see FIG. 16B). During this dry etching, the wiring metal film 59 on the first conductive plug 47 is removed, but the upper portion of the barrier metal 51 constituting the first conductive plug 47 is also removed, and the first conductive plug 47 is removed. A depression is formed around the periphery (see an enlarged view of FIG. 16B).
Such a depression has a high etching selectivity between the wiring metal film 59 and the tungsten 53 (second conductive material) and a small etching selectivity between the wiring metal film 59 and the barrier metal 51 (first conductive material). Formed in case. Therefore, such a depression is not formed only when the material types of the first conductive plug 47 and the wiring metal film 59 in this embodiment are used, but the metal film for the metal wiring pattern. On the other hand, it is formed when the etching selectivity of the first conductive material constituting the first conductive plug is small and the etching selectivity of the second conductive material constituting the first conductive plug is large.

(3) After removing the resist pattern 61, an Ar reverse sputtering process is performed on the surface of the second interlayer insulating film 15 including the formation region of the first conductive plug 47 (see FIG. 16C). ). Here, in the Ar sputter etching chamber of a multi-chamber sputtering apparatus, Ar reverse sputtering processing is performed in a vacuum under the conditions of DC bias: 1250 V, Ar: 20 sccm, pressure: 8.5 mTorr (millitorr), and processing time: 20 seconds. It was. This etching condition is the same as that for etching a thermal oxide film formed in a wet atmosphere at 1000 ° C. by about 50 mm.
By this Ar reverse sputtering process, the outer peripheral portion of the upper surface of the tungsten 53 and the upper end portion of the first connection hole 43 are formed in a tapered shape in the first connection hole 43, and further, the first connection hole 43 on the barrier metal 51 is formed. In the space between the inner wall and the tungsten 53, a reverse sputtering residue 55 containing at least the material of the second interlayer insulating film 15, tungsten and Ar as components is formed (see the enlarged view of FIG. 16C). .

(4) After completion of the Ar reverse sputtering process, a CrSi thin film (metal thin film) 27 for a metal thin film resistor is formed continuously without breaking the vacuum. Here, after a semiconductor wafer is transferred from an Ar sputter etching chamber to a sputter chamber equipped with a CrSi target, a Si / Cr = 80/20 wt% (weight percent) CrSi target is used and a DC power of 0.7 kW ( (Kilowatt), Ar: 85 sccm, pressure: 8.5 mTorr, treatment time: 9 seconds. The CrSi thin film 27 is formed on the entire surface of the second interlayer insulating film 15 including the region where the first conductive plug 47 is formed. Was formed to a thickness of about 50 mm.
Further, a silicon nitride film having a thickness of 1000 mm is formed on the CrSi thin film 27 by a known CVD method, and a silicon oxide film having a thickness of 1000 mm is further formed thereon to form a protective insulating film 28. (See FIG. 16D).

Thus, before forming the CrSi thin film 27 for the metal thin film resistor, the Ar reverse sputtering process is performed on the second interlayer insulating film 15, and the outer periphery of the upper surface of the tungsten 53 is formed in the first connection hole 43. By forming a reverse sputtering residue 55 in the space between the inner wall of the first connection hole 43 and the tungsten 53 on the barrier metal 51, the first sputtered residue 55 is formed. The step coverage of the CrSi thin film 27 in the vicinity of the connection hole 43 can be improved.
Furthermore, as described with reference to FIGS. 5 to 9, by performing the Ar reverse sputtering process, the dependency of the CrSi thin film resistor formed from the CrSi thin film 27 on the subsequent process can be improved.

(5) A resist pattern 63 is formed on the CrSi thin film 27 by the photoengraving technique to demarcate the CrSi thin film resistor and the formation region of the CrSi thin film pattern for the alignment mark. For example, by using an RIE apparatus, the protective insulating film 28 and the CrSi thin film 27 are patterned using the resist pattern 63 as a mask to form a CrSi thin film resistor 21, a CrSi thin film pattern 24a, and protective insulating films 22 and 24b (FIG. 16). (Refer to (f)).

(6) The resist pattern 63 is removed. Here, since the CrSi thin film resistor 21 is electrically connected to the first layer metal wiring pattern 11 via the first conductive plug 47, it is electrically connected to the upper surface of the metal thin film resistor as in the prior art. In order to make a connection, it is not necessary to perform a metal oxide film removal process on the surface of the CrSi thin film resistor 21 with an aqueous hydrofluoric acid solution.
The resist pattern 29 is formed by the photoengraving technique by the same process (4) described with reference to FIG. 3D, and the CrSi thin film pattern 24a, the protective insulating film 24b, and the resist pattern 29 are formed by the dry etching technique. As a mask, the second interlayer insulating film 15 is selectively removed to form a stepped portion 24 c in the second interlayer insulating film 15. As a result, an alignment mark 24 having a CrSi thin film pattern 24a, a protective insulating film 24b, and a stepped portion 24c is formed (see FIG. 16F).

(7) After removing the resist pattern 29, a silicon oxide film and a silicon nitride film as the passivation film 23 are formed on the second interlayer insulating film 15 including the formation region of the CrSi thin film resistor 21 by, for example, plasma CVD. Are sequentially formed. Thus, the manufacturing process of the semiconductor device is completed (see FIG. 15).

  Thus, after forming the first layer metal wiring pattern 11 and the connection holes 43 and 45 and forming the conductive plugs 47 and 49 in the connection holes 43 and 45, the CrSi thin film resistor 21 is formed, Since the CrSi thin film resistor 21 and the first layer metal wiring pattern 11 are electrically connected via the first conductive plug 47, the CrSi thin film resistor 21 is patterned and then electrically connected to the metal thin film resistor. There is no need to perform a wet etching process for forming a wiring pattern for the purpose.

Further, since the contact surface of the CrSi thin film resistor 21 with the first conductive plug 47 is not exposed to the atmosphere, the surface oxide film removing process and the etching preventing barrier film are not performed on the CrSi thin film resistor 21. However, a good electrical connection between the CrSi thin film resistor 21 and the first conductive plug 47 can be stably obtained.
Thereby, regardless of the film thickness of the CrSi thin film resistor 21, it is possible to realize miniaturization of the CrSi thin film resistor 21 and stabilization of the resistance value without increasing the number of steps.

  Further, since the CrSi thin film resistor 21 is formed on the first conductive plug 47 and the second-layer interlayer insulating film 15, the connection hole formed on the wiring pattern described with reference to FIG. As in the case of forming an electrical connection between the metal thin film resistor and the wiring pattern via the metal thin film resistor, the resistance value fluctuation of the metal thin film resistor and the increase in the contact resistance with the electrode are also caused by the deterioration of the step coverage of the metal thin film resistor. Absent.

  Furthermore, since the second conductive plug 49 for electrically connecting the first layer metal wiring pattern 11 and the second layer metal wiring pattern 37 is formed simultaneously with the first conductive plug 47, Compared with the manufacturing process described with reference to FIG. 33, the process for forming the insulating film 123 and the dedicated process for forming the second connection hole 125 and the second conductive plug 127 can be eliminated. Without increasing the thickness, the CrSi thin film resistor 21 can be formed at a low cost and in a short construction period.

  17 and 18 are cross-sectional views showing still another embodiment of the second mode, wherein (A) is a cross-sectional view showing a formation region of a metal thin film resistor and an alignment mark, and (B) is a cross-sectional view of (A). It is an expanded sectional view which expands and shows the part enclosed with the broken line. In both embodiments, the plan view of the alignment mark is the same as FIG. Parts having the same functions as those in FIG. 15 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The embodiment of FIG. 17 differs from the embodiment described with reference to FIG. 15 in that the laser light transmission preventing film 13 made of the metal material pattern 7 and the refractory metal film 9 is different from the first-layer metal wiring pattern 11. It is provided separately. Other structures are the same as those of the embodiment described with reference to FIG. Such a structure can be similarly formed by changing a mask for patterning the first layer metal wiring pattern 11 and the laser light transmission preventing film 13.

  18 is different from the embodiment described with reference to FIG. 15 in that the laser light transmission preventing film 13 is not provided. Other structures are the same as those of the embodiment described with reference to FIG. Such a structure can be similarly formed by changing a mask for patterning the first-layer metal wiring pattern 11.

  Also in the embodiment shown in FIGS. 17 and 18, the CrSi thin film pattern 24a is formed on the second interlayer insulating film 15 which is the base film of the CrSi thin film resistor 21 in a region different from the region where the CrSi thin film resistor 21 is formed. Since the alignment mark 24 having the protective insulating film 24b and the stepped portion 24c is provided, the upper surface of the CrSi thin film resistor 21 and the upper surface of the alignment mark 24 can be arranged at the same height. In addition, it is possible to focus on the CrSi thin film resistor 21 with high accuracy.

  In the embodiment shown in FIGS. 17 and 18, the protective insulating films 22 and 24b are provided on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a, but the second mode is not limited to this. As in the first embodiment shown in FIG. 11, CrSiN films 31 and 24d may be provided on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a. Further, another insulating film such as a recon oxide film, a silicon nitride film, or a laminated film made of a silicon nitride film and a silicon oxide film may be further provided on the CrSiN films 31 and 24d.

  In the second embodiment described with reference to FIGS. 15, 17 and 18, the laser light transmission preventing film 13 includes the first layer metal wiring pattern 11 to which the CrSi thin film resistor 21 is electrically connected. Although formed of the same material, the second aspect of the semiconductor device of the present invention is not limited to this, and the laser light transmission preventing film is formed separately from the first-layer metal wiring pattern 11. The first layer metal wiring pattern 11 may be made of a different metal material, and the laser light transmission preventing film and the metal wiring pattern to which the metal thin film resistor is electrically connected are different from each other. It may be formed on the insulating film of the layer.

  In the second embodiment described with reference to FIGS. 15, 17 and 18, the first conductive plug 47 and the second conductive plug 49 are made of a barrier metal 51 made of titanium and tungsten 53. However, in the present invention, the first conductive plug and the second conductive plug are not limited to this. For example, materials other than titanium, TiW, TiN, W, WSi, etc. can be used as the first conductive material (barrier metal). Moreover, materials other than tungsten, Cu, Al, WSi, etc. can be used as the second conductive material. However, the first conductive material and the second conductive material are not limited to the materials listed here.

In the example of the manufacturing method described with reference to FIG. 16, after forming the second layer metal wiring pattern 37 (see steps (1) and (2)), the CrSi thin film resistor 21 is formed. However, the second-layer metal wiring pattern 37 may be formed after the CrSi thin film resistor 21 is formed (see step (5)). In this case, the upper end portion of the barrier metal 51 is not removed in the first connection hole 43, and the upper surface of the first conductive plug 47 can be formed flat. Even if the Ar reverse sputtering process is performed immediately before the formation of the CrSi thin film for the CrSi thin film resistor 21, the taper shape of the upper peripheral portion of the tungsten 53 and the upper end portion of the first connection hole 43 and the reverse sputtering residue 55 are formed. Not.
However, in order to prevent the CrSi thin film resistor 21 from being etched when the second-layer metal wiring pattern 37 is formed after the formation of the CrSi thin film resistor 21, the protective insulating film 22 or the like is formed on the upper surface of the CrSi thin film resistor 21. It is preferable to provide a CrSiN film 31, a laminated film in which an insulating film is further formed on the CrSiN film, and the like.

  FIG. 19 is a view showing a formation region of a metal thin film resistor and an alignment mark in an example of the third aspect of the semiconductor device, (A) is a plan view of the formation region of the metal thin film resistor, and (B) is ( Sectional drawing containing the AA position of A), (C) is an expanded sectional view which expands and shows the part enclosed with the broken line of (B). Illustration of the passivation film in (A) is omitted. In this embodiment, the plan view of the alignment mark is the same as FIG. Parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

An element isolation oxide film 3 is formed on the silicon substrate 1. A first interlayer insulating film 5 is formed on the silicon substrate 1 including the region where the element isolation oxide film 3 is formed. On the first interlayer insulating film 5, a laser light transmission preventing film 13 made of the metal material pattern 7 and the refractory metal film 9 is formed. In other regions (not shown), a first layer metal wiring pattern composed of a metal material pattern 7 and a refractory metal film 9 is formed on the first layer interlayer insulating film 5.
A second interlayer insulating film 15 is formed on the first interlayer insulating film 5 including the region where the laser light transmission preventing film 13 is formed. On the second-layer interlayer insulating film 15, a second-layer metal wiring pattern 37 including a metal material pattern 33 and a refractory metal film 35 is formed.

  A sidewall 67 made of an insulating material, for example, a CVD oxide film, is formed on the side surface of the second layer metal wiring pattern 37. A reverse sputtering residue 69 (not shown in (A) and (B)) is formed on the surface of the sidewall 67 on the second interlayer insulating film 15 side. The reverse sputtering residue 69 is formed by performing Ar reverse sputtering processing on the second-layer interlayer insulating film 15 after the second-layer metal wiring pattern 37 and the sidewall 67 are formed. The reverse sputtering residue 69 contains at least the material of the second interlayer insulating film 15 and the sidewall 67 and Ar as components.

  A strip-shaped CrSi thin film resistor 21 is formed on the surface of the sidewall 67 between the pair of second-layer metal wiring patterns 37 facing each other, the surface of the reverse sputtering residue 69 and the second-layer interlayer insulating film 15. Both ends of the CrSi thin film resistor 21 are formed on the side wall 67 and the surface of the reverse sputtering residue 69 formed on the side surface opposite to the side surface facing the pair of second layer metal wiring patterns 37 and the second layer interlayer. The CrSi thin film resistor 21 and the second layer metal wiring pattern 37 are formed so as to cross each other.

Alignment having a CrSi thin film pattern 24a, a protective insulating film 24b, and a step 24c on the second interlayer insulating film 15 in a region different from the formation region of the CrSi thin film resistor 21 and the second layer metal wiring pattern 37 A mark 24 is formed.
A passivation film 23 (not shown in (A)) is formed on the second-layer interlayer insulating film 15 including the formation region of the CrSi thin-film resistor 21, the alignment mark 24, and the second-layer metal wiring pattern 37. Yes.

  In this embodiment, similarly to the embodiment described with reference to FIG. 1, the CrSi thin film pattern 24a and the stepped portion 24c are formed on the second interlayer insulating film 15 in a region different from the formation region of the CrSi thin film resistor 21. Since the alignment mark 24 having the CrSiN film 24b is provided, the upper surface of the CrSi thin film resistor 21 and the upper surface of the alignment mark 24 can be arranged at the same height, and the CrSi thin film resistor 21 is subjected to the laser trimming process. The focus can be adjusted with high accuracy.

  Further, since the laser light transmission preventing film 13 made of a metal material is provided between the second-layer interlayer insulating film 15 and the silicon substrate 1 in the region under the CrSi thin film resistor 21, the CrSi thin film resistor is used during the laser trimming process. Even when the CrSi thin film resistor 21 is irradiated with a laser beam 25 having sufficient intensity to cut or alter the body 21, the laser beam 25 transmitted through the second interlayer insulating film 15 is not transmitted through the laser beam transmission preventing film 13. Therefore, it is possible to prevent the silicon substrate 1 from being irradiated with the laser beam 25 by being reflected to the side opposite to the silicon substrate 1.

  FIG. 20 is a process sectional view for explaining an example of the manufacturing method of this embodiment. This embodiment will be described with reference to FIGS.

(1) Similar to step (1) described with reference to FIG. 3A, on the wafer-like silicon substrate 1 on which the formation of the element isolation oxide film 3 and transistor elements (not shown) has been completed. A first interlayer insulating film 5 is formed on the first interlayer insulating film 5, a laser light transmission preventing film 13 made of the metal material pattern 7 and the refractory metal film 9 is formed on the first interlayer insulating film 5, and the second layer An interlayer insulating film 15 is formed.

In the same manner as the first-layer metal wiring pattern 11 is formed in the step (1) described with reference to FIG. 3A, the metal material pattern 33 and the high-level metal pattern 33 are formed on the second-layer interlayer insulating film 15. A second-layer metal wiring pattern 37 made of the melting point metal film 35 is formed (see FIG. 20A).
At this stage, the metal thin film resistor is not formed as in the prior art, and the base film of the second-layer metal wiring pattern 37 is formed of the second-layer interlayer insulating film 15. It is possible to perform patterning of metal films and metal films for wiring with sufficient over-etching by dry etching technology, and there is no need to apply patterning by wet etching technology, which has been a problem of conventional technology, There is no effect on circuit miniaturization.

(2) A plasma CVD oxide film having a thickness of about 2000 mm is formed on the second-layer interlayer insulating film 15 including the formation region of the second-layer metal wiring pattern 37 by plasma CVD, for example, and then etched back. Then, a sidewall 67 made of a plasma CVD oxide film is formed on the side surface of the second-layer metal wiring pattern 37 (see FIG. 20B).

(3) Ar reverse sputtering treatment is performed under the same conditions as the Ar reverse sputtering treatment in step (2) described above with reference to FIG. By this Ar reverse sputtering treatment, a reverse sputtering residue 69 (see FIG. 19C) is formed on the surface of the sidewall 67 on the second interlayer insulating film 15 side.
Next, the CrSi thin film forming step and the protective insulating film forming step in step (2) described with reference to FIG. 3B are performed under the same conditions without breaking the vacuum state after completion of the Ar reverse sputtering process. Subsequently, a CrSi thin film for a metal thin film resistor is formed, and a protective insulating film is formed on the CrSi thin film.
Thereafter, a resist pattern for defining a CrSi thin film resistor and an area for forming a CrSi thin film pattern for alignment marks is formed on the protective insulating film by photolithography, and the resist pattern is formed using, for example, an RIE apparatus. The protective insulating film and the CrSi thin film are patterned using the mask to form the CrSi thin film resistor 21, the CrSi thin film pattern 24a, and the protective insulating films 22 and 24b. Thereafter, the resist pattern is removed (see FIG. 20C). Here, since the CrSi thin film resistor 21 is electrically connected to a part of the second layer metal wiring pattern 37, the hydrofluoric acid is used to make an electrical connection on the upper surface of the metal thin film resistor as in the prior art. It is not necessary to perform a metal oxide film removal process on the surface of the CrSi thin film resistor 21 with an aqueous solution.

(4) A resist pattern 29 is formed by photolithography using the same process as the process (4) described with reference to FIG. 3D, and the protective insulating film 24b and the resist pattern 29 are formed by dry etching. Using the mask, the second interlayer insulating film 15 is selectively removed to form a stepped portion 24c to complete the alignment mark 24 (see FIG. 20D).

(5) After removing the resist pattern 29, a silicon oxide film and a silicon nitride film as the passivation film 23 are sequentially formed on the entire surface of the second interlayer insulating film 15 by, eg, plasma CVD. Thus, the manufacturing process of the semiconductor device is completed (see FIG. 19).

  Thus, after forming the CrSi thin film resistor 21, it is not necessary to perform a wet etching process for forming a wiring pattern for establishing electrical connection with the metal thin film resistor, and in the CrSi thin film resistor 21. Since the contact surface with the second-layer metal wiring pattern 37 is not exposed to the atmosphere, the CrSi thin film resistor can be obtained without performing the surface oxide film removal treatment and the etching prevention barrier film formation on the CrSi thin film resistor 21. Good electrical connection between the body 21 and the second-layer metal wiring pattern 37 can be stably obtained. Thereby, the miniaturization of the CrSi thin film resistor 21 and the stabilization of the resistance value can be realized without increasing the number of processes regardless of the film thickness of the CrSi thin film resistor 21.

  Further, since the CrSi thin film resistor 21 is formed over the second layer interlayer insulating film 15 from the upper surface of the second layer metal wiring pattern 37 through the surface of the sidewall 67 and the reverse sputtering residue 69, the wiring pattern Compared with the case of forming an electrical connection between the metal thin film resistor and the wiring pattern through the connection hole formed above, a series of steps for forming the connection hole is not required, so the process can be shortened and simplified. Therefore, there is no fluctuation in the resistance value of the metal thin film resistor due to the deterioration of the step coverage of the metal thin film resistor and the increase in the contact resistance with the electrode.

Furthermore, since the sidewall 67 is formed on the side surface of the second layer metal wiring pattern 37, it is possible to prevent the step coverage of the CrSi thin film resistor 21 from being deteriorated due to a steep step caused by the side surface of the wiring pattern 11. it can.
Thus, stabilization of the resistance value of the CrSi thin film resistor 21 including the contact resistance with the second layer metal wiring pattern 37 can be realized.

  Further, since both ends of the CrSi thin film resistor 21 are formed so as to intersect with the second layer metal wiring pattern 37, the misalignment of the second layer metal wiring pattern 37 and the CrSi thin film resistor 21 is shifted. Further, variation in the contact area between the second layer metal wiring pattern 37 and the CrSi thin film resistor 21 due to rounding of the end of the CrSi thin film resistor 21 can be eliminated, and a more stable contact resistance can be obtained.

Further, since the refractory metal film 35 functioning as a barrier film is interposed between the CrSi thin film resistor 21 and the metal material pattern 33, the contact resistance of the CrSi thin film resistor 21 and the second layer metal wiring pattern 37 is reduced. Variations can be reduced, and resistance accuracy and yield can be improved.
Furthermore, the refractory metal film 35 also functions as a barrier film and antireflection film, and the refractory metal film 35 can be formed without increasing the number of manufacturing steps as compared with the prior art. It is possible to stabilize the contact resistance between the metal thin film resistor and the wiring pattern.

  Furthermore, since Ar reverse sputtering treatment is performed immediately before the formation of the CrSi thin film for the CrSi thin film resistor 21, as described with reference to FIGS. Can improve sex.

In the embodiment shown in FIG. 19, the sidewall 67 is provided on the side surface of the second-layer metal wiring pattern 37. However, the third mode of the semiconductor device of the present invention is the second layer as shown in FIG. The side metal wiring pattern 37 may have a configuration in which the side wall is not formed on the side surface. In FIG. 21, reference numeral 71 indicates a reverse sputtering residue formed by performing an Ar reverse sputtering process immediately before forming a CrSi thin film for the CrSi thin film resistor 21. The reverse sputtering residue 71 contains at least the refractory metal 35 and the material of the second interlayer insulating film 15 and Ar as components. Further, the upper end portion of the refractory metal 35 is formed in a tapered shape by Ar reverse sputtering treatment. The step coverage of the CrSi thin film resistor 21 is improved by the tapered shape of the reverse sputtering residue 71 and the refractory metal 35. In addition, since the Ar reverse sputtering process is performed immediately before the formation of the CrSi thin film for the CrSi thin film resistor 21, the dependency of the CrSi thin film resistor 21 on the underlying film can be improved.
Further, the embodiment shown in FIGS. 19 and 20 may be configured without the laser light transmission preventing film 13.

  22A and 22B are diagrams showing the formation region of the metal thin film resistor and the alignment mark in one embodiment of the fourth aspect of the semiconductor device. FIG. 22A is a plan view of the formation region of the metal thin film resistor, and FIG. Sectional drawing containing CC position of A), (C) is an expanded sectional view which expands and shows the part enclosed with the broken line of (B). Illustration of the passivation film in (A) is omitted. In this embodiment, the plan view of the alignment mark is the same as FIG. Portions having the same functions as those in FIG. 19 are denoted by the same reference numerals, and detailed description thereof is omitted.

  On the silicon substrate 1, the element isolation oxide film 3, the first layer interlayer insulating film 5, the laser light transmission preventing film 13 made of the metal material pattern 7 and the refractory metal film 9, the second layer interlayer insulating film 15, and A second layer metal wiring pattern 37 made of the metal material pattern 33 and the refractory metal film 35 is formed.

  On the second interlayer insulating film 15, for example, the lower layer side is made of a plasma CVD oxide film and the upper layer side is made of an SOG film. After both films are deposited, an etch back process or a CMP process is performed to form a second layer metal wiring pattern. A base insulating film 73 is formed so as to have a film thickness that exposes the upper surface of 37. In FIG. 22, the plasma CVD oxide film and the SOG film constituting the base insulating film 73 are shown integrally. Here, the base insulating film 73 is not limited to the one made of the plasma CVD oxide film and the SOG film, and is a film in which the upper surface of the second layer metal wiring pattern 37 is exposed on the second layer interlayer insulating film 15. The insulating film is not limited as long as it is a thick insulating film.

  A strip-shaped CrSi thin film resistor 21 is formed on a base insulating film 73 between a pair of opposing second-layer metal wiring patterns 37. Both ends of the CrSi thin film resistor 21 are formed by extending on the base insulating film 73 formed in the vicinity of the side surface opposite to the side surface facing the pair of second layer metal wiring patterns 37, and CrSi The thin film resistor 21 and the second layer metal wiring pattern 37 are formed so as to cross each other.

Alignment having a CrSi thin film pattern 24a, a protective insulating film 24b, and a step 24c on the second interlayer insulating film 15 in a region different from the formation region of the CrSi thin film resistor 21 and the second layer metal wiring pattern 37 A mark 24 is formed.
A passivation film 23 (not shown in (A)) is formed on the second-layer interlayer insulating film 15 including the formation region of the CrSi thin-film resistor 21, the alignment mark 24, and the second-layer metal wiring pattern 37. Yes.

  In this embodiment, since the base insulating film 73 is provided with the alignment mark 24 having the CrSi thin film pattern 24a, the stepped portion 24c and the CrSiN film 24b in a region different from the formation region of the CrSi thin film resistor 21, the CrSi thin film resistor The upper surface of the body 21 and the upper surface of the alignment mark 24 can be arranged at the same height, and the CrSi thin film resistor 21 can be focused with high accuracy during the laser trimming process.

  Further, since the laser light transmission preventing film 13 made of a metal material is provided between the base insulating film 73 and the silicon substrate 1 in the region below the CrSi thin film resistor 21, the CrSi thin film resistor 21 is cut during the laser trimming process. Alternatively, even if the CrSi thin film resistor 21 is irradiated with a laser beam 25 having a sufficient intensity to be altered, the laser beam 25 that has passed through the second interlayer insulating film 15 is transmitted to the silicon substrate 1 by the laser beam transmission preventing film 13. Therefore, the silicon substrate 1 can be prevented from being irradiated with the laser beam 25.

  FIG. 23 is a process sectional view for explaining an example of the manufacturing method of this embodiment. This embodiment will be described with reference to FIGS.

(1) On the wafer-like silicon substrate 1 where the formation of the element isolation oxide film 3, transistor elements, etc. (not shown) is completed in the same manner as the above-described step (1) described with reference to FIG. A first layer interlayer insulating film 5 is formed on the first layer interlayer insulating film 5, and a laser light transmission preventing film 13 made of the metal material pattern 7 and the refractory metal film 9 is formed on the first layer interlayer insulating film 5. An insulating film 15 is formed. In the same manner as the first-layer metal wiring pattern 11 is formed in the step (1) described with reference to FIG. 3A, the metal material pattern 33 and the high-level metal pattern 33 are formed on the second-layer interlayer insulating film 15. A second-layer metal wiring pattern 37 made of the melting point metal film 35 is formed.

  For example, a plasma CVD oxide film is formed to a thickness of about 2000 mm on the second interlayer insulating film 15 including the formation region of the second metal wiring pattern 37 by plasma CVD, and then SOG, which is a known technique. The SOG film is formed by performing the coating process, and the base insulating film 73 is formed. At this time, the upper surface of the second layer metal wiring pattern 37 is covered with the base insulating film 73 (see FIG. 23A).

(2) An etch-back process or a CMP process is performed on the base insulating film 73 until the upper surface of the second-layer metal wiring pattern 37 is exposed (see FIG. 23B).

(3) The second-layer metal wiring pattern 37 under the same conditions as the Ar reverse sputtering process, the CrSi thin film formation, and the protective insulating film formation in the step (2) described with reference to FIG. The second interlayer insulating film 15 including the formation region is subjected to Ar reverse sputtering treatment, and after the Ar sputter etching is completed, the CrSi thin film for the metal thin film resistor is continuously formed without breaking the vacuum state. Then, a protective insulating film is formed.
A resist pattern for defining a formation region of the metal thin film resistor is formed on the protective insulating film by photolithography. For example, using a RIE apparatus, the protective insulating film and the CrSi thin film are patterned using the resist pattern as a mask to form the CrSi thin film resistor 21, the CrSi thin film pattern 24a, and the protective insulating films 22 and 24b. Thereafter, the resist pattern is removed (see FIG. 23C).

(4) A resist pattern 29 is formed by photolithography using the same process as the process (4) described with reference to FIG. 3D, and the protective insulating film 24b and the resist pattern 29 are formed by dry etching. Using the mask, the second interlayer insulating film 15 is selectively removed to form a stepped portion 24c to complete the alignment mark 24 (see FIG. 20D).

(5) After removing the resist pattern 29, a silicon oxide film and a silicon nitride film as the passivation film 23 are sequentially formed on the entire surface of the second interlayer insulating film 15 by, eg, plasma CVD. Thus, the manufacturing process of the semiconductor device is completed (see FIG. 22).

  Thus, in the embodiment shown in FIG. 22 as well, there is no need to perform a wet etching process for forming a wiring pattern for electrical connection with the metal thin film resistor after the CrSi thin film resistor 21 is formed. In addition, since the contact surface of the CrSi thin film resistor 21 with the second layer metal wiring pattern 37 is not exposed to the atmosphere, good electrical properties of the CrSi thin film resistor 21 and the second layer metal wiring pattern 37 are obtained. It is possible to obtain a stable connection and to realize the miniaturization of the CrSi thin film resistor 21 and the stabilization of the resistance value without increasing the number of steps regardless of the film thickness of the CrSi thin film resistor 21. it can.

  Further, as in the embodiment described with reference to FIG. 19, there is no need for a connection hole for electrically connecting the CrSi thin film resistor 21 and the second layer metal wiring pattern 37. As compared with the case of forming the metal thin film resistor, the process can be shortened and simplified, and the resistance of the metal thin film resistor is deteriorated due to the deterioration of the step coverage of the metal thin film resistor due to the connection hole. There is no increase in resistance.

Further, since the base insulating film 73 is formed on the side surface of the second layer metal wiring pattern 37, the step coverage of the CrSi thin film resistor 21 due to the steep step caused by the side surface of the second layer metal wiring pattern 37 is reduced. Deterioration can be prevented.
Thus, stabilization of the resistance value of the CrSi thin film resistor 21 including the contact resistance with the second layer metal wiring pattern 37 can be realized.

  Further, since both ends of the CrSi thin film resistor 21 are formed so as to intersect with the second layer metal wiring pattern 37, the misalignment of the second layer metal wiring pattern 37 and the CrSi thin film resistor 21 is shifted. Further, variation in the contact area between the second layer metal wiring pattern 37 and the CrSi thin film resistor 21 due to rounding of the end of the CrSi thin film resistor 21 can be eliminated, and a more stable contact resistance can be obtained.

Further, since the refractory metal film 35 functioning as a barrier film is interposed between the CrSi thin film resistor 21 and the metal material pattern 33, the contact resistance of the CrSi thin film resistor 21 and the second layer metal wiring pattern 37 is reduced. Variations can be reduced, and resistance accuracy and yield can be improved.
Furthermore, the refractory metal film 35 also functions as a barrier film and antireflection film, and the refractory metal film 35 can be formed without increasing the number of manufacturing steps as compared with the prior art. The contact resistance between the metal thin film resistor and the metal wiring pattern can be stabilized.
Furthermore, by performing the Ar reverse sputtering process, the insulating material on the upper surface of the refractory metal film 35 constituting the second-layer metal wiring pattern 37 can be removed, and a CrSi thin film resistor formed in a later step is used. The base film dependency of the body 21 can be improved.

  In the embodiment shown in FIG. 22, as the base insulating film 73, an SOG film is applied on the plasma CVD oxide film and the SOG film is etched back and planarized. The base insulating film serving as the base is not limited to this. For example, a CVD insulating film formed by HDP (high-density-plasma) -CVD method is etched back to a film thickness where the wiring pattern surface is exposed, or a deposited plasma CVD oxide film is wired by CMP method. It may be polished to such a thickness that the pattern surface is exposed.

Further, in the embodiments shown in FIGS. 19, 21 and 22, the protective insulating films 22 and 24b are provided on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a. However, as in the first embodiment shown in FIG. 11, the CrSiN films 31 and 24d are provided on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a. Also good. Further, another insulating film such as a recon oxide film, a silicon nitride film, or a laminated film made of a silicon nitride film and a silicon oxide film may be further provided on the CrSiN films 31 and 24d.
Further, in the embodiments shown in FIGS. 19, 21 and 22, the laser light transmission preventing film 13 may not be provided.

In the embodiments shown in FIGS. 19, 21 and 22, the CrSi thin film resistor 21 and the second layer metal wiring pattern 37 are provided so as to intersect each other, but the present invention is limited to this. Instead, the end of the metal thin film resistor may be disposed on the metal wiring pattern, or the end of the metal wiring pattern may be disposed under the metal thin film resistor.
In addition, the metal thin film resistor and the metal wiring pattern do not need to be arranged in directions orthogonal to each other, and the metal thin film resistor and the metal wiring pattern are arranged in parallel to each other. The shape, orientation, and arrangement of the are not limited to the examples.

Further, as can be seen from the above embodiments, according to the first aspect, the second aspect, the third aspect, and the fourth aspect of the present invention, after the metal thin film resistor is formed, the electrical connection with the metal thin film resistor is achieved. It is not necessary to perform a wet etching process to form a wiring pattern for removing metal, and the contact surface of the metal thin film resistor with the wiring pattern is not exposed to the atmosphere. Since a good electrical connection between the metal thin film resistor and the wiring pattern can be stably obtained without performing film removal treatment and barrier film formation for etching prevention, the film thickness is 5 to 1000 mm, preferably 20 to Even if it is applied to a semiconductor device having a metal thin film resistor of 500 mm, it is possible to realize miniaturization of the metal thin film resistor and stabilization of the resistance value without increasing the number of steps.
In particular, according to the aspect provided with the above reverse sputtering residue, it is possible to reduce the base film dependency of the sheet resistance of the metal thin film resistor, so that the semiconductor having the metal thin film resistor having the above-described film thickness Even when applied to the apparatus, stabilization of the resistance value of the metal thin film resistor can be realized.

  Moreover, although the Example demonstrated above has the structure which takes the electrical connection of the CrSi thin film resistor 21 in the lower surface of the CrSi thin film resistor 21, this invention is not limited to this, A metal thin film resistor The metal thin film resistor may be electrically connected to the upper surface of the body.

  As shown in FIG. 24, for example, a laminated pattern of a CrSi thin film resistor 21 and a protective insulating film 22 is provided on the first interlayer insulating film 5, and the CrSi thin film pattern 24a is formed on the first interlayer insulating film 5. Including the alignment mark 24 having the insulating film 24b and the stepped portion 24c, and including the regions where the protective insulating film 22 on both ends of the CrSi thin film resistor 21 is removed, on the CrSi thin film resistor 21 and the first layer. The first layer metal wiring pattern 11 may be provided on the interlayer insulating film 5 so that the CrSi thin film resistor 21 and the first layer metal wiring pattern 11 are electrically connected. In the manufacturing process of this embodiment, it is difficult to remove the protective insulating film 22 on both ends of the CrSi thin film resistor 21 by the dry etching technique, but the first layer metal wiring pattern 11 is formed by the dry etching technique. It can be patterned.

  Further, as shown in FIG. 25, a laminated pattern of a CrSi thin film resistor 21 and a protective insulating film 22 is provided on the first interlayer insulating film 5, and a CrSi thin film pattern 24a is formed on the first interlayer insulating film 5. An alignment mark 24 having a protective insulating film 24b and a stepped portion 24c is provided, a second interlayer insulating film 15 is formed on the first interlayer insulating film 5, and both ends of the CrSi thin film resistor 21 are formed. Correspondingly, the second layer metal wiring pattern 37 and the CrSi thin film resistor 21 are electrically connected through the connection holes 45 formed in the second layer interlayer insulating film 15 and the protective insulating film 22. It may be. In the manufacturing process of this embodiment, when the connection hole 45 is formed, the second interlayer insulating film 15 can be selectively removed by a dry etching technique, but the protective insulating film 22 on the CrSi thin film resistor 21 is dried. It is difficult to remove by etching technique.

  24 and FIG. 25 also, the first interlayer insulating film 5 or the second layer interlayer which is the base insulating film of the CrSi thin film resistor 21 in a region different from the region where the CrSi thin film resistor 21 is formed. Since the insulating film 15 includes the alignment mark 24 having the CrSi thin film pattern 24a, the stepped portion 24c, and the CrSiN film 24b, the upper surface of the CrSi thin film resistor 21 and the upper surface of the alignment mark 24 can be arranged at the same height. It is possible to focus on the CrSi thin film resistor 21 with high accuracy during the laser trimming process.

  Thus, according to the present invention, a semiconductor device having a metal thin film resistor on a base insulating film regardless of whether the metal thin film resistor is electrically connected to the upper surface or the lower surface of the metal thin film resistor. By providing an alignment mark having a metal thin film pattern and a stepped portion on the base insulating film in a region different from that of the metal thin film resistor, the metal thin film resistor can be focused with high precision during the laser trimming process. .

In the embodiment shown in FIGS. 24 and 25, the protective insulating films 22 and 24b are provided on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a, but the first embodiment shown in FIG. 11 is implemented. Similarly to the example, CrSiN films 31 and 24d may be provided on the CrSi thin film resistor 21 and the CrSi thin film pattern 24a. Further, another insulating film such as a recon oxide film, a silicon nitride film, or a laminated film made of a silicon nitride film and a silicon oxide film may be further provided on the CrSiN films 31 and 24d.
In the embodiment shown in FIGS. 24 and 25, the CrSi thin film resistor 21 may be further formed on the upper layer side, and a laser light transmission preventing film may be provided under the CrSi thin film resistor 21.

  Moreover, in each Example of the 1st aspect demonstrated with reference to FIG.1, FIG.11, FIG.13 and FIG.14, the 1st layer metal wiring pattern 11 to which the CrSi thin film resistor 21 is electrically connected is used. The second-layer metal wiring formed in the same layer as the CrSi thin-film resistor 21 in each embodiment of the second mode described with reference to FIGS. The pattern 37 is the uppermost metal wiring pattern, and the second layer is also used in the third embodiment described with reference to FIGS. 19 and 21 and the fourth embodiment described with reference to FIG. The eye metal wiring pattern 37 is the uppermost metal wiring pattern. Thereby, for example, a layout change of the metal thin film resistor can be realized by a layout change of the metal thin film resistor and the uppermost metal wiring pattern, and the degree of freedom in design can be improved.

  In the above embodiment, since only the passivation film 23 is formed on the CrSi thin film resistor 21 except for the protective insulating film 22 or the CrSiN film 31, the passivation film is formed on the upper layer of the metal thin film resistor. Compared with the case where other insulating films are also formed, the film thickness variation of the insulating material on the CrSi thin film resistor 21 can be reduced to reduce the film thickness variation. As a result, when the CrSi thin film resistor 21 is irradiated with a laser to perform trimming, the laser given to the CrSi thin film resistor 21 with a small variation in laser interference in the insulating material on the CrSi thin film resistor 21 is provided. Variations in energy can be reduced, and trimming accuracy can be improved. Furthermore, the heat dissipation capability can be improved against the temperature rise of the CrSi thin film resistor 21 caused by laser irradiation during the trimming process.

  Further, if the base insulating film of the CrSi thin film resistor 21 is flattened as in the above embodiment, the resistance value of the metal thin film resistor is caused by the step of the base insulating film. It is possible to prevent variation.

In the above embodiment, the protective insulating film 24b or the CrSiN film 24d is provided on the CrSi thin film pattern 24a, and the stepped portion 24b is dry-etched using the protective insulating film 24b or the CrSiN film 24d and the CrSi thin film pattern 24a as a mask. Although formed by technology, the present invention is not limited to this.
For example, the stepped portion 24c may be formed by selectively removing the base insulating film using the CrSi thin film pattern 24a as a mask by a wet etching technique. In this case, the protective insulating film 24b and the CrSiN film 24d may be formed or may not be formed.

  In the above embodiment, the wiring pattern for taking the potential of the CrSi thin film resistor 21 is made of a metal material pattern and a refractory metal film, but a polysilicon pattern is used instead of the metal material pattern. You can also.

Further, in the above examples and samples, an example using CrSi as the material of the metal thin film resistor is shown, but the present invention is not limited to this, and examples of the material of the metal thin film resistor include _{NiCr, TaN, CrSi 2, CrSiN} , such as CrSi, CrSiO, other materials may be used.

  In the above embodiment, an example in which a TiN film is used as the refractory metal films 9 and 33 formed on the upper surface of the metal wiring pattern is given. However, the refractory metal film constituting the metal wiring pattern is used here. The refractory metal film such as TiW or WSi may be used without limitation.

Further, in the above examples and samples, an example using CrSi as the material of the metal thin film resistor is shown, but the present invention is not limited to this, and examples of the material of the metal thin film resistor include _{NiCr, TaN, CrSi 2, CrSiN} , such as CrSi, CrSiO, other materials may be used.

In the above embodiment, the present invention is applied to a semiconductor device having a single-layer or two-layer metal wiring pattern. However, the present invention is not limited to this, and the metal wiring has three or more layers. The present invention can also be applied to a semiconductor device having a multilayer metal wiring structure provided with a pattern. In that case, the metal wiring pattern in the lower layer of the metal thin film resistor for obtaining the electrical connection of the metal thin film resistor may be any number of metal wiring patterns.
Further, the laser light transmission preventing film disposed under the metal thin film resistor may be formed simultaneously with any layer of the metal wiring pattern as long as it is an area under the metal thin film resistor. The laser light transmission preventing film may be made of a metal material formed separately from the metal wiring pattern.

  In the above embodiment, the metal wiring patterns 11 and 37 are formed by forming a refractory metal film on the upper surface of the metal material pattern. However, the present invention is not limited to this, and metal A wiring pattern made of a metal material pattern in which a refractory metal film is not formed on the upper surface may be used. In this case, when, for example, an Al-based alloy is used as the metal material pattern, a strong natural oxide film is formed on the surface of the metal material pattern, so a metal thin film for the metal thin film resistor is formed after the connection hole is formed. It is preferable to perform a step of removing the natural oxide film on the surface of the metal material pattern at the bottom of the connection hole before. The natural oxide film removing step may also be performed in combination with the Ar reverse sputtering treatment for the purpose of suppressing the change in resistance value of the metal thin film resistor with time. The metal wiring pattern is not limited to the one containing an Al-based alloy, and may be a metal wiring pattern made of another metal material such as a Cu wiring formed by a so-called damascene method.

  The metal thin film resistor constituting the semiconductor device of the present invention can be applied to a semiconductor device provided with an analog circuit, for example. Embodiments of a semiconductor device including an analog circuit including a metal thin film resistor according to the present invention will be described below.

FIG. 26 is a circuit diagram showing an embodiment of a semiconductor device provided with a constant voltage generating circuit which is an analog circuit.
A constant voltage generation circuit 79 is provided in order to stably supply power from the DC power supply 75 to the load 77. The constant voltage generation circuit 79 includes an input terminal (Vbat) 81 to which a DC power supply 75 is connected, a reference voltage generation circuit (Vref) 83, an operational amplifier (comparison circuit) 85, and a P-channel MOS transistor (hereinafter referred to as an output driver). 87, abbreviated as PMOS), divided resistance elements R1 and R2, and an output terminal (Vout) 89.

  In the operational amplifier 85 of the constant voltage generation circuit 79, the output terminal is connected to the gate electrode of the PMOS 87, the reference voltage Vref is applied from the reference voltage generation circuit 83 to the inverting input terminal (−), and the non-inverting input terminal (+) is applied. A voltage obtained by dividing the output voltage Vout by the resistance elements R1 and R2 is applied, and the division voltage of the resistance elements R1 and R2 is controlled to be equal to the reference voltage Vref.

FIG. 27 is a circuit diagram showing an embodiment of a semiconductor device provided with a voltage detection circuit which is an analog circuit.
In the voltage detection circuit 91, reference numeral 85 denotes an operational amplifier. A reference voltage generation circuit 83 is connected to an inverting input terminal (−) of the operational amplifier, and a reference voltage Vref is applied. The voltage of the terminal to be measured input from the input terminal (Vsens) 93 is divided by the dividing resistance elements R1 and R2 and input to the non-inverting input terminal (+) of the operational amplifier 85. The output of the operational amplifier 85 is output to the outside through an output terminal (Vout) 95.

  In the voltage detection circuit 91, when the voltage of the terminal to be measured is high and the voltage divided by the dividing resistance elements R1 and R2 is higher than the reference voltage Vref, the output of the operational amplifier 85 is maintained at the H level and should be measured. When the voltage at the terminal drops and the voltage divided by the dividing resistor elements R1 and R2 becomes equal to or lower than the reference voltage Vref, the output of the operational amplifier 85 becomes L level.

  In general, in the constant voltage generation circuit shown in FIG. 26 and the voltage detection circuit shown in FIG. 27, the reference voltage Vref from the reference voltage generation circuit fluctuates due to variations in the manufacturing process. Using a resistance element circuit (referred to as a division resistance circuit) whose resistance value can be adjusted by cutting a fuse element as a division resistance element, or a division resistance circuit whose resistance value can be adjusted by laser irradiation to the resistance element. The resistance value of the element is adjusted.

  FIG. 28 is a circuit diagram showing an example of a divided resistor circuit to which the metal thin film resistor of the present invention is applied. FIG. 29 is a layout diagram showing a layout example of the coarse adjustment resistor element and the fine adjustment resistor element in the divided resistor circuit.

As shown in FIG. 28, a resistance element Rbottom, a coarse adjustment resistance element 97, a fine adjustment resistance element 99, and a resistance element Rtop are connected in series.
As shown in FIG. 29, the coarse adjustment resistor element 97 has a plurality of strip-shaped metal thin film resistors 21a connected in parallel. The fine adjustment resistance element 99 is composed of a plate-shaped metal thin film resistor 21a. A laser light transmission preventing film 13 is disposed under the metal thin film resistors 21a and 21b via an insulating film (not shown). As the metal thin film resistors 21a and 21b, metal thin film resistors constituting the present invention are used. Although illustration is omitted, an alignment mark made of a metal thin film pattern and a stepped portion is formed in the same layer as the metal thin film resistors 21a and 21b.

  In such a divided resistor circuit, as shown in FIG. 29, for example, as shown by a laser beam locus 25a, an arbitrary number of metal thin film resistors 21a are cut or altered to be insulated, and as shown by a laser beam locus 25b. A desired series resistance value can be obtained by cutting or altering any region of the metal thin film resistor 21b.

According to the metal thin film resistor and the alignment mark that constitute the semiconductor device of the present invention, the upper surface of the metal thin film resistor and the upper surface of the alignment mark can be disposed at the same height, and the metal thin film resistor is subjected to the laser trimming process. Since the body can be focused with high accuracy, the accuracy of the laser trimming process can be improved, and the accuracy of the output voltage of the divided resistor circuit shown in FIG. 28 can be improved.
Further, since the laser beam transmission preventing film is disposed under the metal thin film resistor, the laser beam is not irradiated even when a laser beam having sufficient intensity to cut or alter the metal thin film resistor during the laser trimming process. The constituent requirements of the integrated circuit and the semiconductor substrate can be prevented from being irradiated, and the accuracy of the output voltage of the divided resistor circuit shown in FIG. 28 can be improved.

When the divided resistor circuit shown in FIG. 28 is applied to the divided resistor elements R1 and R2 of the constant voltage generating circuit 79 shown in FIG. 26, for example, the resistor element Rbottom terminal is grounded and the resistor element Rtop terminal is connected to the drain of the PMOS 87. To do. Further, the terminal NodeL between the resistance element Rbottom and the fine adjustment resistance element 99 or the terminal NodeM between the resistance element Rtop and the coarse adjustment resistance element 97 is connected to the non-inverting input terminal of the operational amplifier 85.
According to the divided resistor circuit to which the metal thin film resistor and the laser light transmission preventing film constituting the present invention are applied, the accuracy of the output voltage can be improved, so that the stability of the output voltage of the constant voltage generating circuit 79 is improved. be able to.

When the divided resistor circuit shown in FIG. 28 is applied to the divided resistor elements R1 and R2 of the voltage detecting circuit 91 shown in FIG. 27, for example, the resistor element Rbottom end is grounded and the resistor element Rtop end is connected to the input terminal 93. Connecting. Further, the terminal NodeL between the resistance element Rbottom and the fine adjustment resistance element 99 or the terminal NodeM between the resistance element Rtop and the coarse adjustment resistance element 97 is connected to the non-inverting input terminal of the operational amplifier 85.
According to the divided resistor circuit to which the metal thin film resistor and the laser light transmission preventing film constituting the present invention are applied, the accuracy of the output voltage can be improved, so that the stability of the output voltage of the voltage detection circuit 91 is improved. Can do.

26 to 29, the configuration of the present invention in which the metal thin film resistor and the alignment mark are provided in the same layer, or the configuration in which the laser light transmission preventing film is disposed under the metal thin film resistor is applied. Although an example of a semiconductor device to which the divided resistor circuit is applied has been described, the semiconductor device to which such a divided resistor circuit is applied is limited to a semiconductor device having a constant voltage generation circuit and a semiconductor device having a voltage detection circuit. However, the present invention can be applied to any semiconductor device provided with a divided resistor circuit.
The semiconductor device to which the configuration of the present invention in which the metal thin film resistor and the alignment mark are provided in the same layer, or the configuration in which the laser light transmission preventing film is disposed under the metal thin film resistor is applied is a divided resistor circuit. The present invention can be applied to any semiconductor device including a metal thin film resistor.

  The embodiments of the present invention have been described above. However, the present invention is not limited to these, and the dimensions, shapes, materials, arrangements, and the like are examples, and are within the scope of the present invention described in the claims. Various changes can be made.

It is sectional drawing which shows one Example of a 1st aspect, (A) is sectional drawing which shows the formation area of a metal thin film resistor and an alignment mark, (B) expands the part enclosed with the broken line of (A). FIG. It is a top view which shows the formation area of the alignment mark of the Example. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the Example. It is sectional drawing which expands and shows the state of the connection hole vicinity after giving Ar reverse sputtering process in the manufacturing method of FIG. It is a figure which shows the relationship between the sheet resistance and film thickness of the metal thin film resistor formed by this invention, a vertical axis | shaft shows sheet resistance (ohm / square) and a horizontal axis shows CrSi film thickness (Å). The relationship between the film thickness and the value (σ / AVE) obtained by dividing the standard deviation (σ) of the sheet resistance of the metal thin film resistor formed by the present invention at 63 locations in the wafer surface by the average value (AVE) The vertical axis represents σ / AVE (%), and the horizontal axis represents the CrSi film thickness (Å). The time elapsed since the formation of the sheet resistance of the CrSi thin film resistor and the base film of the metal thin film resistor with and without the Ar reverse sputtering treatment before forming the metal thin film for the metal thin film resistor (A) shows the case where it is performed, (B) shows the case where it is not performed, the vertical axis is the sheet resistance (Ω / □), and the horizontal axis is the elapsed time (hours) after the formation of the base film. ). It is a figure which shows the relationship between the quantity of Ar reverse sputtering processing, and sheet resistance, a vertical axis | shaft shows sheet resistance (ohm / square), and a horizontal axis shows etching amount (thermal oxide film etching amount conversion) (換算). After forming a CrSi thin film for metal thin film resistors, the relationship between the time of standing in the atmosphere at a temperature of 25 ° C. and a humidity of 45% and the rate of change in sheet resistance (ΔR / R0) from the sheet resistance immediately after formation is shown. In the figure, the vertical axis represents ΔR / R0 (%), and the horizontal axis represents the standing time (hour). It is a figure showing the results of investigating fluctuations in the metal thin film resistance and metal wiring contact resistance caused by heat treatment for the sample with the refractory metal film remaining at the bottom of the connection hole and the sample completely removed at the time of forming the connection hole. The axis indicates the value normalized by the contact resistance value before heat treatment, and the horizontal axis indicates the number of heat treatments. It is sectional drawing which shows the other Example of a 1st aspect, (A) is sectional drawing which shows the formation area of a metal thin film resistor and an alignment mark, (B) is an enlarged part enclosed with the broken line of (A). It is an expanded sectional view shown. Is a diagram showing the relationship between the resistivity of the N ₂ partial pressure of the gas for CrSiN film formation and CrSiN film, and the vertical axis resistivity [rho (mohms · cm), the horizontal axis represents the N ₂ partial pressure (%). It is sectional drawing which shows the further another Example of a 1st aspect, (A) is sectional drawing which shows the formation area of a metal thin film resistor and an alignment mark, (B) is the part enclosed with the broken line of (A). It is an expanded sectional view expanding and showing. It is sectional drawing which shows the further another Example of a 1st aspect, (A) is sectional drawing which shows the formation area of a metal thin film resistor and an alignment mark, (B) is the part enclosed with the broken line of (A). It is an expanded sectional view expanding and showing. It is a figure which shows one Example of a 2nd aspect, (A) is sectional drawing, (B) is sectional drawing which expands and shows the 1st connection hole vicinity, (C) is expanded the 2nd connection hole vicinity. It is sectional drawing shown. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the Example. It is a figure which shows the other Example of a 2nd aspect, (A) is sectional drawing, (B) is sectional drawing which expands and shows the 1st connection hole vicinity, (C) expands the 2nd connection hole vicinity. FIG. It is a figure which shows the further another Example of a 2nd aspect, (A) is sectional drawing, (B) is sectional drawing which expands and shows the 1st connection hole vicinity, (C) is expanded the 2nd connection hole vicinity. It is sectional drawing shown. It is a figure which shows the formation area of the metal thin film resistor and alignment mark in one Example of a 3rd aspect, (A) is a top view of the formation area of a metal thin film resistor, (B) is AA of (A). Sectional drawing including the position, (C) is an enlarged sectional view showing an enlarged portion surrounded by a broken line in (B). It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the Example. It is a figure which shows the formation area of the metal thin film resistor in another Example of a 3rd aspect, and an alignment mark, (A) is a top view of the formation area of a metal thin film resistor, (B) is B- of (A). Sectional drawing containing B position, (C) is an expanded sectional view which expands and shows the part enclosed with the broken line of (B). It is a figure which shows the formation area of the metal thin film resistor and alignment mark in one Example of a 4th aspect, (A) is a top view of the formation area of a metal thin film resistor, (B) is CC of (A). Sectional drawing including the position, (C) is an enlarged sectional view showing an enlarged portion surrounded by a broken line in (B). It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the Example. It is sectional drawing which shows the formation area of the metal thin film resistor and the alignment mark in the Example of another aspect. It is sectional drawing which shows the formation area of the metal thin film resistor and alignment mark in the Example of another aspect. 1 is a circuit diagram showing an embodiment of a semiconductor device including a constant voltage generation circuit which is an analog circuit. It is a circuit diagram which shows one Example of the semiconductor device provided with the voltage detection circuit which is an analog circuit. It is a circuit diagram which shows an example of a division resistance circuit. FIG. 10 is a layout diagram illustrating a layout example of a coarse adjustment resistor element and a fine adjustment resistor element in the divided resistor circuit. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. It is sectional drawing for demonstrating the malfunction at the time of applying another conventional semiconductor device. It is sectional drawing for demonstrating the malfunction at the time of applying another conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Element isolation oxide film 5 1st layer interlayer insulation film 7 Metal material pattern 9 Refractory metal film 11 1st layer metal wiring pattern 13 Laser light transmission prevention film 15 2nd layer interlayer insulation film 17 Connection hole 19 Reverse sputtering residue 21 CrSi thin film resistor 21a, 21b Metal thin film resistor 22 Protective insulating film 23 Passivation film 24 Alignment mark 24a CrSi thin film pattern 24b Protective insulating film 24c Stepped portion 24d CrSiN film 25 Laser light 25a, 25b Laser light Trail 27 CrSi thin film 28 Protective insulating film 29 Resist pattern 31 CrSiN film 33 Metal material pattern 35 Refractory metal film 37 Second layer metal wiring pattern 43 First connection hole 45 Second connection hole 47 First conductive plug 49 First 2 conductive plug 51 barrier metal (first conductive material )
53 Tungsten (second conductive material)
55 Reverse sputtering residue 59 Wiring metal film 61, 63 Resist pattern 67 Side wall 69, 71 Reverse sputtering residue 73 Underlying insulating film 75 DC power supply 77 Load 79 Constant voltage generation circuit 81 Input terminal 83 Reference voltage generation circuit 85 Operational amplifier 87 P Channel MOS transistor 89 Output terminal 91 Voltage detection circuit 93 Input terminal 95 Output terminal 97 Rough adjustment resistance element 99 Fine adjustment resistance elements R1, R2 Dividing resistance elements Rbottom, Rtop Resistance elements NodeL, NodeM

Claims (16)

In a semiconductor device provided with a metal thin film resistor on a base insulating film formed on a semiconductor substrate,
A metal thin film pattern formed on the base insulating film in a region different from a region where the metal thin film resistor is formed, and a step formed by selectively removing the base insulating film using the metal thin film pattern as a mask A semiconductor device comprising an alignment mark having a portion.   The semiconductor device according to claim 1, further comprising a protective insulating film on the metal thin film pattern.   3. The semiconductor device according to claim 1, further comprising a metal nitride film covering an upper surface of the metal thin film resistor, wherein a metal oxide film is not formed between the upper surface of the metal thin film resistor and the metal nitride film. A lower layer insulating film formed under the base insulating film, a wiring pattern formed on the lower insulating film, and a connection hole formed in the base insulating film on the wiring pattern;
4. The semiconductor device according to claim 1, wherein the metal thin film resistor is formed over the base insulating film and in the connection hole and is electrically connected to the wiring pattern in the connection hole. 5.   At least an upper end portion of the connection hole is formed in a tapered shape, and a reverse sputtering residue containing at least the wiring pattern, the base insulating film material, and Ar as components is formed on the inner wall of the connection hole. The semiconductor device according to claim 4. A lower insulating film formed under the underlying insulating film, a wiring pattern formed on the lower insulating film, a connection hole formed in the underlying insulating film on the wiring pattern, and in the connecting hole A conductive plug formed on
4. The semiconductor device according to claim 1, wherein the metal thin film resistor is formed from the base insulating film to the conductive plug. A second connection hole formed in the base insulating film on the wiring pattern in a region different from the connection hole, and a second conductive plug formed in the second connection hole simultaneously with the formation of the conductive plug And further comprising a metal wiring pattern formed on the second conductive plug and the base insulating film,
The conductive plug and the second conductive plug include a first conductive material formed on an inner wall surface of the connection hole and the second connection hole, and a second conductive material formed on the first conductive material. Is formed by
In the connection hole formed under the metal thin film resistor, the upper end portion of the first conductive material is formed with a gap from the upper end portion of the connection hole and the upper surface of the second conductive material, An outer peripheral portion of the upper surface of the second conductive material and an upper end portion of the connection hole are formed in a taper shape, and are formed between the inner wall of the connection hole and the second conductive material on the first conductive material. The semiconductor device according to claim 6, wherein a reverse sputtering residue containing at least a material of the base insulating film, the first conductive material, and Ar as components is formed in the space. Comprising a wiring pattern formed on the base insulating film;
4. The semiconductor device according to claim 1, wherein the metal thin film resistor is formed from the base insulating film to the wiring pattern.   9. The semiconductor device according to claim 8, wherein a reverse sputtering residue containing at least a material of the wiring pattern and Ar as components is formed on a surface of the wiring pattern on the base insulating film side. Further comprising a sidewall made of an insulating material on the side surface of the wiring pattern,
The semiconductor device according to claim 8, wherein the metal thin film resistor is formed over the wiring pattern through the sidewall surface from the base insulating film.   The semiconductor device according to claim 10, wherein a reverse sputtering residue containing at least the sidewall material and Ar as components is formed on a surface of the sidewall on the base insulating film side. A lower-layer-side insulating film formed under the base insulating film;
A wiring pattern formed on the lower insulating film,
The base insulating film is formed on the lower insulating film with a thickness at which the upper surface of the wiring pattern is exposed,
4. The semiconductor device according to claim 1, wherein the metal thin film resistor is formed from the base insulating film to the wiring pattern.   The semiconductor device according to claim 1, further comprising a laser light transmission preventing film made of a metal material between the base insulating film and the semiconductor substrate in a region under the metal thin film resistor. In a semiconductor device having a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistor elements and adjusting the voltage output by laser irradiation to the resistor elements,
14. The semiconductor device, wherein the resistance element includes the metal thin film resistor and the alignment mark according to claim 1. A divided resistor circuit for dividing the input voltage to supply a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the divided resistor circuit, and a reference voltage from the reference voltage generating circuit In a semiconductor device including a voltage detection circuit having a comparison circuit for comparison,
A semiconductor device comprising the divided resistor circuit according to claim 14 as the divided resistor circuit. An output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and a divided voltage from the divided resistor circuit In a semiconductor device including a constant voltage generation circuit having a comparison circuit for comparing the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result,
A semiconductor device comprising the divided resistor circuit according to claim 14 as the divided resistor circuit.

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