JP2005250891A - Reading method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To read high-volume data from a storage medium allowing a slow reading speed in a short time. <P>SOLUTION: The hold time and setup time (hereinafter referred to as access time) of a bus controller is set to a set value C1 in which a normal operation is ensured in the specification of a NAND controller (step S101), and the check sum of data recorded in the storage medium is read with the set value C1 (step S102). The access time of the bus controller is set to a set value C2 larger than the set value C1 (step S103), and data stored in the storage medium read with the set value C2 (step S104). Further, based on a check sum calculated by the NAND controller, whether the data read from the storage medium have errors or not is determined (step S105), and data with errors are read again from the storage medium (step S104). This invention is applicable, for example, to reading of data from a NAND type flash memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a reading method and a program, and more particularly, to a reading method and a program capable of reducing the time required to read a large amount of data from a recording medium having a low reading speed.

  2. Description of the Related Art In recent years, with the advancement of functions of information home appliances and mobile terminals, the program size of software (programs) for realizing the functions has increased dramatically. Therefore, as the program size increases, a large-capacity recording medium for recording the program is required, and the time required for starting the program, that is, the startup time tends to be longer.

  Conventionally, programs for information home appliances and portable terminals are recorded in a NOR flash memory that is expensive but can be read at high speed in order to shorten the startup time of the program. However, as the program size increases, it is necessary to mount a NOR-type flash memory with a large capacity, which increases the cost of the product.

  In view of this, a method of recording a program in a NAND flash memory that is relatively inexpensive and capable of realizing a large capacity, reading the program from the NAND flash memory, and starting an information home appliance or a portable terminal has attracted attention. However, the NAND type flash memory has a disadvantage that its reading speed is slower than that of a NOR type flash memory that is conventionally used. Therefore, when a program is read from the NAND flash memory, the startup time of information home appliances and portable terminals becomes long.

  Recently, the data size of data other than programs handled by information home appliances and portable terminals has also increased dramatically, and the read time for reading such data from a recording medium has also become a problem.

  Here, in the storage device in which the storage area such as the flash memory is divided into a plurality of blocks, the applicant of the present invention performs data processing for storing arbitrary data and management information for managing the data in each block. A method is proposed (see Patent Document 1). By managing data in units of blocks, it is possible to extend the life of the storage device and increase the processing speed.

  Furthermore, the applicant monitors whether or not the scheduled processing is being performed, and if the scheduled processing is not being performed, the operation setting value of the functional block that performs the processing is processed. An information processing method is proposed in which processing is performed by setting an operation setting value suitable for performing the process (see Patent Document 2). By setting the operation setting value suitable for executing the processing, the data can be processed quickly.

JP-A-11-110263 JP 2002-312056 A

  As described above, if a recording medium for recording a large amount of data (including a program) is a large-capacity NOR flash memory, the price of the product becomes expensive. In addition, when the recording medium is a NAND flash memory that is inexpensive and can realize a large capacity, the data reading speed is slow.

  The present invention has been made in view of such circumstances, and an object of the present invention is to shorten the time required to read data from a recording medium having a slow reading speed.

  The read method of the present invention changes the setup time and hold time (hereinafter referred to as access time) of the bus controller to the first access time within the guaranteed access time range in which normal operation is guaranteed by the specification of the read means. The first setting step to be set and the check data which is data for checking the error of the data recorded on the recording medium by accessing the reading means with the access time set in the first setting step. Are read from the recording medium, a second setting step for setting the access time for the reading means to a second access time smaller than the guaranteed access time, and a second setting for the reading means Recording media by accessing with the access time set in step A second reading step for reading data recorded on the recording medium, a determination step for determining whether there is an error in the data read from the recording medium based on the check data, and an error by accessing the reading means And a third reading step of reading again the data that has occurred from the recording medium.

  The reading method may further include a third setting step of setting the access time for the reading means to a third access time that is larger than the second access time when there is an error in the data. In the third reading step, the data recorded on the recording medium can be read by accessing with the access time set in the third setting step.

  When there are multiple errors in the data, in the third setting step, the access time for the reading means can be set to a third access time that is larger than the second access time.

  In the recording medium, check data for error check of the divided data is recorded for each divided data obtained by dividing the data into a predetermined divided size, and in the second reading step, in divided data units, Data is read from the recording medium, and in the determination step, it is possible to determine whether there is an error in the data in units of divided data.

  The data recorded on the recording medium may be a program.

  The data recorded on the recording medium may be a program read by an SPL (Secondary Program Loader) after the electronic device is activated.

  The program of the present invention includes a first setting step for setting the access time for the reading means to a first access time within a guaranteed access time range in which normal operation is guaranteed by the specifications of the reading means, and the reading means On the other hand, a first reading step of reading check data, which is data for checking errors in data recorded on the recording medium, from the recording medium by accessing with the access time set in the first setting step. A second setting step for setting the access time for the reading means to a second access time smaller than the guaranteed access time, and accessing the reading means with the access time set in the second setting step. Second reading step for reading data recorded on the recording medium And a determination step for determining whether there is an error in the data read from the recording medium based on the check data, and reading out the erroneous data from the recording medium by accessing the reading means And controlling the reading process including a third reading step.

  In the reading method and program of the present invention, the access time for the reading means is set to the first access time within the guaranteed access time range in which normal operation is guaranteed by the specifications of the reading means. Thus, by accessing at the first access time, check data, which is data for checking an error of data recorded on the recording medium, is read from the recording medium. The access time for the reading means is set to a second access time that is smaller than the guaranteed access time, and the data recorded on the recording medium is read by accessing the reading means with the second access time. It is. Further, based on the check data, it is determined whether there is an error in the data read from the recording medium. By accessing the reading means, the data having the error is read again from the recording medium.

  According to the present invention, data can be read out from a recording medium with a low reading speed in a short time.

  BEST MODE FOR CARRYING OUT THE INVENTION The best mode of the present invention will be described below. Correspondences between constituent features described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, it may be divided in the future. It does not deny the existence of an invention which appears by amendment and is added.

The reading method according to claim 1 comprises:
In a reading method of reading data from the recording medium by accessing reading means (for example, the NAND controller 26 of FIG. 1) for reading data from the recording medium (for example, the NAND flash memory 28 of FIG. 1),
A first setting step for setting the access time for the reading means to a first access time (for example, a guaranteed setting value C1) within a guaranteed access time range in which normal operation is guaranteed by the specifications of the reading means ( For example, the process of step S101 in FIG.
By accessing the reading means with the access time set in the first setting step, check data (for example, FIG. 3) is data for error checking of the data recorded on the recording medium. A first reading step (for example, the process of step S102 of FIG. 6) for reading the checksum data 83) from the recording medium;
A second setting step (for example, the process of step S103 in FIG. 6) for setting the access time for the reading means to a second access time (for example, the operation limit set value C2) smaller than the guaranteed access time;
A second reading step (for example, step S104 in FIG. 6) for reading the data recorded on the recording medium by accessing the reading means with the access time set in the second setting step. Processing)
A determination step for determining whether or not the data read from the recording medium has an error based on the check data (for example, the process of step S106 in FIG. 6);
A third reading step (for example, the process of step S104 in FIG. 6) for reading again the data having an error by accessing the reading means from the recording medium is included.

The reading method according to claim 2 comprises:
When there is an error in the data, a third setting step (for example, setting the access time for the reading means to a third access time (for example, a high-speed setting value C3) larger than the second access time) Further includes the processing of step S131 of FIG.
In the third reading step, the data recorded on the recording medium is read at the access time set in the third setting step.

The program according to claim 7 is:
A read process for reading data from the recording medium by accessing reading means (for example, the bus controller 25 and the NAND controller 26 in FIG. 1) for reading data from the recording medium (for example, the NAND flash memory 28 in FIG. 1). A program for causing a computer to perform control processing,
A first setting step for setting the access time for the reading means to a first access time (for example, a guaranteed setting value C1) within a guaranteed access time range in which normal operation is guaranteed by the specifications of the reading means ( For example, the process of step S101 in FIG.
By accessing the reading means with the access time set in the first setting step, check data (for example, FIG. 3) is data for error checking of the data recorded on the recording medium. A first reading step (for example, the process of step S102 of FIG. 6) for reading the checksum data 83) from the recording medium;
A second setting step (for example, the process of step S103 in FIG. 6) for setting the access time for the reading means to a second access time (for example, the operation limit set value C2) smaller than the guaranteed access time;
A second reading step (for example, step S104 in FIG. 6) for reading the data recorded on the recording medium by accessing the reading means with the access time set in the second setting step. Processing)
A determination step for determining whether or not the data read from the recording medium has an error based on the check data (for example, the process of step S106 in FIG. 6);
A third reading step (for example, the process of step S104 in FIG. 6) for reading the data having an error by accessing the reading unit from the recording medium is included.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of an embodiment of hardware of an information processing system 10 to which the present invention is applied.

  The CPU 21, ASIC 22, ROM 23, RAM 24, bus controller 25, and NAND controller 26 are connected to each other via a bus 27. Further, the NAND controller 26 is connected to a NAND flash memory 28.

  A CPU (Central Processing Unit) 21 performs various processes by executing a program loaded in the RAM 24.

  An ASIC (Application Specific Integrated Circuit) 22 loads an IPL (Initial Program Loader) program 31 stored in a ROM (Read Only Memory) 23 in accordance with a signal when the information processing system 10 is turned on. Memory) 24.

  The ROM 23 stores an IPL program 31 that is executed first when the information processing system 10 is activated. The IPL program 31 is executed by the CPU 21 to load an SPL (Secondary Program Loader) program 32 recorded in the NAND flash memory 28 into the RAM 24. That is, the CPU 21 loads the SPL program 32 recorded in the NAND flash memory 28 into the RAM 24 via the NAND controller 26 by executing the IPL program 31 loaded in the RAM 24.

  The RAM 24 stores an IPL program 31 loaded by the ASIC 22, an SPL program 32 loaded by the CPU 21, and the like. The RAM 24 stores data necessary for the operation of the CPU 21.

  The bus controller 25 holds various setting values such as the bus width and access time (setup time, hold time) for each device connected to the bus 27.

  The NAND controller 26 accesses the NAND flash memory 28 in response to an access from the CPU 21 via the bus 27, and reads the SPL program 32, the system program 33, etc. recorded in the NAND flash memory 28 (load). To do). Further, the NAND controller 26 accesses the NAND flash memory 28 and writes data created by the CPU 21 in response to access from the CPU 21 via the bus 27.

  The bus 27 operates with the bus width and access time set by the bus controller 25.

  In the NAND flash memory 28, in FIG. 1, an SPL program 32, a system program 33 of the information processing system 10, and the like are recorded. The SPL program 32 is executed by the CPU 21 to change the setting value of the bus controller 25 and load the system program 33 from the NAND flash memory 28 to the RAM 24.

  The bus 27 is also connected to a power button of the information processing system 10 and an input unit (none of which is not shown) for the user to operate the CPU 21 via an input / output interface (not shown). ing.

  In the information processing system 10 configured as described above, when the information processing system 10 is powered on, the ASIC 22 loads the IPL program 31 from the ROM 23 to the RAM 24. Then, when the CPU 21 executes the IPL program 31 on the RAM 24, the SPL program 32 is loaded from the NAND flash memory 28 to the RAM 24. Further, when the CPU 21 executes the SPL program 32 on the RAM 24, the system program 33 is loaded from the NAND flash memory 28 onto the RAM 24. Various functions of the information processing system 10 are realized by the CPU 21 executing the system program 33 on the RAM 24.

  The NAND flash memory 28 may be built into the information processing system 10 or may be detachable from the information processing system 10.

  The activation process of the information processing system 10 will be described with reference to the flowchart shown in FIG.

  For example, when the user of the information processing system 10 operates the power switch to turn on the power of the information processing system 10, a signal for turning on the power is input to the information processing system 10 in step S51. In response to this power-on signal, the process proceeds from step S51 to S52, and the ASIC 22 loads (decompresses) the IPL program 31 stored in the ROM 23 into the RAM 24, and then proceeds to step S53. In step S <b> 53, the CPU 21 causes the NAND controller 26 to read the SPL program 32 from the NAND flash memory 28 and load it into the RAM 24 by executing the IPL program 31 on the RAM 24.

  Note that reading of data from the NAND flash memory 28 by the NAND controller 26 is performed by the CPU 21 accessing the NAND controller 26 via the bus 27. In step S53, when the SPL program 32 is read from the NAND flash memory 28, the CPU 21 accesses the NAND controller 26 with an access time within a range in which normal operation of the NAND controller 26 is guaranteed.

  Proceeding from step S 53 to S 54, the CPU 21 executes a SPL program 32 on the RAM 24, thereby controlling a reading process for causing the NAND controller 26 to load the system program 33 recorded in the NAND flash memory 28 onto the RAM 24. The reading process of the system program 33 by the SPL program 32 will be described later with reference to FIG.

  Proceeding from step S54 to S55, the CPU 21 executes the system program 33 loaded in the RAM 24 and ends the activation process.

  It can be said that the time from the input of the power-on signal in step S51 to the execution of the system program 33 in step S55 is the startup time of the information processing system 10. The program size of the IPL program 31 stored in the ROM 23 is sufficiently smaller than the system program 33 in order to reduce the storage capacity of the ROM 23 as much as possible. Further, the program size of the SPL program 32 recorded in the NAND flash memory 28 is also sufficiently smaller than that of the system program 33.

  Accordingly, the load of the IPL program 31 and the load of the SPL program 32 have little influence on the startup time of the information processing system 10, and in order to shorten the startup time, the load is recorded in the NAND flash memory 28 performed in step S54. It can be said that it is most effective to perform the reading process of the system program 33 in a short time.

  However, as described above, the NAND flash memory 28 has a drawback that its reading speed is low. The main reason for the slow reading speed of the NAND flash memory 28 is that the access time to the NAND controller 26 set in the bus controller 25 when executing the process of reading the system program 33 by accessing the NAND flash memory 28. Is low (slow).

  By the way, in general, the access to the NAND controller 26 may sometimes operate normally even if the access time is shorter than the guaranteed access time that is guaranteed (defined) by the specification or the like. Approved above.

  Therefore, it is conceivable to shorten the reading time of the system program 33 by accessing the NAND controller 26 with an access time shorter than the guaranteed access time. However, when the CPU 21 sets an access time shorter than the guaranteed access time to the bus controller 25 and accesses the NAND controller 26, the system program 33 read from the NAND flash memory 28 has an error (reading of the system program 33). May fail).

  Therefore, the SPL program 32 determines whether or not there is an error in the system program 33 read from the NAND flash memory 28. If there is an error, the SPL program 32 reads the system program 33 from the NAND flash memory 28 again. Thus, the system program 33 is reliably read out.

  FIG. 3 shows a memory map of the NAND flash memory 28 in which the SPL program 32 and the system program 33 are recorded.

  In the NAND flash memory 28, the SPL program 32 and the system program 33 of the information processing system 10 are sequentially recorded from the top recording area. The subsequent recording area is a user use area 71.

  The SPL program 32 includes a division size 81 and access time setting information 82. The NAND controller 26 reads the system program 33 recorded in the NAND flash memory 28 in units of one or more blocks of a predetermined size, and the division size 81 is the size of the block ( Program size) information. The access time setting information 82 is information on the access time of the bus controller 25 set for the NAND controller 26.

  Here, the SPL program 32 reads the system program 33 recorded in the NAND flash memory 28 in units of blocks having a division size 81. When the SPL program 32 reads the system program 33 from the NAND flash memory 28 in units of blocks of the division size 81, even if the reading fails, only a part of the blocks that failed to be read can be read again. That's it. Therefore, even when the reading of a certain block fails, the SPL program 32 does not need to read the block that has been successfully read, and the reading time can be shortened. Note that the smaller the division size 81, the smaller the possibility of failure in reading a block of that division size 81.

  Hereinafter, a portion obtained by dividing the system program 33 in units of blocks having a division size 81 will be described as a program image.

  The access time setting information 82 of the bus controller 25 includes a guaranteed set value C1, which is an access time within a range in which normal operation of the NAND controller 26 is guaranteed by specifications, and an access time near the limit at which the NAND controller 26 operates. The operation limit set value C2 (C1> C2) and the high speed set value C3 (C1> C3> C2) which are smaller than the guaranteed set value C1 and larger than the operation limit set value C2 are recorded.

  The high speed setting value C3 may be equal to the guaranteed setting value C1. In this case, only the guaranteed set value C1 and the operation limit set value C2 may be recorded as the setting information 82.

  Further, the guaranteed set value C1 may be the same as or different from the access time when the SPL program 32 reads the SPL program 32 from the NAND flash memory 28 in step S53 of FIG. .

  The system program 33 includes checksum data 83 for each of one or more program images obtained by dividing the system program 33 in units of blocks having a division size 81. The checksum data 83 is data for the NAND controller 26 to check whether there is an error in the program image read from the NAND flash memory 28. The creator of the system program 33 calculates the checksum of each program image in advance, and includes the value in the system program 33 as the checksum data 83 of the program image.

  In the user use area 71, for example, data created by the CPU 21 executing various processes in response to an operation of a user input unit (not shown) or the like is recorded.

  A process of creating the NAND flash memory 28 shown in FIG. 3 will be described with reference to the flowchart of FIG.

  In step S61, a division size 81 that is the size of the program image of the system program 33 is determined. The division size 81 is, for example, an examination of a failure rate when the CPU 21 executing the SPL program 32 controls the bus controller 25 to read a program image of a predetermined size, To do.

  Proceeding from step S61 to S62, the checksum data 83 is calculated for each of one or more program images obtained by dividing the system program 33 by the division size 81. The checksum data 83 for each program image is arranged in the order of the corresponding program image and recorded in the NAND flash memory 28 in step S64 described later.

  In step S62, the CPU 21 executing the SPL program 32 reads the program image from the NAND flash memory 28 via the bus 27 and the NAND controller 26, and represents the access time for the NAND controller 26 on the bus 27. Information 82 is set. That is, in step S63, the access time that is guaranteed to normally read data from the NAND flash memory 28 in the NAND controller 26 is set to the guaranteed set value C1. For example, the guaranteed set value C1 can be an access time for which normal operation is guaranteed by the specification of the NAND controller 26 or the like. In step S63, the high-speed access time near the limit at which the NAND controller 26 operates is set to the operation limit set value C2 (C1> C2). For example, the operation limit set value C2 can be used as a limit operation set value (access time) at which the NAND controller 26 operates by verifying the performance of the NAND controller 26. Further, in step S63, an arbitrary access time that is smaller than the guaranteed set value C1 and greater than the operation limit set value C2 is set to the high-speed set value C3 (C1> C3> C2).

  Proceeding from step S 63 to S 64, the SPL program 32 and the system program 33 are recorded in the NAND flash memory 28. Further, the division size 81 determined in step S61 and the guaranteed setting value C1, the operation limit setting value C2, and the high-speed setting value C3 as the setting information 82 set in step S63 are recorded as attached information of the SPL program 32. Is done. Further, checksum data 83 is recorded as ancillary information of the system program 33.

  The division size 81 determined in step S61 and the setting information 82 set in step S63 are determined by the creator of the SPL program 32, the system program 33, or the NAND flash memory 28 by operating a control unit (not shown). Can be input.

  FIG. 5 shows a configuration example of the NAND controller 26. The NAND controller 26 can read / write data from / to the NAND flash memory 28, but the portion related to data writing is not shown.

  The NAND controller 26 includes a control unit 101, a reading unit 111, and a checksum calculation unit 112.

  The control unit 101 controls the reading unit 111 and the checksum calculation unit 112 under the access time set by the bus controller 25.

  The reading unit 111 reads the division size 81, setting information 82, checksum data 83 data, and the like from the NAND flash memory 28 under the control of the control unit 101.

  The checksum calculation unit 112 acquires the program image read by the reading unit 111 from the NAND flash memory 28 via the control unit 101, calculates the checksum data of the program image, and via the control unit 101, The program is supplied to the SPL program 32 (CPU 21 executing the SPL program 32).

  In the SPL program 32 (the CPU 21 executing the SPL program 32), the reading unit 111 reads from the NAND flash memory 28, and acquires the checksum data 83 stored in the RAM 24 via the control unit 101. In the SPL program 32, the checksum data calculated from the program image from the checksum operation unit 112 matches the checksum data 83 stored in the RAM 24 and read from the NAND flash memory 28. The program image read from the NAND flash memory 28 is checked for errors, that is, whether the program image is successfully read from the NAND flash memory 28 is determined. The control unit 101 is notified of the result.

  The reading process of the system program 33 performed by the SPL program 32 (the CPU 21 executing the program) in step S54 of FIG. 2 will be described with reference to the flowchart of FIG.

  The CPU 21 supplies the setting information 82 to the bus controller 25 by executing the SPL program 32. In step S101, the bus controller 25 sets the access time to the guaranteed setting value C1 according to the setting information 82 supplied from the CPU 21.

  Proceeding from step S101 to S102, the bus 27 operates according to the access time of the guaranteed setting value C1 set in the bus controller 25 in step S101, and the SPL program 32 (the CPU 21 executing the program) is transferred to the NAND controller 26. By accessing, the checksum data 83 is read from the NAND flash memory 28. This checksum data 83 is supplied to and stored in the RAM 24 via the control unit 101.

  In this way, the SPL program 32 (the CPU 21 executing the program) sets the guaranteed setting value C1 that is guaranteed to read data normally in the bus controller 25, and accesses the NAND controller 26. Since the checksum data 83 is read from the NAND flash memory 28, the checksum data 83 can be read reliably.

  Proceeding from step S102 to S103, the SPL program 32 (the CPU 21 executing the program) sets the access time of the bus controller 25 to the operation limit set value C2 in accordance with the setting information 82. Furthermore, in step S103, one of the program images that have not yet been read out of the system program 33 from the NAND flash memory 28 is set as a target image.

  Proceeding from step S103 to S104, the SPL program (CPU 21 executing) accesses the NAND controller 26 according to the current set value of the bus controller 25, that is, the access time of the operation limit set value C2 in this case. As a result, the image of interest in the system program 33 is read from the NAND flash memory 28 (the system program 33 is read in units of blocks of the division size 81) and supplied to the RAM 24 via the control unit 101. , And supplied to the checksum calculation unit 112.

  Thus, by operating the bus 27 with the operation limit setting value C2 of the NAND controller 26, it is possible to read the program image by accessing the NAND controller 26 at a higher speed than when operating with the guaranteed setting value C1. Become. Therefore, it is possible to reduce the time required to read the program image from the NAND flash memory 28.

  Proceeding from step S104 to S105, the checksum calculation unit 112 calculates the checksum data of the image of interest from the control unit 101, stores it in the RAM 24 via the control unit 101, and proceeds to step S106.

  In step S106, the SPL program 32 (the CPU 21 executing the program) acquires the checksum data 83 of the target image from the checksum data 83 stored in the RAM 24 in step S102. In step S105, it is determined whether the checksum data from the checksum calculation unit 112 stored in the RAM 24 matches the checksum data 83 from the RAM 24.

  If it is determined in step S106 that the checksum data stored in the RAM 24 from the checksum calculation unit 112 and the checksum data 83 from the RAM 24 do not match, the SPL program 32 (the CPU 21 executing the program) It is determined that the image reading has failed, and the process proceeds from step S106 to step S121.

  In response to the failure in reading the target image, in step S121, the SPL program 32 (the CPU 21 executing the program) determines whether or not the target image has been read a predetermined number of times one or more times. To do. If it is determined in step S121 that the target image has not been read a predetermined number of times, that is, if the target image read failure count is less than the predetermined number, the process returns to step S104, and the SPL program 32 ( The CPU 21) executing the process accesses the NAND controller 26 at the access time of the operation limit set value C2 set in step S103, and repeats the process of reading the attention image again.

  On the other hand, if it is determined in step S121 that the target image has failed to be read a predetermined number of times, that is, if the target image has failed to be read a predetermined number of times, the process proceeds to step S131 and the SPL program 32 ( Is set to the high speed setting value C3) according to the setting information 82, and the process returns to step S104. In step S104, the SPL program 32 (the CPU 21 executing the program) accesses the NAND controller 26 at the access time of the high-speed setting value C3, and repeats the process of reading the target image.

  In this way, the SPL program 32 (the CPU 21 that executes the program) sets the operation limit set value by setting the access time for the NAND controller 26 of the bus controller 25 to the high speed set value C3 that is larger than the operation limit set value C2. The program image can be more reliably read from the NAND flash memory 28 than when operating in C2.

  Even if the access time of the bus controller 25 to the NAND controller 26 is set to the high speed setting value C3 and the reading of the program image fails, the access time of the bus controller 25 to the NAND controller 26 is set to the high speed setting value C3. It is possible to set a larger guaranteed set value C1.

  On the other hand, if it is determined in step S106 that the checksum data match, the SPL program 32 (the CPU 21 executing the program) notifies the control unit 101 that the target image has been successfully read, and step S107. Proceed to

  In step S107, the SPL program 32 (the CPU 21 executing the program) determines whether all program images have been read. In step S107, if the SPL program 32 (the CPU 21 executing the program) determines that there is a program image that has not yet been read, the process returns to step S103 to set the access time of the bus controller 25 to the NAND controller 26 as the operation limit setting value. C2 is set, and the above process is repeated with one of the program images not yet read from the NAND flash memory 28 as the target image.

  On the other hand, if it is determined in step S107 that all program images have been read, that is, if reading of the system program 33 is completed, the process returns to step S55 in FIG.

  If it is determined in step S107 that there is a program image that has not been read yet, the process returns from step S107 to S103, and the SPL program 32 (the CPU 21 executing the program) operates the access time of the bus controller 25 to the NAND controller 26. However, after the access time for the NAND controller 26 is set to the high speed setting value C3 in step S131, the access time for the NAND controller 26 remains at the high speed setting value C3, that is, step S107. From step S104, the reading process can be repeated.

  As described above, according to the information processing system 10 shown in FIG. 1, the CPU 21 uses the access time of the guaranteed set value C <b> 1 set in the bus controller 25 and guaranteed to operate normally according to the specifications of the NAND controller 26. Since the NAND controller 26 is accessed and the checksum data 83 stored in the NAND flash memory 28 is read, the checksum data 83 can be read reliably.

  Further, the bus 27 operates according to the access time of the operation limit setting value C2 smaller than the guaranteed setting value C1 and reads the system program 33 (program image) from the NAND flash memory 28. Therefore, the system program is read from the NAND flash memory 28. The time required for reading 33 can be reduced.

  Further, the SPL program 32 determines whether or not there is an error in the program image read from the NAND flash memory 28 based on the checksum data 83, and the erroneous program image is read from the NAND flash memory 28 again. Since the data is read, the reliability when the program image is read from the NAND flash memory 28 can be improved.

  Furthermore, since the SPL program 32 increases the access time of the bus controller 25 to the NAND controller 26 when there is an error in the program image read from the NAND flash memory 28, it is ensured. The program image stored in the NAND flash memory 28 can be read out.

  As described above, the system program 33 recorded in the low-speed NAND flash memory 28 is read with the bus controller 25 appropriately set for the access time, although it is inexpensive and has a large capacity. The information processing system 10 can be started up at high speed and reliably.

  In the present embodiment, the SPL program 32 is recorded in the NAND flash memory 28, but the SPL program 32 may be stored in the ROM 23. The SPL program 32 may be downloaded from a site via the Internet or the like.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

  Furthermore, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

  In the present embodiment, the system program 33 is recorded in the NAND flash memory 28. However, the recording medium for recording the system program 33 is limited to the NAND flash memory 28. is not. That is, the system program 33 may be recorded in a memory such as a NOR flash memory or a disk such as a hard disk (HDD).

  Furthermore, the present invention can also be applied to reading data other than programs.

It is a block diagram which shows the structural example of one Embodiment of the hardware of the information processing system to which this invention is applied. It is a flow chart for explaining starting processing of an information processing system. It is a figure for demonstrating the memory map of a NAND type flash memory. It is a flowchart for demonstrating the process which produces NAND type flash memory. It is a figure which shows the structural example of a NAND controller. It is a flowchart for demonstrating read-out processing.

Explanation of symbols

  10 information processing system, 21 CPU, 22 ASIC, 23 ROM, 24 RAM, 25 bus controller, 26 NAND controller, 27 bus, 28 NAND flash memory, 31 IPL program, 32 SPL program, 33 system program, 81 division size, 82 setting information, 83 checksum data, 101 control unit, 111 reading unit, 112 checksum operation unit

Claims (7)

In a reading method of reading data from the recording medium by accessing reading means for reading data from the recording medium,
A first setting step of setting an access time for the reading means to a first access time within a guaranteed access time range in which normal operation is guaranteed by the specification of the reading means;
By accessing the reading means with the access time set in the first setting step, check data which is data for error checking of the data recorded in the recording medium is stored in the recording medium. A first reading step for reading from;
A second setting step of setting an access time for the reading means to a second access time larger than the guaranteed access time;
A second reading step of reading the data recorded on the recording medium by accessing the reading means with the access time set in the second setting step;
A determination step of determining whether there is an error in the data read from the recording medium based on the check data;
A reading method comprising: a third reading step of reading again the data having an error from the recording medium by accessing the reading means. A third setting step of setting an access time for the reading means to a third access time smaller than the second access time when there is an error in the data;
In the third reading step, the data recorded on the recording medium is read by accessing the reading means with the access time set in the third setting step. The reading method according to claim 1. The access time for the reading means is set to a third access time that is smaller than the second access time in the third setting step when there are multiple errors in the data. The reading method according to claim 2. In the recording medium, for each divided data obtained by dividing the data into a predetermined divided size, the check data for error check of the divided data is recorded,
In the second reading step, the data is read from the recording medium in units of the divided data,
2. The reading method according to claim 1, wherein in the determination step, it is determined whether or not there is an error in the data in units of the divided data. The reading method according to claim 1, wherein the data recorded on the recording medium is a program. 2. The reading method according to claim 1, wherein the data recorded on the recording medium is a program read by an SPL (Secondary Program Loader) after the electronic device is activated. A program for causing a computer to perform a process of controlling a reading process of reading data from the recording medium by accessing reading means for reading data from the recording medium,
A first setting step of setting an access time for the reading means to a first access time within a guaranteed access time range in which normal operation is guaranteed by the specification of the reading means;
By accessing the reading means with the access time set in the first setting step, check data which is data for error checking of the data recorded in the recording medium is stored in the recording medium. A first reading step for reading from;
A second setting step of setting an access time for the reading means to a second access time larger than the guaranteed access time;
A second reading step of reading the data recorded on the recording medium by accessing the reading means with the access time set in the second setting step;
A determination step of determining whether there is an error in the data read from the recording medium based on the check data;
A program for controlling the reading process including a third reading step of reading again the erroneous data from the recording medium by accessing the reading means.

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