JP2005244599A - Image processor and electronic iquipment including the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor with a small circuit area, low power consumption and high efficiency and to provide an electronic equipment including the processor. <P>SOLUTION: The image processor 100 is provided with a communication controller 30 creating a packet constituted of a header and image data and transmitting it to a network based on prescribed communication specification, a first bus BUS 1 for connecting with a processor 10, a second bus BUS 2 for connecting with the communication controller 30 and a bus switching circuit 40 connected with the first bus BUS1 and the second bus BUS2. The communication controller 30 includes a first DMA (Direct-Memory-Access) controller 36. The first DMA controller 36 directly accesses a memory through the second bus BUS2 and the bus switching circuit 40, reads the header and image data from the memory, connects the header and image data, which are read, and creates the packet. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus and an electronic apparatus including the image processing apparatus.

With the recent development of communication technology, communication modules that transfer image data input from a camera (image sensor) or the like via a communication line or the like have become widespread. In particular, there is a digital image communication device described in Patent Document 1 in which this communication module is combined with a camera. However, this type of digital image communication device is equipped with a plurality of ICs for performing image processing, communication control, and the like, which impedes cost reduction and lowers performance.
JP 2002-540652A

  The present invention has been made in view of the technical problems as described above, and an object thereof is an image processing apparatus having a small circuit area, low power consumption, and high-efficiency image processing. It is providing the electronic device containing.

  The present invention generates a packet composed of a header and image data and sends it to a network based on a given communication standard, a first bus for connecting to a processor, at least the communication controller, A second bus for connection, and a bus switch circuit connected to the first bus and the second bus, and the communication controller includes a first direct-memory-access (DMA) controller The first DMA controller directly accesses the memory via the second bus and the bus switch circuit, reads the header and the image data from the memory, and combines the read header and the image data. The present invention relates to an image processing apparatus that generates the packet.

  According to the present invention, the first DMA controller can read the header and the image data from the memory without going through the processor, so that the load on the processor can be reduced. Further, since the first DMA controller generates a packet from the read header and image data, it is possible to reduce the load on the processor when generating the packet. Furthermore, since the first DMA controller and the processor are independently connected to the first and second buses, the first DMA controller generates packets stably regardless of the bus occupancy rate of the processor. it can. In addition, since the header and image data can be read from the memory without affecting the first bus to which the processor is connected, the performance of the processor can be improved.

  The present invention further includes an image processing controller connected to the second bus and performing image processing on the input image data. The image processing controller includes a second DMA controller, The second DMA controller may write the image data subjected to image processing directly into the memory via the second bus and the bus switch circuit.

  Since the second DMA controller can directly write the image data subjected to the image processing to the memory without going through the processor, the load on the processor can be reduced. Further, since the second DMA controller is connected to the second bus independent of the first bus to which the processor is connected, the image data can be stably stored in the memory regardless of the bus occupation rate of the processor. Can be written directly. Furthermore, since the image data can be written into the memory without affecting the first bus to which the processor is connected, the performance of the processor can be improved.

  In the present invention, the header is generated by the processor so as to correspond to the image data written in the memory, and is written into the memory by the processor via the first bus and the bus switch circuit. May be.

  Thereby, a header necessary for generating a packet can be generated.

  In the present invention, the first DMA controller directly reads out table information associating a header and image data from the memory via the second bus and the bus switch circuit, and reads the table information. Based on the above, the packet may be generated by combining the header and the image data.

  According to the present invention, the table information that associates the header with the image data is stored in the memory, and the first DMA controller can generate a packet by reading the table information. Also, when reading the table information, it is possible to directly read from the memory without going through the processor, so the load on the processor can be reduced.

  In the present invention, the table information may be generated by the processor and written to the memory by the processor via the first bus and the bus switch circuit.

  Thereby, table information can be generated and the table information can be stored in the memory.

  In the present invention, the image processing controller has an interface for connecting an image sensor that outputs image data, and stores one or a plurality of lines of image data input via the interface. You can have a buffer.

  Thereby, the image processing controller can receive image data from the image sensor (imaging device). In addition, since image data for one or a plurality of lines in the received image data can be stored in the line buffer, image processing can be performed on the image data.

  In the present invention, the image processing controller includes an image processing circuit that performs image processing on the data stored in the line buffer. The image processing circuit performs processing for compressing the image data, and decompresses the compressed data. At least one of processing for cutting out, processing for cutting out part of the image data, and processing for reducing the image size of the image data may be performed.

  Also, in the present invention, the second DMA controller stores the data subjected to the image processing by the image processing circuit as the image data constituting the packet in the memory via the second bus and the bus switch circuit. You may make it write directly.

  According to the present invention, since the image data constituting the packet can be directly written in the memory, the load on the processor can be reduced.

  In the present invention, the communication controller, the first bus, the second bus, and the bus switch circuit may be formed on the same chip.

  As a result, an image processing apparatus having a small circuit scale, low power consumption, and excellent cost performance can be realized.

  In the present invention, the communication controller, the image processing controller, the first bus, the second bus, and the bus switch circuit may be formed on the same chip.

  As a result, an image processing apparatus having a small circuit scale, low power consumption, and excellent cost performance can be realized.

  In the present invention, the processor may be formed on the same chip.

  As a result, an image processing apparatus having a small circuit scale, low power consumption, and excellent cost performance can be realized.

  In the present invention, the header and the memory storing the image data may be formed on the same chip.

  As a result, an image processing apparatus having a small circuit scale, low power consumption, and excellent cost performance can be realized.

  In the present invention, the communication controller, the first bus, the second bus, and the bus switch circuit are formed on the same chip, and a memory for storing the table information is provided on the same chip. It may be formed.

  As a result, an image processing apparatus having a small circuit scale, low power consumption, and excellent cost performance can be realized.

  The present invention also relates to an electronic apparatus including the above-described image processing apparatus, the memory, and a network interface.

  Accordingly, an electronic device having a small circuit scale, low power consumption, and excellent cost performance can be provided.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Image Processing Device FIG. 1 is an overall block diagram of an image processing device 100. The image processing apparatus 100 includes a processor 10, an image controller 20, a communication controller 30, a bus switch circuit 40, an internal memory 50, a memory controller 60, a bus BUS1 (first bus in a broad sense), and a bus BUS2 (second in a broad sense). Including bus). In the following drawings, the same symbols have the same meaning.

  Image data is input to the image processing controller 20 by an image sensor 80 (an imaging device in a broad sense). The image sensor 80 is constituted by, for example, a CCD (Charge-Coupled-Device) or a CMOS (Complementary-Metal-Oxide-Semiconductor) sensor. The input image data is subjected to image processing by the image processing controller 20, and is directly written into the external memory 70 via the bus BUS 2, the bus switch circuit 40 and the memory controller 60. As a modification, the image data that has been subjected to image processing may be directly written in the internal memory 50.

  In the present specification, the process in which the image processing controller 20 or the communication controller 30 directly writes (reads) data to or from the internal memory 50 or the external memory 70 accesses the internal memory 50 or the external memory 70 without going through the processor 10 ( Read or write). The same applies to the following.

  The processor 10 generates a header that constitutes a packet to be sent to the network. At this time, the processor 10 generates a header corresponding to the image data subjected to the image processing stored in the internal memory 50 or the external memory 70 and stores the header in the internal memory 50 or the external memory 70. Further, the processor 10 generates table information for linking the generated header and image data, and stores the table information in the internal memory 50 or the external memory 70.

  The communication controller 30 directly reads the table information stored in the internal memory 50 or the external memory 70, and directly reads the header and image data stored in the internal memory 50 or the external memory 70 based on the table information. The communication controller 30 combines the read header and image data to generate a packet, and sends the generated packet to the network interface 90 based on a given communication standard.

  In the present embodiment, the processor 10, the image controller 20, the communication controller 30, the bus switch circuit 40, the internal memory 50, the memory controller 60, the bus BUS1, and the bus BUS2 are on one chip (in the broad sense, on the same chip). However, the present invention is not limited to this. For example, the processor 10 may not be formed on the same chip as the image controller 20 or the like, and the internal memory 50 may not be provided. Further, the memory controller 60 may not be provided, and the size of the internal memory 50 may be increased so that the external memory 70 is not used.

2. Image Processing Controller FIG. 2 is a block diagram showing a detailed example of the image processing controller 20. The image processing controller 20 includes an image processing interface 22 (interface for connecting an imaging device in a broad sense), a line buffer 24, an image processing circuit 26, and an image processing DMA controller (a second DMA controller in a broad sense). ) 28.

  Image data output from the image sensor 80 is input to the image processing interface 22. Here, the image data output from the image sensor 80 is referred to as raw data. Of the image data input to the image processing interface 22, image data for N lines (N is a natural number) lines (for example, image data for 8 lines, or in a broad sense, one or more lines) is stored in the line buffer 24. Is done. Here, image data for one line means horizontal M dots in one vertical direction in image data of one screen (vertical L dots × horizontal M dots, L and M are natural numbers), that is, one horizontal direction. Represents minute image data. The image data for one screen is divided into N-line image data and sequentially output to the line buffer 24.

  The line buffer 24 outputs the stored image data to the image processing circuit 26, and the image data stored in the line buffer 24 is corresponding to the image data sequentially sent from the image processing interface 22. Update sequentially. In the present embodiment, image data of 8 lines is stored in the line buffer 24, but the image data stored in the line buffer 24 may be, for example, 16 lines, or image data for one screen is stored. May be. Image data for N lines stored in the line buffer 24 is subjected to image processing by the image processing circuit 26.

  The image processing circuit 26 performs image compression processing for compressing input image data, image decompression processing for decompressing compressed image data, and input image data for N lines of input image data. It is possible to perform at least one of an image cut-out process for cutting out a portion and an image reduction process for reducing the image size of input image data. In this embodiment, for example, image compression processing can be performed, and in this case, the JPEG compression method can be used as the image compression processing method. As a modification, the image compression processing method of the image processing circuit 26 may be MPEG (for example, MPEG1, MPEG2, MPEG4), H.264, or the like. Other compression methods such as H.264 / MPEG-4AVC method may be used. The image processing circuit 26 performs image processing on the input image data for N lines, and then outputs the image data subjected to the image processing to the image processing DMA controller 28. Hereinafter, the image data that has been subjected to image processing by the image processing circuit 26 is also referred to as image processing data.

  The image processing DMA controller 28 receives the image processing data from the image processing circuit 26 and directly writes the image processing data into the external memory 70 via the bus switch circuit 40 and the memory controller 60. In this embodiment, the image processing data is written in the external memory 70, but the image processing data may be directly written in the internal memory 50. As described above, the operation of directly writing to the internal memory 50 and the external memory 70 here is an operation performed without going through the processor 10, and the word “direct” included in the word “direct writing” does not go through the processor 10. means.

  The image processing DMA controller 28 may divide the image processing data into a predetermined data size and write it directly into the internal memory 50 or the external memory 70.

  When the processor 10 accesses the internal memory 50, an address corresponding to the internal memory 50 is output to the bus BUS1. Further, when the processor 10 accesses the external memory 70, an address corresponding to the external memory 70 is output to the bus BUS1.

  When the image processing controller 20 accesses the internal memory 50, an address corresponding to the internal memory 50 is output to the bus BUS2, and when the image processing controller 20 accesses the external memory 70, it corresponds to the external memory 70. The address is output to the bus BUS2.

  A bus switch circuit (also referred to as a bus multiplexer) 40 connects the internal memory 50 and the memory controller 60 (external memory 70) to the bus BUS1 and bus BUS2 in accordance with the addresses output to the bus BUS1 and bus BUS2. Specifically, when the address output to the bus BUS1 is an address corresponding to the internal memory 50, the bus switch circuit 40 connects the bus BUS1 and the internal memory 50. When the address output to the bus BUS1 is an address corresponding to the external memory 70, the bus switch circuit 40 connects the bus BUS1 and the memory controller 60. Under the control of the memory controller 60, the bus BUS1 is connected to the external memory 70. Similarly, when the address output to the bus BUS2 is an address corresponding to the internal memory 50, the bus BUS2 is connected to the internal memory 50, and the address output to the bus BUS2 is an address corresponding to the external memory 70. The bus BUS2 is connected to the external memory 70 via the memory controller 60.

  As a countermeasure when the bus BUS1 and the bus BUS2 simultaneously access the internal memory 50 or the external memory 70, priority may be set for the bus BUS1 and the bus BUS2, and an arbitration circuit may be provided in the bus switch circuit 40. The arbitration circuit may be provided between the bus switch circuit 40 and the internal memory 50 and between the bus switch circuit 40 and the memory controller 60. Due to the operation of the arbitration circuit, the bus with the higher priority is connected to the internal memory 50 or the external memory 70 first.

  Next, the flow of operations in which the image processing data and the header are stored in the external memory 70 will be described with reference to FIGS.

  When the image processing controller 20 is activated by the processor 10, the raw data input from the image sensor 80 is subjected to image processing by the image processing controller 20. As indicated by reference numeral A1 in FIG. 3, the image data subjected to image processing (image-processed data) is processed by the bus switch circuit 40 and the memory controller 60 by the action of the image processing DMA controller 28 of the image processing controller 20. Is stored in the external memory 70. At this time, the image data stored in the external memory 70 may be divided into a predetermined data size.

  The image processing controller 20 performs image processing on the raw data for one screen for every N lines of image data, and stores the image processing data in the external memory 70. When the image processing data stored in the external memory 70 reaches a certain amount, the processor 10 generates a header, so that a packet to be sent to the network based on the image processing data stored in the external memory 70 Determine the number of. The above-mentioned fixed amount is, for example, the amount of image data for one screen subjected to image processing. That is, in this case, when the image processing data for one screen corresponding to the raw data for one screen is stored in the external memory 70, the processor 10 starts generating a header. In the present embodiment, the above-mentioned fixed amount is not limited to the amount of image data for one screen. For example, the above-mentioned fixed amount may be the amount of image data for n screens (n is a natural number). The amount of image data may be less than one screen, for example, N lines.

  The processor 10 generates a header corresponding to the number of packets, and stores the header in the external memory 70 via the bus switch circuit 40 and the memory controller 60 (see symbol A2 in FIG. 4). As a modification, the header may be stored in the internal memory 50. For example, when the network standard is Ethernet (registered trademark) and the protocol is TCP / IP, the header includes a MAC header, an IP header, and a TCP header.

  After generating the header, the processor 10 generates table information composed of information (Link information) for associating the header and the image processing data stored in the external memory 70, and stores the information in the internal memory 50 via the bus switch circuit 40. Store (see symbol A3 in FIG. 5). As a modification, the processor 10 may store the table information in the external memory 70 via the bus switch circuit 40 and the memory controller 60.

  Note that the image processing interface 22, the line buffer 24, and the image processing circuit 26 may be omitted from the image processing controller 20.

3. Communication Controller FIG. 6 is a block diagram showing a detailed example of the communication controller 30. The communication controller 30 includes a transfer controller 32, a communication buffer 34, and a communication DMA controller (first DMA controller in a broad sense) 36. The transfer controller 32 performs media access control (MAC) on the packet stored in the communication buffer 34 and outputs the packet to the network interface 90 based on a given communication standard. For example, when the communication standard is Ethernet (registered trademark), the transfer controller 32 adds a preamble, SFD (Start-Frame-Delimiter), and FCS (Frame-Check-Sequence) to the packet stored in the communication buffer 34. Is output to the network interface 90.

  The communication buffer 34 stores a packet output from the communication DMA controller 36. When the communication DMA controller 36 receives a signal for activating the communication DMA controller 36 from the processor 10, it directly accesses the internal memory 50 via the bus BUS 2 and the bus switch circuit 40 without going through the processor 10 and stores it. Read the table information. In this embodiment, the table information is stored in the internal memory 50. However, if the table information is stored in the external memory 70 as a modified example, the communication DMA controller 36 directly accesses the external memory 70 and stores the table information. You may read. The communication DMA controller 36 reads out the header and image processing data (image data in a broad sense) stored in the internal memory 50 or the external memory 70 based on the read table information, and reads out the read header and image processing data. To generate a packet. The packet generated by the communication DMA controller 36 is stored in the communication buffer 34.

  Next, a process of generating a packet from the image processing data stored in the internal memory 50 or the external memory 70 will be described with reference to FIGS.

  When receiving a signal for activating the communication DMA controller 36 from the processor 10, the communication DMA controller 36 first directly accesses the internal memory 50 via the bus switch circuit 40. At this time, the communication DMA controller 36 reads the table information stored in the internal memory 50 (see symbol A4 in FIG. 7). The table information includes position information (for example, address) where the header is stored, size information of the header, position information of the image processing data corresponding to the header (image data in a broad sense), and image processing data corresponding to the header. Size information is associated with each other. Details of the table information will be described later.

  After reading the table information, the communication DMA controller 36 accesses the external memory 70 via the bus switch circuit 40 and the memory controller 60. At this time, the communication DMA controller 36 first reads out the header stored in the external memory 70 based on the previously read table information (see symbol A5 in FIG. 8). Since the table information includes position information where the header is stored and header size information, the communication DMA controller 36 can read the header from the external memory 70 based on these information.

  Next, the communication DMA controller 36 reads out the image processing data corresponding to the previously read out header from the external memory 70 based on the table information (see symbol A6 in FIG. 9). Since the table information includes position information and size information regarding the image processing data corresponding to the header, the communication DMA controller 36 can read out the image processing data based on these information. Thereafter, the communication DMA controller 36 generates a packet by combining the read header and the image processing data, and stores the packet in the communication buffer 34. The transfer controller 32 performs medium access control (MAC) on the packet stored in the communication buffer 34 and transfers the packet subjected to the medium access control to the network interface 90. For example, when the communication standard is Ethernet (registered trademark), a preamble, SFD (Start-Frame-Delimiter), and FSC (Frame-Check-Sequence) are added to the packet by medium access control.

  The communication DMA controller 36 repeats the operations shown in FIGS. 7 to 9 until the end code included in the table information is confirmed. The repetition of the above-described operation can be stopped using an interrupt signal (for example, a stop signal) from the processor 10 or the like.

  Note that the transfer controller 32 and the communication buffer 34 may be omitted from the communication controller 30.

4). Packet Configuration and Table Information FIG. 10 is a diagram illustrating a configuration of data transmitted on the network when the communication standard is Ethernet (registered trademark). In the present embodiment, the packet generated by the communication DMA controller 36 corresponds to the MAC header (header in a broad sense) and MAC frame data (portion indicated by reference numeral B1) in FIG. The MAC frame data includes an IP header (header in a broad sense), a TCP header (header in a broad sense), and payload data (image data in a broad sense). The MAC frame data is defined to have a data size of 46 to 1500 bytes, but the present embodiment is not limited to this. A packet composed of a MAC header, an IP header, a TCP header, and payload data is added with a preamble and an SFD (a portion indicated by a symbol B2) and an FCS (a portion indicated by a symbol B3) by the transfer controller 32.

  FIG. 11 is a diagram illustrating a configuration of table information. The table information stored in the internal memory 50 is composed of data as shown in FIG. Reference numeral 52 denotes a part of the memory space of the internal memory 50, and each data (transmission command, packet size, transmission descriptor, transmission buffer address 1 to m and transmission buffer size 1 to m and transmission buffer size 1 to m in FIG. The above natural number) is generated by the processor 10 and stored in the internal memory 50. The transmission command in FIG. 11 is information representing the operation mode of the communication DMA controller 36. By reading this information, the communication DMA controller 36 confirms the operation mode.

  The packet size in FIG. 11 is information representing the data size of a packet to be generated. The communication DMA controller 36 reads the packet size to confirm the data size of the packet to be generated.

  The transmission descriptor (Descriptor) in FIG. 11 is information indicating a location where table information relating to a packet to be generated next to a packet to be generated is stored. The communication DMA controller 36 can shift to preparation for generating the next packet without depending on the processor 10 by reading the transmission descriptor.

  The transmission buffer address 1 in FIG. 11 is information indicating a storage location of data (for example, header and image data) for forming a packet. The communication DMA controller 36 reads the buffer address 1 to confirm the location where the data (for example, header and image data) for configuring the packet is stored.

  The transmission buffer size 1 in FIG. 11 is information indicating the data size of data (for example, header or image data) whose storage location is indicated by the transmission buffer address 1. Based on each transmission buffer address 1, the communication DMA controller 36 confirms the storage location of each data for composing the packet, and reads data for the data size specified by the transmission buffer size 1.

  The transmission buffer addresses 2 to m and the transmission buffer sizes 2 to m operate in the same manner as the transmission buffer address 1 and the transmission buffer size 1 described above. It is sufficient to prepare m as many as the number of types of data (for example, header and image data) for configuring a packet. When the communication standard is Ethernet (registered trademark), the packet can be composed of four types of data, that is, a MAC header, an IP header, a TCP header, and payload data.

  FIG. 12 is a diagram showing the relationship between table information and each piece of data (for example, header and image data) for configuring a packet. Reference numerals 72 to 78 denote a part of the memory space of the external memory 70. When the communication standard is, for example, Ethernet (registered trademark), four types of data including a MAC header, an IP header, a TCP header, and payload data are generated by the processor 10 and stored in the internal memory 50. For example, the processor 10 stores the MAC header in the memory space 72, the IP header in the memory space 74, the TCP header in the memory space 76, and the payload data in the memory space 78. The processor 10 includes the storage location and data size of the header (MAC header, IP header, TCP header) and image data (payload data) in the table information and stores them in the internal memory 50. At this time, the processor 10 stores the storage location of the MAC header as the transmission buffer address 1 in the memory space 52 and stores the data size of the MAC header as the transmission buffer size 1 in the memory space 52. That is, the transmission buffer address 1 is information indicating the storage location of the MAC header (see reference numeral C1 in FIG. 12).

  Further, the processor 10 stores the IP header storage location as the transmission buffer address 2 in the memory space 52 and stores the IP header data size as the transmission buffer size 1 in the memory space 52. That is, the transmission buffer address 2 is information indicating the storage location of the IP header (see reference numeral C2 in FIG. 12).

  Further, the processor 10 stores the TCP header storage location in the memory space 52 as the transmission buffer address 3, and stores the data size of the TCP header in the memory space 52 as the transmission buffer size 3. That is, the transmission buffer address 3 is information indicating the storage location of the TCP header (see reference numeral C3 in FIG. 12).

  Further, the processor 10 stores the storage location of the payload data in the memory space 52 as the transmission buffer address 4, and stores the data size of the payload data in the memory space 52 as the transmission buffer size 4. That is, the transmission buffer address 4 is information indicating the storage location of the payload data (see reference numeral C4 in FIG. 12).

  FIG. 13 is a diagram showing the relationship between table information corresponding to each packet. For simplification of description, FIG. 13 shows table information corresponding to three packets, but the present invention is not limited to this. In FIG. 13, table information 1 is table information corresponding to the first packet, and table information 2 and 3 are table information corresponding to the second packet and the third packet, respectively.

  In the transmission descriptor of the table information 1, information indicating the storage location of the table information 2 is stored. That is, the communication DMA controller 36 can check the storage location of the table information 2 for generating the second packet by reading the information stored in the transmission descriptor of the table information 1, and does not depend on the processor 10. Table information 2 can be read out.

  Information indicating the storage location of the table information 3 is stored in the transmission descriptor of the table information 2. Since the communication DMA controller 36 can confirm the storage location of the table information 3 without depending on the processor 10 as described above, the communication DMA controller 36 can generate the third packet without depending on the processor 10.

  In FIG. 13, an end code (for example, blank information, Null) is stored in the transmission descriptor of the table information 3. When reading the end code, the communication DMA controller 36 confirms that the table information at that time is the final table information. That is, the communication DMA controller 36 can confirm the final table information without depending on the processor 10. That is, when receiving the enable signal from the processor 10, the communication DMA controller 36 can send a certain amount of image data to the network interface 90, thereby reducing the load on the processor 10.

  Although the end code is stored in the transmission descriptor of the table information 3 in FIG. 13, the present invention is not limited to this. The end code may be stored in the transmission descriptor of the table information corresponding to the last packet.

  The communication controller 30 can also receive data from the network interface 90. When data is received from the network interface 90, the medium access control is performed by the transfer controller 32, and the data (received packet) subjected to the medium access control is stored in the communication buffer 34. When the communication standard is Ethernet (registered trademark), the data stored in the communication buffer 34 includes a MAC header, an IP header, a TCP header, and payload data (for example, application data). Here, the application data includes, for example, data for controlling the image processing apparatus 100 from the network.

  The processor 10 generates reception table information in advance and stores it in the internal memory 50. As a modification, the processor 10 may store the reception table information in the external memory 70. FIG. 14 is a diagram illustrating a configuration of reception table information. Each data (reception command, packet size, reception descriptor, reception buffer address 1 to m, reception buffer size 1 to m) shown in FIG. 14 is the same as each data of the table information shown in FIG. Work. However, there is a difference between the table information in FIG. 11 and the reception table information in FIG. 14, whether the target data of the table information or the reception table information is reception data or transmission data. For example, the reception command is information indicating the operation mode of the communication DMA controller 36, and the packet size in FIG. 16 is information indicating the data size of the reception packet. The reception descriptor is information indicating a storage location of reception table information regarding a reception packet to be read next. The reception buffer addresses 1 to m and the reception buffer sizes 1 to m are information indicating the storage destination and data size of each data constituting the reception packet. When the communication standard is, for example, Ethernet (registered trademark), m is 4 as in FIG.

  FIG. 15 shows reception table information when the communication standard is Ethernet (registered trademark), and each data (MAC header, IP header, TCP header, payload data) constituting a packet stored in the communication buffer 34. It is a figure which shows the correspondence of these. The communication DMA controller 36 reads each data (MAC header, IP header, TCP header, payload data) from the packet stored in the communication buffer 34 based on the reception table information. The communication DMA controller 36 stores the read data (MAC header, IP header, TCP header, payload data) in the external memory 70. As a modification, the communication DMA controller 36 may store the read data (MAC header, IP header, TCP header, payload data) in the internal memory 50.

  The communication DMA controller 36 reads the reception buffer address 1 included in the reception table information to confirm the storage location of the MAC header, and reads the reception buffer size 1 to confirm the data size of the MAC header. After confirming the MAC header storage location and data size, the communication DMA controller 36 stores the MAC header included in the packet stored in the communication buffer 34 in the memory space 72 of the external memory 70 (reference numeral in FIG. 15). D1).

  The same operation as described above is performed by the communication DMA controller 36 for the IP header, TCP header, and payload data. The reception buffer address 2 indicates the storage location (memory space 74) of the IP header (see symbol D2 in FIG. 15), and the reception buffer address 3 indicates the storage location (memory space 76) of the TCP header (see reference symbol D3 in FIG. 15). ), The reception buffer address 4 indicates the storage location (memory space 78) of the payload data (see reference numeral D4 in FIG. 15).

  FIG. 16 is a diagram showing the relationship between each reception table information corresponding to each reception packet. FIG. 16 shows reception table information corresponding to three reception packets for the sake of simplicity. Table information 4 to 6 in FIG. 16 is reception table information corresponding to the first to third received packets. The communication DMA controller 36 reads the reception descriptor of the table information 4 to confirm the storage location of the reception table information (that is, the table information 5) regarding the reception packet to be processed next. Further, by reading the reception descriptor of the table information 5, the storage location of the reception table information (that is, the table information 6) regarding the reception packet to be processed next is confirmed. Further, the communication DMA controller 36 reads the reception descriptor of the table information 6. For example, when an end code (for example, blank information, Null) is stored in the reception descriptor, the communication DMA controller 36 confirms that the current reception table information is the final reception table information.

  That is, due to the operation of the communication DMA controller 36, each data (for example, a MAC header, an IP header, a TCP header, a payload) included in a received packet in the external memory 70 (or the internal memory 50) without depending on the processor 10 Data) can be stored. This means that the load on the processor 10 is reduced.

5). Electronic Device Including Image Processing Device FIG. 17 is a block diagram of a network camera 200 (electronic device including the image processing device 100 in a broad sense). The network camera 200 is an electronic device that can send an image input by the image sensor 80 over a network.

  For example, when a command (for example, a command for requesting image transmission) is transmitted from a terminal on the network to the network camera 200 via the network, the network camera 200 receives the command. For example, when the received command is a command for requesting image transmission, the network camera 200 performs image processing on the image data input from the image sensor 80 based on the received command, and the terminal receives the terminal via the network. Send image data to. For example, when the network camera 200 is installed in a remote place, image data in the remote place can be received via the network by remotely operating the network camera 200.

  Since the network camera 200 includes the image processing apparatus 100 of the present embodiment, the network camera 200 includes a small number of components as shown in FIG. As a result, a small network camera can be manufactured, power consumption can be reduced, and the manufacturing cost can be reduced. Further, since the image processing apparatus 100 can be manufactured on the same chip, more effective manufacturing cost reduction, low power consumption, and downsizing of the main body are possible.

  In FIG. 17, the external memory 70 is provided outside the image processing apparatus 100, but the external memory 70 may be provided inside the image processing apparatus 100 as a modified example.

6). FIG. 18 is an overall block diagram of a network camera 300 that is a comparative example according to the present embodiment. The network camera 300 of the comparative example includes an image sensor 80, a network interface 90, a CPU 310, a JPEG encoder 320, RAMs 330 and 350, a ROM 340 and a network controller 360. The CPU 310, the JPEG encoder 320, the RAMs 330 and 350, the ROM 340, and the network controller 360 are each configured by an independent IC or the like, and the CPU 310, the JPEG encoder 320, the ROM 340, the RAM 350, and the network controller 360 are connected to the common bus BUS3.

  The network camera 300 compresses the image data input from the image sensor 80 by the JPEG encoder 320 one after another. The image data that has been compressed by the JPEG encoder 320 is temporarily stored in the RAM 330. The CPU 310 reads the image data stored in the RAM 330 and generates a packet from the read image data according to the network protocol. CPU 310 temporarily stores the generated packet in RAM 350. The CPU 310 reads the packet stored in the RAM 350 and outputs it to the network controller 360. The network controller 360 outputs the input packet to the network interface 90 based on a given communication standard. The ROM 340 stores firmware (program) and the like.

  From the above description, the CPU 310 frequently repeats the operation until the image data output by the image sensor 80 is converted into data output to the network interface 90. That is, the network camera 300 of the comparative example requires a high processing capability from the CPU 310, and requires a large storage area capacity for temporarily storing image data and the like. As a result, the circuit scale increases, resulting in an increase in manufacturing cost and power consumption. Furthermore, in the network camera 300, since the CPU 310 frequently accesses the RAMs 330 and 350, the occupancy rate of the common bus BUS3 increases, and it is difficult to process large-capacity image data (high-quality image data).

  However, since the network camera 200 of the present embodiment uses the image processing apparatus 100, all of the above-described problems can be solved. Since the image processing apparatus 100 includes the image processing DMA controller 28 and the communication DMA controller 36, the line buffer 24 of the image processing apparatus 100 does not require a large-capacity storage area. That is, the image processing apparatus 100 does not require the RAM 330 that requires a large storage area in the network camera 300.

  The image processing apparatus 100 includes a bus BUS2 that is independent from the bus BUS1 connected to the processor 10, and the image processing DMA controller 28 and the communication DMA controller 36 are connected to the bus BUS2. Therefore, the processor 10 can perform processing efficiently without being significantly affected by the operations of the image processing DMA controller 28 and the communication DMA controller 36.

  Further, the image processing apparatus 100 includes the image processing DMA controller 28 and the communication DMA controller 36, so that the processor 10, the image processing controller 20, the communication controller 30, and the internal memory 50 can be formed on the same chip. Can be produced, and the production cost can be greatly reduced.

  In the comparative example, since the CPU 310 generates a packet, a load is applied to the CPU 310 each time a packet is generated. However, the table information (or reception table information) according to the present embodiment includes a transmission descriptor (or reception descriptor). The communication DMA controller 36 can check the storage location of the header and image data for generating the next packet by reading this transmission descriptor (or reception descriptor), so the packets are continuously transmitted regardless of the processor 10. Can be generated. That is, the processor 10 sends one processing instruction to the communication DMA controller 36, so that the communication DMA controller 36 can generate a plurality of packets (for example, packets corresponding to one screen of image data). Thereby, the load concerning the processor 10 can be reduced significantly.

  The present invention is not limited to the one described in the above embodiment, and various modifications can be made. For example, terms cited as broad or synonymous terms in the description in the specification or drawings can be replaced with broad or synonymous terms in other descriptions in the specification or drawings.

1 is an overall block diagram of an image processing apparatus according to an embodiment. It is a block diagram which shows the image processing controller concerning this embodiment. The figure explaining the flow of operation | movement in which the image-processing data concerning this embodiment and a header are stored in an external memory. The other figure explaining the flow of operation | movement in which the image-processing data concerning this embodiment and a header are stored in an external memory. The other figure explaining the flow of operation | movement in which the image-processing data concerning this embodiment and a header are stored in an external memory. The block diagram which shows the structure of a communication controller. The figure explaining the process which produces | generates a packet from the image-processing data stored in the internal memory or external memory concerning this embodiment. FIG. 6 is another diagram for explaining a process of generating a packet from image processing data stored in the internal memory or the external memory according to the present embodiment. FIG. 6 is another diagram for explaining a process of generating a packet from image processing data stored in the internal memory or the external memory according to the present embodiment. The figure which shows the structure of the data transmitted on a network in case this embodiment is a communication standard Ethernet (trademark). The figure which shows the structure of the table information concerning this embodiment. The figure which shows the relationship between the table information concerning this embodiment, and each data for comprising a packet. The figure which shows the relationship of each table information corresponding to each packet concerning this embodiment. The figure which shows the structure of the table information for reception concerning this embodiment. The figure which shows the correspondence of the table information for reception in case this communication standard is Ethernet (trademark), and each data which comprises the packet stored in the buffer for communication in this embodiment. The figure which shows the relationship of each table information for reception corresponding to each received packet concerning this embodiment. 1 is a block diagram of an electronic apparatus including an image processing apparatus according to an embodiment. The block diagram which shows the comparative example concerning this embodiment.

Explanation of symbols

10 processor, 20 image processing controller, 22 image processing interface,
24 line buffer, 26 image processing circuit,
28 Image processing DMA controller (second DMA controller),
30 communication controller, 32 transfer controller, 34 communication buffer,
36 communication DMA controller (first DMA controller),
40 bus switch circuit, 50 internal memory, 52 memory space,
60 memory controller, 70 external memory, 80 image sensor,
90 network interface, 100 image processing device,
200 network camera (electronic device including the image processing apparatus 100),
300 network camera, 310 CPU, 320 JPEG encoder 330 memory, 340 ROM, 350 memory, 360 network controller BUS1 first bus, BUS2 second bus, BUS3 common bus

Claims (14)

A communication controller that generates a packet composed of a header and image data and sends the packet to a network based on a given communication standard;
A first bus for connecting to the processor;
A second bus for connecting to at least the communication controller;
A bus switch circuit connected to the first bus and the second bus,
The communication controller includes a first DMA (Direct-Memory-Access) controller,
The first DMA controller directly accesses a memory via the second bus and the bus switch circuit, reads a header and image data from the memory, combines the read header and image data, and An image processing apparatus that generates a packet. In claim 1,
An image processing controller connected to the second bus and performing image processing on the input image data;
The image processing controller includes a second DMA controller;
The image processing apparatus, wherein the second DMA controller directly writes image data subjected to image processing to the memory via the second bus and the bus switch circuit. In claim 2,
The header is generated by the processor so as to correspond to the image data written in the memory, and is written into the memory by the processor via the first bus and the bus switch circuit. Image processing device. The first DMA controller according to any one of claims 1 to 3, wherein the first DMA controller directly reads out and reads table information that associates a header and image data from the memory via the second bus and the bus switch circuit. An image processing apparatus that combines the header and image data to generate the packet based on the table information. In claim 4,
The image processing apparatus, wherein the table information is generated by the processor and written to the memory by the processor via the first bus and the bus switch circuit. In claim 4 or 5,
The image processing controller has an interface for connecting an image sensor that outputs image data, and has a line buffer that stores image data for one or a plurality of lines input via the interface. An image processing apparatus. In claim 6,
The image processing controller includes an image processing circuit that performs image processing on data stored in the line buffer;
The image processing circuit performs at least one of processing for compressing image data, processing for expanding compressed data, processing for cutting out part of image data, and processing for reducing the image size of image data. An image processing apparatus. In claim 7,
The second DMA controller directly writes the data subjected to image processing by the image processing circuit as image data constituting the packet into the memory via the second bus and the bus switch circuit. An image processing apparatus. In any one of Claims 1 thru | or 8.
The image processing apparatus, wherein the communication controller, the first bus, the second bus, and the bus switch circuit are formed on the same chip. In any of claims 2 to 8,
The image processing apparatus, wherein the communication controller, the image processing controller, the first bus, the second bus, and the bus switch circuit are formed on the same chip. In claim 9 or 10,
Further, the image processing apparatus is characterized in that the processors are formed on the same chip. In any of claims 9 to 11,
An image processing apparatus, wherein the header and the memory storing the image data are formed on the same chip. In any of claims 4 to 8,
The communication controller, the first bus, the second bus, and the bus switch circuit are formed on the same chip, and a memory for storing the table information is formed on the same chip. A featured image processing apparatus.   An electronic apparatus comprising: the image processing apparatus according to claim 1; the memory; and a network interface.

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