JP2005243117A - Nonvolatile semiconductor storage device and its data erasing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device and its data erasing method with which the erasing time can be shortened. <P>SOLUTION: The data erasing method for the nonvolatile semiconductor storage device has a plurality of blocks BLK consisting of a plurality of electrically rewritable memory cells and can erase the data on a block by block basis. This data erasing method is equipped with following processes. A block group to which the block to be erased belongs is detected among the plurality of block groups SCT consisting of the plurality of blocks. Within the block group to which the block to be erased belongs, the block to be erased is detected. The data for the memory cell inside the detected block to be erased is erased. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a data erasing method of a nonvolatile semiconductor memory device, for example.

  A memory cell array of a flash type EEPROM (electrically erasable programmable read only memory) is divided into blocks each composed of a plurality of memory cells, and information stored in one or more specified memory cells is stored in one block. It is possible to erase at one time by one erase command (multi-block erase). Each block is specified, for example, by combining the same value of several upper bits of the memory cell address into one block.

  FIG. 10 is a block diagram of a conventional flash EEPROM (hereinafter referred to as flash memory) 101, and FIG. 11 is a flowchart of the erasing process of FIG. In this example, the memory cell array MCA is divided into 256 blocks BLK0 to BLK255. First, the block erase command and the address of one or more blocks to be erased are input to the flash memory (step S101). Next, among the block selection registers S0 to S255 provided corresponding to the respective blocks BLK0 to BLK255, all of the blocks corresponding to the erase target block BLK are set (step S102). Next, the value n of the counter inside the write / erase (W / E) control circuit 103 is set to 0 (step S103). Next, the write / erase control circuit 103 determines whether or not the block erase selection register S0 is set (step S104). If it is not set, it is determined whether or not the current scan target block is the last block (step S105), the value n is set to n + 1 (step S106), and the process proceeds to step S104.

  When the set erase target block BLK is detected as a result of repeating the above operations, the write / erase control circuit 102 performs an erase operation on the erase target block BLK (step S107). Next, when the block BLK to be scanned is not the final one, Steps S104 to S107 are repeated, and after all the blocks BLK have been scanned, the erasing process is completed.

  In the case of multi-block erasure, after detecting and erasing the erasure target block BLK, it is unknown whether or not there is a further erasure target block BLK. Therefore, when only one block of 256 blocks is erased as illustrated, the operation of scanning the remaining 255 blocks BLK is wasted time. As a result, this method cannot reduce the time required for the erase operation. Further, since the number of blocks is increased as the capacity of the flash memory is increased, there arises a problem that the erasing time is increased.

Prior art document information related to the invention of this application includes the following.
JP 7-98991 A Japanese Patent Laid-Open No. 6-131889

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing the erasing time and a data erasing method thereof.

  A nonvolatile semiconductor memory device data erasing method according to a first aspect of the present invention includes a plurality of blocks each including a plurality of electrically rewritable memory cells, and the data can be erased for each of the blocks. A method for erasing data in a volatile semiconductor memory device, comprising: detecting a block group to which an erasure target block belongs among a plurality of block groups composed of a plurality of the blocks; Then, the method includes a step of detecting the block to be erased and a step of erasing data of the memory cell in the detected block to be erased.

  A non-volatile semiconductor memory device according to a second aspect of the present invention corresponds to a plurality of blocks each including a plurality of electrically rewritable memory cells, and to each of the plurality of blocks and to the block to be erased A plurality of first registers, each of which is associated with a block group composed of a predetermined number of the blocks, and set corresponding to the inclusion of the block to be erased, A plurality of second registers and a set of the plurality of second registers are detected, and set from the first register corresponding to the block group belonging to the block group corresponding to the detected second register Is detected, and the data of the memory cell in the block corresponding to the detected first register is erased. , Characterized by comprising, an erase control circuit.

  Further, the embodiments of the present invention include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, when an invention is extracted by omitting some constituent elements from all the constituent elements shown in the embodiment, when the extracted invention is carried out, the omitted part is appropriately supplemented by a well-known common technique. It is what is said.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device with a short erasing time and a data erasing method thereof.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 1 is a block diagram schematically showing a configuration of a main part related to data erasure of the nonvolatile semiconductor memory device (flash memory) 1 according to the first embodiment of the present invention. As shown in FIG. 1, the command decoder 2 is supplied with an address signal Add, a data signal Data, a control signal / CE, and a write enable signal / WE from outside the flash memory. The command decoder 2 decodes the data signal Data according to the control signal / CE, the write enable signal / WE, and the like, and controls the write / erase control circuit 3 according to the decoded control content. Reference numeral 12 will be described in the second embodiment.

  The memory cell array MCA has a plurality of flash memory cells. Each memory cell (not shown) is nonvolatile and information can be rewritten and erased by electrical control. Each memory cell includes a floating gate electrode provided on the first gate insulating film on the semiconductor substrate, a control gate electrode provided on the second gate insulating film on the floating gate electrode, and a channel below the floating gate electrode. A source / drain diffusion layer formed on the surface of the semiconductor substrate so as to sandwich the region is provided. One end (drain) of each memory cell is connected to a bit line (not shown).

  The memory cell array MCA is divided into a plurality of blocks in accordance with addresses that can uniquely identify memory cells. In the figure, an example in which the block is divided into 256 blocks BLK (BLK0 to BLK255) is shown. In the case of this example, for example, memory cells having the same upper 8 bits of the memory cell address belong to one block BLK. The flash memory 1 is configured so that data in all memory cells included in the block BLK can be erased collectively in units of blocks.

  Memory cell array MCA is further divided into sectors (block groups) SCT (SCT0 to SCT7) including a plurality of blocks BLK. The sectors SCT0 to SCT7 are used as search units when detecting the block BLK to be erased, as will be described later. The number of blocks BLK constituting one sector SCT is determined according to the total number of blocks BLK so that the block BLK to be erased can be detected most efficiently by a method described later. In the example of the present embodiment, one sector SCT is constituted by 32 blocks BLK, and the total number of sectors SCT is eight. In this case, for example, each sector SCT can be specified by referring to the upper 3 bits of the memory cell address. Note that such a division method is merely an example, and the present invention is not limited to this form.

  The write / erase control circuit 3 has a function of writing or erasing data with respect to a memory cell at a specified address under the control of the command decoder 2. Typically, it includes a substrate potential control circuit, a program voltage generation circuit, a column decoder, a row decoder, and the like. The other end (source) of each memory cell is connected to a substrate potential control circuit. The row decoder and the column decoder control connection between a target memory cell, a substrate potential control circuit, and a program voltage generation circuit. Data is written or erased by applying a program voltage or an erase voltage to the target memory cell by the substrate potential control circuit and the program voltage generation circuit.

  The flash memory 1 has a block selection register group 4 and a sector selection register group 5. The block selection register group 4 is composed of a plurality of block selection registers BS0 to BS255, which is the same number as the number of blocks BLK. Each block selection register BS0 to BS255 is provided for each of the blocks BLK0 to BLK255, and is set when the corresponding block BLK is an erasure target, thereby holding information to that effect.

  The sector selection register group 5 is composed of a plurality of sector selection registers SS having the same number as the number of sectors SCT. According to the above-described example, the sector selection register group 5 is composed of eight sector selection registers SS0 to SS7. Each sector selection register SS0 to SS7 is provided for each of the sectors SCT0 to SCT7, and is set when any block BLK in the corresponding sector SCT is designated as an erasure target, thereby erasing the target block BLK. The information that it contains is held.

  Note that the flash memory includes circuits necessary for reading data in addition to the above-described units.

  FIG. 2 is a block diagram schematically showing a configuration of a main part of the write / erase control circuit 3 of FIG. As shown in FIG. 2, the write / erase control circuit 3 includes counters C1 and C2, a comparison / determination unit 31, a control unit 32, and a write / erase control unit 33. The write / control unit 33 includes a substrate potential control circuit, a program voltage generation circuit, and the like that are directly involved in erasing and writing data.

  The counter C1 can count up to at least the same number as the block selection registers BS0 to BS255. While the value held by the counter C1 is sequentially incremented, the comparison / determination unit 31 sequentially checks whether or not the block selection register BS having the same rank as that value is set, thereby setting the block selection register BS being set. Is detected.

  The counter C2 can count up to at least the same number as the sector selection registers SS0 to SS7. While the values held by the counter C2 are sequentially incremented, the comparison / determination unit 31 sequentially checks whether or not the sector selection registers SS having the same rank as the values are set, thereby setting the sector selection registers SS set. Is detected.

  The control unit 32 controls the increments of the counters C <b> 1 and C <b> 2, the comparison determination unit 31, and the writing / control unit 33 in accordance with the control of the command decoder 2.

  Next, the erase operation of the flash memory according to the first embodiment will be described with reference to FIGS. FIG. 3 shows a timing chart of the overall operation of the erasing process. As shown in FIG. 3, an erase command composed of a plurality of data signals is switched to the erase mode when the control signals / CE and / WE (/ indicates negative logic, the same applies hereinafter) are taken during the low level. Transition. Next, an erase operation is performed on the block to be erased by sequentially inputting one or more addresses of the block to be erased.

  FIG. 4 is a flowchart showing the erase process of the flash memory according to the first embodiment of the present invention. As shown in FIG. 4, an erase command composed of a plurality of data signals and addresses of one or more erase target blocks BLK are supplied to the command decoder 2 (step S1). Next, the command decoder 2 analyzes the address of the erasure target block BLK, sets the block selection register BS corresponding to the erasure target block BLK, and sets the sector selection register SS corresponding to the sector SCT to which the erasure target block BLK belongs. Set (step S2). When the block selection register SS is set, in this example, the memory cell array MCA is divided into 256 blocks BLK0 to BLK255, so that the block BLK to be erased is identified by reading the upper 8 bits of the address, for example. . Similarly, in this example, since the block BLK is divided into eight sectors SCT0 to SCT7, for example, by reading the upper 3 bits of the address, to which sector SCT the block BLK to be erased belongs. Identified.

  Next, the write / erase control circuit 2 sets the value n of the counter C1 and the value m of the counter C2 to 0 (step S3). The write / erase control circuit 3 first scans the sector selection registers SS0 to SS7 to detect the sector SCT to which the erase target block BLK belongs. That is, under the control of the control unit 32, the comparison determination unit 31 determines whether or not the sector selection register SSn is set using the value n of the counter C1 (step S4). If it is not set, it is next determined whether the sector subjected to the comparison determination is the final sector, that is, whether n = 7 in this example (step S5). If it is not the last sector, the control unit 32 increments the value n of the counter C1 to n + 1 (step S6), and then proceeds to step S4. The control unit 32 continues to scan the sector selection register SS, and repeats the processing from step S4 to step S6 until the set sector selection register SS is detected. After detecting the set sector selection register SS, the process proceeds to step S7.

  The control unit 32 detects the erasure target block BLK by scanning the block selection register BS corresponding to the block BLK in the sector SCT to which the erasure target block BLK belongs. That is, first, in accordance with the control of the control unit 32, the comparison / determination unit 31 uses the value m of the counter C2 to determine whether or not the first block selection register BS in the target sector SCT is set (step S7). . If the block selection register BLK to be scanned is not set, it is determined whether this block BLK is the last block BLK in the sector SCT being scanned, that is, whether m = 31 in this example. Performed (step S8). If it is not the final block BLK, the control unit 32 increments the value m of the counter C2 to m + 1 (step S9), and then proceeds to step S7. The control unit 32 continues scanning the block selection register group 4 in the sector to be scanned, and repeats the processing from step S7 to step S9 until the set block selection register BS is detected.

  When the scan by the control unit 32 reaches the block BLK to be erased, the write / erase control unit 33 performs an erase operation on the block BLK according to the control of the control unit 32 (step S10). Thereafter, in step S8, it is determined whether or not the erased block BLK is the last block BLK in the sector being scanned. If it is the final block BLK, the control unit 32 proceeds to step S5.

  In step S5, it is determined whether or not the last sector SCT to be scanned is the last sector SCT. As a result, if it is not the last sector SCT, the control unit 32 performs a process for detecting the next sector SCT to which the erase target block BLK belongs in steps S4 to S6. When a further sector SCT to which the erasure target block BLK belongs is detected, steps S7 to S9 are repeated, and the erasure target block BLK is detected and erased.

  The above operation is repeated, and if the sector SCT to be scanned is the last sector SCT in step S5, the process ends.

  According to the nonvolatile semiconductor memory device of the first embodiment of the present invention, the sector SCT to which the block BLK to be erased belongs is detected as the first stage, and the erase target in the detected sector SCT as the subsequent second stage. Blocks BLK are detected. Also, the sector SCT that does not include the erasure target block BLK is excluded from the block scan target in the second stage. For this reason, it is possible to reduce the time for finding the erasure target block BLK, compared to the method of searching all the blocks BLK and finding the erasure target block BLK.

  The above advantages will be described, for example, when 256 blocks BLK0 to BLK255 are divided into 32 sectors SCT0 to SCT7 composed of 8 blocks BLK. When the erasure target is one block, if all the blocks BLK are scanned as in the prior art, the scan operation is performed 256 times. On the other hand, according to the first embodiment, the sector is scanned 32 times, and the block BLK is scanned 8 times in the sector SCT to which the block to be erased BLK belongs. Therefore, one erasure target block can be detected from 256 blocks by 32 + 8 = 40 scans at the maximum.

(Second Embodiment)
In the second embodiment, the number of blocks BLK constituting one sector SCT is set according to how many erase target blocks BLK are designated.

  A nonvolatile semiconductor memory device according to the second embodiment will be described below with reference to FIGS. FIG. 5 is a block diagram schematically showing main parts of the command decoder 12 of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. As shown in FIG. 5, the command decoder 12 includes a decoder unit 41, a counter C3, a register R1, and a processing unit 42. The decoder unit 41 performs a normal decoder operation. The counter C3 counts the number of erase target blocks BLK designated by one erase command. The register R1 stores the value of the counter C3 when the input of the erase command including the designation of the erase target block is completed. The processing unit 42 determines how many sectors SCT to divide all the blocks BLK0 to BLK255 according to the value of the counter C3. Taking the case where the total number of blocks BLK is 256 as an example, if there are 16 blocks BLK to be erased, the blocks BLK0 to BLK255 are divided into 16 sectors SCT. If the number of blocks BLK to be erased is 17 to 64, the blocks BLK0 to BLK255 are divided into 8 sectors SCT. Further, when the number of blocks BLK to be erased is 65 or more, the blocks BLK0 to BLK255 are not divided into sectors.

  The processing unit 42 also sets the sector selection register SS that is associated with the sector SCT to which the block to be erased BLK belongs in consideration of the previously determined number of sectors SCT. In this case, the processing unit 42 determines which sector SCT the erasure target block BLK belongs to by observing a bit string having the number of digits corresponding to the number of sectors SCT. That is, for example, when the number of sectors SCT is 16, it is specified which sector selection register SS should be set by referring to the upper 4 bits of the address. Similarly, when the number of sectors SCT is 8, the upper 3 bits of the address are referred to.

  The processing unit 42 further supplies the write / erase control circuit 3 with information on how many blocks BLK each sector SCT is composed of.

  The write / erase control circuit 3 first detects the sector SCT to which the erase target block BLK belongs by the same process as in the first embodiment, based on the number of blocks BLK constituting each sector SCT. Next, when the write / erase control circuit 3 detects the sector SCT to which the erase target block BLK belongs, the write / erase control circuit 3 detects the erase target block BLK by scanning the block BLK in the sector SCT and holds the memory cell in the block BLK. Delete the data to be used. After all the blocks BLK in the sector SCT to which the erasure target block BLK belongs are scanned, detection of the next sector SCT to which the further erasure target block BLK belongs, detection of the erasure target block BLK, and data erasure are sequentially performed.

  FIG. 6 is a flowchart showing the erase process of the flash memory according to the second embodiment of the present invention. As shown in FIG. 6, after step S1, the flash memory determines the number of sectors SCT according to the number of blocks to be erased BLK in step S21. The subsequent operations are the same as those in the first embodiment except that the values used for the determinations in step S5 and step S8 are different. That is, in step S5, the number of sectors determined in step S11 is stored in, for example, a register in the write / erase control circuit 3, and the value is compared with the value n of the counter C1. Similarly, in step S8, the number of blocks BLK determined according to the number of sectors is stored in a register or the like in the write / erase control circuit 3, and the value is compared with the value m of the counter C2. .

  According to the nonvolatile semiconductor memory device in accordance with the second embodiment of the present invention, when the erase target block BLK is scanned, the number of sectors SCT is determined according to the number of erase target blocks BLK. Thereafter, the sector SCT to which the erase target block BLK belongs and the erase target block BLK in the sector SCT are detected by the same process as in the first embodiment. For this reason, the same effect as the first embodiment can be obtained. Furthermore, according to the second embodiment, when there are a large number of blocks to be erased BLK, the number of sectors decreases according to the number. For this reason, especially when there are a large number of erasure target blocks BLK and they are distributed over all the blocks BLK, the time for detecting the erasure target block BLK can be reduced by reducing the time for scanning the sector SCT. .

(Third embodiment)
In the third embodiment, unlike the first embodiment and the second embodiment, the block selection register group 4 is scanned while referring to the address of the erase target block BLK.

  FIG. 7 is a block diagram schematically showing a configuration of a main part relating to data erasure of the nonvolatile semiconductor memory device according to the third embodiment of the present invention. As shown in FIG. 7, the flash memory 11 includes a command decoder 22, a write / erase control circuit 23, a block selection register group 4, and a memory cell array MCA. The command decoder 22 sets the block selection register BS associated with the erase target block BLK and supplies the address of the erase target block BLK to the write / erase control circuit 23. The write / erase control circuit 23 temporarily stores the address of the erase target block BLK in its internal register or the like. Next, the write / erase control circuit 23 detects the set block selection register BS from the block selection register group 4 while sequentially narrowing the range of the block selection register 4 to be scanned using this address.

  FIG. 8 is a block diagram schematically showing the configuration of the main part of the write / erase control circuit 23. As shown in FIG. 8, the write / erase control circuit 23 includes a register R 2, an inspection unit 51, a control unit 52, and a write / erase control unit 33. The register R2 stores the address of each erasure target block BLK supplied from the command decoder 22. In the erasing operation, the inspection unit 51 reads information held in the block registers BS0 to BS255, and detects the set block selection register BS while referring to the address stored in the register R2. The inspection unit 51 supplies information including the detection result to the write / erase control unit 33, and the write / erase control unit 33 performs an erase operation on the target block BLK according to this information. The control unit 52 controls the register R2, the inspection unit 51, and the write / erase control unit 33 to perform the above operation.

  The operation of the flash memory according to the third embodiment will be described with reference to FIGS. FIG. 9 is a flowchart showing the erase process of the flash memory according to the third embodiment. As shown in FIG. 9, after the erase command is supplied to the command decoder 21 (step S1), the write / erase control circuit 22 sets the value of the most significant bit (first bit) of the address of the first block to be erased BLK. Is inspected (step S31). This check determines which half of the block selection register group 4 the set block selection register BS belongs to. As a result, the half that does not include the erase target block BLK is excluded from the target of further scanning. That is, for example, when the most significant bit of the address of the erase target block BLK is “0”, the block selection register BS corresponding to the erase target block BLK belongs to the first half of the block selection register group 4. Prove. The block selection register BS belonging to the other half is excluded from the scan target. When “1”, the relationship of each half is reversed.

  Next, the write / erase control circuit 22 checks the value of the bit (second bit) on the least significant bit side of the most significant bit of the address of the erase target block BLK (step S32). Based on the same principle as described for the first bit, the range of the block selection register BS to be scanned is further reduced by half according to the value of the second bit.

  Next, the write / erase control circuit 22 checks the value of the third most significant bit from the second most significant bit of the address of the block to be erased BLK (step S33). As a result, the range of the block selection register BS to be scanned is further reduced by half.

  Similarly, the value of the bit on the least significant bit side is sequentially examined until the block selection register BS to be scanned is specified. For example, when the number of blocks BLK is 256, the target block selection register BS is finally specified by performing inspection and narrowing down the scan target for 8 bits (step S41). Thereafter, the write / erase control circuit 22 erases the data in the memory cells of the block to be erased (step S42).

  Next, in step S43, it is determined whether or not the erase target block is the last one. When there is a further erase target block BLK, the address of this erase target block BLK is read, and the operations from step S32 to step S42 are repeated for this address. After the operations so far are repeated for all the blocks to be erased, the erasing process is completed.

  According to the nonvolatile semiconductor memory device in accordance with the third embodiment of the present invention, the address of the block to be erased BLK is sequentially checked from the most significant bit to the least significant bit, so that the range of the block selection register BS to be scanned can be reduced. It is gradually narrowed to half. Therefore, the scan operation required to specify one block selection register BS is completed by the same number of scan steps as the number of bits that can specify one block BLK. Therefore, it is possible to shorten the time for finding the block to be erased.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a block diagram schematically showing a configuration of main parts related to data erasure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a block diagram schematically showing a configuration of a main part of the write / erase control circuit of FIG. 1. 3 is a flowchart showing erase processing of the flash memory according to the first embodiment of the present invention. The block diagram which shows schematically the structure of the principal part of the command decoder of the non-volatile semiconductor memory device concerning 2nd Embodiment of this invention. The block diagram which shows schematically the structure of the principal part of the command decoder of FIG. 9 is a flowchart showing erase processing of a flash memory according to a second embodiment of the present invention. The block diagram which shows schematically the structure of the principal part of the command decoder of the non-volatile semiconductor memory device which concerns on 3rd Embodiment of this invention. FIG. 8 is a block diagram schematically showing a configuration of a main part of the write / control circuit 23 of FIG. 7. 9 is a flowchart showing erase processing of a flash memory according to a third embodiment of the present invention. The block diagram of the conventional flash memory. 9 is a flowchart showing a conventional flash memory erasing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,11 ... Flash memory, 2,12 ... Command decoder, 3,13 ... Write / erase control circuit, 4 ... Block selection register group, 5 ... Sector selection register group, 31 ... Comparison judgment part, 32, 52 ... Control part , 33... Write / erase control unit, 41... Decoder unit, 42... Processing unit, 51... Inspection unit, MCA. ~ SS7 ... Sector selection register, C1, C2, C3 ... Counter, R1, R2 ... Register.

Claims (5)

A method for erasing data in a nonvolatile semiconductor memory device having a plurality of blocks each consisting of a plurality of electrically rewritable memory cells and capable of erasing data for each block,
Detecting the block group to which the block to be erased belongs among a plurality of block groups composed of a plurality of the blocks;
Detecting the erasure target block in the block group to which the erasure target block belongs;
Erasing data of the memory cell in the detected block to be erased;
A method for erasing data in a nonvolatile semiconductor memory device.   2. The method according to claim 1, further comprising the step of setting the number of blocks constituting one block group in accordance with the number of blocks to be erased before the step of detecting the block group. A method for erasing data in the nonvolatile semiconductor memory device according to the above. A method for erasing data in a nonvolatile semiconductor memory device having a plurality of blocks each consisting of a plurality of electrically rewritable memory cells and capable of erasing data for each block,
Narrowing the range of blocks including the block to be erased by examining the value of the most significant bit of an address having n (n is a natural number) bits that can identify one block;
The block to be erased is specified as a step of further narrowing the range of the block group including the block to be erased by inspecting the value of the bit adjacent to the least significant bit side of the inspected bit. And the process of repeating until
Erasing data of the memory cell in the identified block to be erased;
A method for erasing data in a nonvolatile semiconductor memory device. A plurality of blocks of a plurality of electrically rewritable memory cells;
A plurality of first registers respectively associated with the plurality of blocks and set corresponding to the block to be erased;
A plurality of second registers each corresponding to a block group consisting of a predetermined number of blocks and set corresponding to the inclusion of the block to be erased;
Detecting what is set from the plurality of second registers, and detecting what is set from the first register corresponding to the block group belonging to the block group corresponding to the detected second register And an erase control circuit for erasing data of the memory cell in the block corresponding to the detected first register;
A non-volatile semiconductor memory device comprising: A plurality of blocks of a plurality of electrically rewritable memory cells;
The block to be erased is checked by sequentially checking the value from the most significant bit to the least significant bit of the address of the block to be erased having n bits (n is a natural number) that can identify one block. An erasing control circuit for sequentially narrowing a range of a block group including the data and erasing data of the memory cells in the specified block;
A non-volatile semiconductor memory device comprising:

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