JP2005235125A - Zero-crossing detection circuit, power adjusting unit equipped with the zero-crossing detection circuit, and zero-crossing detecting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a zero-cross detection circuit, wherein zero-crossing signals will not be distorted even in the presence of waveform distortion in the alternating voltage. <P>SOLUTION: The zero-cross detection circuit comprises a transfer means 2 by which the state transfers, when voltage changes to a higher or lower value than the threshold voltage Voa or -Voa near the zero-crossing point of the alternating voltage V0, a zero-crossing signal generation means 3 which generates a zero-crossing signal V9 based on the transfer of the transfer means; and an invalidation means 4 which defines the initial transfer of the transfer means as an effective transfer to generate the zero-crossing signal in the zero-cross signal generation means and invalidates transfers within the time segment, set preliminarily after the initial transfer with reference to the generation of the zero-crossing signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a zero-cross detection circuit, a power regulator including the zero-cross detection circuit, and a zero-cross detection method. The power adjuster is a device that adjusts the power supplied to loads such as various electric devices, electronic devices, and mechanical devices.

  Many power regulators having a zero-cross detection circuit for detecting a zero-cross point of an AC power supply for adjusting power supplied to a load have been proposed (for example, Patent Documents 1, 2, 3, 4). , Etc.). A zero-cross detection circuit included in such a power regulator will be described with reference to FIG. 8. Reference numeral 100 denotes a zero-cross detection circuit, and reference numeral 200 denotes an arithmetic unit (CPU). The zero-cross detection circuit 100 includes a photocoupler PC connected to the AC power supply AC via a current limiting resistor LR, a pull-up resistor PR connected at one end to the DC power supply Vcc, and an input section having a pull-up resistor PR. And an inverter INV connected in common to the photocoupler PC and having an output unit connected to the arithmetic unit 200. The photocoupler PC includes light-emitting diodes PD1 and PD2 connected in parallel with opposite polarities, and a light-receiving transistor TR that conducts to the light-emitting outputs of both light-emitting diodes PD1 and PD2, and both the light-emitting diodes PD1 and PD2 are connected to an AC power supply AC. Connected in parallel, the collector of the light receiving transistor TR is connected between the other end of the pull-up resistor PR and the input part of the inverter INV. In FIG. 8, V0 is the voltage of the AC power supply AC, V1 is the output voltage of the light receiving transistor TR of the photocoupler PC, and V2 is the output voltage of the inverter INV. Here, the light-emitting diode PD1 of the photocoupler PC emits light (ON) when the waveform of the AC power supply AC is in the positive half cycle period and is equal to or higher than the threshold voltage Voa, and becomes non-light-emitting state (OFF) when the waveform is lower than the threshold voltage Voa. The light-emitting diode PD2 emits light (ON) when the waveform of the AC power supply AC is a negative half cycle period and is equal to or higher than the threshold voltage −Voa, and enters a non-light-emitting state (OFF) when the waveform is lower than the threshold voltage −Voa. Here, “more than” and “less than” indicate the magnitude of the absolute value. The threshold voltages Voa and -Voa are fixed values determined by the resistance value of the current limiting resistor LR, the conversion efficiency of the photocoupler PC, the resistance value of the pull-up resistor PR, the voltage value of the DC power supply Vcc, and the like.

  The operation of the zero cross detection circuit 100 will be described with reference to FIG. Here, “above” and “below” also indicate the magnitude of the absolute value. 9A shows the waveform of the AC power supply voltage V0, FIG. 9B shows the waveform of the output voltage V1 of the light receiving transistor TR of the photocoupler PC, and FIG. 9C shows the waveform of the output voltage V2 of the inverter INV. . When the power supply voltage is equal to or higher than the threshold voltage −Voa in the negative half cycle of the AC power supply voltage V0, since the light emitting diode PD2 is turned on and the light receiving transistor TR is turned on, the output voltage V1 of the light receiving transistor TR is 0V. The output voltage V2 of the inverter INV is Vcc. If the AC power supply voltage V0 is equal to or lower than the threshold voltage −Voa in the negative half cycle, the light emitting diodes PD1 and PD2 are in the period until the AC power supply voltage V0 becomes Voa in the positive half cycle. Both are turned off, the output voltage V1 of the light receiving transistor TR becomes Vcc, and the output voltage V2 of the inverter INV becomes 0V. When the AC power supply voltage V0 is equal to or higher than the threshold voltage Voa in the positive half cycle, the light emitting diode PD1 is turned on and the light receiving transistor TR is turned on. Therefore, the output voltage V1 of the light receiving transistor TR is 0V. Yes, the output voltage V2 of the inverter INV is Vcc. As described above, the rectangular voltage of 0V shown in FIG. 9C is applied as the zero-cross signal from the inverter INV to the arithmetic unit (CPU) only in −Voa to Voa in both the positive and negative half cycles of the AC power supply voltage V0. Is done. In the arithmetic unit (CPU), a state in which the zero cross signal is 0V is determined as an active state by a built-in program, and if the zero cross point of the AC power supply voltage V0 exists during the period in which the zero cross signal is active. Recognize and perform necessary calculations for power adjustment to adjust the power supply to the load.

  The zero-cross signal output from the zero-cross detection circuit 100 to the arithmetic unit (CPU) 200 does not indicate the exact timing of the zero-cross point of the AC power supply voltage V0. However, as the arithmetic unit (CPU), the zero-cross signal is active. During this period, it can be recognized that a zero cross point exists, so that it can be used as a circuit that can be realized with a simple configuration if it is only necessary to grasp the rough timing of the zero cross point.

However, depending on the usage environment of the AC power supply AC, the waveform of the power supply voltage V0 may be distorted as shown in FIG. In particular, when there is a waveform distortion that crosses the threshold voltages Voa and -Voa of the light emitting diodes PD1 and PD2 as shown in (1) in the figure, the detailed circuit operation of the zero cross detection circuit 100 is clear from the above description. Therefore, although omitted, the waveform of the output voltage V1 of the light receiving transistor TR of the photocoupler PC is as shown in FIG. 10B, and accordingly, the waveform of the output voltage V2 of the inverter INV is as shown in FIG. However, there is a problem that it is broken into multiple pieces.
JP 2001-265446 A JP 2004-040913 A JP 2004-013668 A JP 2003-209967 A

  The main object of the present invention is to prevent the zero-cross signal from being broken into a plurality due to the waveform distortion even if the AC voltage has waveform distortion.

  The zero-cross detection circuit according to the first aspect of the present invention is a transfer means having a threshold voltage in the vicinity of the zero-cross point on each half cycle side of the AC voltage, and transfer of the transfer means when the AC voltage changes to a level higher or lower than the threshold voltage. Zero cross signal generation means for generating a zero cross signal based on the first transition of the transition means is effective for generating the zero cross signal in the zero cross signal generation means, and within a preset time interval after the first transition. It is characterized by having invalidating means for invalidating the generation of the zero-cross signal with respect to the transfer.

  The zero-cross detection circuit according to the second aspect of the present invention is used to transfer a transition unit having a threshold voltage near each zero-cross point of each half cycle side of the AC voltage, and a transfer unit when the AC voltage changes to a high or low level with respect to the threshold voltage. Zero cross signal generating means for generating a zero cross signal based on the zero cross signal within a preset time interval from the time when the alternating means voltage changes from the low side to the high side with respect to the threshold voltage and the transition of the transition means occurs. And an invalidating means for invalidating signal generation.

  The zero-cross detection circuit according to the third aspect of the present invention includes a transfer means having a threshold voltage in the vicinity of each zero-cycle point on each half cycle side of the AC voltage, and when the AC voltage changes from a higher side to a lower side with respect to the threshold voltage. Based on the transition of the transition means, the zero cross signal is changed to the active level, and the AC voltage is also changed from the lower side to the higher side with respect to the threshold voltage whose positive and negative are opposite to the threshold voltage described above. Based on the transition of the transition means, the zero-cross signal generating means for changing the zero-cross signal to the non-active level, and the time when the transition of the transition means occurs when the AC voltage changes from the lower side to the higher side with respect to the threshold voltage In the preset time interval, a disable means for invalidating the change of the zero cross signal from the non-active level to the active level is provided. The one in which the features.

  According to the present invention, due to the effect of the zero cross signal generating means, the AC voltage (but absolute value) changes from the higher side to the lower side with respect to the threshold voltage (assumed to be A), and then the AC voltage is also The level of the zero cross signal maintains the active level until it changes from the low side to the high side with respect to the above described threshold voltage and positive or negative threshold voltage (assuming that it is B). No matter how many times voltage distortion crosses the threshold voltage of the instep while maintaining the value, the level of the zero cross signal is not affected. In other words, the zero-cross signal generation means can prevent the zero-cross signal from being broken due to voltage distortion across the threshold voltage on the side that caused the transition that causes the change to the active level when the zero-cross signal is maintained at the active level. . In addition, when the zero-cross signal changes from the active level to the non-active level due to the invalidating means changing the AC voltage from the low side to the high side with respect to the threshold voltage of the other in the zero cross signal generating means described above. Thus, the function of changing the zero cross signal of the zero cross signal generating means from the non-active level to the active level can be disabled within a preset time interval. In other words, the null crossing signal can be prevented from being broken by the power supply distortion that crosses the threshold voltages of the former and the second during the preset time interval from the time when the zero crossing signal changes from the non-active level to the active level by the invalidating means. The threshold voltage of the former and the threshold voltage of the second mentioned here means that the positive and negative of each other's voltage are opposite, and the positive / negative of each voltage is not specified.

  As specific examples of configuring the zero-cross signal generation unit and the invalidation unit, in the embodiment, a zero-cross signal generation circuit and an invalidation circuit are included. These include a gate, a one-shot circuit, a flip-flop circuit, and the like. Has been. However, in the embodiment, the configuration is divided for convenience of explanation, and functionally, a part of the zero-cross signal generation circuit of the embodiment constitutes an invalidating means, or a part of the invalidating circuit is zero-crossed. A part of the signal generation means can be configured, and the configuration example of the embodiment does not limit the present invention.

  The circuit configuration of the embodiment is merely a configuration example of a logic circuit. For example, the one-shot circuit of the embodiment is triggered by the falling edge of the input, but conversely, the one-shot circuit may be triggered by the rising edge of the input. A transition output is input from the buffer circuit of the circuit, but an inverter may be interposed between the one-shot circuit and the buffer circuit.

  Note that, as a specific example of configuring the zero-cross signal generation unit and the invalidation unit, in the embodiment, a zero-cross signal generation circuit and an invalidation circuit, which are configured by a gate, a timer circuit, a flip-flop circuit, and the like. ing. However, in the embodiment, the configuration is divided for convenience of explanation, and functionally, a part of the zero-cross signal generation circuit of the embodiment constitutes an invalidating means, or a part of the invalidating circuit is zero-crossed. A part of the signal generation means can be configured, and the configuration example of the embodiment does not limit the present invention.

  A power regulator according to the present invention includes the zero-cross detection circuit, an arithmetic unit that performs a required calculation based on an operation amount for a power adjustment target, and a zero-cross detection output from the zero-cross detection circuit. Is. According to the power conditioner of the present invention, even if there is waveform distortion in the AC voltage, the zero-cross signal without cracks can be obtained from the zero-cross detection circuit, so that the power adjustment for the power adjustment object can be performed accurately.

  In the zero cross detection method according to the present invention, a zero cross signal without cracks can be obtained even if the AC voltage has waveform distortion.

  According to the present invention, even if waveform distortion exists in the AC voltage, the zero cross signal is not broken and the zero cross signal can be generated.

  The best mode of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a zero cross detection circuit according to this embodiment. Reference numeral 1 denotes the entire zero cross detection circuit. 2 is a transition circuit (transition means), 3 is a zero-cross signal generation circuit (zero-cross signal generation means), and 4 is an invalidation circuit (invalidation means).

  In the transition circuit 2, the AC voltage V0 changes higher and lower than the first and second threshold voltages Voa and -Voa set near the zero cross point on the positive half cycle side and the negative half cycle side of the AC voltage V0. The output state sometimes shifts, and the first transition circuit 21 including the first photocoupler PC1, the first pull-up resistor PR1, and the first buffer BF1, the second photocoupler PC2, and the second pull-up. A second transition circuit 22 including an up resistor PR2 and a second buffer BF2 is provided.

  The first transition circuit 21 and the second transition circuit 22 are commonly connected to the AC power supply AC via the current limiting resistor LR. The first photocoupler PC1 includes a first light emitting diode PD11 and a first light receiving transistor TR12, and the second photocoupler PC2 includes a second light emitting diode PD21 and a second light receiving transistor TR22. The first light emitting diode PD11 has an anode connected to the current limiting resistor LR side, and the second light emitting diode PD21 has a cathode connected to the current limiting resistor LR side. The first light receiving transistor TR12 has a collector emitter between the first pull-up resistor PR1 and the ground, and the second light receiving transistor TR22 has a collector emitter between the second pull-up resistor PR2 and the ground, respectively. It is connected. In the first light-emitting diode PD11 of the first photocoupler PC1, Voa becomes the first threshold voltage in the positive half cycle section of the AC voltage V0, and becomes conductive (ON) above Voa and becomes non-conductive (OFF) below Voa. In the second light-emitting diode PD21 of the second photocoupler PC2, -Voa becomes the second threshold voltage in the negative half cycle section of the AC power supply AC, and is turned on when the voltage is higher than -Voa and turned off when the voltage is lower than -Voa. Here, “above” and “below” indicate the absolute value.

  The first transition circuit 21 is configured such that, on the positive half cycle side of the AC voltage V0, the absolute value of the AC voltage V0 changes from a low voltage to a high voltage with respect to the first threshold voltage Voa set near the zero cross point. The output voltage V1 is transferred to one side (0V), and the output voltage V1 is transferred to the other side (Vcc) when changing from a high voltage to a low voltage with respect to the first threshold voltage Voa.

  In the second transition circuit 22, the absolute value of the AC voltage V 0 changes from a low voltage to a high voltage with respect to the second threshold voltage −Voa set near the zero cross point on the negative half cycle side of the AC voltage V 0. Sometimes the output voltage V2 shifts to one side (0V), and when the output voltage V2 changes from a high voltage to a low voltage with respect to the second threshold voltage -Voa, the output voltage V2 shifts to the other side (Vcc).

  The zero cross signal generation circuit 3 includes a first flip-flop circuit FF1, a second flip-flop circuit FF2, and a third AND gate G3.

  The zero-cross signal generation circuit 3 performs the first transition of the second transition circuit 22 when the absolute value of the AC voltage V0 changes from a voltage higher than the threshold voltage −Voa to a lower voltage (for example, times t1 and t5 in FIG. 2, FIG. 3). And the first transition of the first transition circuit 21 when the absolute value of the AC voltage V0 changes from a voltage lower than the threshold voltage Voa to a higher voltage (for example, times t2, t6 in FIG. 2). The zero cross signal V9 (see the pulse width W in FIG. 2 and the pulse width W ′ in FIG. 3) is generated based on the voltage change corresponding to each of the times t2 ′ and t6 in FIG. The first transition of the first transition circuit 21 when the value changes from a voltage higher than the threshold voltage Voa to a lower voltage (see, for example, time t3 in FIG. 2 and time t3 ′ in FIG. 3), and the absolute value of the AC voltage V0 is From threshold voltage -Voa The zero-cross signal V9 (FIG. 2) based on the voltage change corresponding to the first transition of the second transition circuit 22 (for example, time t4 in FIG. 2 and time t4 ′ in FIG. 3) when the voltage changes from high voltage to high voltage. , And the pulse width W ′ of FIG. 3).

  The invalidation circuit 4 includes a first invalidation circuit 41 composed of a first AND gate G1 and a first timer circuit TM1, and a second invalidation circuit 42 composed of a second AND gate G2 and a second timer circuit TM2.

  The first invalidation circuit 41 uses the first transition as the transition effective for the generation of the zero-cross signal V9 in the zero-cross signal generation circuit 3 as the transition from the output voltage V1 of the first transition circuit 21 from 0V to Vcc. The transition from the transition of the output voltage V1 of the circuit 21 from Vcc to OV is invalidated for the generation of the zero-cross signal V9 only during a preset time interval t (see FIGS. 2 and 3). The second invalidation circuit 42 sets the transition of the output voltage V2 of the second transition circuit 22 from 0 V to Vcc as a transition effective for the generation of the zero-cross signal V9 in the zero-cross signal generation circuit 3, and outputs the second transition circuit 22 The generation of the zero cross signal V9 is invalidated only for a preset time interval t (see FIGS. 2 and 3) from the transition of the voltage V2 from Vcc to OV.

  With reference to FIG. 2, the operation when the AC voltage V0 has no waveform distortion will be described.

  In FIG. 2, V0 is an AC voltage, V1 is the output of the first transition circuit 21, V2 is the output of the second transition circuit 22, and V3 is the first output of the first invalidation circuit 41 (the output of the first one-shot circuit OS1). ), V4 is the first output of the second invalidation circuit 42 (output of the second one-shot circuit OS2), V5 is the second output of the first invalidation circuit 41 (output of the first AND gate G1), and V6 is the second output. The second output of the invalidation circuit 42 (output of the second AND gate G2), V7 is the output of the first flip-flop circuit FF1 in the zero-cross signal generation circuit 3, and V8 is the second flip-flop circuit FF2 in the zero-cross signal generation circuit 3 , V9 indicates the output of the zero-cross signal generation circuit 3 (the output of the third AND gate G3), respectively. The first and second timer circuits TM1 and TM2 are, for example, well-known one-shot multivibrators. For example, the states of the outputs V3 and V4 can be controlled by setting time constants of resistors and capacitors. The flip-flop circuits FF1 and FF2 are, for example, well-known D-type flip-flop circuits.

  The first light emitting diode PD11 of the first photocoupler PC1 is turned on before the time t1, and from the time t4 to t5, and the second light emitting diode PD21 of the second photocoupler PC2 is turned on after the time t2 to t3, and after the time t6. Since both the first light emitting diode PD11 and the second light emitting diode PD21 are turned off at times t1 to t2, t3 to t4, and t5 to t6, the output V1 of the first transition circuit 21 and the output V2 of the second transition circuit 22 Is as shown in FIG. When the output V2 rises at time t1, the output V6 of the second AND gate G2 rises, and thereby the output V8 of the second flip-flop circuit FF2 falls. When the output V1 falls at time t2, the output V3 of the first timer circuit TM1 falls, thereby the second flip-flop circuit FF2 is reset and the output V8 rises. The output V3 of the first timer circuit TM1 falls at time t2 and rises after the elapse of time interval t. At time t3, the output V1 rises, the output V5 of the first AND gate G1 rises, and thereby the output V7 of the first flip-flop circuit FF1 falls. At time t4, the output V2 falls, the output V4 of the second timer circuit TM2 falls, and thereby the output V7 of the first flip-flop circuit FF1 rises. The output V4 of the second timer circuit TM2 rises after time t4 after falling at time t4.

  As a result, the output V9 from the third AND gate G3 becomes an active low level at times t1 to t2 and t3 to t4, and the zero-cross signal V9 having the pulse width W is generated.

  With reference to FIG. 3, the operation when waveform distortion exists in the AC voltage V0 will be described.

  In the waveform distortion of FIG. 3, the first light emitting diode PD21 of the second photocoupler PC2 is turned on before time t1 at times t4 ′ to t4 ″, t4 ″ ″ to t5 ′, and t5 ″ to t5 ″ ″. The second light emitting diode PD11 of the first photocoupler PC1 is turned on after time t2 ′ to t2 ″, t2 ″ ″ to t3 ′, t3 ″ to t3 ″, and t6. Both the first light emitting diode PD11 and the second light emitting diode PD21 are time t1 to t2 ′, t2 ″ to t2 ″ ′, t3 ′ to t3 ″, t3 ″ ″ to t4 ′, t4 ″ to t4. ″ ″, T5 ′ to t5 ″, and t5 ″ ″ to t6 are all turned off.

  In FIG. 3, the transition output V2 of the second transition circuit 22 rises at t1, t4 ″, t5 ′, and t5 ″. Among these, at t1 and t5 ′, the output V6 of the second AND gate G2 rises, and as a result, the output V8 of the second flip-flop circuit FF2 falls. On the other hand, at t4 ″ and t5 ″ ″, the output V4 of the second timer circuit TM2 falls at the immediately preceding t4 ′ and t5 ″, respectively, and by maintaining the low level of V4 during the time interval t, Since the rise of the output V6 of the second AND gate G2 does not occur, the output V8 of the second flip-flop circuit FF2 does not fall. However, this operation is conditional on the existence of t4 ″ and t5 ″ ″ before the set time t elapses from t4 ′ and t5 ″. Similarly, the transition output V1 of the first transition circuit 21 rises at t2 ″, t3 ′, and t3 ″. Among these, at t3 ′, the output V5 of the first AND gate G1 rises, and as a result, the output V7 of the first flip-flop circuit FF1 falls. On the other hand, at t2 ″ and t3 ″ ″, the output V3 of the first timer circuit TM1 falls at the immediately preceding t2 ′ and t3 ″, respectively, and the low level of V3 is maintained during the time interval t. Since the rise of the output V5 of the first AND gate G1 does not occur, the output V7 of the first flip-flop circuit FF1 does not fall. However, this operation is conditional on the presence of t2 ″ and t3 ″ ″ before the set time t elapses from t2 ′ and t3 ″.

  Further, the transition output V2 of the second transition circuit 22 falls at t4 ′, t4 ″ ″, and t5 ″. Among these, at t4 ′, the output V4 of the second timer circuit TM1 falls, the first flip-flop circuit FF1 is reset, and the output V7 rises. At t5 ″, the output V4 of the second timer circuit TM2 falls and the first flip-flop circuit FF1 is reset. However, since the output V7 is originally at a high level, no change occurs. At t4 ′ ″, the output V4 of the second timer circuit TM2 falls at the immediately preceding t4 ′ and maintains the low level of V4 during the time interval t. Therefore, V4 does not fall again, and the first The output V7 of the flip-flop circuit FF1 remains at the high level.

  However, this operation is conditional on the presence of t4 ′ ″ before the set time t elapses from t4 ′. Similarly, the transition output V1 of the first transition circuit 21 falls at t2 ′, t2 ″, t3 ″, and t6. Among these, at t2 ′ and t6, the output V3 of the first timer circuit TM1 falls, the second flip-flop circuit FF2 is reset, and the output V8 rises. At t3 ″, the output V3 of the first timer circuit TM1 falls and the second flip-flop circuit FF2 is reset. However, since the output V8 is originally at a high level, no change occurs. At t2 ′ ″, the output V3 of the first timer circuit TM1 falls at the immediately preceding t2 ′ and maintains the low level of V3 for the time interval t. Therefore, V3 does not fall again, and the second The output V8 of the flip-flop circuit FF2 remains at the high level. However, this operation is conditional on the presence of t2 ″ ″ before the set time t has elapsed since t2 ″.

  As described above, the output V9 of the third AND gate becomes an active low level in the period from t1 to t2 ′, t3 ′ to t4 ′, and t5 ′ to t6, and the zero cross signal V9 having the pulse width W ′ is generated. . As a result, since the zero cross point exists in the pulse width and no crack is generated, the next-stage computing unit (CPU) can perform a required operation using the zero cross signal V9.

  The time interval t can be determined in consideration of the degree of waveform distortion of the AC voltage V0. The time when the AC voltage V0 becomes higher than the threshold voltage Voa at the time t2 ′ and then lower than the threshold voltage Voa at the time t2 ″ is X, and then the AC voltage V0 falls from the maximum amplitude at the time t3 ′. When the time until the threshold voltage Voa is reached is Y, X <t <Y. In this case, since the times X and Y are indefinite, it may be set appropriately by experiment or the like. The time interval t is determined based on the magnitude of the threshold voltage Voa and the frequency of the AC voltage V0. However, even if it is assumed that the threshold voltage Voa is very close to the zero cross point, it exceeds the half cycle of the AC voltage V0 at the maximum. Absent.

  The above zero cross detection circuit can be applied to, for example, a power regulator used in a CVD apparatus which is one of semiconductor manufacturing apparatuses. In this CVD apparatus, a substrate such as a silicon wafer is accommodated in a heating furnace, and a reaction gas is supplied while the inside of the heating furnace is heated to a required temperature by a heater to form a thin film on the substrate. In semiconductor manufacturing equipment, the temperature condition in the heating furnace is an important factor that affects the quality of the product. As one of the applications, the power regulator is configured to adjust the power necessary for the heat generation of the heater in the heating furnace. A temperature control system including such a power regulator is shown in FIG. In this system, the power regulator 10 includes a zero-cross detection circuit 11 that detects a zero-cross point of the AC power source 14 and a calculator (CPU) 12 that calculates the phase of the AC power source from the zero-cross point corresponding to the operation amount. . A solid state relay (SSR) 15 is interposed between the heater 13 and the AC power supply 14. Note that other switch elements such as a triac may be used instead of the SSR. In this system, there are a method of controlling the phase of the heater 13 with the waveform shown in FIG. 5 and an optimum cycle control method of controlling the heater 13 with the waveform shown in FIG. In the phase control method shown in FIG. 5, the phase of the AC power source 14 from the zero cross point corresponding to the manipulated variable is calculated by the calculator 11 of the power regulator 10, and the output state corresponding to this calculation is shown in FIG. Is applied to the SSR 15. As a result, the heater 13 is supplied with the current having the waveform shown by the oblique lines in FIG. 5A with respect to the voltage (AC voltage) of the AC power supply 14 shown by the broken lines in FIG. The temperature is controlled. In the optimum cycle control system shown in FIG. 6, the number of half cycles of the AC power supply 14 from the zero cross point corresponding to the operation amount is calculated by the calculator 11 of the power regulator 10, and the output state corresponding to this calculation is shown in FIG. The SSR drive signal indicated by 7 (B) is applied to the SSR 15. As a result, the heater 13 is supplied with a current having a waveform indicated by the oblique lines in FIG. 7A with respect to the voltage (AC voltage) of the AC power source 14 indicated by the broken lines in FIG. The temperature is controlled.

  In the above system, the zero cross signal from the zero cross detection circuit 11 is required for the calculation in the calculator 12 of the power regulator 10. The zero cross detection circuit 1 of the present embodiment can be applied to the zero cross detection circuit 11 shown in FIG. 4 has the SSR 15 provided outside, the SSR 15 can be provided in the power adjuster 10 as shown in FIG.

  When the zero-cross detection circuit 1 of the present embodiment is applied as the zero-cross detection circuit 11 of the power regulator 10, when the frequency of the AC voltage is recognized based on the period in which the zero-cross signal becomes active, the waveform distortion occurs in the AC voltage V0. Even if there is, the zero cross signal is not broken, so that the frequency can be accurately recognized. When power adjustment is performed by phase control or optimum cycle control in a power regulator that supplies power to a heater or the like, the power can be controlled to the intended power.

  Note that the pulse width W of the zero cross signal V9 when the AC voltage V0 has no waveform distortion differs from the pulse width W ′ of the zero cross signal V9 when the AC voltage V0 has waveform distortion. The concerns regarding the intended use in the power regulator 10 and the like due to the difference between the pulse widths W and W ′ will be summarized. First, the frequency of the AC voltage V0 is detected by measuring the period in which the zero cross signal V9 becomes active. If waveform distortion exists in the AC voltage V0, the period in which the zero cross signal V9 becomes active does not become a constant value, but the average value of the period is equivalent to the period when there is no waveform distortion. In this program, a plurality of consecutive periods are measured, and the average value of the measurement is recognized as the period of the waveform, so that there is no problem even if the period changes every half cycle. In addition, this recognition is preferable in that the accuracy can be improved even for a waveform having no waveform distortion. Even if the trigger timing of the SSR 15 is deviated, the timing deviation due to the waveform distortion is small, and since the phase control and the optimum cycle control are originally performed on the assumption that the AC voltage V0 has the waveform distortion, the zero cross signal V9 Even if the pulse width differs depending on the presence or absence of waveform distortion, there is little influence on the accuracy of the control.

Circuit diagram of zero-cross detection circuit according to the best mode of the present invention Timing chart for explaining the operation of the zero-cross detection circuit of FIG. 1 when there is no waveform distortion in the AC voltage Timing chart for explaining the operation of the zero-crossing detection circuit of FIG. 1 when the AC voltage has waveform distortion Circuit diagram of temperature control system Timing chart for explaining the operation of the system of FIG. Timing chart for explaining the operation of the system of FIG. Circuit diagram of another temperature control system Circuit diagram of conventional zero-cross detection circuit Timing chart used to explain the operation of the zero cross detection circuit of FIG. 8 when there is no waveform distortion in the AC voltage Timing chart used to explain the operation of the zero cross detection circuit of FIG. 8 when the AC voltage has waveform distortion

Explanation of symbols

  1 is a zero cross detection circuit, 2 is a transition circuit (transition means), 3 is a zero cross signal generation circuit (zero cross signal generation means), and 4 is an invalidation circuit (invalidation means).

Claims (6)

Transition means having a threshold voltage in the vicinity of the zero-cross point on each half-cycle side of the AC voltage;
Zero-cross signal generating means for generating a zero-cross signal based on the transition of the transition means when the alternating voltage changes to a high or low with respect to the threshold voltage;
The first transition of the transition means is valid for generating the zero cross signal in the zero cross signal generation means, and the transition within the preset time interval after the first transition is invalid for the generation of the zero cross signal. Invalidation means, and
A zero cross detection circuit characterized by comprising: Transition means having a threshold voltage in the vicinity of the zero-cross point on each half-cycle side of the AC voltage;
Zero-cross signal generating means for generating a zero-cross signal based on the transition of the transition means when the alternating voltage changes to a high or low with respect to the threshold voltage;
An invalidating means for invalidating the generation of the zero cross signal within a preset time interval from the time when the alternating voltage is changed from a low side to a high side with respect to the threshold voltage and the transfer of the transfer means occurs.
A zero cross detection circuit characterized by comprising: Transition means having a threshold voltage in the vicinity of the zero-cross point on each half-cycle side of the AC voltage;
Based on the transition of the transition means when the alternating voltage changes from the high side to the low side with respect to the threshold voltage, the zero cross signal is changed to the active level. Similarly, the alternating voltage is positive or negative with the threshold voltage described above. Zero-cross signal generating means for changing the zero-cross signal to a non-active level based on the transition of the transition means when changing from the low side to the high side with respect to the threshold voltage which is the reverse side;
When the AC voltage changes from a low side to a high side with respect to the threshold voltage, the change of the zero cross signal from the non-active level to the active level is invalidated within a preset time interval from the time when the transfer means shifts. Invalidation means,
A zero cross detection circuit characterized by comprising: A zero-cross detection circuit according to any one of claims 1 to 3,
An arithmetic unit that performs a required calculation based on the operation amount for the power adjustment target and the zero cross detection output from the zero cross detection circuit,
A power regulator comprising:   Zero-crossing that generates a zero-cross signal based on the state transition of the transition means when the threshold voltage of the transition means is set in the vicinity of the zero-crossing point on each half-cycle side of the AC voltage and the AC voltage changes to a level higher or lower than the threshold voltage. In the detection method, among the state transitions, the first transition is effective for generating a zero-cross signal, and the transition within a predetermined time interval after the first transition is generated for generating a zero-cross signal. A zero-cross detection method characterized by being invalidated. Based on the transition of the transition means when the threshold voltage of the transition means is set in the vicinity of the zero crossing point on each half cycle side of the AC voltage and the AC voltage changes from the higher side to the lower side with respect to the threshold voltage, Based on the transition of the transition means when the signal is changed to the active level and the AC voltage also changes from the lower side to the higher side with respect to the threshold voltage whose polarity is opposite to the threshold voltage described above, the zero crossing A zero-cross detection method for changing a signal to a non-active level,
When the AC voltage changes from a low side to a high side with respect to the threshold voltage, the change of the zero cross signal from the non-active level to the active level is invalidated within a preset time interval from the time when the transfer means shifts. A zero-cross detection method characterized by that.

Images