JP2005229423A - Apparatus for inverse orthogonal transformation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus for inverse orthogonal transformation, where operating efficiency in an entire circuit is increased. <P>SOLUTION: A determination circuit acquires information (DCT data row information) on the length of a data row in DCT data outputted to DCT data receivers 101a, 101b by decoding processors 13a, 13b from the respective decoders 13a, 13b, and acquires information (processing state information) on the state of processing performed between respective movement compensation sections 15a, 15b and respective external memories from the respective movement compensation sections 15a, 15b. A determination circuit 106 refers to the acquired DCT data row information, and assigns each of output buffers that should output space data to IDCT circuits 103a, 103b. And the determination circuit 106 refers to the acquired processing state information, and assigns each of output buffers that should output the space data to the IDCT circuits 103a, 103b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an apparatus that performs inverse orthogonal transform, and more particularly to an apparatus that performs inverse orthogonal transform in MPEG decompression processing or the like.

  In recent years, in the field of moving image compression / decompression such as MPEG, the target of image size is becoming finer from SD (Standard Definition) to HD (High Definition). In addition, data streams (streams) compressed in MPEG, such as two-screen playback that plays two videos on one screen, and back program recording that plays one video and saves other videos on another recording medium, etc. There has been a demand for semiconductor integrated circuits that can process a plurality of semiconductor devices simultaneously.

  Here, FIG. 6 shows a configuration of a conventional MPEG stream processing apparatus that performs an expansion process on an MPEG moving image. The stream processing unit (STREAM) receives an MPEG stream including encoded moving image data and encoded audio data input from the outside. The separation unit (SETUP) reads the MPEG stream received by the stream processing unit (STREAM), separates it into encoded moving image data and encoded audio data, and transfers the encoded moving image data to the video decoding processing unit (VLDIQ). The encoded audio data is transferred to the audio decoding processing unit (AUDIO). The video decoding processing unit (VLDIQ) performs variable length decoding and inverse quantization on the encoded moving image data, and transfers the result as DCT data to the IDCT operation unit (IDCT). The IDCT calculation unit (IDCT) performs inverse DCT transformation on the DCT data transferred from the video decoding processing unit (VLDIQ), and transfers the result as spatial data to the motion compensation unit (MC). The motion compensation unit (MC) uses the image data of the frames existing before and after the frame including the spatial data transferred from the IDCT calculation unit (IDCT) to the spatial data transferred from the IDCT calculation unit (IDCT). The image is reconstructed by performing motion compensation on the image, and the result is transferred to an external memory or the like (not shown).

  As a method for simultaneously processing a plurality of streams, as shown in FIG. 7, the MPEG stream processing apparatus shown in FIG. 6 is prepared in parallel for the number of streams to be simultaneously processed (method 1), and a circuit capable of operating at higher speed. A method (method 2) in which the MPEG stream processing apparatus shown in FIG.

  When performing time-sharing processing (in the case of method 2), if the number of streams to be processed simultaneously is N, processing performance that is N times that required for processing a single stream is required. As a method for realizing this, as shown in FIG. 8, the calculation performance of each circuit included in the MPEG stream processing apparatus is increased by N times to reduce the time required for calculation to 1 / N (method 2). -A) and a method (method 2-B) for realizing parallel processing by having a plurality of circuits for a portion that can be processed in parallel in the MPEG stream processing apparatus in the MPEG decompression processing.

  In the case of (Method 2-B), the configuration of the MPEG processing circuit is shown in FIG. As an example in which the method (2-B) is used to increase the processing speed, Patent Document 1 is cited. In the method of Patent Document 1, processing is performed at the level of each block (8 × 8 pixels) of Y0 to Y3, Cb, and Cr included in an MPEG macroblock, and part of the video decoding processing unit (VLDIQ) Processes after the above are parallelized. In Patent Document 1, it is intended to realize decoding by an MPEG stream processing apparatus including an arithmetic circuit that operates at a lower speed, and there is no relationship between the number of parallel processes of streams and the degree of parallelism. However, if the processing performance of one circuit is sufficient, it can be expected that a number of streams equal to the parallelism of the circuit can be processed simultaneously.

  As the image size becomes finer, the amount of computation required for moving image expansion processing has increased, so N times the performance required for single stream processing as in (Method 2-A). In order to realize this computing performance, the circuit scale is greatly increased and the difficulty of physical design of the semiconductor integrated circuit is increased, which is not realistic.

  On the other hand, in the case of (Method 1) and (Method 2-B), the circuit scale is almost the same. Therefore, the method (method 1) or (method 2-B) is generally used. Both of these methods prepare circuits in parallel for the number of streams to be processed simultaneously.

  Here, transfer processing from the video decoding processing unit (VLDIQ) to the IDCT calculation unit (IDCT) will be described. In the transfer process from the video decoding processing unit (VLDIQ) to the IDCT operation unit (IDCT), the block data converted into the frequency domain is scanned based on a specific scanning order, and is transferred sequentially for each element. Is done. If all the remaining elements are 0 during scanning, a block end signal is transmitted and no subsequent transmission is performed. Therefore, the time required for data transmission from the video decoding processing unit (VLDIQ) to the IDCT operation unit (IDCT) varies depending on the data contents of each block. When all elements are 0, transmission is completed in one clock cycle. When there is no 0 element, transmission is completed in a maximum of 64 cycles.

  Next, the inverse DCT conversion process performed by the IDCT calculation unit (IDCT) will be described. Inverse DCT conversion processing is generally performed in units of 8 × 8 pixels called blocks. The processing content of the inverse DCT transform is a process of returning data (spatial data) in the spatial domain by performing inverse DCT transform on the data transformed into the frequency domain (frequency data). In general, frequency data often includes zero elements.

Next, MC processing (motion compensation processing) by the motion compensation unit (MC) will be described. In the MC processing by the motion compensation unit (MC), the image data of the previous and subsequent frames is used as described above. Since these data amounts are enormous, generally, data is arranged in an external memory instead of a memory inside the semiconductor integrated circuit, and a process of transferring from the external memory is performed as necessary. In this case, depending on the operation status of the external memory, it may take a long time from the start of the transfer process to the actual transfer. Therefore, the time required for MC processing varies greatly depending on the status of the external memory.
Japanese Patent Laid-Open No. 10-56441 (page 8, FIG. 1)

  As described above, the time required to transfer data to the IDCT calculation unit (IDCT) and the processing time by the motion compensation unit vary greatly depending on the operation situation. That is, the IDCT calculation unit (IDCT) cannot perform the inverse DCT calculation process unless the data transfer is completed, and the IDCT calculation unit (IDCT) transfers the generated spatial data unless the MC process by the motion compensation unit is completed. Can not do it. The period required for data transfer from the video decoding processing unit (VLDIQ) depends on the contents of the data string. The MC processing by the motion compensation unit (MC) depends on the operation status of the external memory. Accordingly, when a plurality of similar IDCT operation units (IDCT) are provided in the MPEG stream processing apparatus and operate in parallel, the operation status of each IDCT operation unit (IDCT) may be greatly different. In that case, it can be said that the operation efficiency is low in the entire apparatus.

  As described in Patent Document 1, a method of performing parallel processing by having a plurality of circuits in a portion that can be processed in parallel in a stream, or MPEG stream processing devices as many as the number of streams to be simultaneously processed as shown in FIG. In the method prepared in parallel, there is a problem that the operation state is different depending on each circuit and the operation efficiency is lowered.

  An object of the present invention is to provide an apparatus capable of improving the operation efficiency of the entire apparatus when processing is performed by a plurality of circuits.

  According to one aspect of the present invention, the inverse orthogonal transform device generates spatial data by performing inverse orthogonal transform on frequency data. The inverse orthogonal transform device includes a determination unit, two or more reception units, two or more inverse orthogonal transform units, and two or more output buffers. The determination unit associates any one of the inverse orthogonal transform units with each of the reception units, and associates any one of the inverse orthogonal transform units with each of the output buffers. Each of the reception units stores frequency data. Each of the inverse orthogonal transform units generates spatial data by performing inverse orthogonal transform on the frequency data stored in the reception unit associated with the inverse orthogonal transform unit by the determination unit. Each of the output buffers stores the spatial data generated by the inverse orthogonal transform unit associated with the output buffer by the determination unit. The determination unit performs the association in each reception unit with reference to the time required for the reception unit to store the frequency data and whether or not the output buffer stores spatial data in each output buffer. .

  In the inverse orthogonal transform apparatus, the determination unit performs inverse orthogonal to the reception unit having a short transmission period by referring to the time (transmission period) required for the reception unit to store frequency data in each reception unit. It is possible to associate an inverse orthogonal transform section having a margin for conversion. In addition, the determination unit refers to the presence or absence of storage of the spatial data in each output buffer in each output buffer, so that the output that does not store the spatial data to the inverse orthogonal transform unit that completes the inverse orthogonal transform processing Buffers can be associated with priority. As described above, it is possible to improve the operation efficiency of the entire apparatus by preferentially associating the arithmetic units having processing margins with the state of transmission data.

  Preferably, the inverse orthogonal transform device is connected between a decoding processing unit that performs decoding on encoded moving image data and generates frequency data, and a motion compensation unit that performs motion compensation on spatial data. Is done. Each of the reception units stores the frequency data generated by the decoding processing unit, and each of the output buffers receives the spatial data generated by the inverse orthogonal transform unit associated with the output buffer by the determination unit. The stored spatial data is output to the motion compensation unit. The determining unit refers to the time required for storing the frequency data from the decoding processing unit corresponding to the receiving unit in each receiving unit and the operation state of the motion compensating unit corresponding to each output buffer. The above association is performed.

  In the inverse orthogonal transform device, the determination unit reverses the reception unit having a short transmission period by referring to the time (transmission period) required for the reception unit to store the frequency data in each reception unit. An inverse orthogonal transform unit having a margin for orthogonal transform can be associated. In addition, the determination unit refers to the presence or absence of storage of the spatial data in each output buffer in each output buffer, so that the output that does not store the spatial data to the inverse orthogonal transform unit that completes the inverse orthogonal transform processing Buffers can be associated with priority. As described above, it is possible to improve the operation efficiency of the entire apparatus by preferentially associating the arithmetic units having processing margins with the state of transmission data.

  Preferably, the inverse orthogonal transform device decodes the encoded moving image data to generate frequency data and two or more motion compensations that perform motion compensation on the spatial data. Connected between the parts. Each of the receiving units corresponds to any one of the decoding processing units on a one-to-one basis, and stores the frequency data generated by the decoding processing unit corresponding to the receiving unit. Each of the output buffers corresponds to any one of the motion compensation units on a one-to-one basis, and stores the spatial data generated by the inverse orthogonal transform unit associated with the output buffer by the determination unit. The stored spatial data is output to the motion compensation unit corresponding to the output buffer. The determining unit refers to the time required for storing the frequency data from the decoding processing unit corresponding to the receiving unit in each receiving unit and the operation state of the motion compensating unit corresponding to each output buffer. The above association is performed.

  In the inverse orthogonal transform device, the determination unit reverses the reception unit having a short transmission period by referring to the time (transmission period) required for the reception unit to store the frequency data in each reception unit. An inverse orthogonal transform unit having a margin for orthogonal transform can be associated. In addition, the determination unit refers to the presence or absence of storage of the spatial data in each output buffer in each output buffer, so that the output that does not store the spatial data to the inverse orthogonal transform unit that completes the inverse orthogonal transform processing Buffers can be associated with priority. As described above, it is possible to improve the operation efficiency of the entire apparatus by preferentially associating the arithmetic units having processing margins with the state of transmission data.

  Preferably, the receiving unit includes a storage unit and an output unit. The storage unit stores the frequency data. The output unit outputs the frequency data stored in the storage unit. The inverse orthogonal transform unit includes a calculation buffer and a calculation unit. The arithmetic buffer stores the frequency data from the output unit. The calculation unit generates spatial data by performing inverse orthogonal transform on the frequency data stored in the calculation buffer.

  In the inverse orthogonal transform device, the output unit outputs the frequency data stored in the storage unit included in the reception unit to the arithmetic buffer included in the inverse orthogonal transform unit. As a result, if the operating speed of the output unit is increased, the time required to output frequency data from the receiving unit to the inverse orthogonal transform unit can be shortened, and the operating efficiency of the entire apparatus can be improved. .

  Preferably, the determination unit further refers to the time required for the receiving unit to store the frequency data in each of the receiving units and whether or not spatial data is stored by the output buffer in each of the output buffers. Then, the inverse orthogonal transform unit that does not need to perform an operation among the inverse orthogonal transform units is stopped.

  In the inverse orthogonal transform apparatus, it is possible to reduce power consumption by stopping the inverse orthogonal transform unit that is not operating. Thereby, an effect can be expected particularly in an apparatus used for a device that requires lower power consumption.

  Preferably, the two or more inverse orthogonal transform units include at least one simplification operation unit. The simplified calculation unit performs a calculation that is simpler than the calculation performed by another inverse orthogonal transform unit. The determination unit further associates the simplification calculation unit with the reception unit that stores the frequency data according to the content of the frequency data stored in each of the reception units.

  In the inverse orthogonal transform apparatus, for example, the simplified calculation unit is associated with the reception unit that stores the frequency data that causes little deterioration in image quality even when the simplified calculation is performed. Even if the simplified calculation is performed, the calculation speed of the frequency data that causes little deterioration in image quality is higher in the calculation performed by the simplified calculation unit than in the calculation performed by other inverse orthogonal transform units. As a result, the processing speed by inverse orthogonal transformation can be increased, and the operation efficiency of the entire apparatus can be improved. Further, the same level of processing can be realized with a simpler calculation unit, and the deterioration in data quality can be minimized.

  Preferably, the inverse orthogonal transform is an inverse DCT transform.

  Preferably, the determination unit selects a receiving unit having the shortest time required to store the frequency data among the two or more receiving units as an output buffer in which the spatial data is not stored among the two or more output buffers. Associate with.

  Preferably, the determination unit stops any of the orthogonal transform units when determining that each of the output buffers stores the frequency data longer than a predetermined time.

  As described above, it is possible to improve the operation efficiency of the entire apparatus by preferentially associating the arithmetic units with processing margins in accordance with the state of transmission data.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(First embodiment)
<Overall configuration>
FIG. 1 shows the overall configuration of an MPEG stream processing apparatus according to the first embodiment of the present invention. This apparatus includes a stream processing unit 11, a separation unit 12, decoding processing units 13a and 13b, an IDCT calculation unit 14, and motion compensation units 15a and 15b. The stream processing unit 11 receives an MPEG stream including encoded moving image data (encoded moving image data) and encoded audio data (encoded audio data) from the outside. The separation unit 12 reads the MPEG stream received by the stream processing unit 11, separates the encoded moving image data and the encoded audio data included in the MPEG stream, and decodes the encoded moving image data to the decoding processing units 13a and 13b. Forward to. Each of the decoding processing units 13a and 13b performs variable length decoding and inverse quantization on the encoded moving image data transferred by the separation unit 12, and outputs the result as DCT data. The IDCT calculation unit 14 performs inverse DCT transformation on the DCT data output by each of the decoding processing units 13a and 14b, and outputs the result as spatial data. Each of the motion compensation units 15a and 15b acquires image data of a frame existing before and after the frame including the spatial data output by the IDCT calculation unit 14 from an external memory or the like (not shown), and acquires the acquired image data. Is used to reconstruct an image by performing motion compensation on the spatial data output by the IDCT computing unit 14 and transfer the result to an external memory or the like (not shown).

  Note that a description of a circuit that decodes encoded audio data is omitted.

<Internal configuration of IDCT calculation unit>
FIG. 2 shows an internal configuration of the IDCT calculation unit 14 shown in FIG. The IDCT operation unit 14 includes DCT data receiving units 101a and 101b, selectors 102 and 104, IDCT circuits 103a and 103b, output buffers 105a and 105b, and a determination circuit 106. The DCT data receiving units 101a and 101b have a one-to-one correspondence with the decoding processing units 13a and 13b, respectively, and receive the DCT data output from the decoding processing units 13a and 13b corresponding to themselves. Each of the IDCT circuits 103a and 103b performs inverse DCT conversion on the DCT data output from the DCT data receiving units 101a and 101b, and outputs the result as spatial data. Each of the output buffers 105a and 105b stores the spatial data output from the IDCT circuits 103a and 103b. The motion compensation units 15a and 15b have a one-to-one correspondence with the output buffers 105a and 105b, respectively, issue a transfer instruction to the output buffers 105a and 105b corresponding to the motion compensation units 15a and 15b, and are stored in the output buffers 105a and 105b. Spatial data is received, and motion compensation is performed on the received spatial data. The determination circuit 106 acquires information (DCT data content information) on the content of DCT data transmitted from the decoding processing units 13a and 13b to the DCT data receiving units 101a and 101b from each of the decoding processing units 13a and 13b. Information about the processing status of the compensation units 15a and 15b (processing status information) is acquired from each of the motion compensation units 15a and 15b. The determination circuit 106 assigns IDCT circuits 103a and 103b to the DCT data receiving units 101a and 101b based on the DCT data content information acquired from the decoding processing units 13a and 13b, and each of the motion compensation units 15a and 15b. The output buffers 105a and 105b are allocated to the IDCT circuits 103a and 103b based on the processing status information acquired from the above. The selector 1 connects the DCT data receiving units 101a and 101b and the IDCT circuits 103a and 103b according to the assignment by the determination circuit 106. The selector 2 connects the IDCT circuits 103 a and 103 b and the output buffers 105 a and 105 b according to the assignment by the determination circuit 106.

<Operation>
Next, the operation of the MPEG stream processing apparatus shown in FIG. 1 will be described. Here, it is assumed that the MPEG stream input to the separation unit 12 includes two types of encoded moving image data (encoded moving image data A and B). Here, it is assumed that the separating unit 12 separates the encoded moving image data from the MPEG stream and outputs the encoded moving image data to the decoding processing units 13a and 13b for each block.

  First, the stream processing unit 11 receives an MPEG stream from the outside.

  Next, the separation unit 12 separates the encoded moving image data A and B from the MPEG stream received by the stream processing unit 11. Here, it is assumed that the separating unit 12 outputs the encoded video data A among the separated encoded moving image data to the decoding processing unit 13a and outputs the encoded moving image data B to the decoding processing unit 13b.

  Next, the decoding processing unit 13a performs variable length decoding and inverse quantization on the encoded moving image data A for one block output from the separating unit 12, and the result is used as DCT data for one block. The data is output to the DCT data receiving unit 101a corresponding to itself. Similar to the decoding processing unit 13a, the decoding processing unit 13b performs variable-length decoding and inverse quantization on the encoded moving image data B for one block output from the separation unit 12, and outputs the result as one block. Output to the DCT data receiving unit 101b corresponding to itself as the DCT data of the minute. Here, the determination circuit 106 receives information (DCT data sequence information) on the length of the DCT data sequence output to the DCT data receiving units 101a and 101b corresponding to the decoding processing units 13a and 13b. , 13b.

  On the other hand, the motion compensation unit 15a performs motion compensation on one block of spatial data received from the output buffer 105a corresponding to itself, and outputs the result as moving image data. Similar to the motion compensation unit 15a, the motion compensation unit 15b performs motion compensation on the spatial data for one block received from the output buffer 105b corresponding to itself, and outputs the result as moving image data. Here, the determination circuit 106 acquires information (processing status information) regarding the status of processing performed between each of the motion compensation units 15a and 15b and the external memory from each of the motion compensation units 15a and 15b. For example, the processing status information is information indicating whether or not a transfer instruction to be output to the output buffers 15a and 15b corresponding to itself when each of the motion compensation units 15a and 15b starts motion compensation is currently output. (Information on presence / absence of transfer instruction).

  Next, the determination circuit 106 uses the DCT data string information acquired from each of the decoding processing units 13a and 13b to allow the decoding processing units 13a and 13b to send one block worth of data to the corresponding DCT data receiving units 101a and 101b. The time (transmission period) required for outputting DCT data is calculated. The transmission period depends on the content of the data string of DCT data for one block. For example, when all the DCT coefficients included in the transmitted DCT data are “0”, a period of one clock cycle is required, and when it is not “0”, a period of 64 clock cycles is required. The determination circuit 106 refers to each calculated transmission period and assigns an IDCT circuit that should output DCT data to each of the DCT data receiving units 101a and 101b.

  Further, the determination circuit 106 uses the processing status information acquired from each of the motion compensation units 15a and 15b to determine whether or not spatial data is stored in each of the output buffers 105a and 105b (output buffers 15a and 15b). Availability). For example, if the processing status information is information regarding the presence / absence of a transfer instruction in each of the motion compensation units 15a and 15b, the availability of the output buffer depends on the presence / absence of the transfer instruction, and the output buffer for which the transfer instruction has been issued The stored spatial data is output, and the output buffer to which no transfer instruction is issued holds the spatial data stored in itself. The determination circuit 106 refers to the result of determination for each of the output buffers 105a and 105b (the availability of the output buffers 15a and 15b), and determines which output buffer should each output spatial data to the IDCT circuits 103a and 103b. assign.

  Next, the selector 102 connects each of the DCT data receiving units 101a and 101b to the IDCT circuits 103a and 103b assigned to the DCT data receiving units 101a and 101b by the determination circuit 106. On the other hand, the selector connects each of the IDCT circuits 103a and 103b to the output buffers 105a and 105b assigned to the IDCT circuits 103a and 103b by the determination circuit 106.

  Next, when each of the DCT data receiving units 101a and 101b has received one block of DCT data from the decoding processing units 13a and 13b corresponding to the DCT data receiving units 101a and 101b, the DCT data receiving units 101a and 101b select the received DCT data from the IDCT circuits 103a and 103b. The output starts to the IDCT circuit connected by 102.

  Next, when each of the IDCT circuits 103a and 103b has received one block of DCT data from the DCT data receiving unit connected by the selector 102 of the DCT data receiving units 101a and 101b, the IDCT circuits 103a and 103b receive the one block received. Inverse DCT transform is performed on the DCT data.

  Next, when the IDCT circuits 103a and 103b complete the inverse DCT conversion, the IDCT circuits 103a and 103b start outputting the result of the inverse DCT conversion as spatial data to the output buffer connected by the selector 104 among the output buffers 105a and 105b.

  Next, when each of the output buffers 105a and 105b finishes storing one block of spatial data from the IDCT circuit connected by the selector 104 of the IDCT circuits 103a and 103b, the motion compensation units 15a and 15b corresponding to the output buffers 105a and 105b. In response to the transfer instruction from each of the data, the stored spatial data for one block is output to the motion compensation units 15a and 15b.

  Next, when each of the motion compensation units 15a and 15b has received one block of spatial data from the output buffers 105a and 105b corresponding to the motion compensation units 15a and 15b, it stops the transfer instruction to the output buffers 105a and 105b corresponding to itself. After obtaining image data necessary for performing motion compensation on the received spatial data for one block from the external memory, motion compensation is performed on the spatial data for one block using the image data.

<IDCT circuit and output buffer allocation method by determination circuit 106>
Next, a method for assigning IDCT circuits 103a and 103b to DCT data receiving sections 101a and 101b and a method for assigning output buffers 105a and 105b to IDCT circuits 103a and 103b in determination circuit 106 will be described. When decoding and inverse quantization are performed on the encoded moving image data A (or encoded moving image data B), DCT data A (or DCT data B) is generated, and DCT data A (or DCT data B) is generated. When the inverse DCT transform is performed on the spatial data A, spatial data A (or spatial data B) is generated.

<< Assignment of IDCT circuit to DCT data receiver >>
The DCT data receiving unit 101a receives from the decoding processing unit 13a the DCT data A obtained by further decoding the encoded moving image data A. On the other hand, the DCT data receiving unit 101b receives the DCT data B obtained by further decoding the encoded moving image data B from the decoding processing unit 13B.

  For example, if the DCT data receiving unit 101a and the IDCT circuit 103a are connected and the DCT data receiving unit 101b and the IDCT circuit 103b are connected, the IDCT circuit 103a is connected to the DCT data receiving unit by one block of DCT data A. The IDCT circuit 103b receives DCT data B for one block from the DCT data receiving unit.

  Here, it is assumed that the output of DCT data from the DCT data receiving unit 101a to the IDCT circuit 103a is completed, and the decoding processing unit 13a starts outputting DCT data to the DCT data receiving unit 101a. On the other hand, it is assumed that the output of DCT data from the DCT data receiving unit 101b to the IDCT circuit 103b is not completed.

  At this time, the determination circuit 106 calculates the transmission period a of the DCT data receiving unit 101a and the transmission period b of the DCT data receiving unit 101b from the DCT data string information acquired from each of the decoding processing units 13a and 13b, and calculates these. Compare.

  As a result of the comparison, when it is determined that the transmission period a of the DCT data receiving unit 101a is shorter than the transmission period b of the DCT data receiving unit 101b, the determination circuit 106 assigns the IDCT circuit 101b to the DCT data receiving unit 101a. .

  As described above, when the determination circuit 106 refers to the transmission periods a and b acquired from the decoding processing units 13a and 13b and determines that there is room for processing by the IDCT circuit, the DCT data reception units 101a and 101b. The assignment of IDCT circuits 103a and 103b to is changed.

<< Assignment of output buffer to IDCT circuit >>
The motion compensation unit 15a receives the spatial data stored in the output buffer 105a and performs motion compensation on the received spatial data, and the motion compensation unit 15b receives the spatial data stored in the output buffer 105b and receives the received spatial data. Motion compensation for

  For example, if the IDCT circuit 103a and the output buffer 105a are connected, and the IDCT circuit and the output buffer 105b are connected, the output buffer 105a stores the spatial data A generated by the IDCT circuit 103a, and the output buffer 105b. Stores the spatial data B generated by the IDCT circuit 103b.

  If the motion compensation unit 15a issues a transfer instruction to the output buffer 105a to perform motion compensation, the output buffer 105a starts to output the spatial data A stored therein to the motion compensation unit 15a. On the other hand, if the transfer instruction from the motion compensation unit 15b is not issued to the output buffer 105b, the output buffer 105b holds the spatial data B stored therein.

  Further, it is assumed that the IDCT circuit 103b completes the inverse DCT conversion process faster than the IDCT circuit 103a.

  At this time, the determination circuit 106 refers to the processing status information acquired from each of the motion compensation units 15a and 15b, and the output buffer 15a outputs the stored spatial data to the motion compensation unit 15a. It is judged that 15b holds the stored spatial data. Therefore, the determination circuit 106 determines that the output buffer 105a becomes “empty” earlier than the output buffer 105b, and allocates the output buffer 105a to the IDCT circuit 103b that completes the inverse DCT conversion processing.

  As described above, when the determination circuit 106 refers to the processing status information acquired from the motion compensation units 15a and 15b and determines that there is room in the processing by the motion compensation unit, the output buffers 105a and 103b for the IDCT circuits 103a and 103b. The allocation of 105b is changed.

  The following can be considered as an example of the processing flow of the determination circuit 106. The determination circuit 106 determines which of the motion compensation units 15a and 15b completes the processing earlier based on the processing status such as the acquisition status of image data in the external memory in the subsequent motion compensation units 15a and 15b. Get information. Further, information such as which data string of the preceding decoding processing units 13a and 13b requires a longer transfer time is obtained. From these pieces of information, a data sequence that requires less transfer time is transferred to the motion compensation unit 15a, 15b that completes processing earlier, so that the motion compensation unit does not stop processing. To. On the contrary, the motion compensation units 15a and 15b that are delayed in completion of motion compensation transfer a data string that requires a long transfer time, and the IDCT circuits 103a and 103b stop when the motion compensation unit waits for completion. To prevent that.

<Effect>
As described above, a DCT data receiving unit with a short transmission period is preferentially assigned to an IDCT circuit having a margin for arithmetic processing, whereby the IDCT circuit having a margin for arithmetic processing receives DCT data from the DCT data receiving unit. Can reduce the time to wait. In addition, by preferentially assigning an IDCT circuit that completes arithmetic processing to an output buffer that can store spatial data, the time that the IDCT circuit waits to output spatial data to the output buffer is reduced. Can do. Thereby, it is possible to improve the operation efficiency of the entire apparatus.

  In general, the IDCT calculation unit often has a buffer for one block in the calculation circuit. This buffer is often used both as an input buffer for receiving data transmitted from the decoding processing unit and as an operation buffer for holding intermediate results of processing. If the arithmetic circuit has only one buffer, the buffer cannot be used as an arithmetic buffer during data transfer from the decoding processing unit, and the arithmetic processing cannot proceed. On the other hand, since the IDCT operation unit according to the present embodiment has two buffers, the processing performance can be ensured.

(Second Embodiment)
<Overall configuration>
The MPEG stream processing apparatus according to the second embodiment of the present invention includes an IDCT operation unit 20 shown in FIG. 3 instead of the IDCT operation unit shown in FIGS. Other configurations are the same as those in FIG.

<Internal configuration of IDCT calculation unit>
3 replaces the DCT data receivers 101a and 1010b and the IDCT circuits 103a and 103b shown in FIG. 2 with DCT data receivers 201a and 201b, high-speed transmission circuits 202a and 202b, IDCT circuits 203a and 203b. The DCT data receiving units 201a and 201b include input buffers 211a and 211b that can store data for one block. The IDCT circuits 203a and 203b include operation buffers 213a and 213b that can store data for one block, and operation processing units 214a and 214b. Other configurations are the same as those in FIG. Each of the DCT data receiving units 201a and 201b, like the DCT data receiving units 101a and 101b, has a one-to-one correspondence with the decoding processing units 13a and 13b, and is output by the decoding processing units 13a and 13b corresponding to itself. The DCT data thus stored is stored in its own input buffers 211a and 211b. Each of the high-speed transmission circuits 202a and 202b operates at a higher speed than the DCT data receiving units 201a and 201b, and receives DCT data for one block stored in the input buffers 211a and 211b included in the DCT data receiving units 201a and 201b. Output. Each of the IDCT circuits 203a and 203b is connected to the high-speed transmission circuits 202a and 202b corresponding to each of the DCT data reception units 201a and 201b by the selector 102, and one block worth output from the connected high-speed transmission circuits 202a and 202b. DCT data is stored in its own operation buffers 213a and 213b. Each of the arithmetic processing units 214 a and 214 b performs inverse DCT conversion on one block of DCT data stored in its own arithmetic buffers 213 a and 213 b, and outputs to the output buffers 105 a and 105 b connected to itself by the selector 104. The result of the inverse DCT transform is output as spatial data.

<Operation>
The operation of the MPEG stream processing apparatus according to the second embodiment will be described. Compared with the operation according to the first embodiment, the operation by this apparatus is different from the operation by the DCT data receiving units 201a and 201b and the operation by the IDCT circuits 203a and 203b.

<< Operation in DCT Data Receiving Unit and IDCT Circuit >>
First, as in the first embodiment, the decoding processing units 13a and 13b start outputting DCT data for one block to the DCT data receiving units 201a and 201b. Next, the DCT data receiving units 201a and 201b store the DCT data output from the corresponding decoding processing units 13a and 13b in their own buffers 211a and 211b. At this time, as in the first embodiment, the determination circuit 106 obtains the respective transmission periods of the DCT data receiving units 201a and 201b from the DCT data sequence information acquired from the decoding processing units 13a and 13b. With reference to the transmission period, IDCT circuits 203a and 203b are assigned to the high-speed transmission circuits 202a and 202b corresponding to the DCT data receiving units 201a and 201b, respectively.

  The selector 102 connects the high-speed transmission circuits 202a and 202b and the IDCT circuits 203a and 203b according to the assignment by the determination circuit 106.

  When one block of DCT data is stored in the input buffers 211a and 211b of the DCT data receiving units 201a and 201b, the high-speed transmission circuits 202a and 202b receive the DCT data for one block stored in the buffers 211a and 211b. Of the IDCT circuits 203a and 203b, the selector 102 starts outputting at high speed to the IDCT circuit connected to itself. For example, the high-speed transmission circuits 202a and 202b operate with a clock faster than the DCT data receiving units 201a and 201b.

  When the arithmetic processing units 214a and 214b of the IDCT circuits 203a and 203b store DCT data for one block in the arithmetic buffers 213a and 213b included in the IDCT circuits 203a and 203b, the arithmetic processing units 214a and 214b respectively store one block of data stored in the arithmetic buffers 213a and 214b. The inverse DCT transform is performed on the DCT data, and the result is output as spatial data.

  Next, as in the first embodiment, each of the output buffers 105 a and 105 b stores the spatial data output from the IDCT circuits 203 a and 203 b connected to itself by the selector 104.

<Effect>
As described above, when data transfer from the decoding processing unit to the data receiving unit is completed, transfer to the IDCT circuit is performed in a short period by the high-speed transmission circuit, and thereafter, data transfer from the decoding processing unit to the data receiving unit is possible. become. As a result, the time required for the IDCT circuit to receive DCT data from the DCT data receiving unit can be shortened, and the operation efficiency of the entire circuit can be improved.

  The transfer method using the high-speed transmission circuit includes a method of connecting the elements of both buffers in a one-to-one relationship, but is not particularly limited.

(Third embodiment)
<Overall configuration>
An MPEG stream processing apparatus according to the third embodiment of the present invention includes an IDCT operation unit 30 shown in FIG. 4 in place of the IDCT operation unit 14 shown in FIGS. Other configurations are the same as those in FIG.

<Internal configuration of IDCT calculation unit>
4 includes IDCT circuits 301a and 301b and a determination circuit 302 instead of the IDCT circuits 103a and 103b and the determination circuit 106 illustrated in FIG. Other configurations are the same as those in FIG. In addition to the operation of the determination circuit 106, the determination circuit 302 refers to the DCT data sequence information acquired from each of the decoding processing units 13a and 13b and the processing status information acquired from each of the motion compensation units 15a and 15b, and the IDCT circuit 301a and 301b are controlled. Each of the IDCT circuits 301a and 301b is activated or stopped under the control of the determination circuit 302 in addition to the operation of the IDCT circuits 103a and 103b.

<Operation>
The operation of the MPEG stream processing apparatus according to the third embodiment of the present invention differs from the operation according to the first embodiment in the operation of the IDCT operation unit 30 shown in FIG. In the operation by the IDCT calculation unit 30 shown in FIG. 4, in addition to the operation by the IDCT calculation unit 14 shown in FIG. 2, a process (startup control process) for stopping the IDCT circuits 301a and 301b depending on the situation is performed.

《Startup control processing》
First, processing similar to that of the first embodiment is performed, and the determination circuit 302 acquires DCT data sequence information from each of the decoding processing units 13a and 13b, and processing status information from each of the motion compensation units 15a and 15b. get.

  Next, the determination circuit 302 refers to each acquired DCT data string information and each processing status information to determine whether or not each of the IDCT circuits 301a and 301b needs to perform inverse DCT conversion. Judging.

  When it is determined that either one of the IDCT circuits 301a and 302b does not need to perform inverse DCT conversion, the determination circuit 302 determines whether the IDCT circuit 301a or 301b does not need to perform inverse DCT conversion. Stop operation. For example, the determination circuit 302 stops the clock signal input to the IDCT circuit that is determined not to perform the inverse DCT conversion among the IDCT circuits 301a and 301b.

  Next, as in the first embodiment, the determination circuit 302 refers to the calculated transmission period and assigns the IDCT circuits 301a and 301b to the DCT data reception units 101a and 101b. At this time, the determination circuit 302 does not assign one of the IDCT circuits 301a and 301b whose operation is stopped to the DCT data receiving units 101a and 101b. Similarly to the first embodiment, the determination circuit 302 refers to the determination results for the output buffers 105a and 105b, and assigns the output buffers 105a and 105b to the IDCT circuits 301a and 301b. Also at this time, the determination circuit 302 does not assign the output buffers 105a and 105b to the IDCT circuit 301a or 301b whose operation is stopped.

  On the other hand, when it is determined that both of the IDCT circuits 301a and 301b need to perform inverse DCT conversion, the determination circuit 302 refers to the calculated transmission period, as in the first embodiment, and receives the DCT data reception unit. The IDCT circuits 301a and 301b are assigned to the terminals 101a and 101b, and the output buffers 105a and 105b are assigned to the IDCT circuits 301a and 301b with reference to the determination results for the output buffers 105a and 105b.

  The following processing can be considered as a process for stopping one of the IDCT circuits 301a and 301b. Even when the parallel processing of the IDCT circuits 301a and 301b is performed, such as when the subsequent motion compensation units 15a and 15b take extremely long time to acquire the image data of the external memory necessary for motion compensation, the motion compensation unit always waits for completion. May occur. In this case, when the determination circuit 302 receives information such as the time taken for the processing of the motion compensation units 15a and 15b and exceeds a certain threshold value, one IDCT circuit is stopped.

<Effect>
As described above, the IDCT circuit works dynamically under the control of the determination circuit 302, and repeatedly stops and starts the circuit as necessary. Thereby, power consumption in the IDCT circuit can be reduced.

  In the present embodiment, the method of stopping the IDCT circuit is exemplified by stopping the clock signal. However, the present invention is not limited to this.

(Fourth embodiment)
In the inverse DCT conversion process, a method for simplifying the calculation process may be used. Examples include down-decode processing that performs IDCT processing by thinning out horizontal or vertical data, and zero data output processing that outputs all zero data without performing inverse DCT conversion processing when all elements are zero. As mentioned. In the former case (down decode processing), a slight deterioration in image quality occurs, but depending on the input data string, a processing result having almost no problem in actual use can be obtained. In the latter case (zero data output processing), there is no influence on the image quality.

<Overall configuration>
An MPEG stream processing apparatus according to the fourth embodiment of the present invention includes an IDCT operation unit 40 shown in FIG. 5 instead of the IDCT operation unit 14 shown in FIGS. Other configurations are the same as those in FIG.

<Internal configuration of IDCT calculation unit>
The IDCT operation unit 40 illustrated in FIG. 5 includes a simplified operation circuit 401 and a determination circuit 401 instead of the IDCT circuit 103b and the determination circuit 106 illustrated in FIG. The simplified arithmetic circuit 401 performs arithmetic processing that is simpler than the arithmetic processing by the IDCT circuit 103a. For example, the simplified arithmetic circuit 401 performs the above-described down-decoding process, zero data output process, and the like. The determination circuit 402 acquires DCT data sequence information from each of the decoding processing units 13a and 13b, and information (data content) indicating the contents of DCT data output from the decoding processing units 13a and 13b to the DCT data receiving units 101a and 101b. Information) is acquired from each of the decoding processing units 13a and 13b. For example, the data content information is information regarding the type of frame to which the DCT data belongs, the value of the DCT coefficient included in the DCT data, and the like.

<Operation>
The operation of the IDCT calculation unit 40 shown in FIG. 5 will be described. The IDCT calculation unit 40 shown in FIG. 5 performs a process (calculation method change process) for changing the calculation process according to the content of the MPEG stream.

<Calculation method change processing>
First, the same processing as in the first embodiment is performed, and the decoding processing units 13a and 13b start outputting DCT data for one block to the corresponding DCT data receiving units 101a and 101b. At this time, the determination circuit 402 acquires the DCT data string information from each of the decoding processing units 13a and 13b, and information (data content information) indicating the content of data to be output to the DCT data receiving unit. From each of 13b.

  Next, the determination circuit 402 refers to the data content information acquired from each of the decoding processing units 13a and 13b, and simplified arithmetic processing for the DCT data stored in each of the DCT data receiving units 101a and 101b. Thus, it is determined whether or not there is a possibility that the image quality is degraded when the inverse DCT transform is performed.

  If it is determined that there is a low possibility that the image quality is lowered, the determination circuit 402 simplifies the DCT data receiving unit corresponding to the decoding processing unit that acquired the data content information among the DCT data receiving units 101a and 101b. 401 is assigned. Similarly to the first embodiment, the determination circuit 402 refers to the calculated transmission period, and determines the DCT data receivers that are not assigned to the simplified arithmetic circuit 401 among the DCT data receivers 101a and 101b. IDCT circuit 103a is assigned.

  On the other hand, if it is determined that there is a high possibility that the image quality will be reduced, the determination circuit 402 refers to the calculated transmission period, as in the first embodiment, to each of the DCT data reception units 101a and 101b. Assign. At this time, the determination circuit 402 does not assign a simplified arithmetic circuit to any of the DCT data receiving units 101a and 101b.

  In the above operation, when the data content information is information on the value of the DCT coefficient included in the DCT data, the determination circuit 402 refers to the data content information and all the values of the DCT coefficient included in the DCT data are “0”. It is determined whether or not. When it is determined that the values of the DCT coefficients included in the DCT data are all “0”, the determination circuit 402 simplifies the operation circuit 401 for the DCT data reception unit corresponding to the decoding processing unit that acquired the data content information. Assign. The simplified arithmetic circuit 401 performs zero data output processing and outputs “0” data as spatial data for any input.

  In the above operation, when the data content information is information on the type of picture including DCT data, the determination circuit 402 refers to the data content information and the type of picture including DCT data is “B picture”. It is determined whether or not. When it is determined that the type of picture including the DCT data is “B picture”, the determination circuit 402 sends the simplified arithmetic circuit 401 to the DCT data reception unit corresponding to the decoding processing unit that acquired the data content information. Assign. The simplification arithmetic circuit performs down-decoding processing on the input DCT data and outputs the result as spatial data.

<Effect>
As described above, the simplified arithmetic circuit is associated with the receiving unit that stores the frequency data in which the deterioration in image quality is small even when the simplified calculation is performed. The speed at which the calculation is performed on the frequency data with little degradation in image quality even if the simplified calculation is performed is faster in the calculation by the simplified calculation circuit than in the calculation by other inverse orthogonal transform circuits. As a result, the processing speed by inverse orthogonal transform can be increased, and the operation efficiency of the entire apparatus can be improved. Further, even if a simpler circuit than the IDCT circuit of the first embodiment is used, the same level of processing as that of the first embodiment can be realized, and deterioration in image quality can be minimized.

  As described above, the present invention is useful for a circuit that performs inverse DCT conversion of an apparatus that decodes image data from an MPEG stream.

1 is a block diagram showing an overall configuration of an MPEG stream processing apparatus according to a first embodiment of the present invention. It is a block diagram which shows the internal structure of the IDCT calculating part shown in FIG. It is a block diagram which shows the internal structure of the IDCT calculating part by 2nd Embodiment of this invention. It is a block diagram which shows the internal structure of the IDCT calculating part by 3rd Embodiment of this invention. It is a block diagram which shows the internal structure of the IDCT calculating part by 4th Embodiment of this invention. It is a block diagram which shows the whole structure of the conventional MPEG stream processing apparatus. FIG. 7 is a block diagram showing a conventional MPEG stream processing apparatus including the MPEG stream processing apparatuses shown in FIG. 6 in parallel for the number of streams to be simultaneously processed. FIG. 7 is a block diagram showing a conventional MPEG stream processing apparatus that processes each circuit included in the MPEG stream processing apparatus shown in FIG. 6 in a time division manner when processing a plurality of streams simultaneously. 6 shows a conventional MPEG stream processing apparatus that performs parallel processing by having a plurality of circuits in a portion that can be processed in parallel within the MPEG decompression processing of the MPEG stream processing apparatus shown in FIG. 6 when processing a plurality of streams simultaneously. It is a block diagram.

Explanation of symbols

11 Stream processing unit 12 Separation unit 13a, 13b Decoding processing unit 14, 20, 30, 40 IDCT operation unit 15a, 15b Motion compensation unit 101a, 101b, 201a, 201b, DCT data receiving unit 102, 104 Selector 103a, 103b, 203a , 203b, 301a, 301b IDCT circuits 105a, 105b Output buffers 106, 203, 402 Judgment circuits 211a, 211b Input buffers 202a, 202b High-speed transmission circuits 213a, 213b Arithmetic buffers 214a, 214b Arithmetic processing unit 401 Simplified arithmetic circuit

Claims (7)

An apparatus that generates spatial data by performing inverse orthogonal transform on frequency data,
A determination unit, two or more reception units, two or more inverse orthogonal transform units, and two or more output buffers,
The determination unit
Associating any one of the inverse orthogonal transform units with each of the receiving units, and associating any one of the inverse orthogonal transform units with each of the output buffers,
Each of the receivers is
Storing the frequency data;
Each of the inverse orthogonal transform units includes:
The spatial data is generated by performing inverse orthogonal transform on the frequency data stored in the reception unit associated with the inverse orthogonal transform unit by the determination unit,
Each of the output buffers
The spatial data generated by the inverse orthogonal transform unit associated with the output buffer by the determination unit is stored,
The determination unit further refers to the time required for the reception unit to store the frequency data in each of the reception units and whether or not spatial data is stored by the output buffer in each of the output buffers. An inverse orthogonal transforming device characterized by performing attaching. In claim 1,
The inverse orthogonal transform device includes:
Connected between a decoding processing unit that decodes the encoded moving image data to generate frequency data and a motion compensation unit that performs motion compensation on the spatial data,
Each of the receivers is
Storing the frequency data generated by the decoding processing unit;
Each of the output buffers
Storing the spatial data generated by the inverse orthogonal transform unit associated with the output buffer by the determination unit, and outputting the stored spatial data to the motion compensation unit;
The determination unit
Refer to the time required for storing the frequency data from the decoding processing unit corresponding to the receiving unit in each of the receiving units and the operation state of the motion compensation unit corresponding to each of the output buffers. An inverse orthogonal transforming device characterized by performing attaching. In claim 1,
The inverse orthogonal transform device includes:
Connected between two or more decoding processing units that decode the encoded moving image data and generate frequency data, and two or more motion compensation units that perform motion compensation on the spatial data,
Each of the receivers is
One-to-one correspondence with any one of the decryption processing units,
Storing the frequency data generated by the decoding processing unit corresponding to the receiving unit;
Each of the output buffers
One-to-one correspondence with any one of the motion compensation units,
Storing the spatial data generated by the inverse orthogonal transform unit associated with the output buffer by the determination unit, and outputting the stored spatial data to the motion compensation unit corresponding to the output buffer;
The determination unit
Refer to the time required for storing the frequency data from the decoding processing unit corresponding to the receiving unit in each of the receiving units and the operation state of the motion compensation unit corresponding to each of the output buffers. An inverse orthogonal transforming device characterized by performing attaching. In claim 1,
The receiver is
A storage unit for storing the frequency data;
An output unit for outputting the frequency data stored in the storage unit,
The inverse orthogonal transform unit includes:
An operation buffer for storing frequency data from the output unit;
An inverse orthogonal transform apparatus comprising: an arithmetic unit that generates spatial data by performing inverse orthogonal transform on the frequency data stored in the arithmetic buffer. In claim 1,
The determination unit further refers to the time required for the receiving unit to store the frequency data in each of the receiving units and whether or not the output buffer stores spatial data in each of the output buffers. An inverse orthogonal transform apparatus characterized by stopping an inverse orthogonal transform unit that does not need to perform an operation among orthogonal transform units. In claim 1,
The two or more inverse orthogonal transform units include at least one simplified computation unit that performs a computation that is simplified as compared to computations performed by other inverse orthogonal transform units,
The determination unit further associates the simplification calculation unit with the reception unit that stores the frequency data according to the content of the frequency data stored in each of the reception units. In claim 1,
The inverse orthogonal transform device is characterized in that the inverse orthogonal transform is an inverse DCT transform.

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